Soft error rate rapid estimation method and system based on graph neural network

Abstract

The invention discloses a rapid soft error rate estimation method and system based on a graph neural network, and the method comprises the steps: converting an estimated combinational circuit into a directed acyclic graph, enabling nodes in the directed acyclic graph to be an input unit, an AND gate unit and an output unit in the estimated combinational circuit, and enabling edges to be a connection relation between the nodes; adding feature information to the directed acyclic graph; and the directed acyclic graph added with the feature information is subjected to regression prediction of the soft error rate of the combinational circuit by using a pre-trained graph neural network, and the graph neural network is pre-trained to establish a mapping relation between the directed acyclic graph and the soft error rate. The invention aims to quickly and efficiently estimate the soft error rate of each unit in the combinational logic circuit under the condition of only considering the logic shielding effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit electronic design automation (EDA), and in particular to a method and system for fast estimating soft error rate based on graph neural network. Background Art

[0002] Electronic design automation refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design and other processes of very large-scale integrated circuits. Soft errors in integrated circuits refer to errors caused by single-particle effects. Single-particle effects are one of the most important ionizing radiation effects. When a single-particle effect occurs, particles bombarding different locations of the circuit will cause different phenomena and faults. According to whether the fault can be recovered, it can be divided into two categories: ① Destructive single-particle effects, also known as hard errors, will cause irreversible damage to the circuit after they occur, such as single-particle latch, single-particle burnout, single-particle gate penetration, single-particle dielectric breakdown, single-particle bit lock, etc.; ② Non-destructive single-particle effects, also known as soft errors, will cause circuit system state errors after they occur, but will not cause hardware damage. They can be restored to normal through software and hardware algorithms or restart and reset, such as single-particle upset, multi-unit upset, block error, column error, row error, single-particle functional interrupt, single-particle transient and single-particle multi-transient, etc. When a combinational circuit unit is affected by a single-particle transient and a soft error occurs, the probability that it can propagate along the circuit direction and be successfully captured by the output end is the soft error rate.

[0003] Single-particle transient is one of the most important single-particle effects. Its external manifestation is that when a unit in the circuit is bombarded by particles, a transient pulse is generated. The pulse propagates backward along the circuit path. If it can reach the output end and be successfully captured by the timing unit, the transient pulse causes a soft error and affects the normal operation of the circuit. However, the probability that a single-particle transient can propagate to the output end is not high. The reason is that there are three shielding effects, logical shielding, electrical shielding, and latch window shielding. Logical shielding refers to the inability of a transient pulse to propagate backward when it encounters a unit in a closed state. Electrical shielding refers to the attenuation of the width and amplitude of the pulse waveform due to parasitic effects such as capacitance and resistance when the transient pulse passes through a unit or wire network, resulting in the inability to continue to propagate backward. Latch window shielding refers to the fact that the transient pulse must arrive at the right time within the clock cycle and meet the requirements of hold time and setup time in order to be successfully captured by the downstream timing unit. Logical shielding is the most important and complex shielding effect among the three shielding effects, because it is related to the current input stimulus of the circuit and is in dynamic change. With the advancement of technology and the improvement of circuit performance, the effect of electrical shielding has gradually weakened, and the use of latch window shielding to filter single-particle transient pulses has become difficult due to the reduction of clock cycles. The logical shielding effect is less affected by the process, and the same analysis method is still effective under different processes. In addition, the new problems caused by size reduction also make it more important to analyze the logical structure of the circuit. Considering only the logical shielding effect, how to quickly and efficiently estimate the soft error rate of each unit in the combinational logic circuit has become a key technical problem that needs to be solved urgently. Summary of the invention

[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method and system for fast estimation of soft error rate based on graph neural network is provided. The present invention aims to quickly and efficiently estimate the soft error rate of each unit in a combinational logic circuit.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for fast estimating soft error rate based on graph neural network includes the following steps: S1, converting the estimated combinational circuit into a directed acyclic graph, wherein the nodes in the directed acyclic graph are inputs, AND gates and output units in the estimated combinational circuit, and the edges are the connection relationships between the nodes; S2, add feature information to the directed acyclic graph; S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0006] Optionally, adding feature information to the directed acyclic graph in step S2 includes adding node feature information to the nodes in the directed acyclic graph, and the node feature information added to the directed acyclic graph includes part or all of the topological order of the nodes, the fan-in and fan-out numbers of the nodes, the number of associated inputs of the nodes, the number of outputs associated with the nodes, the number of paths between the nodes and the outputs, the average length of the paths between the nodes and the outputs, and the average number of inputs associated with the paths between the nodes and the outputs.

[0007] Optionally, the nodes in the directed acyclic graph in step S1 are AND gates of the combinational circuit, the edges are connection lines of the AND gates in the combinational circuit, the NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph, and the use of a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit refers to using a pre-trained graph neural network to regress and predict the soft error rate of the AND gate in the combinational circuit; adding feature information to the directed acyclic graph in step S2 includes adding edge feature information to the edges in the directed acyclic graph, and the function expression of the added edge feature information is: , In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

[0008] Optionally, converting the estimated combinational circuit into a directed acyclic graph in step S1 includes: S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2; S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the combinational circuit in bench format into verilog format, and then use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a combinational circuit in verilog format, use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool yosys to convert the sequential circuit into table format, and then use the trigger as the main input or main output of the sub-circuit, divide the sequential circuit in table format into sub-circuits according to the trigger to obtain bench format sub-circuits, convert the bench format sub-circuit into verilog format, and use the tool yosys to convert the verilog format into AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit; S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

[0009] Optionally, step S3 also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate: S101, obtaining a combinational circuit sample; S102, converting the combinational circuit sample into a combinational circuit sample in AIG format; S103, reading the structure information of the combinational circuit sample in AIG format, checking whether the read circuit structure information meets the specification, and discarding it if it does not meet the specification; S104, for each AIG format combinational circuit sample, convert the combinational circuit sample into a directed acyclic graph, where the nodes in the directed acyclic graph are circuit units of the combinational circuit sample, and the edges are connection lines of the circuit units in the combinational circuit sample, add feature information to the directed acyclic graph, and use the soft error rate of the node in the combinational circuit sample as a node label to add node label information to construct a circuit data set; S105, dividing the circuit data set into a training set and a test set; S106, use the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0010] Optionally, acquiring the soft error rate of the node in the combinational circuit sample includes: S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit unit to the main output port; S202, traversing and selecting a circuit unit as a current circuit unit; S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked; S204, adding the constraints of the sensitized path to the SAT solver; S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit, if a satisfiable solution cannot be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution, if there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to shield the current solution that has been obtained, and jump to step S205; S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

[0011] Optionally, when using the depth-first search method in step S201 to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it includes using a dual stack to store the intermediate process of traversing the entire graph, and the dual stack includes a main stack and an auxiliary stack. The main stack is used to store a single element, and the element is used to represent a node on the current path. The auxiliary stack stores a list of adjacent nodes corresponding to the element in the main stack. The length of the auxiliary stack is always consistent with that of the main stack. During the full-graph search, the main stack and the auxiliary stack are constantly changing, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

[0012] In addition, the present invention also provides a system for rapid estimation of soft error rate based on graph neural network, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for rapid estimation of soft error rate based on graph neural network.

[0013] In addition, the present invention also provides a computer-readable storage medium, which stores a computer program or instruction, and the computer program or instruction is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0014] In addition, the present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0015] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes converting the estimated combinational circuit into a directed acyclic graph, the nodes in the directed acyclic graph are the circuit units of the combinational circuit, and the edges are the connection lines of the circuit units in the combinational circuit; adding feature information to the directed acyclic graph; using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit with the directed acyclic graph after adding the feature information, and the graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate. The present invention can quickly and efficiently estimate the soft error rate of each unit in the combinational logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a basic flow chart of the rapid estimation of soft error rate in the method of the embodiment of the present invention.

[0017] Figure 2 FIG. 4 is a schematic diagram of the structure of a combinational circuit to be estimated in an embodiment of the present invention.

[0018] Figure 3 FIG. 4 is a schematic diagram of a directed acyclic graph of a combinational circuit to be estimated in an embodiment of the present invention.

[0019] Figure 4 The figure is a schematic diagram of a process of constructing a circuit data set in an embodiment of the present invention.

[0020] Figure 5 Schematic diagram of the training process of the neural network in the figure according to an embodiment of the present invention.

[0021] Figure 6 Schematic diagram of the process of converting the format of combinational circuit samples when training a graph neural network in an embodiment of the present invention.

[0022] Figure 7 Schematic diagram of the process of training a graph neural network in an embodiment of the present invention.

[0023] Figure 8 It is a schematic diagram of adding AND gate constraints to MiniSAT in an embodiment of the present invention.

[0024] Fig. 9 Schematic diagram of a flow chart of calculating the soft error rate of a circuit unit using MiniSAT in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] like Figure 1 As shown, the method for fast estimating soft error rate based on graph neural network in this embodiment includes the following steps: S1, converting the estimated combinational circuit into a directed acyclic graph, wherein the nodes in the directed acyclic graph are inputs, AND gates and output units in the estimated combinational circuit, and the edges are the connection relationships between the nodes; S2, add feature information to the directed acyclic graph; S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate.

[0026] In step S2 of this embodiment, adding feature information to the directed acyclic graph includes adding node feature information to the nodes in the directed acyclic graph, and the node feature information added to the directed acyclic graph includes part or all of the topological order of the nodes, the fan-in and fan-out numbers of the nodes, the number of associated inputs of the nodes, the number of outputs associated with the nodes, the number of paths between the nodes and the outputs, the average length of the paths between the nodes and the outputs, and the average number of inputs associated with the paths between the nodes and the outputs.

[0027] As an optional implementation, the nodes in the directed acyclic graph in step S1 of this embodiment are AND gates of the combinational circuit, the edges are connection lines of the AND gates in the combinational circuit, the NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph, and using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit refers to using a pre-trained graph neural network to regress and predict the soft error rate of the AND gates in the combinational circuit. Figure 2 1 is a combinational circuit to be evaluated in an embodiment of the present invention, wherein 1-3 are input ports, 7 is an output port, 4-6 are AND gates, and further includes 2 NOT gates. Figure 3 for Figure 2 The directed acyclic graph of the estimated combinational circuit, wherein two NOT gates (NOT) are not present as nodes in the directed acyclic graph but are integrated on the edge of the directed acyclic graph. In order to reflect the position of the edge in the graph and whether there is a NOT gate on the edge, this embodiment uses a 32-dimensional feature to quantify the information. In step S2 of this embodiment, when adding feature information to the directed acyclic graph, it includes adding edge feature information to the edge in the directed acyclic graph, and the function expression of the added edge feature information is: , In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

[0028] In step S1 of this embodiment, converting the estimated combinatorial circuit into a directed acyclic graph includes: S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2; S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the combinational circuit in bench format into verilog format, and then use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a combinational circuit in verilog format, use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool yosys to convert the sequential circuit into table format, and then use the trigger as the main input or main output of the sub-circuit, divide the sequential circuit in table format into sub-circuits according to the trigger to obtain bench format sub-circuits, convert the bench format sub-circuit into verilog format, and use the tool yosys to convert the verilog format into AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit; S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

[0029] like Figure 4 and Figure 5 As shown, step S3 of this embodiment also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate: S101, obtaining a combinational circuit sample; As an optional implementation, such as Figure 6 As shown, the combinational circuit samples in step S101 of this embodiment are from the ISCAS'85 test set, the EPFL test set and Opencores, wherein the circuits in the ISCAS'85 test set are in bench format, and the circuits in the EPFL test set and Opencores are in Verilog format.

[0030] S102, convert the combinational circuit samples into combinational circuit samples in AIG format; in this embodiment, the open source tool yosys is used to uniformly convert the circuits from Verilog format to AIG format through its built-in related instructions; in addition, combinational circuit samples can be obtained from other existing data sets or made by yourself as needed; when processing the ISCAS'85 circuit test set, all the circuits in the test set are combinational circuits in bench format. This embodiment first uses the bench_to_verilog.py script to convert the bench format combinational circuit into verilog format, and then uses the open source tool yosys to convert the verilog format circuit into AIG format. The instruction flow in this embodiment is as follows: yosys -import read_verilog * synth-flatten-auto-top aigmap write_aiger -ascii . / test.aag exit In the above instruction stream, the first line of instructions is to import the combinational circuit in Verilog format into the open source tool yosys; the second line is to read all the files of the imported combinational circuit in Verilog format in the current directory; the third line is to perform the synthesis operation, the -flatten option means to flatten the circuit hierarchy, and the -auto-top option automatically determines the top-level module; the fourth line is to map the circuit to AIG format, which is the step of preparing to output the AIG file; the fifth line is to write the AIG format circuit in ASCII encoding into a file named test.aag, and the sixth line is to exit the open source tool yosys. When processing the EPFL circuit test set, the test set contains combinational circuits in verilog format. This embodiment uses the open source tool yosys to convert this part of the circuit into AIG format. Figure 6As shown, when processing the circuits in Opencores, it includes both combinational circuits and sequential circuits. For combinational circuits, this embodiment uses the open source tool yosys to convert them into the AIG format; for sequential circuits, this embodiment first uses the open source tool yosys to convert them into a table format, and then uses the table_to_bench.py ​​script to divide the sequential circuit into sub-circuits based on the trigger (using the trigger as the main input or main output of the sub-circuit), and obtains the bench format sub-circuit, and then uses the bench_to_verilog.py script to convert it into the verilog format, and finally uses the open source tool yosys to convert it into the AIG format circuit. The purpose of using sequential circuits for sub-circuit division is to expand the scale of the circuit data set; S103, read the structure information of the combinational circuit sample in AIG format, check whether the read circuit structure information meets the specification, and discard it if it does not meet the specification; when reading the circuit structure information in AIG format, the aiger_open_and_read_from_file() method provided by the AIGER And-Inverter-Graph Library code repository can be used to read the circuit structure information; the aiger_check() method provided by the AIGER And-Inverter-Graph Library code repository can be used to check whether the read circuit structure information meets the specification; S104, for each combinational circuit sample in AIG format, convert the combinational circuit sample into a directed acyclic graph, where the nodes in the directed acyclic graph are circuit units of the combinational circuit sample, and the edges are connecting lines of the circuit units in the combinational circuit sample, add feature information to the directed acyclic graph, and use the soft error rate of the nodes in the combinational circuit sample as node labels to add node label information to construct a circuit data set; when adding node label information, the node label is the soft error rate data, which is the target of regression prediction using the graph neural network in this embodiment. In the training set, the label needs to be added to the node to calculate the current error and guide the direction of parameter adjustment of the model. In the test set, the label needs to be used to calculate the error between the predicted value and the standard value to verify the generalization performance of the model; S105, divide the circuit data set into a training set and a test set; divide the circuit data set, convert the AIG format combinational circuit into a graph data structure, and after adding node feature information, edge feature information and node label information, a complete circuit data set can be formed. Then, the circuits in the data set need to be randomly divided into a training set and a test set according to a suitable ratio. As an optional implementation, in this embodiment, the data set is randomly divided into a training set and a test set at a ratio of 7:3; S106, using the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate, including: first establishing an initial graph neural network, Figure 5 In the figure, the initial graph neural network is represented as graph neural network model M1, and then the model parameters are adjusted using the training set, and the generalization is verified using the test set. Then the trained graph neural network is represented as graph neural network M1'.

[0031] Graph neural network refers to the extension of neural network methods to the field of graph data processing, extracting and discovering key features and patterns in graph structure data, and ultimately achieving prediction of the target. Graph neural networks can be classified according to their architecture and the way they process graph structure data, mainly including the following three categories: (1) Graph convolutional neural network: The convolution operation in the convolutional neural network (CNN) is extended to the graph field to achieve the update of node features. (2) Graph recurrent neural network: The structure of the recurrent neural network (RNN) is used to perform recursive calculations on the graph. This type of network is suitable for dynamic graphs or time series graphs. (3) Graph attention network: The attention mechanism is introduced to replace the static normalization constant in the graph convolutional network, and a learnable importance weight parameter is calculated for all neighbor nodes of each node. The graph neural network can adopt the required graph neural network type as needed. For example, as an optional implementation method, this embodiment uses a graph neural network model specifically for directed acyclic graphs: the DAGTransformer model. The model is trained on the training set, and the hyperparameters used by the DAG Transformer model are continuously adjusted to enable it to have better performance on the test set. The model parameter dictionary corresponding to the best performance on the test set is saved, and the model is used to predict the soft error rate of each unit of the new combinational circuit. Figure 7As shown, in step S106 of this embodiment, when using the training set and the test set to train the graph neural network (DAG Transformer model), the following steps are included: (1) Normalizing feature data and label data: In certain calculation processes of the graph neural network, the gradient descent algorithm needs to be used. If the scale of the feature data is very different, it may cause numerical instability or gradient disappearance / explosion problems. Using normalization helps to avoid such numerical problems. At the same time, scaling the feature data to the same scale also helps to accelerate the convergence speed of the algorithm. (2) Optimizer adjustment: The optimizer is an algorithm for back propagation, which can adaptively adjust the parameters in the graph neural network model so that the graph neural network can perform better on the training set. The optimizer and the gradient descent algorithm are closely related. The gradient descent algorithm has many problems (such as falling into local optimality, oscillation, slow convergence, etc.). Different optimizers will introduce different techniques to optimize the gradient descent algorithm. Therefore, when training the graph neural network, this embodiment tries to use various optimizers and finally selects the one with the best performance. (3) Learning rate adjustment: The learning rate is a very important hyperparameter in supervised learning. It controls the learning progress of the graph neural network and determines whether the graph neural network can succeed or how long it takes to successfully find the global optimal solution. If the learning rate is too large, the graph neural network will not be able to converge and will hover around the optimal solution; if the learning rate is too small, the graph neural network will converge very slowly, greatly increasing the time to find the optimal solution, and may converge after finding a local extreme point, failing to find the true optimal solution. Therefore, this embodiment tried a variety of different options when setting the learning rate (initial learning rate setting: ), and as the number of training rounds increases, the learning rate gradually decreases, and finally a starting learning rate with the best performance and the smallest error is selected. (4) Loss function adjustment: The role of the loss function is to express the degree of difference between the predicted value and the true value, which can measure the quality of the model prediction. For node regression type prediction tasks, the mean squared error (MSE) or mean absolute error (MAE) is generally used as the loss function. Finally, the training set is used to adjust the model parameters, the test set is used to verify the generalization, and then the model parameters with the best effect on the test set are saved to obtain the trained DAG Transformer model.

[0032] It should be noted that the soft error rate of the nodes in the combinational circuit sample can be obtained as needed. For each combinational circuit unit, whether a single-particle transient type (SET) soft error can be propagated to the output end and captured depends on the current input state. Therefore, a method that is easy to think of is to perform a fault simulation for each input state of the combinational circuit, and finally count the number of times the soft error can propagate to the output end and be captured. The soft error rate of the combinational circuit unit is defined as: the number of times captured by the output end / the total number of input states. However, based on the fault simulation technical requirements of simulation, exhaustive simulation is required to calculate the soft error rate of each unit in the combinational circuit (2 N times, where N is the number of main inputs of the circuit). Therefore, this method has a very high time complexity and is extremely time-consuming. In addition to the simplest fault simulation technology mentioned above, there is another approach that is to convert the soft error rate calculation problem of the combinational circuit unit into a satisfiability problem (SAT) for solution. Assuming that a soft error occurs in a unit in the combinational circuit, the soft error rate of the unit is the ratio of the number of input combinations that the error can propagate to the output to the total number of input combinations. How to convert this problem into a satisfiability problem includes: First, a combinational circuit is equivalent to a set of constraints. Each logic gate in the circuit can be represented by a SAT constraint. For example, a SAT constraint corresponding to a gate is as follows: Figure 8 As shown, P and Q are the inputs of the AND gate, R is the output of the AND gate, and the function expression of the SAT constraint corresponding to the AND gate is: ,in" " is the NOT operation," " is the AND operation," " is an OR operation. And for the convenience of solving, the combinational circuit is usually converted into AIG format, which only contains AND gates and NOT gates. After adding the original SAT constraints of the circuit, it is necessary to obtain all the paths from the combinational circuit unit where the soft error occurs to the output end, add sensitization constraints to each path independently, and finally send it to the SAT solver (such as MiniSAT) to solve the number of satisfactory solutions. The soft error rate of the combinational circuit unit is defined as: the sum of the number of satisfactory solutions of all paths divided by the total number of input states. This method has a certain degree of improvement in speed (about 15 times) compared with the simulation-based fault simulation technology, but this method still takes a long time and is limited by the number of inputs of the combinational circuit. It cannot handle circuits with larger scale and more main inputs. As an optional implementation method, the soft error rate of the circuit unit is calculated in this embodiment. For each unit in the combinational circuit, MiniSAT is used to calculate the probability that the unit can be successfully propagated to the output end after a soft error occurs. Specifically, Fig. 9 As shown, the acquisition of the soft error rate of the node in the combinational circuit sample in this embodiment includes: S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit unit to the main output port; S202, traversing and selecting a circuit unit as a current circuit unit; S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked; S204, adding the constraint conditions of the sensitized path to the SAT solver; as an optional implementation, the SAT solver in this embodiment uses MiniSAT as the SAT solver, and other SAT solvers may also be used as needed; for each combinational circuit, its structure information and connection relationship are a set of SAT constraint conditions, so it is necessary to add the constraint conditions consisting of the structure information and connection relationship on the sensitized path to the MiniSAT solver; S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit, if a satisfiable solution cannot be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution, if there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to shield the current solution that has been obtained, and jump to step S205; S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

[0033] When the SAT solver is used in step S205 for loop solution, according to the solution principle of MiniSAT, only one set of satisfiable solutions can be obtained after adding the constraints. If you want to obtain all the satisfiable solutions, you need to add additional constraints to shield the solutions that have been obtained when solving the satisfiable solutions. After adding the additional constraints, if a satisfiable solution can still be obtained, continue to add constraints to shield the current solution and continue to use MiniSAT for solution. After adding the additional constraints, if a satisfiable solution (unsat) cannot be obtained, all the satisfiable solutions for this sensitized path have been obtained, and this solution is terminated. After adding the additional constraints, if a satisfiable solution can be obtained, but a signal in the satisfiable solution is undef (undefined), it means that this solution has failed (possibly caused by timeout, etc.), and this solution can also be terminated.

[0034] The problem of using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample is a full-graph traversal problem. As an optional implementation method, based on the depth-first search DFS, when using a depth-first search method in step S201 of this embodiment to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it further includes using a dual stack to store the intermediate process of the full-graph traversal, the dual stack includes a main stack and an auxiliary stack, the main stack is used to store a single element, the element is used to represent a node on the current path, the auxiliary stack stores a list of adjacent nodes corresponding to the element of the main stack, the length of the auxiliary stack is always consistent with that of the main stack, and the main stack and the auxiliary stack are constantly changing during the full-graph search process, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

[0035] In summary, the method for fast estimation of soft error rate based on graph neural network in this embodiment can estimate the sensitivity of each unit of the combinational circuit to single particle transient (SET) type soft errors more quickly. The invention includes four core contents: 1) circuit format conversion; 2) using MiniSAT tool to calculate the label data of each unit of the combinational circuit; 3) circuit modeling and data set construction; 4) training graph neural network and verifying its generalization performance on a new circuit. The method of this embodiment includes proposing to use triggers as the main input or main output, randomly divide the timing circuit into sub-circuits, obtain a large number of smaller-scale combinational circuits, and expand the scale of the data set. The method of this embodiment includes proposing to use the open source tool MiniSAT to calculate the soft error rate (that is, the number of satisfactory solutions) of each unit of the combinational circuit. Generally speaking, MiniSAT will only obtain a set of satisfactory solutions for specific constraints. However, in this embodiment, the requirement is to obtain all satisfactory solutions for specific constraints, so the idea of ​​​​cyclic solution is proposed, that is, in the process of solving, the solutions that have been obtained are continuously shielded until the constraints are unsatisfactory. The method of this embodiment includes proposing a new modeling method for AIG format combinational circuits. Considering that the goal is to estimate the soft error rate of the AND gate in the combinational circuit, the input, AND gate and output of the combinational circuit are nodes, and the connection relationship between them is an edge. And when considering the connection relationship, the NOT gate is directly skipped, and the NOT gate is quantified on the edge in the form of a feature. Overall, the method of this embodiment proposes a set of systematic technical frameworks to quickly estimate the soft error rate of each unit of the combinational circuit. Compared with previous methods, whether it is a fault model based on simulation or a method based on Boolean satisfaction problem, the time overhead is very large. For a brand-new combinational circuit (about 10,000 gates), it often takes several hours or even days to get an accurate result using the previous method; while using the method of this embodiment, it only takes about ten minutes to get the estimated result, and the average absolute value error of the soft error rate of each AND gate of the combinational circuit is within 10%. This embodiment can be aimed at integrated circuit electronic design automation (EDA), and can quickly and efficiently estimate the soft error rate of each unit in the combinational logic circuit when only considering the logical shielding effect.

[0036] In addition, this embodiment also provides a system for rapid estimation of soft error rate based on graph neural network, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the method for rapid estimation of soft error rate based on graph neural network.

[0037] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instructions, and the computer program or instructions are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0038] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method for fast soft error rate estimation based on graph neural network through a processor.

[0039] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0040] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for fast soft error rate estimation based on graph neural network, characterized in that: The steps include: S1, converting the estimated combinational circuit into a directed acyclic graph, wherein the nodes in the directed acyclic graph are inputs, AND gates and output units in the estimated combinational circuit, and the edges are the connection relationships between the nodes; S2, add feature information to the directed acyclic graph; S3, using a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit using the directed acyclic graph after adding feature information. The graph neural network is pre-trained to establish a mapping relationship between the directed acyclic graph and the soft error rate.

2. The method for fast soft error rate estimation based on graph neural network according to claim 1, characterized in that: Adding characteristic information to the directed acyclic graph in step S2 includes adding node characteristic information to the nodes in the directed acyclic graph, and the node characteristic information added to the directed acyclic graph includes part or all of the topological order of the nodes, the fan-in and fan-out numbers of the nodes, the number of associated inputs of the nodes, the number of outputs associated with the nodes, the number of paths between the nodes and the outputs, the average length of the paths between the nodes and the outputs, and the average number of inputs associated with the paths between the nodes and the outputs.

3. The method for fast soft error rate estimation based on graph neural network according to claim 1, characterized in that: The nodes in the directed acyclic graph in step S1 are AND gates of the combinational circuit, the edges are the connection lines of the AND gates in the combinational circuit, the NOT gates in the combinational circuit do not exist as nodes in the directed acyclic graph but are integrated on the edges of the directed acyclic graph, and the use of a pre-trained graph neural network to regress and predict the soft error rate of the combinational circuit refers to the use of a pre-trained graph neural network to regress and predict the soft error rate of the AND gate in the combinational circuit; adding feature information to the directed acyclic graph in step S2 includes adding edge feature information to the edges in the directed acyclic graph, and the function expression of the added edge feature information is: ， In the above formula, is the edge feature information; Used to indicate whether there is a NOT gate on the edge. If there is a NOT gate If there is no NOT gate, then ; Indicates the starting node position of the edge; Indicates the end node position of the edge, is the number of layers of the graph neural network.

4. The method for fast soft error rate estimation based on graph neural network according to claim 3 is characterized in that: The step S1 of converting the estimated combinational circuit into a directed acyclic graph includes: S1.1, if the estimated combinational circuit is a combinational circuit in AIG format, jump to step S1.3, otherwise jump to step S1.2; S1.2, if the estimated combinational circuit is a combinational circuit in bench format, convert the combinational circuit in bench format into verilog format, and then use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a combinational circuit in verilog format, use the tool yosys to convert the verilog format into AIG format; if the estimated combinational circuit is a sequential circuit, first use the tool yosys to convert the sequential circuit into table format, and then use the trigger as the main input or main output of the sub-circuit, divide the sequential circuit in table format into sub-circuits according to the trigger to obtain bench format sub-circuits, convert the bench format sub-circuit into verilog format, and use the tool yosys to convert the verilog format into AIG format; if converted to AIG format, jump to step S1.3, otherwise end and exit; S1.3, read the structural information of the combinational circuit in the AIG format, and check whether the read circuit structural information meets the specification. If it meets the specification, generate a directed acyclic graph of the estimated combinational circuit according to the structural information of the combinational circuit in the AIG format, otherwise end and exit.

5. The method for fast soft error rate estimation based on graph neural network according to claim 1, characterized in that: Step S3 also includes training a graph neural network to establish a mapping relationship between a directed acyclic graph and a soft error rate: S101, obtaining a combinational circuit sample; S102, converting the combinational circuit sample into a combinational circuit sample in AIG format; S103, reading the structure information of the combinational circuit sample in AIG format, checking whether the read circuit structure information meets the specification, and discarding it if it does not meet the specification; S104, for each AIG format combinational circuit sample, convert the combinational circuit sample into a directed acyclic graph, where the nodes in the directed acyclic graph are circuit units of the combinational circuit sample, and the edges are connection lines of the circuit units in the combinational circuit sample, add feature information to the directed acyclic graph, and use the soft error rate of the node in the combinational circuit sample as a node label to add node label information to construct a circuit data set; S105, dividing the circuit data set into a training set and a test set; S106, use the training set and the test set to train the graph neural network to establish a mapping relationship between the directed acyclic graph and the soft error rate.

6. The method for fast soft error rate estimation based on graph neural network according to claim 5, characterized in that: The acquisition of the soft error rate of the node in the combinational circuit sample includes: S201, using a depth-first search method to obtain a set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, and store all paths from the circuit unit to the main output port; S202, traversing and selecting a circuit unit as a current circuit unit; S203, conveniently selecting a sensitized path from all paths of the current circuit unit, wherein the sensitized path refers to a path from which a soft error can be successfully propagated to a main output without being logically masked; S204, adding the constraints of the sensitized path to the SAT solver; S205, using a SAT solver to cyclically solve for a satisfiable solution for the soft error of the current circuit unit, if a satisfiable solution cannot be obtained, jump to step S206; otherwise, determine whether there is an undefined signal in the obtained satisfiable solution, if there is an undefined signal in the satisfiable solution, jump to step S206; if there is no undefined signal in the satisfiable solution, add additional constraints to the SAT solver to shield the current solution that has been obtained, and jump to step S205; S206, determine whether the sensitization path of the current circuit unit has been traversed. If the sensitization path of the current circuit unit has not been traversed, jump to step S203; otherwise, determine whether the circuit unit has been traversed. If the circuit unit has not been traversed, jump to step S202. If the circuit unit has been traversed, the soft error rate of the node in the combinational circuit sample is obtained.

7. The method for fast soft error rate estimation based on graph neural network according to claim 6, characterized in that: In step S201, when using the depth-first search method to obtain the set of circuit units that can affect the main output port in the directed acyclic graph of the combinational circuit sample, it includes using a double stack to store the intermediate process of traversing the entire graph, and the double stack includes a main stack and an auxiliary stack. The main stack is used to store a single element, and the element is used to represent a node on the current path. The auxiliary stack stores a list of adjacent nodes corresponding to the element of the main stack. The length of the auxiliary stack is always consistent with that of the main stack. During the full-graph search, the main stack and the auxiliary stack are constantly changing, so that all paths between the target starting point and the main output port are obtained during the change of the main stack and the auxiliary stack.

8. A system for fast soft error rate estimation based on graph neural network, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method for fast soft error rate estimation based on graph neural network as described in any one of claims 1 to 7 through a processor.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method for fast estimating soft error rate based on graph neural network as described in any one of claims 1 to 7 through a processor.

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