Multi-chip parallel packaging design method and system applying same

Abstract

The invention discloses a multi-chip parallel packaging design method and a system applying the same. The multi-chip parallel packaging design system comprises model analysis, three-dimensional model analysis and electrical simulation. The model analysis obtains a pin connection mode of the design circuit according to the design circuit, obtains at least one conductive layer of the design circuit according to the stack structure information, selects a transmission line model conforming to the pin connection mode and the at least one conductive layer from a plurality of transmission line models, and substitutes the stack structure information and the design rule into the selected transmission line model, generating a corresponding relation between the transmission line length and the characteristic parameter according to the equivalent circuit, and obtaining the transmission line length corresponding to the characteristic parameter design target according to the corresponding relation. The three-dimensional model analysis constructs a three-dimensional model of the design circuit according to the acquired length of the transmission line. Whether the characteristic parameters of the three-dimensional model meet the characteristic parameter design target or not is judged through electrical simulation.

Description

Technical Field

[0001] The invention relates to a multi-chip parallel package design method and a multi-chip parallel package design system using the method. Background Art

[0002] The existing packaging design process is that the layout engineer performs circuit routing layout according to the design rules, and then the electrical engineer performs packaging circuit design simulation analysis based on experience (such as commercial design tool software Cadence / Ansys), and then performs functional verification. If the verification is successful, it ends. If the verification is unsuccessful, the previous steps are repeated. However, manual adjustments are prone to misjudgment and time-consuming. Therefore, how to improve the aforementioned known problems is one of the goals of the industry in this technical field. Summary of the invention

[0003] Therefore, the present invention proposes a multi-chip parallel packaging design method and a multi-chip parallel packaging design system using the same, which is suitable for a systematic packaging design method for vertically or horizontally paralleling multiple chips. The chip information and process design rules are input, and a general parallel design and electrical optimization method are completed through this parallel design method.

[0004] An embodiment of the present invention provides a multi-chip parallel package design method. The multi-chip parallel package design method includes the following steps: obtaining a circuit diagram of a design circuit; performing a circuit layout according to the circuit diagram of the design circuit; constructing a three-dimensional model of the design circuit according to the circuit layout; when the characteristic parameter does not meet the characteristic parameter design target, selecting a patent document that meets the circuit layout from a patent database; and optimizing the design circuit according to the patent document. The step of performing the circuit layout according to the circuit diagram of the design circuit includes: obtaining a pin connection mode of the design circuit according to the circuit diagram of the design circuit; obtaining at least one conductive layer of the design circuit according to a layer of stacking structure information; selecting a transmission line model that meets the pin connection mode and at least one conductive layer from a plurality of transmission line models in an electrical simulation database; substituting the stacking structure information and a design rule into an equivalent circuit corresponding to the selected transmission line model; generating a corresponding relationship between a transmission line length and a characteristic parameter according to the equivalent circuit; obtaining a transmission line length corresponding to the characteristic parameter design target according to the corresponding relationship between the transmission line length and the characteristic parameter, and the transmission line length is used as a design restriction during the circuit layout. The step of constructing a three-dimensional model of the circuit layout includes: designing the circuit layout of the circuit according to the obtained transmission line length as a design restriction, and constructing a three-dimensional model of the circuit layout.

[0005] Another embodiment of the present invention provides a multi-chip parallel package design system. The multi-chip parallel package design system includes a model analysis, a three-dimensional model analysis, and an electrical simulation. The model analysis is used to: obtain a circuit diagram of a design circuit; and, based on the circuit diagram of the design circuit, perform a circuit layout. The three-dimensional model analysis is used to: construct a three-dimensional model of the circuit layout. The electrical simulation is used to: determine whether a characteristic parameter of the three-dimensional model meets a characteristic parameter design target; when the characteristic parameter does not meet the characteristic parameter design target, select a patent document that meets the circuit layout from a patent database; and, based on the patent document, optimize the design circuit. The model analysis is also used to: obtain a pin connection mode of the design circuit based on a circuit diagram of a design circuit; obtain at least one conductive layer of the design circuit based on a layer of stacking information; select a transmission line model that meets the pin connection mode and at least one conductive layer from a plurality of transmission line models in an electrical simulation database; substitute the stacking information and a design rule into the selected transmission line model to generate an equivalent circuit; generate a corresponding relationship between a transmission line length and a characteristic parameter based on the equivalent circuit; and obtain a transmission line length corresponding to a characteristic parameter design target based on the corresponding relationship between the transmission line length and the characteristic parameter, and use the transmission line length as a design restriction during line layout. The three-dimensional model analysis is also used to: perform line layout of the design circuit based on the obtained transmission line length as a design restriction, and construct a three-dimensional model of the line layout.

[0006] The embodiment of the present invention utilizes a packaging design method to import a transmission line model database and a patent database, and is applicable to multi-chip parallel packaging in horizontal and vertical directions.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a functional block diagram of a multi-chip package design system according to an embodiment of the present invention.

[0009] Figure 2 A schematic diagram showing a partial circuit diagram of a design circuit according to an embodiment of the present invention is shown.

[0010] Figure 3 Draw Figure 1 Schematic cross-sections of several transmission line models from the transmission line model database.

[0011] Figure 4 Draw the selection that matches Figure 1 A schematic diagram of an equivalent circuit of a pin connection mode and a transmission line model of at least one conductive layer.

[0012] Figure 5A partial cross-sectional view of a semiconductor package structure of a design circuit according to an embodiment of the present invention is shown.

[0013] Figure 6 Draw Figure 4 Schematic diagram of the insertion loss S21 parameter curve of the equivalent circuit.

[0014] Figure 7 Draw Figure 4 A schematic diagram of the corresponding relationship SR1 between a transmission line length and a characteristic parameter VL (voltage loss) of an equivalent circuit.

[0015] Figure 8 A partial front view of a three-dimensional model of a designed circuit constructed based on the acquired transmission line length and layer stacking structure information is shown.

[0016] Fig. 9 Draw Figure 1 A flow chart of a packaging design method for a multi-chip parallel packaging design system.

[0017] Fig.10 FIG. 4 is a schematic diagram illustrating a technology / efficiency / goal matrix according to an embodiment of the present invention.

[0018] Fig.11 Draw Figure 4 A schematic diagram of the corresponding relationship SR2 between a transmission line length and a characteristic parameter IL (insertion loss) of an equivalent circuit.

[0019] Fig.12 Draw Figure 4 Schematic diagram of the reflection loss S11 curve of the equivalent circuit.

[0020] Fig.13 Draw Figure 4 A schematic diagram of a corresponding relationship SR3 between a transmission line length and a characteristic parameter RL (reflection loss) of an equivalent circuit.

[0021] Fig.14 Draw Figure 8 Characteristic parameter Zo (characteristic impedance) diagram of the three-dimensional model.

[0022] Fig.15 FIG. 4 is a schematic diagram showing a technology / efficiency / goal matrix according to another embodiment of the present invention.

[0023] Fig.16 Draw Figure 8 A partial front view of the improved 3D model.

[0024]

Explanation of symbols

[0025] 100: Multi-chip parallel packaging design system

[0026] 110: Model Analysis

[0027] 120: 3D model analysis

[0028] 130:Electrical simulation

[0029] A, B: Components

[0030] A1, A2, B1, B2: Pins

[0031] C: Speed ​​of light

[0032] CF: Circuit diagram

[0033] CM: Pin connection mode

[0034] C P , C S :capacitance

[0035] C1, C2, C air :Capacitance value

[0036] DR: Design Rules

[0037] DK, ε r1 , δ r2 , δ eff : Dielectric constant

[0038] DF: loss tangent

[0039] d: Transmission line width

[0040] EC: Equivalent Circuit

[0041] EM: Transmission Line Model Database

[0042] EM1: Transmission Line Model

[0043] f0: input signal frequency

[0044] G: Ground pin

[0045] K(k1), (k'1): complete elliptic integral

[0046] h1, h2: thickness

[0047] h3, h4: distance

[0048] LM: Conductive layer

[0049] L SS :inductance

[0050] EM1a, EM1b, EM1c, EM1d, EM1e, EM1f, EM1g, EM1h: Transmission Line Model

[0051] LS:Layer structure information

[0052] M1: 3D Model

[0053] PD: Patent Database

[0054] PD1, PD1a, PD1b, PD1c, PD2, PD2a, PD2b, PD2c: Patent Documents

[0055] R S :resistance

[0056] R: Resistance of the transmission line

[0057] S: Signal line pin

[0058] S11: Reflection loss parameter curve

[0059] S21: Insertion loss parameter curve

[0060] SR1, SR2, SR3: Correspondence

[0061] S110~S194: Steps

[0062] t: Transmission line thickness

[0063] TL: Transmission line length

[0064] TM1, TM2: Matrix

[0065] VL, IL, RL, Zo: characteristic parameters

[0066] V L I , I.L. I :Characteristic parameter design target

[0067] w: Groove width

[0068] Z o :Characteristic impedance

[0069] Z L : Transmission line characteristic impedance

[0070] ΔZo: Design tolerance

[0071] ρ: Resistivity

[0072] Г: Reflection coefficient DETAILED DESCRIPTION

[0073] The embodiment of the present invention applies the packaging design method to a transmission line model database and a patent database, and is suitable for multi-chip integrated packaging in horizontal and vertical directions.

[0074] Please refer to Figures 1 to 8 , Figure 1FIG. 1 is a functional block diagram of a multi-chip package design system 100 according to an embodiment of the present invention. Figure 2 FIG. 4 is a schematic diagram showing a partial circuit diagram CF of a design circuit according to an embodiment of the present invention. Figure 3 Draw Figure 1 Schematic diagram of several transmission line models EM1 of the transmission line model database EM, Figure 4 Draw Selection Figure 1 A schematic diagram of an equivalent circuit EC of a transmission line model EM1c that complies with a pin connection mode CM and at least one conductive layer LM, Figure 5 A partial cross-sectional view of a semiconductor package structure of a design circuit according to an embodiment of the present invention is shown. Figure 6 Draw Figure 4 Schematic diagram of the insertion loss S21 parameter curve of the equivalent circuit EC, Figure 7 Draw Figure 4 The schematic diagram of the corresponding relationship SR1 between the transmission line length and the characteristic parameter VL (reflection loss) of the equivalent circuit EC is shown in FIG. Figure 8 A partial front view of a three-dimensional model M1 of a designed circuit constructed according to the obtained transmission line length TL and layer stacking structure information LS is shown.

[0075] like Figure 1 As shown, the multi-chip parallel package design system 100 includes a model analysis 110, a three-dimensional model analysis 120, an electrical simulation 130, a transmission line model database EM, layer stackup information LS, a design rule DR, and a patent database PD. The transmission line model database EM stores a plurality of transmission line models EM1. The patent database PD stores a plurality of patent documents PD1. In addition, the transmission line model database EM, the layer stackup information LS, and / or the design rule DR may be pre-stored in the multi-chip parallel package design system 100, for example, in a memory (not shown) or the model analysis 110 of the multi-chip parallel package design system 100. In addition, the model analysis 110, the three-dimensional model analysis 120, and / or the electrical simulation 130 are, for example, physical circuits formed by semiconductor process technology, such as semiconductor chips, semiconductor packages, etc. At least two of the model analysis 110 , the 3D model analysis 120 , and the electrical simulation 130 may be integrated into a single unit, or the model analysis 110 , the 3D model analysis 120 , and / or the electrical simulation 130 may be integrated into a controller or a processor.

[0076] The model analysis 110 is used to obtain the circuit diagram CF of the design circuit and perform circuit layout according to the circuit diagram CF of the design circuit. The three-dimensional model analysis 120 is used to construct a three-dimensional model M1 of the design circuit according to the circuit layout. The electrical simulation 130 is used to determine whether the characteristic parameters of the three-dimensional model M1 meet the characteristic parameter design target; when the characteristic parameters do not meet the characteristic parameter design target, select patent documents that meet the circuit layout from the patent database PD; and, based on the patent documents, optimize the design circuit.

[0077] Further, if Figure 1 As shown, the model analysis 110 is used to analyze the circuit diagram CF of a design circuit (for example, the circuit diagram CF is shown in FIG. Figure 2 ), obtain the pin connection mode of the design circuit; obtain at least one conductive layer LM according to a layer of stacking structure information LS (as shown in Table 1 below); from a plurality of transmission line models EM1 (for example, the transmission line model EM1 is shown in Figure 3 ), select a transmission line model EM1 that meets the pin connection mode CM and at least one conductive layer LM; substitute the stacking structure information LS and the design rule DR into the selected transmission line model EM1 to generate the corresponding equivalent circuit EC; based on the equivalent circuit EC, generate a corresponding relationship SR1 between the transmission line length and the characteristic parameter (for example, the corresponding relationship SR1 is shown in Figure 7 ); and, according to the corresponding relationship SR1 between the transmission line length and the characteristic parameter, obtaining the transmission line length TL corresponding to a characteristic parameter design target (for example, the transmission line length TL is shown in Figure 7 ), the transmission line length TL can be used as a design constraint for circuit layout. The three-dimensional model analysis 120 is used to perform circuit layout of the design circuit based on the obtained transmission line length TL as a design constraint, and construct a three-dimensional model M1 of the design circuit (for example, the three-dimensional model M1 is shown in FIG. Figure 8 ). The electrical simulation 130 is used to obtain the characteristic parameters of the three-dimensional model M1 to meet the characteristic parameter design goals; and when the characteristic parameters of the three-dimensional model M1 do not meet the characteristic parameter design goals, a technology / efficiency / target matrix is ​​used to filter out the patent document PD1 that meets the characteristic parameter design goals from the patent database PD, and the structure disclosed in the patent document PD1 is placed in the three-dimensional model M1 of the circuit layout. In this way, the multi-chip parallel packaging design system 100 filters out the patent documents that meet the characteristic parameter design goals from the patent database PD based on the circuit diagram information (if the characteristic parameters of the three-dimensional model M1 do not meet the characteristic parameter design goals). The patent document PD1 is, for example, a patent number, such as a patent number, a publication number, an application number, etc.

[0078] Please refer to Fig. 9 , which shows Figure 1 Flow chart of a package design method of a multi-chip parallel package design system 100.

[0079] In step S105, the model analysis 110 obtains the circuit diagram CF of the design circuit (such as Figure 2 shown).

[0080] Then, the model analysis 110 can perform circuit layout according to the circuit diagram of the designed circuit. The circuit layout, for example, includes the following steps S110 to S160.

[0081] In step S110, the model analysis 110 may be based on the circuit diagram CF (eg, Figure 2 In one embodiment, the model analysis 110 can analyze the circuit diagram CF to obtain the pin connection mode CM, or the pin connection mode CM can be manually input into the model analysis 110.

[0082] Specifically, if Figure 2 As shown, circuit diagram CF is a connection mode of component A and component B. Component A includes at least two pins A1 and A2, and component B includes at least two pins B1 and B2, wherein pin A1 is electrically connected to pin B1, and pin A2 is electrically connected to pin B2. Accordingly, the pin connection mode CM of component A and component B is a "2 to 2" connection mode. Component A and component B are, for example, chips. Component A and component B can be arranged horizontally or stacked vertically. In another embodiment, the number of components is not limited to two, and can also be three or more than three.

[0083] In step S120, the model analysis 110 obtains at least one conductive layer LM of the design circuit according to the layer stacking information LS. The layer stacking information LS displays information of each layer of the semiconductor package structure corresponding to the design circuit, such as layer thickness, material, and material parameters (such as conductivity and / or dielectric constant, loss tangent, etc.). In one embodiment, the model analysis 110 can analyze the layer stacking information LS to obtain at least one conductive layer LM, or at least one conductive layer LM can be manually input into the model analysis 110.

[0084] As shown in Table 1, the stacking structure information LS lists the thickness, material and conductivity of each conductive layer of the designed circuit and the thickness, material and material parameters (such as dielectric constant and conductivity) of each layer. From Table 1, the model analysis 110 obtains that the number of at least one conductive layer of the designed circuit is 2 layers.

[0085] Table 1 (Layer stacking structure information LS)

[0086]

[0087] In step S130, the model analysis 110 Figure 3 A transmission line model EM1 that meets the pin connection mode CM and at least one conductive layer LM is selected from a plurality of transmission line models EM1 in the transmission line model database EM.

[0088] like Figure 3 As shown, the transmission line model database EM includes at least one conductive layer (layers on the same horizontal level are the same conductive layer), and one of the at least one conductive layer includes at least one signal line pin S and / or at least one ground line pin G (optional). For example, the number LM of at least one conductive layer of the transmission line model EM1a is 2, and the pin connection mode CM is 1 to 1; the number LM of at least one conductive layer of the transmission line model EM1b is 3, and the pin connection mode CM is 1 to 1; the number LM of at least one conductive layer of the transmission line model EM1c is 1, and the pin connection mode CM is 1 to 1; the number LM of at least one conductive layer of the transmission line model EM1d is 2, and the pin connection mode CM is 1 to 1; the number LM of at least one conductive layer of the transmission line model EM1e is 2, and the pin connection mode CM is 2 to 2; the number LM of at least one conductive layer of the transmission line model EM1f is 3, and the pin connection mode CM is 2 to 2; the number LM of at least one conductive layer of the transmission line model EM1g is 1, and the pin connection mode CM is 2 to 2; the number LM of at least one conductive layer of the transmission line model EM1h is 2, and the pin connection mode CM is 2 to 2.

[0089] The model analysis 110 can obtain information that the pin connection mode CM is 2 to 2 and the number LM of at least one conductive layer is 2 from the first two steps S110 to S120, and perform simulation using two connected transmission line models EM1e or EM1h.

[0090] In step S140, the model analysis 110 substitutes the stacking structure information LS and the design rule DR into the selected transmission line model EM1e to generate Figure 4 The equivalent circuit EC is shown.

[0091] As shown in Table 2 below, the design rule DR shows the design rules (or design restrictions) such as the transmission line diameter, transmission line distance, transmission line thickness, pad spacing, conductive hole width, and dielectric layer back of the semiconductor package structure corresponding to the design circuit. Figure 5 As shown, the symbols P1 to P2 in Table 2 are indicated at Figure 5 Design circuit semiconductor packaging structure.

[0092] Table 2 (Design Rules DR)

[0093]

[0094] like Figure 4 As shown, the equivalent circuit EC includes at least one impedance, such as a capacitor C P , C S 、Inductance L S and / or resistor R S Capacitor C P , CS 、Inductance L S and / or resistor R S The value of may depend on the specification of the design rule DR, and is not limited in the embodiment of the present invention. Figure 4 Taking a 1-to-1 equivalent circuit as an example, two 1-to-1 equivalent circuits can be connected into a 2-to-2 equivalent circuit. Figure 4 Capacitance C P , C S 、Inductance L S And the resistor R S It can be obtained according to the following formulas (A) to (D2).

[0095]

[0096]

[0097]

[0098] C cpw =C1+C2+C air …(A3)

[0099]

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113] R s =R / 2…(C)

[0114]

[0115]

[0116]

[0117] L=C s *Z o 2 …(D2)

[0118] In the formula, Figure 3 The transmission line model EM1c is shown in Figure 1. K(k1) and K(k'1) are complete elliptic integrals, h1 is the thickness of the lower dielectric layer, and ε r1 is the dielectric constant of the lower dielectric layer, h2 is the thickness of the upper dielectric layer, ε r2 is the dielectric constant of the upper dielectric layer, length is the length of the transmission line, ρ is the resistivity of the transmission line material, t is the thickness of the transmission line, R is the resistance of the transmission line, and C is the speed of light 3*10 8 m / s, h3 is Figure 3 The distance between the conductor above EM1c (as a shield, not shown) and the coplanar waveguide structure, h4 is Figure 3 The distance between the conductor (as a shield, not shown) below the transmission line model EM1c and the coplanar waveguide structure is, d is the transmission line width, and w is the trench width.

[0119] Calculate the equivalent dielectric constant ε eff And characteristic impedance Z o Conformal mapping technology is used. Therefore, it is assumed that the conductor thickness t = 0 and the magnetic field wall appears along the dielectric boundary condition containing the groove. Assuming that the electric field exists in some areas, the coplanar waveguide structure can be broken down into three blocks for analysis, separated by dielectric materials, including the first dielectric constant ε r1 The coplanar waveguide has a second dielectric constant ε r2 The coplanar waveguide and the vacuum material above and below (ε r =1), the three blocks above each form capacitance values ​​C1, C2 and C air , the total capacitance value of the coplanar waveguide structure is equal to the sum of the capacitance values ​​of the three blocks.

[0120] In step S150, please also refer to Figures 4 to 6 As shown, in this step, the model analysis 110 generates a corresponding relationship SR1 between the transmission line length and the characteristic parameter according to the equivalent circuit EC.

[0121] In this embodiment, the characteristic parameter VL is described by taking “voltage amplitude loss” as an example.

[0122] For example, the model analysis 110 can obtain the characteristic parameter VL (voltage loss) of the series connection of different numbers n of equivalent circuits EC to establish the corresponding relationship SR1. n is a positive integer equal to or greater than 1, and the embodiment of the present invention does not limit the upper limit of n. For example, for an equivalent circuit EC (n=1), the model analysis 110 can obtain the insertion loss of an equivalent circuit EC (shown in FIG. Figure 6 ) and obtain the parameter value of the parameter curve S21 corresponding to an input signal frequency f0 (e.g., 2.4 GHz) from the S21 parameter curve (i.e., S21(f0), and obtain the corresponding characteristic parameter VL according to the following formula (1). Based on this principle, the model analysis 110 can obtain the characteristic parameter VL of n equivalent circuits EC connected in series (one corresponding characteristic parameter VL can be obtained for each additional equivalent circuit EC connected in series), and thus construct the following Figure 7 The corresponding relationship between the transmission line length and the characteristic parameter VL (voltage loss) is shown in SR1. Figure 7 As shown, the horizontal axis is the length of the transmission line after n equivalent circuits EC are connected in series, and the unit is millimeter (mm).

[0123]

[0124] In step S160, the model analysis 110 can obtain a corresponding characteristic parameter design target VL according to the corresponding relationship SR1. I The transmission line length TL can be used as a design restriction during line layout. Figure 7 As shown, the target VL is designed with characteristic parameters I For example, the allowable voltage loss is from 1V to 0.85V, and the corresponding transmission line length TL of 0.85V is 8 millimeters (mm). In other words, the transmission line length of the conductive layer of the designed circuit should not exceed 8mm to avoid the voltage at the end of the transmission line being lower than 0.85V.

[0125] In step S170, if Figure 8 As shown, after obtaining the transmission line length TL, the 3D model analysis 120 can perform circuit layout of the design circuit according to the transmission line length TL and the stacking structure information LS, and construct a 3D model M1 of the design circuit (ie, a 3D model of the semiconductor package structure).

[0126] In step S180, the electrical simulation 130 determines whether the characteristic parameter VL of the three-dimensional model M1 satisfies the characteristic parameter design target VL IFor example, after constructing the three-dimensional model M1, the electrical simulation 130 may use a suitable analysis technology to analyze the three-dimensional model M1 to obtain the characteristic parameter VL of the three-dimensional model M1. The aforementioned analysis technology is, for example, electronic design automation (EDA), such as EDA software developed by Ansys or Cadence.

[0127] If the characteristic parameter VL meets the characteristic parameter design target VL I , then the process ends. If the characteristic parameter VL does not meet the characteristic parameter design target VL I , the process enters step S190, searching for a solution (improvement) from the transmission line model database EM (patent document).

[0128] In step S190, please refer to Fig.10 , which illustrates a schematic diagram of a technology / efficiency / target matrix TM1 according to an embodiment of the present invention. The electrical simulation 130 uses a technology / efficiency / target matrix to select from the patent database PD the characteristic parameters of the three-dimensional model M1 that meet the characteristic parameter design target VL I "Patent document.

[0129] Then, the circuit design can be optimized based on the patent documents.

[0130] For example, if Fig.10 As shown, the technology / efficacy / goal matrix TM1 lists the relationship between technology, efficacy, design goals and corresponding patent documents (for example, patent numbers). From the technology / efficacy / goal matrix TM1, it can be seen that the reduction of voltage loss is related to the adjustment of conductor loss and dielectric loss, among which the conductor loss is related to the transmission line width, transmission line length and transmission line thickness, and the dielectric loss is related to the dielectric layer thickness, dielectric constant DK and loss tangent DF of the dielectric layer. The patent document related to this information is patent document PD1a. According to the content of patent document PD1a, let the "characteristic parameters of the three-dimensional model M1 meet the characteristic parameter design target VL I "A ground island structure can be used.

[0131] In step S192, the three-dimensional model analysis 120 constructs a corresponding three-dimensional model M1. The multi-chip parallel package design method places the structure disclosed in the patent document in the three-dimensional model of the circuit layout. For example, the three-dimensional model analysis 120 updates (or modifies) the three-dimensional model M1 according to the improved technical solution in the selected patent document. For specific methods of updating (or modifying) the three-dimensional model M1, please refer to the following Fig.16 and its related description.

[0132] In step S194, the electrical simulation 130 determines whether the characteristic parameter VL (voltage loss) of the updated (or modified) three-dimensional model M1 meets the characteristic parameter design target VL I For example, after the three-dimensional model M1 is updated (or modified), the electrical simulation 130 may use, for example, the aforementioned EDA analysis technology to obtain the characteristic parameter VL of the updated (or modified) three-dimensional model M1.

[0133] If the updated (or modified) characteristic parameter VL of the three-dimensional model M1 meets the characteristic parameter design target VL I , then the process ends. If the characteristic parameters of the updated three-dimensional model M1 do not meet the characteristic parameter design target VL I , the process returns to step S190 and searches for a solution from patent technologies again.

[0134] The following is a flow chart of a second packaging design method of the multi-chip parallel packaging design system 100. The packaging design method of this embodiment includes a similar process to the above process, and the differences between the two steps are described below, and similar or identical steps are not repeated here.

[0135] In step S150, please refer to Fig.11 , which shows Figure 4 The model analysis 110 generates a corresponding relationship SR2 between the length of a transmission line and the characteristic parameter according to the equivalent circuit EC.

[0136] In this embodiment, the characteristic parameter IL is described by taking “insertion loss” as an example.

[0137] For example, the model analysis 110 can obtain the insertion loss IL of the equivalent circuit EC with different series connection numbers n to establish the corresponding relationship SR2. n is a positive integer equal to or greater than 1, and the embodiment of the present invention does not limit the upper limit of n. For an equivalent circuit EC (n=1), the model analysis 110 can obtain an insertion loss S21 parameter curve of an equivalent circuit EC (the S21 parameter curve is shown in Figure 6 ), and obtain the parameter value of the parameter curve S21 corresponding to the input signal frequency f0 (for example, 2.4 GHz) from the parameter curve S21 (ie, S21(f0)), and this parameter value constructs Fig.11 According to this principle, the model analysis 110 can obtain the characteristic parameter IL (insertion loss) of n equivalent circuits EC connected in series (each more equivalent circuit EC can obtain a corresponding characteristic parameter IL), and construct the following Fig.11 The corresponding relationship between the transmission line length and the characteristic parameter IL is shown in SR2. Fig.11As shown, the horizontal axis is the length of the transmission line after n equivalent circuits EC are connected in series, and the unit is millimeter (mm).

[0138] In step S160, the model analysis 110 can obtain a corresponding characteristic parameter design target IL according to the corresponding relationship SR2. I For example, if Fig.11 As shown, the target IL is designed with characteristic parameters I For example, if the allowable insertion loss is -1.41dB, the transmission line length TL corresponding to the insertion loss of -1.41dB is 8mm. In other words, the transmission line length of the conductive layer of the designed circuit should not exceed 8mm to avoid the allowable insertion loss of the transmission line being lower than -1.41dB.

[0139] In addition, the model analysis 110 can use the following formula (2) to obtain the characteristic parameter design target IL I In formula (2), V out Indicates the output voltage value, while V in Indicates the input voltage value. Input voltage value V in Take 1V as an example, and the output voltage value V out Taking 0.85V as an example, the target IL is designed based on the characteristic parameters obtained. I It is -1.41dB.

[0140]

[0141] In step S170, if Figure 8 As shown, after obtaining the transmission line length TL, the 3D model analysis 120 can construct a 3D model M1 of the design circuit (ie, a semiconductor structure package 3D model) according to the obtained transmission line length TL and the stacking structure information LS.

[0142] In step S180, the electrical simulation 130 determines whether the characteristic parameter IL (insertion loss) of the three-dimensional model M1 satisfies the characteristic parameter design target IL I For example, after constructing the three-dimensional model M1, the electrical simulation 130 may use appropriate analysis technology to analyze the three-dimensional model M1 to obtain the characteristic parameter IL of the three-dimensional model M1. The aforementioned analysis technology is, for example, electronic design automation, such as EDA software developed by Ansys or Cadence.

[0143] If the characteristic parameter IL meets the characteristic parameter design target IL I If the characteristic parameter IL does not meet the characteristic parameter design target IL I , the process enters step S190, searching for a solution from the transmission line model database EM (patent document).

[0144] In step S190, the electrical simulation 130 uses a technology / efficiency / target matrix to select from the patent database PD the characteristics parameters of the three-dimensional model M1 that meet the characteristic parameter design target IL I "The method of obtaining patent documents is similar to Fig.10 The description will not be repeated here.

[0145] In step S192, the 3D model analysis 120 constructs the corresponding 3D model M1. The multi-chip parallel package design method places the structure disclosed in the patent document in the 3D model of the circuit layout. For example, the 3D model analysis 120 updates (or modifies) the 3D model M1 according to the improved technical solution in the selected patent document.

[0146] In step S194, the electrical simulation 130 determines whether the characteristic parameter IL (insertion loss) of the updated (or modified) three-dimensional model M1 meets the characteristic parameter design target IL I For example, after the three-dimensional model M1 is updated, the electrical simulation 130 may use, for example, the aforementioned EDA analysis technology to obtain the characteristic parameter IL of the updated three-dimensional model M1.

[0147] If the updated characteristic parameter IL of the three-dimensional model M1 meets the characteristic parameter design target IL I , then the process ends. If the characteristic parameters of the updated three-dimensional model M1 do not meet the characteristic parameter design target IL I , the process returns to step S190 and searches for a solution from patent technologies again.

[0148] The following is a flow chart of a third package design method of the multi-chip parallel package design system 100. The package design method of this embodiment includes a similar process to the above process, and the differences between the two steps are described below, and similar or identical steps are not repeated here.

[0149] In step S150, please refer to Figures 12-13 , Fig.12 Draw Figure 4 Schematic diagram of the S11 parameter curve of the reflection loss of the equivalent circuit EC, and Fig.13 Draw Figure 4 The model analysis 110 generates a corresponding relationship SR3 between the length of a transmission line and the characteristic parameter RL (reflection loss) according to the equivalent circuit EC.

[0150] In this embodiment, the characteristic parameter RL is described by taking “reflection loss” as an example.

[0151] For example, the model analysis 110 can obtain the reflection loss of different numbers n of equivalent circuits EC connected in series to establish the corresponding relationship SR3. n is a positive integer equal to or greater than 1. For an equivalent circuit EC (n=1), the model analysis 110 can obtain the S11 parameter curve of the reflection loss of the equivalent circuit EC (the S11 parameter curve is shown in Fig.12 ), and obtain the parameter value of the parameter curve S11 corresponding to the input signal frequency f0 (for example, 2.4 GHz) from the S11 parameter curve (ie, S11(f0)), and this parameter value constructs Fig.13 According to this principle, the model analysis 110 can obtain the characteristic parameter RL (reflection loss) of n equivalent circuits EC connected in series (a corresponding characteristic parameter RL can be obtained for each additional equivalent circuit EC connected in series), and thus construct the following Fig.13 The corresponding relationship between the transmission line length and the characteristic parameter RL is shown in SR3. Fig.13 As shown, the horizontal axis is the length of the transmission line after n equivalent circuits EC are connected in series, and the unit is millimeter (mm). Fig.13 The vertical axis represents the reflection loss.

[0152] In step S160, the model analysis 110 can obtain a corresponding characteristic parameter design target RL according to the corresponding relationship SR3. I For example, if Fig.13 As shown, the target RL is designed with characteristic parameters I For example, if the allowable reflection loss is -25dB, the transmission line length TL corresponding to -25dB is 8mm. In other words, the length of the transmission line of the conductive layer of the designed circuit should not exceed 8mm to avoid the reflection loss of the transmission line being greater than -25dB.

[0153] The electrical simulation 130 can use the following formulas (3A) to (3C) to obtain the characteristic parameter RL (reflection loss). O represents the characteristic impedance of the signal source (e.g., component A), Z L represents the characteristic impedance of the transmission line, Г represents the reflection coefficient, and ΔZo represents the design tolerance.

[0154] RL=-20*log|Г|....(3A)

[0155] Г=(Z L -Z O ) / (Z L +Z O )…(3B)

[0156] Z L =Zo±ΔZo…(3C)

[0157] The signal source characteristic impedance ZO For example, if the design tolerance ΔZo is 5% for 50 ohms (Ω), the calculated characteristic parameter RL (reflection loss) is between -32.3dB and -35.3dB.

[0158] In step S170, if Figure 8 As shown, after obtaining the transmission line length TL, the 3D model analysis 120 can construct a 3D model M1 of the design circuit (ie, a 3D model of the semiconductor package structure) according to the obtained transmission line length TL and the stacking structure information LS.

[0159] In step S180, the electrical simulation 130 determines whether the characteristic parameter Zo (characteristic impedance) of the three-dimensional model M1 satisfies the characteristic parameter design target Z O ±ΔZo. For example, after constructing the three-dimensional model M1, the electrical simulation 130 may use a suitable analysis technique to analyze the three-dimensional model M1 to obtain the characteristic parameter Z of the three-dimensional model M1. O The aforementioned analysis technology is, for example, electronic design automation, such as EDA software developed by Ansys or Cadence.

[0160] Please refer to Fig.14 , which shows Figure 8 Schematic diagram of the characteristic parameters of the three-dimensional model M1. As can be seen from the figure, the maximum characteristic parameter Zo(max)(112Ω) of the three-dimensional model M1 is greater than 110Ω. That is, the characteristic parameter Zo exceeds the characteristic parameter design target Z O ±ΔZo. (Between 90Ω and 110Ω). The characteristic parameter design target Z of a transmission line O is 50Ω, and the transmission line of the embodiment of the present invention is a pair, so the characteristic parameter design target Z O is 100Ω. After considering the 10% tolerance, the characteristic parameter design target Z O Between 90Ω and 110Ω.

[0161] If the characteristic parameter Zo (characteristic impedance) meets the characteristic parameter design target Z O ±10% range, the process ends. If the characteristic parameter Zo (characteristic impedance) exceeds the characteristic parameter design target Z O Within the range of ±10%, the process enters step S190 to search for a solution from the transmission line model database EM (patent document).

[0162] In step S190, please refer to Fig.15, which is a schematic diagram of a technology / efficiency / target matrix TM2 according to another embodiment of the present invention. The electrical simulation 130 uses the technology / efficiency / target matrix TM2 to select from the patent database PD the three-dimensional model M1 whose characteristic parameter Zo (characteristic impedance) falls within the characteristic parameter design target Z. O ±ΔZo range” patent document.

[0163] For example, if Fig.15 As shown, the technology / efficiency / goal matrix TM2 lists the relationship between technology, efficacy, design goals and corresponding patent documents (for example, patent numbers). From the technology / efficiency / goal matrix TM2, it can be seen that the adjustment of capacitance and inductance values ​​is related to reducing reflection loss, among which the capacitance value is related to the transmission line distance, thickness and dielectric constant (DK) of the dielectric layer, and the inductance value is related to the transmission line width, length and thickness. The patent document related to this information is patent document PD2a. According to the content of patent document PD2a, let "the characteristic parameter Zo (max) of the three-dimensional model M1 fall within the characteristic parameter design target Z O ±ΔZo range” can adopt a ground island structure.

[0164] In step S192, please refer to Fig.16 , which shows Figure 8 The three-dimensional model analysis 120 constructs the corresponding three-dimensional model M1. The multi-chip parallel package design method places the structure disclosed in the patent document in the three-dimensional model of the circuit layout. For example, the three-dimensional model analysis 120 places the improved structure of the ground island structure M1G in the previous three-dimensional model M1.

[0165] In step S194, the electrical simulation 130 determines whether the characteristic parameter Zo (characteristic impedance) of the updated (or modified) three-dimensional model M1 satisfies the characteristic parameter design target Z O ±ΔZo. For example, after the three-dimensional model M1 is updated (or modified), the electrical simulation 130 may use, for example, EDA analysis technology to obtain the maximum characteristic impedance Zo(max) of the updated three-dimensional model M1.

[0166] If the characteristic parameter Zo of the updated (or modified) three-dimensional model M1 is within the characteristic parameter design target Z O If the characteristic parameter Zo of the updated three-dimensional model M1 exceeds the characteristic parameter design target Z O ±ΔZo, the process returns to step S190 and searches for a solution from patented technologies again.

[0167] In summary, although the present invention has been described above with reference to the embodiments, it is not intended to limit the present invention. A person skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A multi-chip parallel package design method, comprising: Obtain a circuit diagram of the designed circuit; Performing circuit layout according to the circuit diagram of the designed circuit; constructing a three-dimensional model of the circuit layout; Determining whether the characteristic parameters of the three-dimensional model meet the characteristic parameter design goals; When the characteristic parameter does not meet the characteristic parameter design target, a patent document meeting the circuit layout is screened out from the patent database; as well as According to the patent document, the design circuit is optimized; The step of performing the circuit layout according to the circuit diagram of the designed circuit includes: According to the circuit diagram of the designed circuit, obtaining a pin connection mode of the designed circuit; Obtaining at least one conductive layer of the designed circuit according to the layer stacking structure information; Selecting the transmission line model that matches the pin connection mode and the at least one conductive layer from a plurality of transmission line models in a transmission line model database; Substituting the stacking structure information and design rules into the selected transmission line model to generate an equivalent circuit; According to the equivalent circuit, a corresponding relationship between the transmission line length and the characteristic parameter is generated; According to the correspondence between the transmission line length and the characteristic parameter, the transmission line length corresponding to the characteristic parameter design target is obtained, and the transmission line length is used as the design restriction during the line layout; and The step of constructing the three-dimensional model of the circuit layout includes: The circuit layout of the design circuit is performed according to the obtained transmission line length as a design constraint, and the three-dimensional model of the circuit layout is constructed.

2. The multi-chip parallel package design method as claimed in claim 1, wherein the step of selecting the patent document that matches the circuit layout from the patent database comprises: When the characteristic parameter does not meet the characteristic parameter design target, the technology / efficiency / target matrix is ​​used to screen out the patent document that meets the characteristic parameter design target from the patent database, and the structure disclosed in the patent document is placed in the three-dimensional model of the circuit layout.

3. The multi-chip parallel package design method as claimed in claim 1, wherein the characteristic parameter VL is voltage loss; the multi-chip parallel package design method further comprises: The voltage loss is obtained according to the following formula (1): Where f0 represents the input signal frequency and S21 represents the insertion loss of the S parameter.

4. The multi-chip parallel package design method as claimed in claim 3, wherein the multi-chip parallel package design method further comprises: The voltage loss of the equivalent circuits with different numbers of series connection is obtained to establish a corresponding relationship between the transmission line length and the voltage loss.

5. The multi-chip parallel package design method as claimed in claim 1, wherein the characteristic parameter is insertion loss; the multi-chip parallel package design method further comprises: According to the following formula (2), the characteristic parameter design target IL is obtained: I ; ) Among them, V out Indicates the output voltage value, while V in Indicates the input voltage value.

6. The multi-chip parallel package design method as claimed in claim 5, wherein the multi-chip parallel package design method further comprises: The insertion loss of the equivalent circuits with different numbers of series connection is obtained to establish a corresponding relationship between the transmission line length and the insertion loss.

7. The multi-chip parallel package design method as claimed in claim 1, wherein the characteristic parameter is reflection loss; the multi-chip parallel package design method further comprises: The characteristic parameter design target RL is obtained according to the following formula; RL = -20*log|Г|; Among them, the reflection coefficient Г=(Z L -Z o ) / (Z L +Z o ), where Z L is the characteristic impedance of the transmission line, Z o is the characteristic impedance of the signal source.

8. The multi-chip parallel package design method as claimed in claim 7, wherein the multi-chip parallel package design method further comprises: The reflection loss after different numbers of the equivalent circuits are connected in series is obtained to establish a corresponding relationship between the transmission line length and the reflection loss.

9. A multi-chip parallel package design system, comprising: Model analysis to: Obtain a circuit diagram of the designed circuit; and Performing circuit layout according to the circuit diagram of the designed circuit; 3D model analysis for: constructing a three-dimensional model of the circuit layout; Electrical simulation for: Determining whether the characteristic parameters of the three-dimensional model meet the characteristic parameter design goals; When the characteristic parameter does not meet the characteristic parameter design target, the patent document meeting the characteristic parameter design target is screened out from the patent database; and According to the patent document, the design circuit is optimized; Among other things, the model analysis is also used to: According to the circuit diagram of the designed circuit, a pin connection mode of the designed circuit is obtained; Obtaining at least one conductive layer of the designed circuit according to the layer stacking structure information; Selecting the transmission line model that matches the pin connection mode and the at least one conductive layer from a plurality of transmission line models in the electrical simulation database; Substituting the stacking structure information and the design rules into the selected transmission line model to generate an equivalent circuit; According to the equivalent circuit, a corresponding relationship between the transmission line length and the characteristic parameter is generated; and According to the correspondence between the transmission line length and the characteristic parameter, the transmission line length corresponding to the characteristic parameter design target is obtained, and the transmission line length is used as the design restriction during the line layout; Among them, the three-dimensional model analysis is also used to: The circuit layout of the design circuit is performed according to the obtained transmission line length as a design constraint, and the three-dimensional model of the circuit layout is constructed.

10. The multi-chip package design system as claimed in claim 9, wherein the electrical simulation is further used for: When the characteristic parameter does not meet the characteristic parameter design target, the technology / efficiency / target matrix is ​​used to screen out the patent document that meets the characteristic impedance target from the patent database, and the structure disclosed in the patent document is placed in the three-dimensional model of the circuit layout.

11. The multi-chip parallel package design system as claimed in claim 9, wherein the characteristic parameter VL is voltage loss; and the model analysis is further used for: The voltage loss is obtained according to the following formula (1): in, f0 represents the input signal frequency, and S21 represents the insertion loss of the S parameter.

12. The multi-chip package design system as claimed in claim 11, wherein the model analysis is further used for: The voltage loss after different numbers of the equivalent circuits are connected in series is obtained to establish a corresponding relationship between the transmission line length and the voltage loss.

13. The multi-chip parallel package design system as claimed in claim 9, wherein the characteristic parameter is insertion loss; and the model analysis is further used for: According to the following formula (2), the characteristic parameter design target IL is obtained: I ; in, V out Indicates the output voltage value, while V in Indicates the input voltage value.

14. The multi-chip package design system as claimed in claim 13, wherein the model analysis is further used for: The insertion loss of the equivalent circuits with different numbers of series connections is obtained to establish a corresponding relationship between the transmission line length and the insertion loss.

15. The multi-chip parallel package design system as claimed in claim 9, wherein the characteristic parameter is reflection loss; and the model analysis is further used for: The characteristic parameter design target RL is obtained according to the following formula; RL = -20*log|Г|; in, Reflection coefficient Γ=(Z L -Z o ) / (Z L +Z o ), where Z L is the characteristic impedance of the transmission line, Z o is the characteristic impedance of the signal source.

16. The multi-chip package design system as claimed in claim 15, wherein the model analysis is further used for: The reflection loss of the equivalent circuits with different numbers of series connections is obtained to establish a corresponding relationship between the transmission line length and the reflection loss.

Images