Integrated circuit layout optimization method and device, electronic equipment and storage medium

Abstract

The invention discloses an integrated circuit layout optimization method and device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the steps: determining the initial positions of a plurality of units in each line network; determining movement constraint conditions of the plurality of units in the bounding box of the corresponding net; determining moving areas of the units in the corresponding bounding boxes according to the initial positions and moving constraint conditions; dividing each line net into a plurality of sub-line nets; solving target positions of a plurality of units by taking the shortest line length as a target according to each sub-line net and the corresponding moving area; and moving the plurality of units from the initial position to the corresponding target position. According to the method, the moving area is determined according to the initial position and the moving constraint condition of the unit, the shortest line length is solved in the moving area, the initial layout of the unit is fully considered, and the problem that the quality of a final layout scheme is greatly reduced due to the fact that the search space is too small can be solved; and the calculation burden of solving the shortest line length can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit layout optimization method, device, electronic device and storage medium. Background Art

[0002] In the physical design process, placement is to determine the position and direction of all circuit components in a plane so that the optimization goal can be achieved under the constraints. The constraints generally require that there is no overlap between components, that there is a certain spacing between components, and that component congestion is avoided. The optimization goal requires minimizing the line length and reducing signal transmission delay.

[0003] Placement refinement refers to a method of performing more refined optimization on an existing initial layout. It can further optimize circuit performance indicators and improve layout quality. However, the prior art does not consider the initial layout of circuit components, resulting in poor quality of the final layout solution. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide an integrated circuit layout optimization method, device, electronic device and storage medium to improve the layout quality of the integrated circuit.

[0005] To achieve the above objective, an embodiment of the present application provides an integrated circuit layout optimization method in one aspect, the method comprising the following steps:

[0006] Determine the initial positions of several units in each network;

[0007] determining movement constraints of a plurality of said units within a bounding box corresponding to said wire mesh;

[0008] Determining a moving area of ​​a plurality of the units within the corresponding bounding box according to the initial position and the moving constraint condition;

[0009] Dividing each of the wire nets into a plurality of sub-wire nets;

[0010] Solving the target positions of the plurality of the units according to the respective sub-line networks and the corresponding moving areas with the shortest line length as the goal;

[0011] A plurality of the units are moved from the initial positions to corresponding target positions.

[0012] In some embodiments, determining the movement areas of the plurality of units within the corresponding bounding box according to the initial positions and the movement constraint conditions comprises the following steps:

[0013] Determine the boundary distance between each of the units and the corresponding boundary box according to the initial position;

[0014] The forces acting on each of the units in four directions are obtained by fitting using Hooke's law, the boundary distance and the movement constraint condition; wherein the four directions are movable directions of the units, and the four directions are respectively the positive and negative directions of each of the units in the horizontal direction and the positive and negative directions in the vertical direction;

[0015] Calculating a corresponding optimization potential coefficient according to the density of each of the cells within each of the bounding boxes;

[0016] Performing weighted summation of the forces in the four directions corresponding to each of the units and the optimization potential coefficient to obtain a resultant force corresponding to each of the units;

[0017] The movement area corresponding to the unit is determined according to the resultant force.

[0018] In some embodiments, the step of calculating the corresponding optimization potential coefficient according to the density of each of the cells in each of the bounding boxes comprises the following steps:

[0019] Calculate the optimization potential coefficient corresponding to each of the bounding boxes according to a density calculation formula;

[0020] The density calculation formula is:

[0021]

[0022] Among them, Density n represents the density of each of the cells within the bounding box of the nth mesh; w c represents the width of the cth unit; h represents the height of each unit; W n represents the width of the bounding box; H n Indicates the height of the bounding box; Cell n Represents each of the units within the nth bounding box; 1-Density n represents the optimization potential coefficient;

[0023] The step of performing weighted summation of the forces in the four directions corresponding to each of the units and the optimization potential coefficient to obtain the resultant force corresponding to each of the units comprises the following steps:

[0024] Calculating the weighted forces in the four directions according to the optimization potential coefficient and the normalized distance of the boundary distance;

[0025] The calculation formula of the weighted force is:

[0026]

[0027] in, represents the weighted force of the nth wire mesh on the ith unit; dir represents the direction, dir includes the four directions; k represents the coefficient of Hooke's law; Represents the normalized distance; 1-Density n represents the optimization potential coefficient;

[0028] Summing each of the weighted forces in the corresponding directions to obtain the resultant forces in the four directions;

[0029] The calculation formula of the resultant force is:

[0030]

[0031] in, Represents the resultant force acting on the i-th element in the dir direction.

[0032] In some embodiments, solving the target positions of the plurality of the units based on the respective sub-line networks and the corresponding moving areas with the shortest line length as the target comprises the following steps:

[0033] Determining the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net;

[0034] Determine a sub-movement area of ​​the sub-line network according to the position of the center of gravity and the corresponding movement area;

[0035] Taking the shortest line length as the goal, solving the sum of the first half perimeter line length between each of the centers of gravity and the second half perimeter line length of each of the sub-line nets in the corresponding sub-movement area;

[0036] The position of each of the units when the sum of the first half perimeter line length and the second half perimeter line length reaches a minimum value is determined as the target position.

[0037] In some embodiments, determining the geometric center of the connecting pin in each of the sub-nets as the center of gravity of the corresponding sub-net comprises the following steps:

[0038] Determine the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net according to the center of gravity coordinate calculation formula;

[0039] The barycenter coordinate calculation formula is:

[0040]

[0041] Wherein, |C| represents the number of units in set C; Denotes the center of gravity G i The X coordinate ofc represents the X coordinate of the cth said unit; Denotes the center of gravity G i Y coordinate of c represents the Y coordinate of the cth said unit; Indicates that in the sub-line network S i The unit in .

[0042] In some embodiments, determining movement constraints of the plurality of the units within a bounding box corresponding to the wire mesh comprises the following steps:

[0043] Determining the movement constraints of the plurality of units within the corresponding bounding box includes the following constraints:

[0044] Each of the units can be continuously moved in the X direction within the corresponding bounding box, and each of the units moves at least one unit when moving in the Y direction within the corresponding bounding box;

[0045] The X direction and the Y direction are perpendicular to each other;

[0046] The length of the unit is greater than or equal to the length of each of the units in the Y direction;

[0047] The difference in absolute value of the coordinate values ​​in the X direction between any two units in the same bounding box is greater than a preset distance threshold;

[0048] The difference in absolute value of the coordinate values ​​in the Y direction between any two of the units in the same bounding box is greater than one unit.

[0049] In some embodiments, dividing each of the wire nets into a plurality of sub-wire nets comprises the following steps:

[0050] The line net whose number of the cells in the boundary box reaches a preset division threshold is divided into a plurality of the sub-line nets.

[0051] To achieve the above-mentioned purpose, another aspect of the embodiment of the present application provides an integrated circuit layout optimization device, the device comprising:

[0052] An initial position determination module is used to determine the initial positions of several units in each network;

[0053] A constraint condition determination module, used to determine movement constraint conditions of a plurality of said units within a boundary box corresponding to said wire mesh;

[0054] A moving area determination module, used to determine the moving areas of a plurality of the units within the corresponding boundary box according to the initial positions and the moving constraint conditions;

[0055] A wire net division module, used for dividing each of the wire nets into a plurality of sub-wire nets;

[0056] A target position solving module, used for solving the target positions of a plurality of the units according to each of the sub-line networks and the corresponding moving areas with the shortest line length as the target;

[0057] The layout optimization module moves a plurality of the units from the initial positions to corresponding target positions.

[0058] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above method when executing the computer program.

[0059] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processor.

[0060] The embodiments of the present application include at least the following beneficial effects:

[0061] The present application can determine the initial positions of several units in each wire mesh; determine the movement constraints of several units within the bounding box of the corresponding wire mesh; determine the movement area of ​​several units within the corresponding bounding box according to the initial position and the movement constraints; divide each wire mesh into multiple sub-wire meshes; solve the target positions of several units with the shortest line length as the goal according to each sub-wire mesh and the corresponding movement area; move several units from the initial position to the corresponding target position. The present application determines the movement area according to the initial position and movement constraints of the unit, and then solves the shortest line length in the movement area, which fully considers the initial layout of the unit, and can reduce the problem of a significant decrease in the quality of the final layout solution due to an excessively small search space; and the present application can divide each wire mesh into multiple sub-wire meshes based on a full analysis of the initial layout, realizes reasonable pruning of the movement area, and can reduce the computational burden of solving the shortest line length. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0063] Figure 1 A schematic diagram of a flow chart of an integrated circuit layout optimization method provided in an embodiment of the present application;

[0064] Figure 2 An example diagram of a bounding box and a unit of a wire mesh provided in an embodiment of the present application;

[0065] Figure 3 An example diagram of possible locations of various units in different wire nets provided in the embodiments of the present application;

[0066] Figure 4 An example diagram of optimized space in wire meshes of different densities provided in an embodiment of the present application;

[0067] Figure 5 An example diagram of a unit layout provided in an embodiment of the present application;

[0068] Figure 6 An example diagram of line length prediction based on center of gravity provided in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the structure of an integrated circuit layout optimization device provided in an embodiment of the present application;

[0070] Figure 8 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0072] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0073] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0075] Before describing the embodiments of the present application in detail, some related technologies involved in the embodiments of the present application are first described as follows:

[0076] The present application relates to the field of placement in the physical design flow of very large-scale integrated circuits, which is a cornerstone stage in the development process and has a significant impact on circuit performance, power consumption and area.

[0077] In the physical design process, placement is to determine the position and direction of all circuit components in a plane so that the optimization goal can be achieved under the constraints. The constraints generally require that there is no overlap between components, that there is a certain spacing between components, and that component congestion is avoided. The optimization goal requires minimizing the line length and reducing signal transmission delay.

[0078] Placement refinement refers to a method of performing more refined optimization on an existing initial layout. It can further optimize circuit performance indicators and improve layout quality. In recent years, many algorithms have been proposed to improve layout. Mixed-Integer Programming (MIP) is a method for solving optimization problems involving continuous variables and integer variables through linear programming techniques. It can greatly improve layout quality because MIP can perform finer-grained layout through precise MIP formulas, while flexibly modeling layout optimization problems and considering multiple indicators to obtain high-quality solutions.

[0079] In recent years, some MIP model-based solutions have optimized multiple indicators to a considerable degree in the layout problem. The models of some related technologies fully consider the layout problem, but due to the introduction of too many integer variables, their experiments only contain 36 cells. Some related technologies introduce sliding window techniques to rearrange only a small part of the cells in the selected window, making large-scale layout optimization possible. Some related technologies reduce integer variables by optimizing the representation of each position. They expand the window size and the number of cells in each window to at most 12. However, they use Half-Perimeter Wirelength (HPWL) as the objective function. HPWL estimates the length of the wire by calculating half of the perimeter of the minimum bounding rectangle of all connected pins in a wire net, which may not accurately reflect the true wire length of high-order networks. Some related technologies solve the Rectilinear Steiner Minimum Tree (RSMT) problem in the MIP model and have timing-driven capabilities. This method is able to optimize multiple indicators and achieve excellent results. However, since it adopts simple rules when refining the entire circuit, it is inefficient and cannot be optimized on a large scale. Some related technologies generate candidate positions for some key units in advance to reduce the computational burden of solving the MIP model. Some related technologies run a mini MIP model to determine the best position in the window as the candidate position, which reduces the computational burden of solving the final MIP model. However, their candidate position selection method does not fully consider the factors of the initial position, and the candidate positions are all limited number of precise discrete positions, which overly narrows the search space and limits the optimization level. Some related technologies use the concept of cell median (median gcell) to calculate the candidate position, that is, the median position of other connected cells in the horizontal and vertical directions.

[0080] Compared with the prior art solutions that do not consider the initial layout, this application avoids the substantial decline in the quality of the final solution due to a small search space. At the same time, based on a full analysis of the initial layout, a reasonable pruning technique is proposed to reduce the computational burden of the MIP model.

[0081] Therefore, the embodiments of the present application provide an integrated circuit layout optimization method, device, electronic device and storage medium. The technical solution of the present application includes: determining the initial position of several units in each wire net; determining the movement constraints of several units within the boundary box of the corresponding wire net; determining the movement area of ​​several units within the corresponding boundary box according to the initial position and the movement constraints; dividing each wire net into multiple sub-wire nets; solving the target position of several units with the shortest line length as the goal according to each sub-wire net and the corresponding movement area; moving several units from the initial position to the corresponding target position. The present application determines the movement area according to the initial position and movement constraints of the unit, and then solves the shortest line length in the movement area, which fully considers the initial layout of the unit, and can reduce the problem of a significant decrease in the quality of the final layout solution due to too small a search space; and the present application can divide each wire net into multiple sub-wire nets on the basis of fully analyzing the initial layout, realizes reasonable pruning of the movement area, and can reduce the computational burden of solving the shortest line length.

[0082] The embodiments of the present application provide an integrated circuit layout optimization method, device, electronic device and storage medium, and relate to the field of integrated circuit technology. The integrated circuit layout optimization method provided in the embodiments of the present application can be applied to a terminal, can also be applied to a server, and can also be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or it can be configured as a server cluster or distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements an integrated circuit layout optimization method, etc., but is not limited to the above forms.

[0083] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0084] Reference Figure 1 , the embodiment of the present application provides an integrated circuit layout optimization method, the method may include but is not limited to including S100 to S150, specifically as follows:

[0085] S100: Determine the initial positions of a plurality of units in each wire mesh.

[0086] Exemplarily, the initial position of the unit in this embodiment may be given, for example, determined by some layout algorithm, and the initial position may also become the initial solution of the layout algorithm.

[0087] It should be noted that the units in the embodiments of the present application are obtained by abstracting circuit elements, that is, one unit can represent one circuit element, and the shape of the unit can be rectangular; each wire mesh can include one or more units.

[0088] S110: Determine movement constraints of a plurality of the units within a boundary box corresponding to the wire mesh.

[0089] Furthermore, S110 may include:

[0090] Determining the movement constraints of the plurality of units within the corresponding bounding box includes the following constraints:

[0091] Each of the units can be continuously moved in the X direction within the corresponding bounding box, and each of the units moves at least one unit when moving in the Y direction within the corresponding bounding box;

[0092] The X direction and the Y direction are perpendicular to each other;

[0093] The length of the unit is greater than or equal to the length of each of the units in the Y direction;

[0094] The difference in absolute value of the coordinate values ​​in the X direction between any two units in the same bounding box is greater than a preset distance threshold;

[0095] The difference in absolute value of the coordinate values ​​in the Y direction between any two of the units in the same bounding box is greater than one unit.

[0096] Specifically, the problem solved by this embodiment is to find a new unit position so that the total length of the network is the shortest. In the optimization problem of this embodiment, the detailed placement results of m rectangular standard units are given as the initial solution. Each unit i has the same height h and different width w i , and connected in a set of wire nets Net i middle.

[0097] This embodiment uses XY coordinates to determine the location of each cell, which represents the lower left corner of the cell. Figure 2 (a) is an explanation of the basic position. Since each unit must be aligned to a row, this embodiment sets the Y coordinate to an integer variable of the corresponding row index. Since the spacing between sites is small, this embodiment sets X to a continuous variable of the horizontal position to explore more possibilities and finally align with the nearest site. The description of the important symbols in this embodiment is shown in Table 1.

[0098] Table 1 Symbols that may be used in the embodiments of this application

[0099]

[0100]

[0101] This embodiment mainly uses two constraint formulas to ensure the legitimacy of the above XY variables. One is to ensure that each unit moves within a rectangular area and does not cross the boundary of the area through the constraints in formula 1. This embodiment uses the initials of up, down, left, right to represent these four directions. The other is to avoid overlap between two units. If this embodiment wants to ensure that there is no overlap between two units, they should maintain a certain horizontal or vertical distance. Either the difference in the absolute value of their X is greater than a certain value, or the difference in the absolute value of their Y is greater than 1. Therefore, if this embodiment wants to achieve the above goals and there are m units in the entire layout, this will introduce O(m 2 ) integer variables, which is the main factor limiting the speed of this embodiment. This embodiment proposes a force-directed potential region allocation technology to perform pruning processing.

[0102] Formula 1 is the equation that constrains each unit to move within a rectangular area:

[0103]

[0104] The moving left boundary of unit i;

[0105] The moving right boundary of unit i;

[0106] The moving lower boundary of unit i;

[0107] The moving upper boundary of unit i;

[0108] X i : X coordinate of unit i;

[0109] Y i : Y coordinate of unit i;

[0110] w i : Line length of unit i.

[0111] The goal of this embodiment is to reduce the line length. Different from the previous solutions, this embodiment adopts a new line length prediction formula, that is, the line length prediction based on the center of gravity, which is more accurate for high-order line nets.

[0112] S120: Determine a movement area of ​​a plurality of the units within the corresponding boundary box according to the initial position and the movement constraint condition.

[0113] Furthermore, S120 may include S121 to S125:

[0114] S121: determining the boundary distance between each of the units and the corresponding boundary box according to the initial position;

[0115] S122: fitting the forces of each unit in four directions using Hooke's law, the boundary distance and the movement constraint condition; wherein the four directions are movable directions of the unit, and the four directions are respectively positive and negative directions of each unit in the horizontal direction and positive and negative directions in the vertical direction;

[0116] S123: Calculating a corresponding optimization potential coefficient according to the density of each of the cells in each of the boundary boxes;

[0117] S124: performing weighted summation of the forces in the four directions corresponding to each of the units and the optimization potential coefficient to obtain a resultant force corresponding to each of the units;

[0118] S125: Determine the moving area corresponding to the unit according to the combined force.

[0119] Furthermore, S123 may include:

[0120] Calculate the optimization potential coefficient corresponding to each of the bounding boxes according to a density calculation formula;

[0121] The density calculation formula is:

[0122]

[0123] Among them, Density n represents the density of each of the cells within the bounding box of the nth mesh; w c represents the width of the cth unit; h represents the height of each unit; W n represents the width of the bounding box; H n Indicates the height of the bounding box; Cell n Represents each of the units within the nth bounding box; 1-Density n represents the optimization potential coefficient.

[0124] Furthermore, S124 may include:

[0125] Calculating the weighted forces in the four directions according to the optimization potential coefficient and the normalized distance of the boundary distance;

[0126] The calculation formula of the weighted force is:

[0127]

[0128] in, represents the weighted force of the nth wire mesh on the ith unit; dir represents the direction, dir includes the four directions; k represents the coefficient of Hooke's law; Represents the normalized distance; 1-Density n represents the optimization potential coefficient;

[0129] Summing each of the weighted forces in the corresponding directions to obtain the resultant forces in the four directions;

[0130] The calculation formula of the resultant force is:

[0131]

[0132] in, Represents the resultant force acting on the i-th element in the dir direction.

[0133] Specifically, the O(m 2 ) integer variables. This embodiment can modify the moving boundary Bd of each unit in formula (1)i To reduce these variables, Figure 2 The entire circuit in (a) to Figure 2 The displacement area within the dotted box in (b). Since each unit can only move within its own area, this embodiment only needs to avoid overlapping displacement areas of two units, such as C1 and C2. On the one hand, this technique can reduce the number of integer variables to O(m), greatly reducing the number of variables. On the other hand, it follows the results of the global layout, thus avoiding destroying some optimized goals, such as global routability. Calculating the displacement area is an important issue. As a pruning technique, the displacement areas retained by this embodiment should have more potential to improve performance, and units with greater impact should have larger movement areas. Therefore, this embodiment develops a force-directed potential area allocation algorithm to calculate the movement area, which is based on the initial position and wire network connectivity.

[0134] like Figure 3 As shown in the three cases, only one cell needs to be moved, and this cell is only connected to one net. Considering that the bounding box of a net can well represent the placement area of ​​the connected cells of the net, the net has a preferred direction for the movement of cells. If the cell is at the edge of the net's bounding box, the net will tend to move it inwards to get closer to other cells. For example, C0 in net A is located in the upper right corner, so net A will tend to move it to the lower left to get closer to C1 and C2. Similarly, C0 in net B also tends to move to the right, and both vertical directions of movement are acceptable. If the cell is within the bounding box of the net, it may move in four directions, up, down, left, and right, but the probability of moving in each direction is different. For example, C0 in net C is almost in the middle of its bounding box. Moving in four directions may reduce the length of the line, but the tendency of movement is different.

[0135] In actual situations, a unit is usually connected to multiple nets, so the joint effect of all nets should be considered, such as Figure 4 C0 in (a) connects three wire meshes. Each wire mesh provides a directional preference for each unit, so the final displacement area of ​​the unit can be considered by the combined preference of all the wire meshes connected to it. In this embodiment, the directional preference of each wire mesh is analogized to a force that pulls the unit in its preferred direction. The force is described by magnitude and direction, and these forces are integrated together by calculating the resultant force.

[0136] In physics, this embodiment uses a unit length direction vector to describe the direction of a force, and the direction vector can be represented by n component values ​​in an n-dimensional orthogonal coordinate system. In order to formalize the direction of the force in this embodiment, this embodiment decomposes each force into four components: up, down, left, and right. The relative magnitude of the four components can well describe the direction. In order to ensure consistency between preference and force, this embodiment uses Hooke's law f = kΔx to determine the relative magnitude of each component. Δx refers to the distance between the unit and the bounding box of the wire mesh in one direction, denoted as Figure 4 (a) shows an example of boundary distance, such as and The further a cell is from the bounding box in a certain direction, the more it should move in that direction to get closer to the other most connected cells. This is a good quantification of the preference of a single net in various directions, so it makes sense to establish this proportional relationship.

[0137] As for the force of each wire mesh, it reflects the optimization potential of the wire mesh, which is closely related to the density of the wire mesh. Figure 5 In the example in , the direction of the net force exerted by mesh J and mesh K on C0 is similar. If this embodiment directly uses Hooke's law to calculate the size, the size of mesh K will be larger because its boundary distance is larger. However, if C0 is moved to the lower left of mesh K, the wire length will not be reduced much, because the connected cells in the boundary box of mesh K are already very dense and there is not much room for improvement. On the contrary, if this embodiment moves C0 in mesh J to the lower left, the wire length will definitely be reduced because there are no other cells in its boundary box. Therefore, this embodiment should use the density of connected cells to quantify the optimization potential of each mesh, rather than the boundary distance.

[0138] Based on the above analysis, this embodiment can quantify the force of each wire mesh on a unit in one direction as shown in Formula 2. In Formula 2, since the boundary distance only affects the direction of the force, it is normalized in Formula 3 to limit its impact on the amplitude. Since a high density of connected units in the bounding box means a low optimization potential coefficient, this embodiment uses 1-Density n To quantify the amplitude, where Density is calculated in Formula 4 n , ranging from 0 to 1, W n and H n Represents the width and height of the wire mesh bounding box respectively. Figure 4 This process is illustrated in Figure 4(b). The force of each mesh in Figure 4(a) is proportional to the boundary distance, but the proportionality factor for the low-density mesh (mesh A) is larger than that for the high-density mesh (mesh B).

[0139] Formula 2 is the force exerted by each wire mesh on a unit in one direction:

[0140]

[0141] The force exerted by the wire net n on the unit i, dir indicates the direction;

[0142] k: Hooke's law coefficient;

[0143] The normalized distance between the bounding box of cell i and net n in the dir direction;

[0144] Density n : The density of the wire mesh n.

[0145] The effect of Equation 3 is to normalize the boundary distance to limit its effect on the magnitude:

[0146]

[0147] The normalized distance between the bounding box of cell i and net n in the dir direction;

[0148] The distance between the bounding box of cell i and net n in the dir direction;

[0149] The distance between cell i and the bounding box of net n in the upward direction;

[0150] The distance between cell i and the bounding box of net n in the downward direction;

[0151] The distance between cell i and the bounding box of net n in the left direction;

[0152] The distance of cell i from the bounding box of net n in the right direction.

[0153] Formula 4 is the density calculation formula:

[0154]

[0155] Density n : the density of the wire mesh n;

[0156] w c : The width of unit c;

[0157] h: height of the unit;

[0158] W n : The width of the wire mesh bounding box;

[0159] H n : Height of the wire mesh bounding box.

[0160] After calculating the force of each wire mesh separately, this embodiment calculates the resultant force by summing the forces in each direction using Formula 5. Figure 4 As shown in (b), if there are two forces in opposite directions, such as and They don't cancel each other out, because moving one direction still has the potential to reduce the line length. By this summation formula, the more lines the unit connects to, the larger the movement area will naturally be, which is consistent with the fact that they have a greater impact on the final result.

[0161] Formula 5 is the formula for calculating the resultant force:

[0162]

[0163] The resultant force acting on element i, dir indicates the direction;

[0164] The force exerted by network n on element i, dir indicates the direction.

[0165] By quantifying the preferred movement direction of each wire mesh through Hooke's law and calculating their weighted sum according to the optimization potential coefficient of the wire mesh, this embodiment obtains a reasonable displacement area around each unit. In addition, allocating a continuous area instead of a discrete one can provide more possibilities and increase the chance of finding a better solution.

[0166] Finally, through the pruning scheme of this embodiment, this embodiment can make the number of integer variables grow linearly with the number of units, and the quality is not much reduced. However, the complexity of solving MIP does not grow linearly with the increase in the number of integer variables, but grows exponentially. Therefore, it is still necessary to unify the size of each MIP model to ensure its solvability. To achieve this goal, this embodiment introduces a spatial uniform partitioning scheme to refine each part separately.

[0167] S130: Divide each of the wire nets into a plurality of sub-wire nets.

[0168] Further, S130 may include:

[0169] The line net whose number of the cells in the boundary box reaches a preset division threshold is divided into a plurality of the sub-line nets.

[0170] Specifically, the objective function is an important part of the MIP model and can directly determine the final optimization effect. Compared with the additional complexity brought by the wire length of RSMT, HPWL only needs to calculate the half perimeter of the bounding box of the wire net because of its convenience. Most wire length driven solutions use it as the objective function. However, since HPWL is determined only by the bounding box of the wire net, it ignores the layout details within the bounding box. As the wire net degree increases and there are more cells in the bounding box, its accuracy decreases. In fact, HPWL is the lowest limit of the actual wire length, which means that this embodiment will always underestimate the wire length of high-degree nets in HPWL. Experiments under different conditions show that if HPWL is set as the objective function, MIP can always reduce HPWL, but in the actual wiring process, reducing HPWL does not mean reducing the wire length. If the average wire net degree is very high, MIP using HPWL can even increase the wire length. In order to deal with this problem, this embodiment develops an accurate wire length prediction method specifically for high-degree nets by introducing the concept of net breaking centroid.

[0171] Since the fundamental reason why HPWL is inaccurate in high-grid nets is that the placement inside the huge bounding box is ignored, this embodiment first introduces the net segmentation technology to specify the internal placement. This embodiment uses parameter D to set the size of the sub-net, and any net with a degree higher than D (preset division threshold) will be classified as a high-grid net. The pins of a high-grid net will be evenly divided into sub-nets according to their X coordinates. Figure 6 As shown, in this embodiment, D is set to 6.

[0172] S140: solving target positions of a plurality of the units according to each of the sub-line networks and the corresponding moving areas with the shortest line length as a target.

[0173] Furthermore, S140 may include:

[0174] S141: Determine the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net;

[0175] S142: determining a sub-movement area of ​​the sub-line network according to the position of the center of gravity and the corresponding movement area;

[0176] S143: taking the shortest line length as the goal, solving the sum of the first half circumference line length between the centers of gravity and the second half circumference line length of each sub-line network in the corresponding sub-movement area;

[0177] S144: Determine the position of each of the units when the sum of the first half perimeter line length and the second half perimeter line length reaches a minimum value as the target position.

[0178] Furthermore, S141 may include:

[0179] Determine the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net according to the center of gravity coordinate calculation formula;

[0180] The barycenter coordinate calculation formula is:

[0181]

[0182] Wherein, |C| represents the number of units in set C; Denotes the center of gravity G i The X coordinate of c represents the X coordinate of the cth said unit; Denotes the center of gravity G i Y coordinate of c represents the Y coordinate of the cth said unit; Indicates that in the sub-line network S i The unit in .

[0183] After the network is segmented, the HPWL of each sub-network and the bridge between adjacent sub-networks is more accurate than the original rough estimate. However, there is still an error between the HPWL of each sub-network and its actual length. In order to cover the length of the bridge and balance the difference between the HPWL of each sub-network and its actual length, this embodiment introduces the concept of geometry to represent each sub-network. i The centroid represented is the geometric center of the connecting pins in the sub-net, and its XY coordinates are defined as shown in Formula 6, where |C| refers to the number of cells in the set C. It tends to be close to where most of the connected cells are gathered and describes their overall position well. The line length between the centroids has two major advantages. The first is that it will cover the line length connecting adjacent sub-nets, that is, the distance between their nearest pins, which is usually smaller than the distance between adjacent centroids. The second is that the overflow in each sub-net can be understood as the distance from its centroid to the pin, which can compensate for the difference between its HPWL and the actual line length, thereby achieving a certain degree of balance. Therefore, the final estimated line length of a high-degree net can be expressed as the sum of the HPWL between the centroids and the HPWL of each sub-net, as shown in Formula 7. Figure 6 In the example, the total HPWL length of the undivided high-height net is 19, while the actual length is at least 27. If this example is divided into two sub-nets and formula 7 is used, the result will be 27.83, which gives a more accurate estimate. The calculation is as follows:

[0184]

[0185] Formula 6 is the calculation formula of the center of gravity coordinates:

[0186]

[0187] |C|: the number of elements in set C;

[0188] Center of Gravity G i The X coordinate of

[0189] X c : X coordinate of cell c;

[0190] Center of Gravity G i The Y coordinate of

[0191] Y c : Y coordinate of cell c;

[0192] In the sub-line network S i unit.

[0193] Formula 7 is the final estimated line length formula for the high-degree line network:

[0194]

[0195] WL n : estimated line length of line network n;

[0196] HPWL G : The length of the semicircumference of the center of mass G;

[0197] Sub-line network S i Half the circumference of the line length.

[0198] From another perspective, setting HPWL as the objective function actually encourages cells on the net boundary box to move inward. However, cells already inside the box will ignore the influence of this net. This disregard becomes very influential in high-degree nets because most cells are inside their boxes. In contrast, the method of this embodiment divides its large box into smaller boxes to obtain more detailed excitation. In Formula 7, Promote each box to shrink, while the first HPWL G The sub-nets are promoted to be close to each other. Therefore, this embodiment provides a more reasonable incentive for high-number nets without adding too much complexity.

[0199] S150: moving a plurality of the units from the initial position to the corresponding target position.

[0200] Some embodiments of the present application have the following advantages and effects compared with the prior art:

[0201] 1. Some embodiments of the present application propose a force-directed scheme based on MIP and take into account the initial layout information, which can achieve a good balance between efficiency and quality to optimize large-scale layout while ensuring the reliability of the algorithm.

[0202] 2. Some embodiments of the present application propose a new force-directed solution to calculate the moving area, which can further reduce the line length of each unit by quantifying the optimization space in each direction.

[0203] 3. Some embodiments of the present application propose a fast wire length prediction method based on the concept of the centroid of wire mesh segmentation as an objective function. This method is more accurate than the traditional HPWL method on high-degree wire meshes.

[0204] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.

[0205] This embodiment uses the benchmarks of ISPD 2018 and ISPD 2019 competitions to evaluate the solution of this embodiment. The detailed operating environment is shown in Table 2.

[0206] Table 2 Operating environment

[0207]

[0208] CUGR will be used to test the optimization ratio of line length and vias. Since CUGR cannot parse the initial DEF files of ISPD19_test 4 and ISPD19_test 5, they are not shown in the results. The upper row of Table 3 shows several important indicators for each benchmark. The number of standard cells ranges from 9k to 899k, and in some cases also includes macro cells in the layout. This embodiment also shows three indicators about the degree of the wire net, including the maximum degree of the wire net (MD), the average degree of the wire net (AD), and the proportion of high-degree wire nets (Rh). In the experiment, this embodiment sets the size of the sub-wire net D=9, and any wire net with a degree greater than 9 will be decomposed into sub-wire nets. In addition, this embodiment also shows the placement density (PD). The model of this embodiment has two operating modes. One is to use the center of gravity-based wire length prediction method as the objective function, denoted as MIP. The other mode still uses the conventional semi-perimeter wire length as the objective function and marks it as MIP-h. In the partitioning technical solution of this embodiment, this embodiment divides the layout into about 1000 units per part and allocates about 100 seconds of optimization time for each part. Therefore, the total running time of each test case (the time in Table 3) is about 1 / 10 of the number of units. The results of the optimization rate are summarized in Table 3. The model of this embodiment can reduce the line length by 1.02% on average, reduce the number of through holes by 0.58%, and ensure positive line length optimization in each benchmark.

[0209] Table 3 Basic information of ISPD18 and ISPD19 standards

[0210]

[0211]

[0212] Table 3 (continued)

[0213]

[0214]

[0215]

[0216] Table 3 compares the optimization ratios of HPWL, line length, and number of vias when running in MIP and MIP-h modes.

[0217] This embodiment also compares the impact of the new line length prediction method and the half-circumference line length from the results of MIP and MIP-h. Taking the half-circumference line length as an indicator, MIP-h can achieve a higher reduction ratio, which is its direct goal. However, MIP-h cannot maintain this advantage in the optimization of the actual line length (the line length in Table 3). In most test cases, the proportion of highly digitized wire meshes remains between 5.0% and 5.2%, and the average degree of the wire mesh remains between 4.29 and 4.45. In the above test cases, MIP is only slightly better than MIP-h. However, ISPD18_Test 1 and ISPD19_Test 1 show great uniqueness, with their highly digitized wire meshes accounting for 9.29% and the average degree of the wire mesh being 5.46. Since high-degree nets play a more important role in these cases, MIP-h, while doing a good job in reducing half-perimeter wire length, fails to optimize ISPD18_Test1 and even negatively affects ISPD19_Test1, increasing wire length by 0.38%. These are good examples of how half-perimeter wire length does not necessarily correspond to actual wire length. ISPD19_Test3 is also noteworthy because it has only 4.76% of high-degree nets and an average net degree of only 3.37. MIP-h outperforms MIP by 0.13% because low-degree nets play a dominant role. Therefore, it is recommended to use the centroid wire length prediction based on the average net degree. It can effectively eliminate the difference between the half-perimeter wire length and the actual wire length in the case of high-degree nets and achieve better optimization results in test cases with high average net degrees.

[0218] Reference Figure 7 The embodiment of the present application further provides an integrated circuit layout optimization device, which can implement the above-mentioned integrated circuit layout optimization method, and the device includes:

[0219] An initial position determination module is used to determine the initial positions of several units in each network;

[0220] A constraint condition determination module, used to determine movement constraint conditions of a plurality of said units within a boundary box corresponding to said wire mesh;

[0221] A moving area determination module, used to determine the moving areas of a plurality of the units within the corresponding boundary box according to the initial positions and the moving constraint conditions;

[0222] A wire net division module, used for dividing each of the wire nets into a plurality of sub-wire nets;

[0223] A target position solving module, used for solving the target positions of a plurality of the units according to each of the sub-line networks and the corresponding moving areas with the shortest line length as the target;

[0224] The layout optimization module moves a plurality of the units from the initial positions to corresponding target positions.

[0225] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0226] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned integrated circuit layout optimization method when executing the computer program. The electronic device can be any smart terminal including a tablet computer, a car computer, etc.

[0227] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0228] See also Figure 8 , Figure 8 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0229] The processor 801 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0230] The memory 802 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 802, and the processor 801 calls and executes an integrated circuit layout optimization method of the embodiment of the present application;

[0231] Input / output interface 803, used to implement information input and output;

[0232] The communication interface 804 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0233] A bus 805 that transmits information between the various components of the device (e.g., the processor 801, the memory 802, the input / output interface 803, and the communication interface 804);

[0234] The processor 801 , the memory 802 , the input / output interface 803 and the communication interface 804 are connected to each other in communication within the device via a bus 805 .

[0235] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned integrated circuit layout optimization method is implemented.

[0236] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0237] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0238] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0239] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0240] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0241] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0242] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0243] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0244] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0245] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0246] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0247] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0248] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for optimizing integrated circuit layout, characterized in that: The method comprises the following steps: Determine the initial positions of several units in each network; determining movement constraints of a plurality of said units within a bounding box corresponding to said wire mesh; Determining a moving area of ​​a plurality of the units within the corresponding bounding box according to the initial position and the moving constraint condition; Dividing each of the wire nets into a plurality of sub-wire nets; Solving the target positions of the plurality of the units according to the respective sub-line networks and the corresponding moving areas with the shortest line length as the goal; A plurality of the units are moved from the initial positions to corresponding target positions.

2. The integrated circuit layout optimization method according to claim 1, characterized in that: Determining the moving areas of the plurality of units within the corresponding bounding box according to the initial positions and the moving constraint conditions comprises the following steps: Determine the boundary distance between each of the units and the corresponding boundary box according to the initial position; The forces acting on each of the units in four directions are obtained by fitting using Hooke's law, the boundary distance and the movement constraint condition; wherein the four directions are movable directions of the units, and the four directions are respectively the positive and negative directions of each of the units in the horizontal direction and the positive and negative directions in the vertical direction; Calculating a corresponding optimization potential coefficient according to the density of each of the cells within each of the bounding boxes; Performing weighted summation of the forces in the four directions corresponding to each of the units and the optimization potential coefficient to obtain a resultant force corresponding to each of the units; The movement area corresponding to the unit is determined according to the resultant force.

3. The integrated circuit layout optimization method according to claim 2, characterized in that: The step of calculating the corresponding optimization potential coefficient according to the density of each of the units in each of the bounding boxes comprises the following steps: Calculate the optimization potential coefficient corresponding to each of the bounding boxes according to a density calculation formula; The density calculation formula is: Among them, Density n represents the density of each of the cells within the bounding box of the nth mesh; w c represents the width of the cth unit; h represents the height of each unit; W n represents the width of the bounding box; H n Indicates the height of the bounding box; Cell n Represents each of the units within the nth bounding box; 1-Density n represents the optimization potential coefficient; The step of performing weighted summation of the forces in the four directions corresponding to each of the units and the optimization potential coefficient to obtain the resultant force corresponding to each of the units comprises the following steps: Calculating the weighted forces in the four directions according to the optimization potential coefficient and the normalized distance of the boundary distance; The calculation formula of the weighted force is: in, represents the weighted force of the nth wire mesh on the ith unit; dir represents the direction, dir includes the four directions; k represents the coefficient of Hooke's law; Represents the normalized distance; 1-Density n represents the optimization potential coefficient; Summing each of the weighted forces in the corresponding directions to obtain the resultant forces in the four directions; The calculation formula of the resultant force is: in, Represents the resultant force acting on the i-th element in the dir direction.

4. The integrated circuit layout optimization method according to claim 1, characterized in that: The method of solving the target positions of the plurality of units based on each of the sub-line networks and the corresponding moving areas with the shortest line length as the goal comprises the following steps: Determining the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net; Determine a sub-movement area of ​​the sub-line network according to the position of the center of gravity and the corresponding movement area; Taking the shortest line length as the goal, solving the sum of the first half perimeter line length between each of the centers of gravity and the second half perimeter line length of each of the sub-line nets in the corresponding sub-movement area; The position of each of the units when the sum of the first half perimeter line length and the second half perimeter line length reaches a minimum value is determined as the target position.

5. The integrated circuit layout optimization method according to claim 4, characterized in that: Determining the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net includes the following steps: Determine the geometric center of the connecting pins in each of the sub-nets as the center of gravity of the corresponding sub-net according to the center of gravity coordinate calculation formula; The center of gravity coordinate calculation formula is: Wherein, |C| represents the number of units in set C; Denotes the center of gravity G i The X coordinate of c represents the X coordinate of the cth said unit; Denotes the center of gravity G i Y coordinate of c represents the Y coordinate of the cth said unit; Indicates that in the sub-line network S i The unit in .

6. The integrated circuit layout optimization method according to claim 1, characterized in that: Determining the movement constraints of the plurality of units within a boundary box corresponding to the wire mesh comprises the following steps: Determining the movement constraints of the plurality of units within the corresponding bounding box includes the following constraints: Each of the units can be continuously moved in the X direction within the corresponding bounding box, and each of the units moves at least one unit when moving in the Y direction within the corresponding bounding box; The X direction and the Y direction are perpendicular to each other; The length of the unit is greater than or equal to the length of each of the units in the Y direction; The difference in absolute value of the coordinate values ​​in the X direction between any two units in the same bounding box is greater than a preset distance threshold; The difference in absolute value of the coordinate values ​​in the Y direction between any two of the units in the same bounding box is greater than one unit.

7. An integrated circuit layout optimization method according to any one of claims 1 to 6, characterized in that: The step of dividing each of the wire nets into a plurality of sub-wire nets comprises the following steps: The line net whose number of the cells in the boundary box reaches a preset division threshold is divided into a plurality of the sub-line nets.

8. An integrated circuit layout optimization device, characterized in that: The device comprises: An initial position determination module is used to determine the initial positions of several units in each network; A constraint condition determination module, used to determine movement constraint conditions of a plurality of said units within a boundary box corresponding to said wire mesh; A moving area determination module, used to determine the moving areas of a plurality of the units within the corresponding boundary box according to the initial positions and the moving constraint conditions; A wire net division module, used for dividing each of the wire nets into a plurality of sub-wire nets; A target position solving module, used for solving the target positions of a plurality of the units according to each of the sub-line networks and the corresponding moving areas with the shortest line length as the target; The layout optimization module moves a plurality of the units from the initial positions to corresponding target positions.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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