Quantum simulation acceleration device and method

Abstract

The invention discloses quantum simulation acceleration equipment and a quantum simulation acceleration method. The quantum simulation acceleration device may configure a one-dimensional (1D) column vector [# imgabs0 #, # imgabs1 #] from a quantum state of an input qubit, perform a quantum gate operation on the 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component, or a combination thereof, and track a quantum state of the qubit that changes according to the quantum gate operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Korean Patent No. 10-2023-0149049, filed on November 1, 2023, and Korean Patent No. 10-2024-0133159, filed on September 30, 2024, which are hereby incorporated by reference into this application in their entirety. Technical Field

[0002] The present disclosure relates generally to quantum computing technology, and more particularly to quantum simulation acceleration technology. Background Art

[0003] Quantum computers are future supercomputers based on quantum mechanics such as entanglement and superposition. As quantum computers are expected to be commercialized in the near future, quantum computer technology has attracted attention because future technology will solve challenges that humans have not yet been able to overcome, such as the development of new materials, new drugs, and aerospace progress. IBM became the first company to introduce quantum computing to the public cloud to enable users to access quantum computers remotely, and Google announced to the scientific community in 2018 that it had achieved quantum advantage using a 54-qubit quantum processor named Sycamore. This trend has raised expectations for innovations in a variety of fields, including quantum chemistry, cosmology, medicine, and energy physics, which are difficult to process with classical computers. However, since the physical realization of reliable quantum computers is still in its early stages, a large amount of research in this field still relies on quantum simulations using classical computers.

[0004] One of the most representative of the classical quantum simulator methods is the state vector simulator, and is configured to store all quantum states in the form of vector arrays in a computer memory, and simulate quantum state changes by executing sequential quantum gates. This involves preparing an entire state array of N qubits represented by two unit vectors at the initial startup of the simulator, and storing the result of the matrix multiplication corresponding to the input quantum gate in each state vector array. However, the limitation of this method is that it requires exponentially increasing memory as the number of qubits increases. Basically, each quantum state has an amplitude represented by a 16-byte complex number, and therefore the amount of memory required for a quantum circuit with N qubits can be 2 N+4 For example, the minimum memory requirement for running a 60-qubit quantum algorithm reaches 16 exabytes (EB), a scale that even the latest modern supercomputers cannot simulate. With current technology, quantum simulations using classical computing are only able to execute 30-qubit circuits on desktop computers, 35-qubit circuits on advanced servers, and 50-qubit circuits on supercomputers.

[0005] In addition, Korean Patent Application Publication No. 10-2023-0094098, entitled “Quantum Simulation Apparatus and Method,” discloses a method for representing more quantum bit states in a smaller memory space by managing only quantum states with physical reality in a reduced quantum state space when simulating the quantum state of a quantum bit using a digital computer. Summary of the invention

[0006] Therefore, the present disclosure has been proposed in view of the above-mentioned problems occurring in the related art, and an object of the present disclosure is to realize an effective quantum simulation targeting a quantum state having physical reality in a reduced Hilbert space.

[0007] Another object of the present disclosure is to enable fast quantum simulation at a lower computational cost than existing methods, taking into account the fact that quantum computing properties of quantum gates are different from each other.

[0008] Another object of the present disclosure is to utilize quantum simulation in fields such as quantum security, materials science, chemistry, and pharmacology, for example in drug development by accurately simulating complex molecular structures and reactions, in materials science by analyzing the properties of materials at the atomic level, and in finance by utilizing quantum simulation for modeling complex economic systems, risk management, development of advanced investment strategies, etc.

[0009] According to one aspect of the present disclosure, in order to achieve the above-mentioned purpose, a quantum simulation acceleration device is provided, comprising one or more processors, and a memory configured to store at least one program executed by the one or more processors, wherein the at least one program is configured to configure a one-dimensional (1D) column vector [ , ], performing a quantum gate operation on a 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component or a combination thereof, and tracking the quantum state of the qubit that changes depending on the quantum gate operation.

[0010] Here, the quantum state of a qubit may be defined as three quantum states for each qubit depending on the qubit pattern.

[0011] Here, the quantum state of a qubit can be defined as three quantum states, including |0> state S_ZERO, for |1> state S_ONE, and for when the qubit is in superposition |0>+ |1> Status S_SUPERPOSED.

[0012] Here, at least one program may be configured to perform a quantum gate operation that changes only a 1D column vector [ , ] The value does not change The value of , in this quantum gate, the value of the component in the first column and the first row of the matrix is ​​1.

[0013] Here, at least one program may be configured to perform quantum gate operations only on diagonal components using a quantum gate in a quantum gate having diagonal components, in which the values ​​of the components in the first column and the first row of the components of the matrix and the values ​​of the components in the second column and the second row satisfy the Euler equation.

[0014] Here, at least one program may be configured to perform a quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a first column among components of a matrix of quantum gates having off-diagonal components when the quantum state of the qubit is S_ZERO.

[0015] Here, at least one program may be configured to perform a quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a second column among components of a matrix of quantum gates having off-diagonal components when the quantum state of the qubit is S_ONE.

[0016] Here, at least one program may be configured to, when the quantum state of the qubit is S_SUPERPOSED, perform a full matrix operation between a 1D column vector and a matrix of quantum gates having off-diagonal components, and update the quantum state of the qubit only if both the value of the 1D column vector and the result of performing the full matrix operation are greater than zero.

[0017] Here, at least one program may be configured to update the quantum state of the qubits stored in the memory based on the quantum state change in each quantum gate operation.

[0018] Here, at least one program may be configured to directly update a quantum state of a qubit in the memory when a quantum gate operation is performed using a quantum gate having a diagonal component, the quantum state changing as a result of the quantum gate operation.

[0019] Here, the at least one program may be configured to, when a quantum gate operation is performed using a quantum gate having a non-diagonal component, temporarily store the quantum state of the qubit that changes as a result of the quantum gate operation in a temporary memory, and batch update the quantum state temporarily stored in the memory after the quantum gate operation on all qubits is terminated.

[0020] According to another aspect of the present disclosure, in order to achieve the above-mentioned purpose, a quantum simulation acceleration method performed by a quantum simulation acceleration device is provided, comprising: configuring a one-dimensional (1D) column vector [ , ], performing a quantum gate operation on a 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component or a combination thereof, and tracking the quantum state of a qubit that changes depending on the quantum gate operation.

[0021] Here, the quantum state of a qubit may be defined as three quantum states for each qubit depending on the qubit pattern.

[0022] Here, the quantum state of a qubit is defined as three quantum states, including |0> state S_ZERO, for |1> state, and for when the qubit is in superposition |0>+ |1> Status S_SUPERPOSED.

[0023] Here, performing a quantum gate operation may include performing a quantum gate operation using a quantum gate having a diagonal component to change only a 1D column vector [ , ] The value does not change A quantum gate operation is performed on the value of , in which the value of the component in the first column and the first row of the component of the matrix is ​​1.

[0024] Here, performing the quantum gate may also include performing a quantum gate operation only on the diagonal components using a quantum gate in a quantum gate having diagonal components, in which the values ​​of the components in the first column and the first row and the values ​​of the components in the second column and the second row of the components of the matrix satisfy the Euler equation.

[0025] Here, executing the quantum gate may further include: when the quantum state of the qubit is S_ZERO, executing the quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a first column among components of a matrix of quantum gates having off-diagonal components.

[0026] Here, executing the quantum gate may further include: when the quantum state of the qubit is S_ONE, executing the quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a second column among components of the matrix of the quantum gate having non-diagonal components.

[0027] Here, executing the quantum gate may further include: when the quantum state of the qubit is S_SUPERPOSED, performing a full matrix operation between the 1D column vector and the matrix of the quantum gate having non-diagonal components, and updating the quantum state of the qubit only if the value of the 1D column vector and the result of performing the full matrix operation are both greater than 0.

[0028] Here, tracking the quantum state of the qubit may include updating the quantum state of the qubit stored in a memory based on the quantum state change in each quantum gate operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a diagram showing a quantum simulator using a reduced Hilbert space according to an embodiment of the present disclosure; Figure 2 is a diagram showing a quantum state evolution process for an input quantum gate when an arbitrary quantum gate is given as an input in a quantum simulator using a reduced Hilbert space according to an embodiment of the present disclosure; Figure 3 is a block diagram showing a quantum simulation acceleration device according to an embodiment of the present disclosure; Figure 4 is a diagram showing a quantum bit state transition process in a reduced Hilbert space according to an embodiment of the present disclosure; Figure 5 is an operational flow chart showing a quantum simulation acceleration method according to an embodiment of the present disclosure; Figure 6 is a diagram showing quantum matrix operation characteristics of a diagonal gate according to an embodiment of the present disclosure; Figure 7 is a diagram showing the results of comparing the effects of the calculation process on the diagonal gate according to an embodiment of the present disclosure; Figure 8 is a diagram showing a pseudo code of a diagonal gate processing algorithm according to an embodiment of the present disclosure; Fig. 9 is a diagram showing a pseudo code of a non-diagonal gate processing algorithm according to an embodiment of the present disclosure; and Fig.10 is a diagram illustrating a computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The present disclosure will be described in detail below with reference to the accompanying drawings. Repeated descriptions and descriptions of known functions and configurations that are considered to make the subject matter of the present disclosure unnecessarily obscure will be omitted below. The embodiments of the present disclosure are intended to fully describe the present disclosure to persons with ordinary knowledge of the field to which the present disclosure belongs. Therefore, the shapes, sizes, etc. of the components in the accompanying drawings may be exaggerated to make the description clearer.

[0031] In the specification, when an element is referred to as “comprising” or “including” an element, it does not exclude another element but may further include other elements unless the context clearly states otherwise.

[0032] The present disclosure may be variously modified and may have various embodiments, and the embodiments are intended to be shown and described in detail in the drawings.

[0033] However, this is not intended to limit the present disclosure to a specific practice mode, and it should be understood that all changes, equivalents, or substitutes that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure.

[0034] In the description of the elements of the embodiments of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish one element from other elements, and the nature, order, or sequence of the elements are not limited by the terms.

[0035] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0036] It will be understood that when an element is referred to as being “associated with” another element, it can be directly associated with or connected to the other element or intervening elements may be present therebetween.

[0037] The terms used herein are intended only to describe specific embodiments and are not intended to limit the present disclosure. Unless otherwise specifically indicated in the context, singular expressions include plural expressions. It will be further understood that when used in this specification, the terms "include", "comprise", "have", etc. specify the presence of the features, numbers, steps, operations, elements, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, or combinations thereof.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the present disclosure, independent reference numerals are used to designate the same elements in the drawings to facilitate overall understanding.

[0039] Hereinafter, a quantum simulator in the embodiments of the present disclosure refers to a classical quantum simulator using a computer, rather than specifying an actual physical quantum system.

[0040] Hereinafter, the technology of applying the present disclosure is not limited to execution in a specific hardware environment. The present disclosure can be configured using a general-purpose computer or storage device.

[0041] Hereinafter, the quantum simulation acceleration device and method according to the embodiments of the present disclosure are designed to operate based on the previously submitted quantum simulation device and method (Korean Patent Application Publication No. 10-2023-0094098 and U.S. Patent Application Publication No. US2023-0196157). According to the patents submitted above, a method for representing more qubits in a smaller memory space by managing only quantum states with physical reality in a reduced quantum state space when simulating the quantum state of qubits using a digital computer can be provided. That is, when given N qubits, a conventional digital quantum simulation device always needs to have 2 N+4 The previously filed patent enables quantum simulation using more qubits in a smaller memory space in the same computing environment.

[0042] Figure 1 is a diagram illustrating a quantum simulator using a reduced Hilbert space according to an embodiment of the present disclosure.

[0043] refer to Figure 1 , the quantum simulator 103 using the reduced Hilbert space according to an embodiment of the present disclosure can receive each input quantum state 101A and output an evolving quantum state 101B as the quantum gate is executed. Here, the conventional full state vector-based quantum simulator and the quantum simulator 103 using the reduced Hilbert space can output the same quantum state 101B as the execution result when receiving the same input quantum state 101A.

[0044] Here, the quantum simulator 103 using the reduced Hilbert space can dynamically manage the amplitude less than 2 according to whether the amplitude value exists in the reduced Hilbert space 104. N Instead of storing 2 state vectors unconditionally in memory, N The reason why only state vectors having amplitude values ​​greater than 0 are selectively managed in this way is that an amplitude value of 0 not only makes the result of mathematical calculation 0 but also means a physically meaningless quantum state.

[0045] In detail, the quantum simulator 103 using the reduced Hilbert space has a characteristic of expanding or reducing the number of states by applying quantum gates after starting from one vector array during the first initialization of the simulator. That is, the quantum simulator 103 using the reduced Hilbert space includes a state vector ranging from a minimum of one state vector to a maximum of 2 N The state vectors of the state vectors are used as the state vectors to be managed in the memory, and most quantum algorithms require state vectors between the two limits. In addition, because the quantum simulator 103 using the reduced Hilbert space cannot equally distribute the state vectors to the execution threads 103B, it has the characteristic of dynamically distributing the state vector group by means of the concept of quantum state index.

[0046] Hereinafter, the quantum state index described in the present disclosure refers to the position information of the corresponding state vector in the range of the entire size of the full quantum state space, that is, from 0 to 2 N-1 For example, in a quantum memory consisting of three qubits, |000> represents index #0, and |111> represents index #7.

[0047] Figure 2 is a diagram showing a quantum state evolution process for an input quantum gate when an arbitrary quantum gate is given as an input in a quantum simulator using a reduced Hilbert space according to an embodiment of the present disclosure.

[0048] refer to Figure 2 ,To simplify the example, assume that the quantum simulator processes three qubit operations.

[0049] An example of a quantum space 201 for representing three qubits in a conventional full state vector based quantum simulator is depicted. Quantum space 201 may always require 2 3 (=8) vector arrays. However, quantum space 201 is only an example for comparing concepts in conventional full-state-vector-based quantum simulators, rather than a memory structure maintained in an actual memory by a quantum simulator using a reduced Hilbert space.

[0050] The quantum space 202A in the quantum simulator using the reduced Hilbert space is characterized in that only a single vector array (i.e., vector array #0) is used in the initialization phase 203A (initial Z qubits) instead of two 3 (=8) vector arrays are used to configure quantum space 202A. The value retained in vector array #0 is 1, which represents the state amplitude probability value. In this case, the mathematical expression of the initialized quantum state 204A can be represented by ψ>=(1)000>, indicating that the quantum state has been initialized to a single quantum state |000> with an amplitude probability value of 1.

[0051] When the Hadamard gate is applied to qubit 0 (203B) and the Hadamard gate operation is performed, the state vector changes from quantum state 204A to quantum state 202B.

[0052] When the X-gate is applied to qubit 2 (203C) and the X-gate operation is performed, the state vector changes from quantum state 202B to quantum state 202C.

[0053] like Figure 2 As shown, it can be seen that when the Hadamard gate is initially applied to qubit 0 (203B), only a single matrix operation is performed. That is, the process 203B of applying the Hadamard gate to qubit 0 uses the value of the already existing |000> state as the input of the matrix, assumes that the amplitude of the |001> state that does not exist in the memory is 0, and uses the amplitude 0 as the input of the unitary matrix for the matrix calculation. The process 203B of applying the Hadamard gate to qubit 0 produces 1 / √v2|000> and 1 / √v2|001> as the result of the subsequent calculation 202B. The process 203B of applying the Hadamard gate to qubit 0 only updates the amplitude value in the same vector array from 1 to 1 / √v2 because the |000> state already exists in the memory. In contrast, because the |000> state becomes to have a non-zero value under quantum calculation, it can be seen that a new state vector array is added. That is, the existing quantum simulator needs to update all 2 3 Each of the (=8) vectors requires four matrix calculations to perform the same operation, while a quantum simulator using a reduced quantum state space requires only a single matrix operation for the same condition.

[0054] The process 203C of applying the X gate to qubit 2 can also be similar to the process 203B of applying the Hadamard gate to qubit 0. Because the process 203C of applying the X gate to qubit 2 performs calculations on quantum states having amplitudes, quantum calculations can be performed using two matrix operations instead of four matrix operations. Finally, the mathematical expression of the final quantum state 204B to which the two gate operations are applied is represented.

[0055] In this way, because the quantum simulator using the reduced Hilbert space dynamically manages the state vector array according to the quantum gate operation, the advantage is that faster quantum operations can be performed in a smaller memory space compared to the prior art. However, this method still has the problem of computational cost optimization. The reason for this is that when an arbitrary quantum gate is given as input, matrix calculations are performed unconditionally.

[0056] For example, assume that an arbitrary qubit that is not superposed is in the 0> state, and a Z operation is applied to the qubit. The Z operation has the characteristic of only inverting the |1> state without exerting an effect on the 0> state. That is, it can be considered that the Z operation does not cause a quantum change in the qubit in the 0> state, which means that the quantum operation does not need to be performed in the simulator. Nevertheless, the previously filed patent, a quantum simulator using a reduced Hilbert space (Korean Patent Application Publication No. 10-2023-0094098 and U.S. Patent Application Publication No. US2023-0196157), requires always performing matrix operations (four multiplications and two additions) unconditionally, regardless of the characteristics of the quantum state. In addition, because such matrix operations are performed on all state vectors present in the memory, it is difficult to avoid the problem that the computational load attributable to unnecessary matrix calculations increases in proportion to the number of state vectors present.

[0057] Therefore, the quantum simulation acceleration device and method according to the embodiments of the present disclosure are intended to improve simulation performance by selectively applying algorithms that depend on the operating characteristics of diagonal gates or off-diagonal gates and by performing efficient quantum calculations using the quantum states of individual quantum bits, rather than unconditionally applying matrix operations of quantum gates to all quantum states present in the memory of a quantum simulator using a reduced Hilbert space.

[0058] Figure 3 is a block diagram showing a quantum simulation acceleration device according to an embodiment of the present disclosure.

[0059] refer to Figure 3 , showing a quantum simulation acceleration device using a quantum simulator of a reduced Hilbert space.

[0060] The quantum simulation acceleration device according to an embodiment of the present disclosure includes a quantum register 301 and a parallel computing operation unit 304 .

[0061] Quantum register 301 may store an array of quantum state vectors in computer memory.

[0062] The quantum register 301 may include a plurality of storage containers (quantum state containers) 302 for managing individual state vectors and a balanced state storage processor 303. The number of storage containers 302 operated by the quantum simulator may vary according to the number of CPU cores installed in the server. The present disclosure does not specify the number of storage containers 302 in detail. The number of storage containers 302 may be set statically or dynamically, but may be variably applied according to the system environment in the implementation stage of the present disclosure.

[0063] The equilibrium state storage processor 303 may store a state vector in any one of the storage containers 302 based on a preset rule.

[0064] Here, the state storage processor 303 utilizes the quantum index of each state vector as a method for selecting a container to store the corresponding state vector, and may follow a uniform state vector distribution rule based on a modulo operation such as “quantum index% number of containers”.

[0065] For example, the state vector |000> may be converted to quantum index “0”, and the state vector |010> may be converted to quantum index “2”, which means that the respective state vectors are stored in container #0 and container #2.

[0066] The parallel calculation operation unit 304 may perform matrix calculations by obtaining a state vector from the quantum register 301 when a quantum gate input is given.

[0067] The parallel computing operation unit 304 may include multiple parallel execution threads 305A to 305C as a computing space, in which quantum computing is performed when any quantum gate input is given. However, since the functional operation of all threads is the same, the present disclosure is limited to describing how a single thread operates.

[0068] Each of execution threads 305A-305C may include a state vector dispatcher 306, a real-time qubit state tracker 307, a diagonal gate processor 308A, and an off-diagonal gate processor 308B.

[0069] State vector dispatcher 306 may read from the quantum registers the qubit states on which the matrix calculations will be performed in each execution thread.

[0070] Here, the state vector dispatcher 306 may read the quantum state of the qubit stored in the memory and may configure a one-dimensional (1D) column vector [α, β] from the input quantum state of the qubit.

[0071] In this case, the state vector dispatcher 306 may configure a 1D column vector [α, β] from the qubit state, and then transmit the column vector as input to any one of the diagonal gate processor 308A and the off-diagonal gate processor 308B according to the characteristics of the quantum gate.

[0072] The state vector dispatcher 306 can establish an authorization relationship between the execution thread and the storage container to ensure data concurrency between all execution threads 305A to 305C, and the type of authorization can be classified into ownership rights and reference rights. Ownership rights can follow the rule of "number of threads% number of containers". For example, execution thread #0 can maintain the ownership rights of storage container #0, and can maintain the reference rights of the remaining storage containers not owned by execution thread #0. All execution threads 305A to 305C can be responsible for matrix calculations of all quantum states stored in their own containers. When one of the state vectors α and β constituting the unitary matrix is ​​stored in a container that is not owned, all execution threads 305A to 305C can read the corresponding state vector with reference rights.

[0073] The real-time qubit state tracker 307 can track the quantum state of each qubit that changes with the quantum gate operation. The present disclosure can define the quantum state of each qubit as three types.

[0074] Here, as the quantum state of the qubit, three quantum states can be defined for each qubit according to the quantum pattern.

[0075] Here, the quantum state of a qubit can be defined as three quantum states, namely, S_ZERO for the α|0〉 state, S_ONE for the β|1〉 state, and S_SUPERPOSED for the α|0〉 + β|1〉 state where the qubit is in superposition.

[0076] The quantum state of the qubit may be classified as S_ZERO when the qubit is in the α|0> state, S_ONE when the qubit is in the β|1> state, and S_SUPERPOSED when the qubit is in superposition and in the α|0> + β|1> state. The quantum state of the qubit may be maintained independently for all qubits. Here, the real-time qubit state tracker 307 may update the change of the qubit state in each quantum gate operation.

[0077] Here, real-time qubit state tracker 307 may update the quantum state stored in the memory based on the qubit state that changes in each quantum gate operation.

[0078] Each of the diagonal gate processor 308A and the off-diagonal gate processor 308B may perform quantum computation using a given quantum matrix and a unitary matrix.

[0079] Each of the diagonal gate processor 308A and the off-diagonal gate processor 308B may perform a quantum gate operation on a one-dimensional (1D) column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component, or a combination thereof.

[0080] Unlike the prior art that follows the same gate processing rules for all quantum operations, the present disclosure can separately include diagonal gate processors 308A and off-diagonal gate processors 308B to optimize computational costs. That is, a given unitary matrix can be selectively transmitted to the diagonal gate processor 308A or the off-diagonal gate processor 308B according to gate characteristics, thereby supporting quantum computing, so that quantum computing can be performed at a minimum cost.

[0081] The diagonal gate processor 308A and the off-diagonal gate processor 308B may update the state vector of the completed quantum calculation back to the quantum register 301 .

[0082] Here, the diagonal gate processor 308A and the off-diagonal gate processor 308B may follow different memory paths depending on where the quantum computation has been performed.

[0083] The diagonal gate processor 308A can directly (in-place) update the result of performing quantum computation in the state vector memory of the storage container 302 without passing through a separate bypass stage. The reason for this is that, in the case of a gate with a diagonal component, only the amplitude value of the corresponding state is changed while maintaining the position of the state vector.

[0084] Here, the diagonal gate processor 308A may perform a quantum gate operation of changing only the value of β of the 1D column vector [α, β] without changing the value of α of the 1D column vector based on a quantum gate having a value of 1 as a component in the first column and the first row among components of a matrix in a quantum gate having a diagonal component.

[0085] In this case, the diagonal gate processor 308A may perform a quantum gate operation only on the diagonal components using a quantum gate in a quantum gate having diagonal components, in which the values ​​of the components in the first column and the first row and the values ​​of the components in the second column and the second row of the components of the matrix satisfy the Euler equation.

[0086] Here, when a quantum gate operation is performed using a quantum gate having a diagonal component, the diagonal gate processor 308A may directly (in-place) update the qubit states in the memory that are changed as a result of the quantum gate operation.

[0087] Because the result of performing quantum calculation in the off-diagonal gate processor 308B involves the change of the position of the state vector, the calculation result can be directly stored in the corresponding storage container 302, or can be saved in a separate temporary memory 309 according to the calculation result. Here, the off-diagonal gate processor 308B can perform batch updates after the calculation of all state vectors is terminated. Here, the temporary memory 309 can be maintained independently for each storage container 302 to maximize the effect of parallel processing.

[0088] Here, when the quantum state of the qubit is S_ZERO, the off-diagonal gate processor 308B may perform the quantum gate operation as a multiplication operation between a 1D column vector and the value of a component corresponding to the first column among the components of the matrix of the quantum gate having off-diagonal components.

[0089] Here, when the quantum state of the qubit is S_ONE, the off-diagonal gate processor 308B may perform the quantum gate operation as a multiplication operation between a 1D column vector and a value corresponding to the second column in the components of the matrix of the quantum gate having off-diagonal components.

[0090] Here, when the quantum state of the qubit is S_SUPERPOSED, the off-diagonal gate processor 308B may perform a full matrix operation between the 1D column vector and the matrix of quantum gates having off-diagonal components, and may update the quantum state when both the value of the 1D column vector and the result of performing the full matrix operation are greater than 0.

[0091] In this case, when a quantum gate operation is performed using a quantum gate having a non-diagonal component, the non-diagonal gate processor 308B may temporarily store the quantum states of the qubits changed as a result of the quantum gate operation in a temporary memory, and may batch update the quantum states temporarily stored in the memory after the quantum gate operations of all qubits are terminated.

[0092] For example, the diagonal gate processor 308A may include a Z gate, an S gate, a T gate, an SDG gate, a TDG gate, a U1 gate, a P gate, a CZ gate, a CRZ gate, and a CU1 gate.

[0093] A Z-gate, also known as a Pauli-Z gate, may be a gate that rotates a qubit state around a Z-axis in a quantum rotation, and may convert the phase of the qubit state.

[0094] The S-gate is a special form of the P-gate and can be used in = π / 2.

[0095] The T gate may be another gate that applies a phase change and may correspond to the phase change in the P gate. = π / 4.

[0096] The SDG(S†) gate can be the Hermitian adjoint (inverse matrix) of the S gate.

[0097] The TDG(T†) gate can be the Hermitian adjoint (inverse matrix) of the T gate.

[0098] The U1 gate is a unitary gate similar to the P gate, and may be a gate for adding a given phase change λ.

[0099] The P gate (Phase Gate), which is a gate for adding the phase to the corresponding state, can indicate a general phase change, and the parameter to adjust the phase shift.

[0100] A controlled Z (CZ) gate can be a controlled Z gate between two qubits. When the control qubit is in the |1> state, the Z gate can be applied to the target qubit. That is, the phase of the target qubit can be reversed.

[0101] The CRZ (controlled RZ) gate may be a controlled rotation gate, and the RZ(θ) gate may be applied to the target qubit when the control qubit is in the 1> state. The CRZ gate may be a controlled gate for rotating the state of the target qubit around the Z axis. The rotation angle θ may be given as a parameter.

[0102] The CU1 gate can be a controlled unitary gate, and when the control qubit is in the |1> state, a U1(λ) gate can be applied to the target qubit. U1(λ) can indicate a specific phase change λ, and can represent a more general phase change, although it is similar to CRZ.

[0103] Furthermore, the off-diagonal gate processor 308B may include an X gate, a Y gate, an H gate, an RX gate, an RY gate, a CX gate, a CY gate, a CH gate, and a CU3 gate.

[0104] The X-gate (Pauli-X gate) can be a quantum version of the NOT gate. The state of the qubit can be flipped from |0> to |1> or from |1> to |0>.

[0105] A Y gate (Pauli-Y gate) may be a gate for inverting the state of a qubit with respect to a Y axis, and may change the phase when the |0> and |1> states are swapped.

[0106] An H-gate (Hadamard gate) may be a gate that transforms the state of a qubit into an equal superposition state.

[0107] The RX gate may be a rotation gate that rotates the state of the qubit around the X-axis and may change the state according to the rotation angle θ.

[0108] The RY gate may be a rotation gate that rotates the state of a qubit around the Y axis, and may change the state according to the rotation angle θ.

[0109] A CX gate (CNOT gate) can be a controlled X gate, and when the control qubit is in the |1> state, the state of the qubit can be reversed by applying the X gate (NOT) to the target qubit. A CX gate can also be called a CNOT gate, and can be mainly used to entangle the states of two qubits.

[0110] The CY gate can be a controlled Y gate, and the Y gate can be applied to the target qubit when the control qubit is in the |1> state.

[0111] The CH gate can be a controlled Hadamard gate. When the control qubit is in the |1> state, the Hadamard gate can be applied to the target qubit.

[0112] The CU3 gate can be a controlled unitary rotation gate and can perform a rotation transformation by receiving three parameters θ, φ, and λ. When the control qubit is in the |1> state, the unitary transformation can be applied to the target qubit.

[0113] Figure 4 is a diagram illustrating a quantum bit state transition process in a reduced Hilbert space according to an embodiment of the present disclosure.

[0114] refer to Figure 4 , which shows the process of tracking the state of each qubit by the above-mentioned real-time qubit state tracker 307.

[0115] The quantum state storage (quantum state table) 401 may store the latest state of the corresponding qubit. The quantum state storage 401 may be located in an independent memory space in the quantum register 301. The quantum state storage 401 may maintain a plurality of vector arrays the same as the number of qubits, and may maintain a value corresponding to one of S_ZERO, S_ONE, and S_SUPERPOSED. Whenever the quantum gate operation is terminated, the corresponding state value is updated.

[0116] The quantum gate operation processor 402 may correspond to Figure 3 Execution threads 305A to 305C are illustrated in FIG. A quantum gate execution request may be given for a specific qubit.

[0117] In this case, the quantum gate operation processor 402 can track the quantum state transition 403 depending on the change of the quantum state of the input qubit based on the matrix calculation while referring to the latest state of the qubit 401. In addition, after the quantum gate operation is completed, the tracked qubit state can be updated to its latest value again through the quantum state storage 401.

[0118] The qubit state transition 403 may occur in the form of S_ZERO, S_ONE, and S_SUPERPOSED, each of which may transition to any other state, including remaining in the same state. For example, assume that the most recent state of the qubit immediately before performing a quantum operation is a S_ZERO state such as α|0>. If a Z gate, an S gate, or a T gate is given as an input quantum gate, the result of the operation may always be α|0>, and may have the property of retaining the same S_ZERO as its previous state. That is, a transition of the qubit to its own state is performed, wherein no change occurs in the quantum state memory 401. However, when a Hadamard gate is applied to the same quantum state α|0>, the state of the corresponding qubit may be changed to α'|0>+β|1>, and then a state transition from S_ZERO to S_SUPERPOSED may occur.

[0119] The rules for quantum bit state transition based on the above quantum gate characteristics can be represented by the following Table 1.

[0120] Table 1

[0121] Table 1 above describes the quantum bit state transitions of various quantum gates from a conceptual perspective, and its detailed embodiments can be found in Figure 5 In Figure 5 The process of tracking the quantum bit state transition in the quantum simulation acceleration method shown can be included in the reference Figure 3 The quantum operation processing in the execution threads 305A to 305C is described.

[0122] Figure 5 is a flowchart showing the operation of a quantum simulation acceleration method according to an embodiment of the present disclosure.

[0123] refer to Figure 5 In step S501, when the input of the quantum gate is given, the execution thread 305 may first define two variables isLower and isUpper required to track the state of the quantum bit.

[0124] In step S501, two variables may be initialized to a false state and may be updated in such a manner that when the qubit component corresponding to the input qubit in the state to be stored in quantum register 301 after matrix calculation is |0>, the variable isLower is updated to true, and when the qubit component is |1>, the variable isUpper is updated to true.

[0125] In step S502 , the execution thread 305 may look up and extract a one-dimensional (1D) column vector [α, β] from the quantum register 301 .

[0126] That is, at step S502 , each execution thread 305 may read from the quantum register 301 the quantum bit state on which the matrix calculation will be performed.

[0127] Here, in step S502, the qubit state may be read from the memory, and a 1D column vector [α, β] may be configured from the quantum state of the input qubit.

[0128] In this case, the 1D column vector [α, β] can be configured from the read qubit state and can then be passed as input to any one of the diagonal gate processor 308A and the off-diagonal gate processor 308B depending on the characteristics of the quantum gate.

[0129] In step S502, an authorization relationship between the execution thread and the storage container can be established to ensure data concurrency between all execution threads 305A to 305C, and the type of authorization can be classified into ownership rights and reference rights. Ownership rights can follow the rule of "number of threads% number of containers". For example, execution thread #0 can maintain ownership rights for storage container #0, and can maintain reference rights for the remaining storage containers not maintained by execution thread #0. All execution threads 305A to 305C can be responsible for matrix calculations on all quantum states stored in their own containers. When one of the state vectors α and β constituting the unitary matrix is ​​stored in a container that is not owned, all execution threads 305A to 305C can read the corresponding state vector with reference rights.

[0130] In step S503, when the calculation of all state vectors assigned to the execution thread 305 has not been completed, the quantum gate operation may be repeatedly performed until the calculation is completed in step S504.

[0131] In step S504, matrix calculation may be performed on a given state vector matrix.

[0132] That is, in step S504, a quantum gate operation on a 1D column vector may be performed using at least one of a quantum gate having a diagonal component or a quantum gate having a non-diagonal component or a combination thereof.

[0133] Here, in step S504, quantum computations may be performed, each quantum computation using a given quantum matrix and a unitary matrix.

[0134] That is, in step S504, a quantum gate operation on a 1D column vector may be performed using at least one of a quantum gate having a diagonal component or a quantum gate having a non-diagonal component or a combination thereof.

[0135] Unlike the prior art that follows the same gate processing rules for all quantum operations, the present disclosure can separately include diagonal gate processors 308A and off-diagonal gate processors 308B to optimize the computational cost. That is, in step S504, a given unitary matrix can be selectively transmitted to the diagonal gate processor 308A or the off-diagonal gate processor 308B according to the gate characteristics, thereby supporting quantum computing, so that quantum computing can be performed at a minimum cost.

[0136] Here, at step S504, the diagonal gate processor 308A can directly (in-place) update the result of performing quantum computation in the state vector memory of the storage container 302 without passing through a separate bypass stage. The reason for this is that, in the case of a gate with a diagonal component, only the amplitude value of the corresponding state is changed while maintaining the position of the state vector.

[0137] Here, in step S504, the diagonal gate processor 308A may perform a quantum gate operation of changing only the value of β of the 1D column vector [α, β] without changing the value of α of the 1D column vector based on a quantum gate having a value of 1 as a component in the first column and the first row in a quantum gate having a diagonal component in a component of the matrix.

[0138] Here, in step S504, the diagonal gate processor 308A may perform a quantum gate operation only on the diagonal components using a quantum gate in a quantum gate having diagonal components, in which the values ​​of the components in the first column and the first row and the values ​​of the components in the second column and the second row of the components of the matrix satisfy the Euler equation.

[0139] Furthermore, at step S504, when a quantum gate operation is performed using a quantum gate having a diagonal component, the diagonal gate processor 308A may directly (in-place) update the quantum bit states in the memory that are changed as a result of the quantum gate operation.

[0140] In step S504, because the result of performing quantum computation in the off-diagonal gate processor 308B involves a change in the position of the state vector, the computation result may be directly stored in the corresponding storage container 302, or may be saved in a separate temporary memory 309 according to the computation result.

[0141] Here, in step S504, the off-diagonal gate processor 308B may perform a batch update after the calculation of all state vectors is terminated. Here, the temporary memory 309 may be maintained independently for each storage container 302 in order to maximize the effect of parallel processing.

[0142] Here, in step S504, when the quantum state of the qubit is S_ZERO, the off-diagonal gate processor 308B may perform the quantum gate operation as a multiplication operation between a 1D column vector and the value of a component in a first column of the components of the matrix of the quantum gate having off-diagonal components.

[0143] Here, in step S504, when the quantum state of the qubit is S_ONE, the off-diagonal gate processor 308B may perform a quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to the second column of the components of the matrix of the quantum gate having off-diagonal components.

[0144] Here, in step S504, when the quantum state of the quantum bit is S_SUPERPOSED, the off-diagonal gate processor 308B may perform a full matrix operation between the 1D column vector and the matrix of quantum gates having off-diagonal components, and may update the quantum state when both the value of the 1D column vector and the result of performing the full matrix operation are greater than 0.

[0145] Furthermore, at step S504, when a quantum gate operation is performed using a quantum gate having a non-diagonal component, the non-diagonal gate processor 308B may temporarily store a quantum state changed as a result of the quantum gate operation in a temporary memory, and may batch update the quantum state temporarily stored in the memory after the quantum gate operation of all qubits is terminated.

[0146] In step S505, an updated quantum state may be obtained through matrix calculation, and four branches ranging from steps S506A to S506D may occur according to the amplitude value of the result.

[0147] In step S506A, from the perspective of the quantum state of the input qubit, the addition or update of the state bit of the |0> component may be performed.

[0148] At step S507A, an addition or update of the status bit of the |0> component occurs and the variable isLower may be changed to true.

[0149] Here, in step S507A, the state transition of the qubit depending on the result of the current calculation may be processed to perform calculations on subsequent states.

[0150] In step S506B, the status bit of the |0> component may be removed.

[0151] In step S506C, adding or updating of the status bit of the |1> component may be performed.

[0152] At step S507B, an addition or update of the status bit of the |1> component occurs and the variable isUpper may be changed to true.

[0153] Here, in step S507B, the state transition of the qubit depending on the result of the current calculation may be processed to perform calculations on subsequent states.

[0154] In step S506D, the status bit of the component |1> may be removed.

[0155] In step S508, until the state transition of the qubit depending on the result of the current calculation is processed, the process can return to step S502 of finding and obtaining the 1D column vector [α, β], and the corresponding execution thread can be terminated when all state transitions are processed.

[0156] Here, as quantum states of a qubit, three quantum states can be defined for each qubit according to the qubit pattern.

[0157] Here, the quantum state of a qubit can be defined as three quantum states, namely, S_ZERO for the state α|0〉, S_ONE for the state β|1〉, and S_SUPERPOSED for the state α|0〉+β|1〉 where the qubit is in superposition.

[0158] In steps S509A to S509C, the quantum state of the qubit that changes with the quantum gate operation can be tracked. The present disclosure can define the quantum state of each qubit as three types.

[0159] Here, in steps S509A to S509C, the change of the quantum state of the qubit may be updated in each quantum gate operation.

[0160] In step S509A, the final state of the qubit may be determined depending on the values ​​of the variables isLower and isUpper.

[0161] Here, in step S509A, when the variables isLower and isUpper are both true, the state of the qubit may be updated to S_SUPERPOSED, and thereafter the execution thread may be terminated in step S510A.

[0162] Here, in step S509B, when only the variable isLower is true, the state of the qubit may be updated to S_ZERO, and thereafter the execution thread may be terminated in step S510B.

[0163] Here, in step S509C, when only the variable isUpper is true, the state of the qubit may be updated to S_ONE, and thereafter the execution thread may be terminated in step S510C.

[0164] Figure 6is a diagram illustrating characteristics of quantum matrix operations of diagonal gates according to an embodiment of the present disclosure. Figure 7 is a diagram showing the results of comparing the effects of a calculation process on a diagonal gate according to an embodiment of the present disclosure.

[0165] A diagonal gate refers to a quantum operation in which the remaining components in a matrix except for the diagonal components are 0, and in the present disclosure, gates following the diagonal matrix property among quantum gates can be classified into two types.

[0166] refer to Figure 6 , the first diagonal gate type 601 indicates a quantum gate in which the value of the component in the first column and the first row of the components of the matrix is ​​1. This type of quantum gate 601 may include a Z gate, a P gate, an S gate, a T gate, an SDG gate, a TDG gate, and a U1 gate.

[0167] A Z-gate, also known as a Pauli-Z gate, may be a gate that rotates a qubit state around a Z-axis in a quantum rotation, and may convert the phase of the qubit state.

[0168] The P gate (Phase Gate) is a gate used to add phase to the corresponding state, which can indicate a general phase change and can use parameters Adjust the phase shift.

[0169] The S-gate is a special form of the P-gate and can be used in = π / 2.

[0170] The T gate may be another gate that applies a phase change and may correspond to the phase change in the P gate. = π / 2.

[0171] The SDG(S†) gate can be the Hermitian adjoint (inverse matrix) of the S gate.

[0172] The TDG(T†) gate can be the Hermitian adjoint (inverse matrix) of the T gate.

[0173] The U1 gate is a unitary gate similar to the P gate, and may be a gate for adding a given phase change λ.

[0174] The RZ gate can be a rotation gate used to rotate a qubit around the Z axis in quantum computing. The RZ gate can transform the phase of the state of a qubit by rotating the qubit along the Z axis by an arbitrary angle. This can be determined according to a parameter indicating the rotation angle. is defined.

[0175] Gate 601 may have a gate for a 1D column vector [ , ] 603 Update only The value does not change That is, in conventional technology, the standardized formula such as [(1× ) + (0× ) = ] applied to matrices such as 1D column vectors [ , ] 603. However, in this case, The value of does not change, and thus the calculation itself is not necessary. Therefore, only Apply calculations, and this also makes it possible to simply pass such as [(m× ) = m ] instead of [(0× ) + (m× ) = m ] completes quantum computing with one calculation.

[0176] The second diagonal gate type 602 is a quantum gate in which the values ​​of the components in the first column and the first row and the values ​​of the components in the second column and the second row of the components of the matrix are given by Euler's equations. An RZ gate that performs a rotation about the Z axis on the Bloch sphere may correspond to this type. This type may have properties similar to those of the quantum gate 601 and may be described by simplifying the formula "m 1 × = m 1 ” and “m 2 × = m 2 " instead of "(m 1 × ) + (0× ) = m 1 ” and “(0× ) + (m 2 × ) = m 2 " to process, thereby removing unnecessary computing costs.

[0177] Furthermore, each diagonal gate has another unique property that indicates that the position of the unit vector in the matrix is ​​unchanged. That is, in-place updates at the memory locations storing the qubit states can be performed without moving the state vector entries present in the quantum register.

[0178] Reference Figure 7 It can be seen that the effect of the above-mentioned diagonal gate calculation processing is explained through an actual detailed calculation example.

[0179] Figure 7A comparison between a diagonal gate calculation process 701 of a conventional quantum simulation device and a diagonal gate calculation process 702 of a reduced Hilbert space according to an embodiment of the present disclosure is shown.

[0180] For the sake of clarity, a quantum register consisting of three qubits is assumed. Assume that there is a same 2 with a value greater than 0 in both the conventional computing process 701 and the computing process 702 of the present disclosure. 3 A state vector array of (=8) values.

[0181] It is assumed that each of the conventional calculation process 701 and the calculation process 702 of the present disclosure uses a Z gate, which is a representative diagonal gate, as an input.

[0182] When performing a Z-gate operation, conventional computation processing 701 can be performed by configuring all state vectors as column vectors [ , ] to perform a total of four matrix calculations. The individual matrix calculations are [(m00× )+(m01× ) = '] and [(m10× )+(m11× ) = '], so a total of 16 multiplications and 8 additions are required to process the Z gate.

[0183] In contrast, the computation process 702 proposed in the present disclosure only requires a reduced type of computation, rather than applying a full matrix computation. That is, because the computation process 702 of the present disclosure does not cause The quantum state of the quantum state is changed, so the calculation itself is not performed, and it can be calculated by simply multiplying -1 by the component To update the amplitude value of the state. In this case, the processing of the Z gate can be completed by only a total of four multiplications.

[0184] Based on the above description, the present disclosure may be characterized in that, when a quantum gate input is given, a quantum operation algorithm is selectively applied depending on the characteristics of the gate. Unlike a conventional calculation process in which an unconditional calculation method is applied to all quantum gates, the present disclosure may have the advantage of reducing the calculation cost by applying an algorithm that takes into account the operation method of the quantum gate.

[0185] In order to describe in detail the differences and advantages associated with the computational process, Figure 7 The general method for applying quantum gates is described in Figure 8 and Fig. 9 The detailed method of the quantum gate algorithm proposed in this disclosure is described in.

[0186] Figure 8is a diagram showing a pseudo code of a diagonal gate processing algorithm according to an embodiment of the present disclosure.

[0187] refer to Figure 8 , the diagonal gates can correspond to Z gates, P gates, S gates, T gates, SDG gates, TDG gates, U1 gates and RZ gates.

[0188] When any quantum gate input is given, the diagonal gate processing algorithm 901 according to an embodiment of the present disclosure may allocate container memory to the execution threads in lines 02 and 03. This means that each execution thread has ownership of the container memory allocated thereto. Thereafter, in line 04, each thread may sequentially read the state vectors stored in the allocated container memory while traversing (going around) all state vectors.

[0189] The diagonal gate processing algorithm 901 according to the embodiment of the present disclosure has an excellent characteristic of not configuring the state pair that is the target of matrix calculation in the case of the conventional technology. The reason for this is that only The |1> state requires a single multiplication, rather than applying a 2×2 matrix calculation to a given input gate. However, the RZ gate is |0>Status and |1> Each of the states requires a multiplication.

[0190] The diagonal gate processing algorithm 901 according to an embodiment of the present disclosure may perform quantum operations of the diagonal gate through the process from line 08 to line 12.

[0191] In line 08, it is determined whether the qubit component of the input qubit in the quantum state obtained from the container memory is |0>.

[0192] When the qubit component is |0>component, m00 corresponding to the first column and first row of the matrix can be multiplied by The value of , and the result of the multiplication can be updated in the corresponding state vector. This case can be limited to RZ gates.

[0193] When the qubit component is |1>component, m11 corresponding to the second column and second row of the matrix can be multiplied by The value of , and the result of the multiplication can be updated in the corresponding state vector. This situation can be applied to all diagonal gates.

[0194] The effect of the above diagonal algorithm can be summarized.

[0195] First, the state vector pairs to which the matrix calculation will be applied are not configured.

[0196] Second, each thread can quickly process only the state vectors in the container storage assigned to it, without concurrent interference between executing threads.

[0197] third,[ , The number of quantum matrix calculations for a state pair can be reduced from the existing number corresponding to "four multiplications + two additions" to the number corresponding to "one multiplication or two multiplications for special cases". The two multiplications for the special case can only correspond to when the qubit has the state |0>+ |1> when the RZ gate is executed.

[0198] Fig. 9 is a diagram showing a pseudo code of a non-diagonal gate processing algorithm according to an embodiment of the present disclosure.

[0199] refer to Fig. 9 , the non-diagonal gate processing algorithm 1001 according to an embodiment of the present disclosure can be applied to all single qubit gates except diagonal gates.

[0200] In lines 06 to 08, you can Figure 8 The container storage is allocated to the execution threads in the same manner, and the state vector can be sequentially read from the container storage to which each execution thread is allocated. Here, a state read from the corresponding container storage by the execution thread can be referred to as a read state (RS).

[0201] The off-diagonal gate execution algorithm proposed in the present disclosure has an excellent property of showing different processing methods according to the quantum state of the qubit.

[0202] Under the first condition, when the quantum state of the qubit is S_ZERO, as in the case of row 09, the quantum state of the target qubit may correspond to |0>. Because |1> in the component is 0, so no calculation of components m01 and m11 is performed, and two multiplications can be performed, such as The multiplication between and m00 and The final quantum state after calculation can be ( ×m00)|0>+ ( ×m10)|1>, and can comply with the following update rules depending on the calculated result value.

[0203] when When ×m00 = 0, the amplitude value of the existing RS may be 0, and thus RS may be a state vector that no longer needs to be maintained in the reduced Hilbert space. Therefore, in order to delete the RS stored in the container, the RS may be maintained in delRSList which is a temporary storage space.

[0204] when When ×m00>0, the existing RS value present in the container memory can be directly updated by only changing the state value of the state vector without changing the position of the state vector.

[0205] when When ×m10 = 0, no matrix calculation is applied.

[0206] when ×m10>0, the new state vector ( ×m10)|1> is kept in addRSList as a temporary storage space to add the new state vector to the container.

[0207] Under the second condition, as in the case of row 15, the case where the quantum state of the qubit is S_ONE can correspond to the quantum state of the target qubit being |1> state. Because |0> in the component is 0, so no calculation of the m00 and m10 components is performed, and two multiplications can be performed, such as The multiplication of m01 and and m11. The final quantum state after calculation can be ( ×m01)|0>+ ( ×m11)|1>, and can comply with the following update rules depending on the calculated result value.

[0208] when When ×m01 = 0, no matrix calculation is applied.

[0209] when ×m01>0, the new state vector ( x m01)|0> is kept in addRSList as a temporary storage space to add the new state vector to the container.

[0210] when ×m11 = 0, the amplitude value of the existing RS may be 0, and thus RS may be a state vector that no longer needs to be maintained in the reduced Hilbert space. Therefore, in order to delete the RS stored in the container, the RS may be maintained in delRSList which is a temporary storage space.

[0211] when When ×m11>0, the existing RS value present in the container storage can be directly updated by simply changing the state value of the state vector without changing the position of the state vector.

[0212] Under the third condition, the case where the quantum state of the qubit is S_SUPERPOSED, as in the case of row 21, may correspond to a state where the quantum state of the target qubit is in superposition, such as |0>+ |1>.

[0213] First, it is checked whether the state bit of the target qubit in the read RS is |0> or |1>, as in the case of line 22. When the state bit is |1>, the process can return to line 08 (which is the beginning of the loop) to perform the corresponding process. The reason is that in order to prevent repeated calculations for the same state pair between threads, only the thread that obtains the RS with the state bit |0> in the state vector of the target qubit in superposition performs calculations finitely. With this, the process of verifying whether the calculation of the state pair has been completed in other execution threads in the conventional quantum gate processing algorithm can be skipped.

[0214] In line 23, the one-dimensional (1D) column vector [ , ].

[0215] In lines 24 to 26, full matrix operations can be applied to a 1D column vector [ , ]. Here, in lines 24 to 26, four multiplications and two additions can be performed in the same manner as in the conventional technology.

[0216] In lines 27 to 32, the calculation results can be stored in the quantum register. In lines 27 to 32, when the input vector and are greater than 0 and the calculated result 'and ' are also greater than 0, the corresponding state vector can be directly updated in the memory of the container memory. The reason is that under the corresponding conditions, the positions of the two state vectors do not change, and only the value of the calculation result is changed. That is, it is possible to quickly update the value (such as → 'and → ') to complete lines 27 to 32, because for the input quantum state |0>+ |1>, the result is '|0>+ '|1>. In the remaining cases except the above conditions, lines 27 to 32 may store the state vector to be added or deleted in addRSList or delRSList according to the calculation results, and the temporarily stored addRSList or delRSList may be reflected in the container storage, as in the cases of lines 36 and 37.

[0217] In addition, in addition to the illustrated algorithms and processes, the present disclosure may present a detailed cost model for executing quantum gates through the following equation.

[0218]

[0219] Where P: # of state pairs used for matrix calculation M: cost of magnitude multiplication UD: Cost of direct status update (1) It can be seen that equation (1) indicates a cost analysis model for a diagonal gate processing algorithm according to an embodiment of the present disclosure.

[0220] In equation (1), P represents the number of state vector pairs that need to be calculated.

[0221] In equation (1), M is the multiplication cost required for matrix calculation.

[0222] In equation (1), UD is the cost of updating the matrix computation result in-place in the memory stored in the container, where the quantum state is maintained without passing through temporary storage space.

[0223] The diagonal gate processing algorithm can be composed of reduced matrix operations and state vector update steps based on the operation results. Compared with conventional techniques, unnecessary processing can be minimized and fast execution can be ensured by reduced calculations instead of full matrix calculations.

[0224] Where P: # of state pairs used for matrix calculation M: cost of magnitude multiplication UD: Cost of Direct Status Update R: Ratio of direct status updates UI: Cost of indirect state updates (2) It can be seen that equation (2) shows the cost analysis model S_ZERO or S_ONE of the off-diagonal gate processing algorithm according to an embodiment of the present disclosure.

[0225] Referring to equation (2), a cost analysis model of the off-diagonal gate processing algorithm is represented when the quantum state of the target qubit on which the quantum gate is to be performed is S_ZERO or S_ONE.

[0226] In equation (2), P represents the number of state vector pairs that need to be calculated.

[0227] In equation (2), M is the multiplication cost required for matrix calculation.

[0228] In equation (2), UD is the cost of updating the matrix calculation result in-place in the memory of the container memory, where the quantum state is maintained without passing through temporary storage space.

[0229] In equation (2), R represents the ratio of the number of direct (in-place) updates (UD) in the container storage without passing through the temporary storage space to the total number of quantum state pairs P. That is, when the ratio of UD to any P is R, the ratio of UI can be 1-R.

[0230] In equation (2), UI is the cost of applying the result of the matrix calculation to the state vector by an indirect method via temporary storage space.

[0231] Although there are differences depending on the specifications of the server performing the calculation, on average, the speed of UD can be significantly faster than that of UI.

[0232] When the quantum state of the target qubit is S_ZERO or S_ONE, the magnitude of the state vector pair of the corresponding state is 0, so the state vector pair may not exist in the container memory. Therefore, equation (2) does not require a search process for configuring a state pair or a process for verifying whether the calculation of the state pair has been completed. Therefore, for the quantum state processed by the execution thread, only the calculation of the matrix and the update of the calculation result may be required.

[0233] Compared to conventional techniques, equation (2) can reduce processing cost by using only at most two multiplications, because even in matrix calculations, the column vector [ , ]’s quantum bit state also has a value of 0.

[0234] In addition, equation (2) can perform full matrix operations in the case of non-diagonal gates, and according to the result of the calculation state, the result of the full matrix operation can be directly stored (UD) in the container memory, or can be indirectly stored (UI) via a temporary storage space together with direct storage. The cost of UD is significantly lower than that of UI, and therefore it can be predicted that in terms of storage cost, the cost of equation (2) may be greatly reduced compared to conventional technologies.

[0235]

[0236] Where F: the cost of finding a state pair P: # of state pairs used for matrix calculations M: cost of magnitude multiplication A: The cost of amplitude addition UD: Cost of Direct Status Update R: Ratio of direct status updates UI: Cost of indirect state updates (3) Equation (3) represents the cost analysis model S_SUPERPOSED of the off-diagonal gate processing algorithm according to an embodiment of the present disclosure.

[0237] Referring to equation (3), a cost analysis model of the off-diagonal gate processing algorithm when the quantum state of the target qubit on which the quantum gate is to be performed is S_SUPERPOSED is represented.

[0238] In equation (3), F is the 1D column vector [ , ] is the cost of the state pair.

[0239] In equation (3), P represents the number of state vector pairs that need to be calculated.

[0240] In equation (3), M is the multiplication cost required for matrix calculation.

[0241] In equation (3), A is the additive cost of the matrix computation.

[0242] In equation (3), UD is the cost of updating the matrix computation result in-place in the memory stored in the container, where the quantum state is maintained without passing through temporary storage space.

[0243] In equation (3), R represents the ratio of the number of direct (in-place) updates (UD) in the container storage without passing through the temporary storage space to the total number of quantum state pairs P. That is, when the ratio of UD to any P is R, the ratio of UI can be 1-R.

[0244] In equation (3), UI is the cost of applying the result of the matrix calculation to the state vector by an indirect method via temporary storage space.

[0245] Although there are differences depending on the specifications of the server performing the calculation, on average, the speed of UD can be significantly faster than that of UI.

[0246] Because equation (3) is only limitedly calculated for threads that obtain RS (where the state bit of the target qubit in the read state vector is 0), in order to prevent repeated calculations between threads of the same state pair, unlike conventional techniques, there is no need to verify whether the calculation of the state pair has been completed.

[0247] Furthermore, as in the case of Equation 2, even in the method for storing the calculation result in the container memory, Equation (3) supports UD and UI separately according to the calculation result, thus reducing the processing cost compared with the conventional technology.

[0248] Fig.10 is a diagram illustrating a computer system according to an embodiment of the present disclosure.

[0249] refer to Fig.10 The quantum simulation acceleration device according to the embodiment of the present disclosure can be implemented in a computer system 1100 such as a computer readable storage medium. Fig.10 As shown, the computer system 1100 may include one or more processors 1110, a memory 1130, a user interface input device 1140, a user interface output device 1150, and a memory 1160, which communicate with each other through a bus 1120. The computer system 1100 may also include a network interface 1170 connected to a network 1180. Each processor 1110 may be a central processing unit (CPU) or a semiconductor device for executing a program or processing instruction stored in the memory 1130 or the storage device 1160. Each of the memory 1130 and the storage device 1160 may be any of various types of volatile or non-volatile storage media. For example, the memory 1130 may include a read-only memory (ROM) 1131 or a random access memory (RAM) 1132.

[0250] In addition, the quantum simulation acceleration device according to the embodiment of the present disclosure may include all types of devices, apparatuses and machines for processing digital and / or quantum data, such as programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, or combinations thereof. The device may be or further include a dedicated logic circuit, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or a quantum simulator, i.e., a quantum data processing device designed to simulate or generate information of a specific quantum system. In particular, a quantum simulator is a dedicated quantum computer that lacks the ability to perform general quantum computing. In addition to hardware, the device may optionally include code for creating an execution environment for digital and / or quantum computer programs, for example, code for configuring processor firmware, a protocol stack, a database management system, an operating system or a combination of one or more thereof.

[0251] In addition, a computer system according to an embodiment of the present disclosure can be used on a classical quantum simulator of a quantum circuit that can be executed on a classical computer. The classical quantum simulator can be executed on a cloud computing platform that accesses multiple computing nodes in a parallel or distributed manner. In some cases, a classical quantum simulator can be used to perform all or part of a quantum mechanical energy and / or electronic structure calculation.

[0252] In addition, a classical quantum simulator can be a quantum mechanical system composed of multiple fabricated qubits. A classical quantum simulator can be designed to simulate a quantum system by using a physically different but mathematically equivalent or approximately equivalent system. In a classical quantum simulator, each qubit can be implemented using ions from a string of atomic ions trapped within a linear radio frequency trap. A bias source known as a local field bias can be coupled to each qubit. The local field bias on the qubit can be programmable and controllable. In some cases, a qubit control system including a digital processing unit can be connected to the qubit system, and programming and adjustment of the local field bias on the qubit can be implemented.

[0253] The quantum simulation acceleration device according to an embodiment of the present disclosure may include one or more processors 1110 and a memory 1130, wherein the memory 1130 is configured to store at least one program executed by the one or more processors 110, wherein the memory 1130 stores the quantum state of a qubit, and the at least one program is configured to configure a one-dimensional (1D) column vector [ , ], performing a quantum gate operation on a 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having a non-diagonal component or a combination thereof, and tracking the quantum state of the quantum bit that is changed according to the quantum gate operation.

[0254] Here, the quantum state of a qubit may be defined as three quantum states for each qubit depending on the qubit pattern.

[0255] Here, the quantum state of a qubit can be defined as three quantum states, including |0> state S_ZERO, for |1> state, and for S_ONE when the qubit is in superposition |0>+ |1> Status S_SUPERPOSED.

[0256] Here, at least one program may be configured to perform a quantum gate operation that changes only a 1D column vector [ , ] The value does not change The value of , in this quantum gate, the value of the component in the first column and the first row of the matrix is ​​1.

[0257] Here, at least one program may be configured to perform quantum gate operations only on diagonal components using a quantum gate in a quantum gate having diagonal components, in which the values ​​of the components in the first column and the first row of the components of the matrix and the values ​​of the components in the second column and the second row satisfy the Euler equation.

[0258] Here, at least one program may be configured to: when the quantum state of the qubit is S_ZERO, perform the quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a first column among components of a matrix of quantum gates having off-diagonal components.

[0259] Here, at least one program may be configured to: when the quantum state of the qubit is S_ONE, perform the quantum gate operation as a multiplication operation between a 1D column vector and a value of a component corresponding to a second column among components of a matrix of quantum gates having off-diagonal components.

[0260] Here, at least one program may be configured to: when the quantum state of the qubit is S_SUPERPOSED, perform a full matrix operation between the 1D column vector and the matrix of quantum gates having off-diagonal components, and update the quantum state of the qubit only if the value of the 1D column vector and the result of performing the full matrix operation are both greater than 0.

[0261] Here, at least one program may be configured to update the quantum state of the qubits stored in the memory based on the quantum state change in each quantum gate operation.

[0262] Here, at least one program may be configured to directly update a quantum state of a qubit in the memory when a quantum gate operation is performed using a quantum gate having a diagonal component, the quantum state changing as a result of the quantum gate operation.

[0263] Here, at least one program may be configured to: when a quantum gate operation is performed using a quantum gate having a non-diagonal component, temporarily store the quantum state of the qubit that changes as a result of the quantum gate operation in a temporary memory, and batch update the quantum state temporarily stored in the memory after the quantum gate operation on all qubits is terminated.

[0264] A quantum simulation acceleration device and method according to an embodiment of the present disclosure relates to a method and a device for accelerating quantum simulation using a classical computer.

[0265] More specifically, the quantum simulation acceleration device and method according to the embodiments of the present disclosure are intended to achieve an effective quantum simulation of quantum states having physical reality in a reduced Hilbert space.

[0266] In addition, considering the fact that the quantum computing characteristics of each gate are different from each other, unlike the traditional quantum simulation method that follows the mathematical model of the quantum gate without change, the quantum simulation acceleration device and method according to the embodiments of the present disclosure enable high-speed quantum simulation at a lower computing cost than the traditional method.

[0267] In addition, by applying selective algorithms based on the operating characteristics of diagonal gates or off-diagonal gates, and efficient quantum computing using the quantum states of individual quantum bits, the quantum simulation acceleration device and method according to the embodiments of the present disclosure can provide performance improvements of dozens of times or more compared to traditional technologies.

[0268] In addition, the quantum simulation acceleration device and method according to the embodiments of the present disclosure can verify that, based on the results of simulations performed on an actual Linux server, the diagonal gates exhibit approximately 30 to 130 times the performance improvement, while the non-diagonal gates exhibit approximately 12 to 25 times the performance improvement, compared to traditional technologies.

[0269] In addition, the quantum simulation acceleration device and method according to the embodiments of the present disclosure can be combined with traditional classical quantum simulation devices as separate element technologies, and the integrated configuration of the technologies can be implemented in the form of a complete quantum simulator.

[0270] The present disclosure can achieve efficient quantum simulation in a reduced Hilbert space with the goal of having physically realistic quantum states.

[0271] Furthermore, considering the fact that quantum computing properties of quantum gates are different from each other, the present disclosure can perform fast quantum simulation at a lower computational cost than existing methods.

[0272] In addition, the present disclosure can utilize quantum simulation in fields such as quantum security, materials science, chemistry, and pharmacology, for example by accurately simulating complex molecular structures and reactions in drug development, by analyzing the properties of materials at the atomic level in materials science, and by utilizing quantum simulation for modeling complex economic systems in finance, risk management, development of advanced investment strategies, etc.

[0273] As described above, in the quantum simulation acceleration device and method according to the present disclosure, the configurations and schemes in the above embodiments are applied without limitation, and some or all of the above embodiments may be selectively combined and configured, so that various modifications are possible.

Claims

1. A quantum simulation acceleration device, comprising: one or more processors; as well as a memory configured to store at least one program executed by the one or more processors, Wherein, the at least one program is configured to: The quantum state of the input qubit is configured as a one-dimensional (1D) column vector [ , ], performing a quantum gate operation on the 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component or a combination thereof, and Tracking the quantum state of a qubit as it changes based on quantum gate operations.

2. The quantum simulation acceleration device according to claim 1, wherein: The quantum states of the qubits are defined as three quantum states for each qubit that depend on the qubit pattern.

3. The quantum simulation acceleration device according to claim 2, wherein: The quantum state of the qubit is defined as three quantum states, including: against |0> state S_ZERO, against |1> state S_ONE, and For when the qubit is in superposition |0>+ |1> Status S_ SUPERPOSED.

4. The quantum simulation acceleration device according to claim 1, wherein: The at least one program is configured to perform a quantum gate operation that changes only the 1D column vector [ , ] The value does not change In the quantum gate, the value of the component in the first column and the first row of the matrix is ​​1.

5. The quantum simulation acceleration device according to claim 4, wherein: The at least one program is configured to perform quantum gate operations only on diagonal components using quantum gates in quantum gates having diagonal components, wherein values ​​of components in a first column and a first row and values ​​of components in a second column and a second row of components of a matrix satisfy Euler's equation.

6. The quantum simulation acceleration device as claimed in claim 3, wherein: The at least one program is configured to, when the quantum state of the qubit is S_ZERO, perform a quantum gate operation as a multiplication operation between a 1D column vector and a value corresponding to a component of a first column of a component of a matrix of quantum gates having off-diagonal components.

7. The quantum simulation acceleration device as claimed in claim 3, wherein: The at least one program is configured to, when the quantum state of the qubit is S_ONE, perform a quantum gate operation as a multiplication operation between a ID column vector and a value corresponding to a component of a second column of a component of a matrix of quantum gates having off-diagonal components.

8. The quantum simulation acceleration device as claimed in claim 3, wherein: The at least one program is configured to, when the quantum state of the qubit is S_SUPERPOSED, perform a full matrix operation between a 1D column vector and a matrix of quantum gates having off-diagonal components, and update the quantum state of the qubit only if both a value of the 1D column vector and a result of performing the full matrix operation are greater than zero.

9. The quantum simulation acceleration device according to claim 1, wherein: The at least one program is configured to update the quantum state of the qubit stored in the memory based on the quantum state change in each quantum gate operation.

10. The quantum simulation acceleration device according to claim 9, wherein: The at least one program is configured to directly update the quantum state of the qubit in the memory when a quantum gate operation is performed using a quantum gate having a diagonal component, the quantum state of the qubit changing as a result of the quantum gate operation.

11. The quantum simulation acceleration device according to claim 10, wherein: The at least one program is configured to: when a quantum gate operation is performed using a quantum gate having a non-diagonal component, temporarily store the quantum state of the qubit that changes as a result of the quantum gate operation in a temporary memory, and after the quantum gate operation on all qubits is terminated, batch update the quantum state temporarily stored in the memory.

12. A quantum simulation acceleration method performed by a quantum simulation acceleration device, comprising: The quantum state of the input qubit is configured as a one-dimensional (1D) column vector [ , ]; performing a quantum gate operation on the 1D column vector using at least one of a quantum gate having a diagonal component or a quantum gate having an off-diagonal component, or a combination thereof; and The quantum state of the qubit that changes according to the quantum gate operation is tracked.

13. The quantum simulation acceleration method according to claim 12, wherein: The quantum states of the qubits are defined as three quantum states for each qubit that depend on the qubit pattern.

14. The quantum simulation acceleration method according to claim 13, wherein: The quantum state of the qubit is defined as three quantum states, including: against |0> state S_ZERO, against |1> state S_ONE, and For when the qubit is in superposition |0>+ |1> Status S_ SUPERPOSED.

15. The quantum simulation acceleration method according to claim 12, wherein: Performing quantum gate operations involves: Perform a quantum gate operation that changes only the 1D column vector [ , ] The value does not change In the quantum gate, the value of the component in the first column and the first row of the matrix is ​​1.

16. The quantum simulation acceleration method according to claim 15, wherein: Performing quantum gate operations also includes: A quantum gate using a quantum gate with diagonal components in which values ​​of components in a first column and a first row and values ​​of components in a second column and a second row of components of a matrix satisfy the Euler equation performs a quantum gate operation only on the diagonal components.

17. The quantum simulation acceleration method according to claim 14, wherein: Performing quantum gate operations involves: When the quantum state of the qubit is S_ZERO, the quantum gate operation is performed as a multiplication operation between the 1D column vector and a value of a component corresponding to a first column among components of the matrix of the quantum gate having the off-diagonal components.

18. The quantum simulation acceleration method according to claim 14, wherein: Performing quantum gate operations involves: When the quantum state of the qubit is S_ONE, a quantum gate operation is performed as a multiplication operation between a 1D column vector and a value corresponding to a component of a second column among components of a matrix of quantum gates having off-diagonal components.

19. The quantum simulation acceleration method according to claim 14, wherein: Performing quantum gate operations involves: When the quantum state of the qubit is S_SUPERPOSED, a full matrix operation is performed between the 1D column vector and the matrix of quantum gates having off-diagonal components, and the quantum state of the qubit is updated only if both the value of the 1D column vector and the result of performing the full matrix operation are greater than zero.

20. The quantum simulation acceleration method according to claim 12, wherein: Tracking the quantum state of the qubit includes: The quantum state of the qubit stored in the memory is updated based on the quantum state change in each quantum gate operation.

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