Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing the area occupied by a driving circuit. The display panel includes: a substrate; the driving circuit and the output line are located on one side of the substrate; at least part of the output line extends in the first direction; the driving circuit comprises a plurality of cascaded driving units, and the plurality of driving units are arranged along a second direction; the second direction intersects with the first direction; the driving unit comprises an input end and an output end; the output line is connected with the output end of the current-stage driving unit; the driving unit comprises an output module, the output module comprises a first capacitor, the first capacitor is electrically connected with the output end, and the output line is at least partially overlapped with at least one polar plate of the first capacitor in the direction perpendicular to the plane where the substrate is located.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to control the pixel driving circuit in the display panel, a driving circuit that provides a control signal to the pixel driving circuit and a plurality of wirings connected to the driving circuit need to be provided in the display panel. Currently, the driving circuit and wirings occupy a large space in the display panel, which limits the improvement of the visual effect of the display panel. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device, which are used to reduce the total area occupied by a driving circuit and a first output line in the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] A driving circuit and a first output line are located on one side of the substrate; at least a portion of the first output line extends along a first direction;

[0007] The driving circuit includes a plurality of driving units arranged in cascade, and the plurality of driving units are arranged along a second direction; the second direction intersects with the first direction;

[0008] The driving unit comprises a first input terminal and a first output terminal; the first output line is connected to the first output terminal of the current stage driving unit;

[0009] The driving unit includes an output module, the output module includes a first capacitor, and the first capacitor is electrically connected to the first output terminal.

[0010] and,

[0011] Along a direction perpendicular to the plane where the substrate is located, the first output line at least partially overlaps with at least one plate of the first capacitor.

[0012] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0013] By adopting the solution provided by the embodiment of the present invention, the occupied area of ​​the first output line and the driving unit in the display panel can be reduced, which is beneficial to improving the visual effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of the connection relationship between a driving circuit and a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 3 A circuit diagram of a driving unit provided by an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of wiring of a first output line and a driving unit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic diagram of wiring of another first output line and a driving unit provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0021] Figure 7 A working timing diagram of a driving unit provided by an embodiment of the present invention;

[0022] Figure 8 Another working timing diagram of a driving unit provided by an embodiment of the present invention;

[0023] Fig. 9 for Figure 4 An enlarged schematic diagram of the middle region E1;

[0024] Fig.10 for Fig. 9 A schematic cross-sectional view along B1-B1';

[0025] Fig.11 A schematic diagram of wiring of another driving unit and a first output line provided by an embodiment of the present invention;

[0026] Fig.12 for Fig.11 An enlarged schematic diagram of the middle region E2;

[0027] Fig.13 for Fig.12 A schematic cross-sectional view along B2-B2';

[0028] Fig.14 An enlarged schematic diagram of a first connecting portion and a first capacitor provided by an embodiment of the present invention;

[0029] Fig.15 for Fig.14 A schematic cross-sectional view along B00-B00';

[0030] Fig.16 for Fig.14 A simplified distribution diagram of the three vias in the figure;

[0031] Fig.17 An enlarged schematic diagram of another first connecting portion and a first capacitor provided by an embodiment of the present invention;

[0032] Fig.18 for Fig.17 A schematic cross-sectional view along B0-B0';

[0033] Fig.19 for Fig. 9 A schematic diagram of the first output line in;

[0034] Fig. 20 An enlarged schematic diagram of another first connecting portion and a first capacitor provided in an embodiment of the present invention;

[0035] Fig.21 for Fig. 20 A schematic diagram of the first output line in;

[0036] Fig. 22 for Fig. 9 A schematic cross-sectional view along B3-B3';

[0037] Fig.23 for Fig. 9 A schematic cross-sectional view along B4-B4';

[0038] Fig.24 for Figure 4 An enlarged schematic diagram of the middle region E3;

[0039] Fig.25 for Fig.24 A schematic cross-sectional view along B5-B5';

[0040] Fig.26 for Fig.24 An enlarged schematic diagram of the middle region E4;

[0041] Fig. 27 for Fig.26 A schematic cross-sectional view along B6-B6';

[0042] Fig.28 for Fig.26A schematic cross-sectional view along B7-B7';

[0043] Fig.29 A schematic diagram of local wiring of another driving unit provided by an embodiment of the present invention;

[0044] Fig.30 for Fig.29 A schematic cross-sectional view along B8-B8',

[0045] Fig.31 for Fig.29 An enlarged schematic diagram of the middle region E5;

[0046] Fig.32 for Figure 4 An enlarged schematic diagram of the middle region E6;

[0047] Fig.33 for Fig.32 A schematic cross-sectional view along B10-B10';

[0048] Fig.34 for Fig.32 A schematic cross-sectional view along B11-B11';

[0049] Fig.35 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0053] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0054] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention, the display panel includes a substrate 1 and a driving circuit 2 located on one side of the substrate 1, a light emitting element ( Figure 1 not shown) and the pixel circuit 3.

[0055] The pixel circuit 3 is electrically connected to the light emitting element. The pixel circuit 3 is used to provide a driving current to the light emitting element to drive the light emitting element to emit light. Exemplarily, the light emitting element includes any one of a micro light emitting diode (Micro-LED), a sub-millimeter light emitting diode (Mini-LED), and an organic light emitting diode (OLED).

[0056] In the embodiment of the present invention, the driving circuit 2 is used to provide a first control signal to the pixel circuit 3 to control the on and off of the corresponding transistor in the pixel circuit 3. Figure 1 As shown, the display panel further includes a scanning control line 31 , and the driving circuit 2 provides a first control signal to the pixel circuit 3 through the scanning control line 31 .

[0057] For example, Figure 1 and Figure 2 As shown, Figure 2 The present invention provides a schematic diagram of the connection relationship between a driving circuit and a pixel circuit, wherein the driving circuit 2 includes N driving units 20, where N≥2 and N is an integer. The multiple driving units 20 are used to output first control signals to corresponding pixel circuits 3 step by step.

[0058] Combination Figure 2 and Figure 3 As shown, Figure 3 A circuit diagram of a driving unit provided in an embodiment of the present invention, the driving unit 20 includes a first input terminal IN1 and a first output terminal OUT1. Optionally, the first input terminal IN1 is used to receive a first input signal, and the first output terminal OUT1 is used to output a first output signal. In the driving circuit 2, a plurality of driving units 20 are cascaded, that is, the first output terminal OUT1 of the i-th driving unit 20_i is electrically connected to the first input terminal IN1 of the i+1-th driving unit 20_i+1. In other words, for two adjacent driving units 20, the first output terminal OUT1 of the previous driving unit 20 is electrically connected to the first input terminal IN1 of the next driving unit 20.

[0059] It should be noted that if Figure 2As shown, for the first-stage driving unit 20 in the driving circuit 2, its first input terminal IN1 can be electrically connected to the start signal line STV to receive the start signal. For the last-stage driving unit 20_N in the driving circuit 2, its first output terminal OUT1 can be connected to the corresponding pixel circuit 3, but not electrically connected to other driving units 20.

[0060] For example, Figure 4 As shown, Figure 4 A wiring diagram of a driving unit provided in an embodiment of the present invention, the display panel further includes a plurality of first output lines OUT1 (in order to more clearly illustrate the connection relationship between each wiring and the corresponding signal terminal in the driving unit, the same reference numerals are used to mark the corresponding signal lines and the corresponding signal terminals in the embodiment of the present invention, such as the first output line and the first output terminal are both represented by OUT1), and the first output line OUT1 is electrically connected to the first output terminal OUT1 of the current stage driving unit 20. Taking the driving circuit 2 including N cascaded driving units 20 as an example, the display panel may include N first output lines OUT1, wherein the N first output lines OUT1 are electrically connected to the first output terminals OUT1 of the N driving units 20 in a one-to-one correspondence. The current stage driving unit 20 corresponding to the first output line OUT1 is the driving unit 20 whose first output terminal OUT1 is connected to the first output line OUT1 among the multiple driving units 20.

[0061] For example, Figure 1 and Figure 4 As shown, at least a portion of the first output line OUT1 extends along a first direction h11, and a plurality of driving units 20 are arranged along a second direction h12, wherein the second direction h12 intersects with the first direction h11.

[0062] For example, Figure 1 and Figure 4 As shown, the first output line OUT1 includes a main body OUT10, and the main body OUT10 and the driving unit 20 are arranged along the second direction h12. Along the second direction h12, the main body OUT10 is located on the side of the current stage driving unit 20 close to the next stage driving unit 20. Optionally, as Figure 4 As shown, at least a portion of the main body portion OUT10 may extend along the first direction h11. Figure 1 and Figure 4 The first direction h11 and the second direction h12 are perpendicular to each other as an example. Alternatively, the first direction h11 may also be other parts of the first output line OUT11 that do not extend along the second direction h12. The embodiment of the present invention does not limit the angle between the first direction h11 and the second direction h12.

[0063] Combination Figure 2 , Figure 3 and Figure 4 As shown, the drive unit 20 further includes an output module 4 .

[0064] like Figure 3 and Figure 4 As shown, the output module 4 includes a first capacitor C1, which is electrically connected to the first output terminal OUT1. The first capacitor C1 can improve the potential stability of the first output signal output by the first output terminal OUT1. Figure 3 As shown, the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor C1 is electrically connected to the first output terminal OUT1, and the second plate C12 is electrically connected to the second level signal terminal VGL.

[0065] When setting the first output line OUT1 and the first capacitor C1, illustratively, as Figure 4 As shown, along the direction h2 perpendicular to the plane where the substrate 1 is located, the embodiment of the present invention can make the first output line OUT1 at least partially overlap with at least one electrode plate of the first capacitor C1. Based on this arrangement, compared with the arrangement in which the first output line OUT1 and the two electrodes of the first capacitor C1 are staggered in the direction h2 perpendicular to the plane where the substrate 1 is located, the total area occupied by the first output line OUT1 and the first capacitor C1 in the display panel can be reduced. Figure 5 As shown, Figure 5 A wiring diagram of another driving unit provided by an embodiment of the present invention, wherein the first output line OUT1 and the first capacitor C1 do not overlap in a direction h2 perpendicular to the plane where the substrate 1 is located. Figure 5 As shown, the first output line OUT1 includes a first portion 101 extending along the second direction h12, and at least a portion of the first portion 101 and the first capacitor C1 are arranged along the first direction h11. Figure 5 compared to, Figure 4 The illustrated manner can compress the length d1 of the driving unit 20 in the first direction h11 .

[0066] like Figure 2 and Figure 3 As shown, the driving unit 20 also includes a first control signal output terminal OUT2, which is used to output the first control signal under the control of the first output terminal OUT1. The pixel circuit 3 is used to receive the first control signal and generate a driving current under the control of the first control signal to drive the light-emitting element to emit light.

[0067] Optional, combined Figure 2 , Figure 3 , Figure 4 and Figure 5As shown, the output module 4 includes a first output module 41 and a second output module 42; wherein the first output module 41 is electrically connected to the first output terminal OUT1, and the second output module 42 is electrically connected to the first control signal output terminal OUT2. Figure 3 As shown, the first output module 41 electrically connects the first output terminal OUT1 and the first level signal terminal VGH in response to the signal of the first node N1, and electrically connects the first output terminal OUT1 and the second level signal terminal VGL in response to the signal of the second node N2. The second output module 42 electrically connects the first control signal output terminal OUT2 and the first control signal input terminal IN21 in response to the signal of the first node N1; and electrically connects the first control signal output terminal OUT2 and the second control signal input terminal IN22 in response to the signal of the first output terminal OUT1.

[0068] Optional, such as Figure 3 As shown, the first output module 41 includes a first output transistor T21 and a third output transistor T22, wherein the gate of the first output transistor T21 is electrically connected to the first node N1, and the first electrode and the second electrode are electrically connected to the first level signal terminal VGH and the first output terminal OUT1, respectively. The gate of the third output transistor T22 is electrically connected to the second node N2, and the first electrode and the second electrode are electrically connected to the second level signal terminal VGL and the first output terminal OUT1, respectively.

[0069] For example, Figure 3 As shown, the second output module 42 includes a second output transistor T31 and a fourth output transistor T32, wherein the gate of the second output transistor T31 is electrically connected to the first node N1, the first electrode is electrically connected to the first control signal input terminal IN21, and the second electrode is electrically connected to the first control signal output terminal OUT2. The gate of the fourth output transistor T32 is electrically connected to the first output terminal OUT1, and the first electrode and the second electrode are electrically connected to the second control signal input terminal IN22 and the first control signal output terminal OUT2, respectively.

[0070] Optional, such as Figure 3As shown, the driving unit 20 further includes a first processing module 21 electrically connected to the first node N1 and a second processing module 22 electrically connected to the second node N2. When the driving unit 20 is working, the first processing module 21 and the second processing module 22 are used to write signals to the first node N1 and the second node N2 respectively. When the first node N1 is written with an enable level, the third output transistor T22 is turned on, and the second level signal provided by the second level signal terminal VGL can be written to the first output terminal OUT1. Under the control of the first output terminal OUT1, the fourth output transistor T32 is turned on, and the signal provided by the second control signal input terminal IN22 can be written to the first control signal output terminal OUT2 through the turned-on fourth output transistor T32, so that the first control signal output terminal OUT2 outputs the first control signal, and the first control signal is provided to the corresponding pixel circuit 3.

[0071] Optional, such as Figure 6 As shown, Figure 6 A schematic diagram of a pixel circuit provided in an embodiment of the present invention, the pixel circuit 3 includes a pulse width modulation module 10 and a pulse amplitude modulation module 20. Among them, the pulse width modulation module 10 receives a sweep signal SWEEP, controls the duration of providing a light-emitting driving current to the light-emitting element 12, thereby controlling the light-emitting duration of the light-emitting element 12, so as to adjust the brightness of the light emitted by the light-emitting element 12. The pulse amplitude modulation module 20 is used to provide a light-emitting driving current to the light-emitting element 12, and control the light-emitting efficiency of the light-emitting element 12 by adjusting the amplitude of the light-emitting driving current. Based on this setting, the light-emitting element 12 can be made to work under a suitable driving current, which is conducive to enabling the light-emitting element 12 to achieve higher light-emitting efficiency and better display effect.

[0072] Optional, such as Figure 6 As shown, the pulse amplitude modulation module 20 may include a first light emission control transistor T021, a first driving transistor Td1, a second light emission control transistor T022, a pulse amplitude data writing transistor T023, a pulse amplitude compensation transistor T024, a pulse amplitude gate reset transistor T025, a pulse amplitude anode reset transistor T026 and a first storage capacitor Cst1.

[0073] The first electrode of the first light emitting control transistor T021 is electrically connected to the first power line PAM_VDD, and the second electrode is electrically connected to the first electrode of the first driving transistor Td1.

[0074] A first electrode of the second light emission control transistor T022 is electrically connected to a second electrode of the first driving transistor Td1 , and a second electrode of the second light emission control transistor T022 is electrically connected to a first electrode of the light emitting element 12 .

[0075] The gate of the first light emission control transistor T021 and the gate of the second light emission control transistor T022 receive the pulse amplitude light emission control signal provided by the pulse amplitude light emission control signal terminal PAM_EM.

[0076] A first electrode of the pulse amplitude data writing transistor T023 is electrically connected to the first data signal line PAM_DATA, and a second electrode is electrically connected to a first electrode of the first driving transistor Td1 .

[0077] A first electrode of the pulse amplitude compensating transistor T024 is electrically connected to a second electrode of the first driving transistor Td1 , and a second electrode of the pulse amplitude compensating transistor T024 is electrically connected to a gate of the first driving transistor Td1 .

[0078] A first electrode of the pulse amplitude gate reset transistor T025 is electrically connected to the first reset signal line PAM_REF, and a second electrode is electrically connected to the gate of the first driving transistor Td1.

[0079] A first electrode of the pulse amplitude anode reset transistor T026 is electrically connected to the third power line PVEE, and a second electrode is electrically connected to a first electrode of the light emitting element 12 .

[0080] The gate of the pulse amplitude gate reset transistor T025 receives the first scanning signal provided by the first scanning signal line PAM_S1, and the gates of the pulse amplitude data writing transistor T023, the pulse amplitude compensation transistor T024 and the pulse amplitude anode reset transistor T026 receive the second scanning signal provided by the second scanning signal line PAM_S2.

[0081] Continue to refer to Figure 6 The pulse width modulation module 10 may include a third light emission control transistor T031, a pulse width data writing transistor T032, a second driving transistor Td2, a pulse width compensation transistor T033, a pulse width gate reset transistor T034, a fourth light emission control transistor T035 and a second storage capacitor Cst2.

[0082] The first electrode of the third light emitting control transistor T031 is electrically connected to the second power line PWM_VDD, and the second electrode is electrically connected to the first electrode of the second driving transistor Td2.

[0083] A first electrode of the fourth light emitting control transistor T035 is electrically connected to a second electrode of the second driving transistor Td2 , and a second electrode of the fourth light emitting control transistor T035 is electrically connected to a gate of the first driving transistor Td1 in the pulse amplitude modulation module 20 .

[0084] A first electrode of the pulse width data writing transistor T032 is electrically connected to the second data signal line PWM_DATA, and a second electrode is electrically connected to a first electrode of the second driving transistor Td2 .

[0085] A first electrode of the pulse width compensation transistor T033 is electrically connected to a second electrode of the second driving transistor Td2 , and a second electrode of the pulse width compensation transistor T033 is electrically connected to a gate of the second driving transistor Td2 .

[0086] A first electrode of the pulse width gate reset transistor T034 is electrically connected to the second reset signal line PWM_REF, and a second electrode is electrically connected to the gate of the second driving transistor Td2 .

[0087] One plate of the second storage capacitor Cst2 is electrically connected to the gate of the second driving transistor Td2 , and the other plate is electrically connected to the sweep signal terminal SWEEP.

[0088] A gate of the third light emission control transistor T031 and a gate of the fourth light emission control transistor T035 are electrically connected to the pulse width light emission control signal line PWM_EM to receive a pulse width light emission control signal provided by the pulse width light emission control signal line PWM_EM.

[0089] A gate of the pulse width gate reset transistor T034 is electrically connected to the third scan signal line PWM_S1 to receive the third scan signal provided by the third scan signal line PWM_S1.

[0090] Gates of the pulse width data writing transistor T032 and the pulse width compensating transistor T033 are electrically connected to the fourth scanning signal line PWM_S2 to receive the fourth scanning signal provided by the fourth scanning signal line PWM_S2.

[0091] When the pixel circuit 3 is working, a reference voltage (such as the voltage on the second power line PWM_VDD) is set at the first electrode of the second driving transistor Td2 of the pulse width modulation module 10, and a variable potential is formed at the gate of the second driving transistor Td2 through the data voltage on the second data signal line PWM_DATA and the sweep signal on the sweep signal terminal SWEEP. When the voltage difference between the gate and the first electrode of the second driving transistor Td2 is greater than the threshold voltage of the second driving transistor Td2, the second driving transistor Td2 is in a cut-off state, so that the pulse width modulation module 10 does not provide a control signal to the pulse amplitude modulation module 20, and the first driving transistor Td1 in the pulse amplitude modulation module 20 provides a light-emitting driving current to the light-emitting element 12 according to the voltage on the first data signal line PAM_DATA.

[0092] As the voltage of the signal transmitted by the sweep signal terminal SWEEP changes, the potential of the gate of the second driving transistor Td2 changes synchronously, until the voltage difference between the gate and the first electrode of the second driving transistor Td2 is equal to (or less than) the threshold voltage of the second driving transistor Td2, the second driving transistor Td2 is turned on, and the second driving transistor Td2 transmits the voltage on the second power line PWM_VDD as the cut-off voltage to the pulse amplitude modulation module 20, so that the first driving transistor Td1 in the pulse amplitude modulation module 20 is cut off, thereby stopping the supply of driving current to the light-emitting element 12. It can be seen that the pulse width modulation module 10 can control the duration of the pulse amplitude modulation module 20 outputting the light-emitting driving current, so as to adjust the effective light-emitting duration of the light-emitting element 12 within a frame time, and then adjust the light-emitting brightness of the light-emitting element 12.

[0093] Exemplarily, the first control signal output by the driving unit 20 includes a sweep signal SWEEP; that is, the first control signal output terminal OUT2 of the driving circuit can be connected to Figure 6 The first control signal input terminal IN21 includes a constant signal terminal; illustratively, the constant signal terminal can be used to transmit a constant high level or a constant low level. The second control signal input terminal IN22 includes a sweep frequency input signal terminal SWEEP_IN. illustratively, as Figure 7 As shown, Figure 7 A working timing diagram of a driving unit provided in an embodiment of the present invention, wherein the sweep frequency input signal terminal SWEEP_IN is used to transmit a triangular ramp signal. Optionally, the triangular ramp signal can be a signal whose level gradually increases over time, or a signal whose level gradually decreases over time, which is not limited in the embodiment of the present invention.

[0094] Alternatively, the first control signal output by the driving unit 20 may also include a pulse amplitude light emitting control signal PAM_EM; that is, the first control signal output terminal OUT2 of the driving circuit may be connected to the first control signal output terminal OUT2 of the driving circuit. Figure 4 The pulse amplitude emission control signal terminal PAM_EM of the pixel circuit 3 shown is electrically connected. The first control signal input terminal IN21 includes a constant signal terminal; illustratively, the constant signal terminal can be used to transmit a constant high level or a constant low level. The second control signal input terminal IN22 includes a pulse amplitude emission control signal input terminal PAM_EM_IN. illustratively, as Figure 8 As shown, Figure 8 A working timing diagram of a driving unit provided by an embodiment of the present invention, wherein the pulse amplitude light emitting control signal input terminal PAM_EM_IN is used to transmit a square wave signal.

[0095] It should be noted that Figure 6The circuit structure of the pixel circuit 3 shown is only an illustration, and the structure of the pixel circuit 3 provided in the embodiment of the present invention is not limited thereto. The embodiment of the present invention does not specifically limit the structure of the pixel circuit 3.

[0096] For example, Figure 4 As shown, the display panel further includes a second level signal connection line VGL (using the same mark as the second level signal terminal) and a first level signal connection line VGH (using the same mark as the first level signal terminal). At least a portion of the second level signal connection line VGL and at least a portion of the first level signal connection line VGH both extend along the first direction h11. Moreover, along the second direction h12, at least a portion of the second level signal connection line VGL is located between the first level signal connection line VGH and the main body OUT10 of the first output line OUT1.

[0097] When the first output transistor T21 and the third output transistor T22 are set, illustratively, as Figure 4 As shown, along the second direction h12, the first output transistor T21 can be located on the side of the first capacitor C1 close to the first level signal connection line VGH. Based on this arrangement, the distance between the first output transistor T21 and the first level signal connection line VGH can be shortened, which can facilitate the connection between the first electrode of the first output transistor T21 and the first level signal connection line VGH.

[0098] For example, Figure 4 As shown, along the second direction h12, at least a portion of the third output transistor T22 can be located on a side of the first capacitor C1 away from the first output transistor T21 to shorten the distance between the third output transistor T22 and the second level signal line VGL, thereby facilitating the connection of the third output transistor T22 to the second level signal connection line VGL.

[0099] For example, Figure 4 , Fig. 9 and Fig.10 As shown, Fig. 9 for Figure 4 An enlarged schematic diagram of the middle area E1, Fig.10 for Fig. 9 In a cross-sectional schematic diagram along B1-B1', the first output line OUT1 includes a first connection portion OUT11 and a main body portion OUT10 connected to each other, and along a direction h2 perpendicular to the plane where the substrate 1 is located, the first connection portion OUT11 overlaps with at least one plate of the first capacitor C1. Moreover, the first connection portion OUT11 is located on a side of at least one plate of the first capacitor C1 away from the substrate 1.

[0100] For example, Fig.10As shown, the display panel includes a semiconductor layer S, a first gate metal layer M1, a capacitor metal layer MC and a source-drain metal layer M2. The first gate metal layer M1 is located on a side of the semiconductor layer S away from the substrate 1, the capacitor metal layer MC is located on a side of the first gate metal layer M1 away from the semiconductor layer S, and the source-drain metal layer M2 is located on a side of the capacitor metal layer MC away from the first gate metal layer M1.

[0101] Exemplarily, the first electrode plate C11 of the first capacitor C1 may be located on a side of the second electrode plate C12 away from the substrate 1 . Fig.10 As an example, the capacitor metal layer MC includes a first electrode plate C11 of the first capacitor C1, and the first gate metal layer M1 includes a second electrode plate C12 of the first capacitor C1.

[0102] Optionally, the embodiment of the present invention can make the first connection portion OUT11 located at a side of the second electrode plate C12 of the first capacitor C1 away from the substrate 1. For example, the embodiment of the present invention can make the first connection portion OUT11 and the first electrode plate C11 of the first capacitor C1 be arranged on the same layer, or the first connection portion OUT11 can be located at a side of the first electrode plate C11 of the first capacitor C1 away from the substrate 1. The film layer position of the first connection portion OUT11 will be described in detail below and will not be repeated here. Fig.10 As an example, the first connection portion OUT11 and the first electrode plate C11 of the first capacitor C1 are arranged on the same layer of the capacitor metal layer MC.

[0103] The embodiment of the present invention can reduce the total area occupied by the first connection portion OUT11 and the first capacitor C1 in the display panel by making the first connection portion OUT11 at least partially overlap with at least one plate of the first capacitor C1 in the direction h2 perpendicular to the plane of the substrate 1, which is beneficial to compressing the area occupied by the driving circuit 2 in the display panel.

[0104] In the embodiment of the present invention, Fig. 9 As shown, the second electrode of the first output transistor T21 and the second electrode of the third output transistor T22 are connected at least through the first connection portion OUT11.

[0105] Optional, such as Fig. 9 As shown, in addition to the first connection portion OUT11 and the main body portion OUT10, the first output line OUT1 also includes a first sub-connection portion OUT12 and a second sub-connection portion OUT13. Along a direction h2 perpendicular to the plane where the substrate 1 is located, the first sub-connection portion OUT12 and the two plates of the first capacitor C1 are at least partially non-overlapping, and the second sub-connection portion OUT13 and the two plates of the first capacitor C1 are at least partially non-overlapping.

[0106] For example, Fig. 9As shown, the second electrode of the first output transistor T21 can be connected to the first plate C11 of the first capacitor C1 through the first sub-connection part OUT12, and the second electrode of the third output transistor T22 can be connected to the first plate C11 of the first capacitor C1 through the second sub-connection part OUT13.

[0107] For example, in the embodiment of the present invention, at least a portion of the first plate C11 of the first capacitor C1 can be reused as the first connection portion OUT11. Fig. 9 and Fig.10 As shown, in the embodiment of the present invention, the first connection portion OUT11 can be located on the capacitor metal layer MC, that is, the first connection portion OUT11 is located on the side of the second plate C12 of the first capacitor C1 away from the substrate 1. Based on this arrangement, it is equivalent to making the first plate C11 of the first capacitor C1 and the first sub-connection portion OUT12 and the second sub-connection portion OUT13 together form a connection structure connecting the second electrode of the first output transistor T21 and the second electrode of the third output transistor T22. While realizing the electrical connection between the second electrode of the first output transistor T21 and the second electrode of the third output transistor T22, there is no need to set up an additional connection structure, which is conducive to simplifying the wiring structure of the driving unit 20.

[0108] For example, Fig.10 As shown, along a direction h2 perpendicular to the plane where the substrate 1 is located, the first sub-connection portion OUT12 and the second sub-connection portion OUT13 may be located on a side of the first capacitor C1 away from the substrate 1 .

[0109] Optional, such as Fig. 9 and Fig.10 As shown, in the embodiment of the present invention, the first connection portion OUT11 can be connected to the first sub-connection portion OUT12 through the via K01, and the first connection portion OUT11 can be connected to the second sub-connection portion OUT13 through the via K02.

[0110] In another optional implementation, the embodiment of the present invention may also allow at least a portion of the first connection portion OUT11 to be located on a side of the first electrode plate C11 of the first capacitor C1 away from the substrate 1. Fig.11 , Fig.12 and Fig.13 As shown, Fig.11 A wiring diagram of another driving unit provided in an embodiment of the present invention, Fig.12 for Fig.11 An enlarged schematic diagram of the middle area E2, Fig.13 for Fig.12A schematic cross-sectional view along B2-B2', in which the source-drain metal layer M2 includes at least part of the first connection portion OUT11 as an illustration. Based on this arrangement, the degree of freedom of arrangement of the first connection portion OUT11 can be increased. For example, a material with a greater electrical conductivity can be selected to form the first connection portion OUT11, which is conducive to reducing the resistance of the first connection portion OUT11, thereby reducing the delay of the first output signal transmitted by the first connection portion OUT11 during the transmission process. When at least part of the first connection portion OUT11 is located on the side of the first plate C11 of the first capacitor C1 away from the substrate 1, the first connection portion OUT11 is electrically connected to the first plate C11 of the first capacitor C1 through the hole.

[0111] For example, in the embodiment of the present invention, the first connection portion OUT11 may be electrically connected to the first electrode plate C11 of the first capacitor C1 through at least two vias, and the two vias are arranged at intervals. Fig.12 and Fig.13 As shown, one end of the first connection portion OUT11 is electrically connected to the first electrode plate C11 of the first capacitor C1 through the via K01, and the other end is electrically connected to the first electrode plate C11 of the first capacitor C1 through the via K02. Based on this arrangement, it is equivalent to connecting the first connection portion OUT11 and the first electrode plate C11 in parallel, which is beneficial to further reduce the resistance of the first output line OUT1.

[0112] For example, Fig.13 As shown, the first connection part OUT11 can be in the same layer and directly connected to the first sub-connection part OUT12, and in the same layer and directly connected to the second sub-connection part OUT13. The via K01 connects the second electrode of the first output transistor T21 and the first plate C11 of the first capacitor C1, and also connects the first connection part OUT11 and the first plate C11 of the first capacitor C1. The via K02 is used to connect the second electrode of the third output transistor T22 and the first plate C11 of the first capacitor C1, and also connects the first connection part OUT11 and the first plate C11 of the first capacitor C1.

[0113] like Fig.13 As shown, a first insulating layer L1 is included between the capacitor metal layer MC and the source-drain metal layer M2 , and the via holes K01 and K02 pass through the first insulating layer L1 .

[0114] Fig.12 and Fig.13 The description is made by taking the example that the first connection portion OUT11 is electrically connected to the first electrode plate C11 of the first capacitor C1 through two vias. Of course, the first connection portion OUT11 and the first electrode plate C11 of the first capacitor C1 may be electrically connected through a greater number of vias.

[0115] For example, Fig.14 and Fig.15 As shown, Fig.14 An enlarged schematic diagram of a first connecting portion and a first capacitor provided in an embodiment of the present invention, Fig.15 for Fig.14 A cross-sectional schematic diagram along B00-B00', wherein the first connection portion OUT11 is electrically connected to the first electrode plate C11 through three vias. The three vias include the vias K01 and K02 described above, and also include a via K03. The vias K01 and K02 may be located at both ends of the first connection portion OUT11, and the vias K03 may be located between the vias K01 and K02 along the extension direction of the first connection portion OUT11.

[0116] When the first connection portion OUT11 is electrically connected to the first electrode plate C11 of the first capacitor C1 through at least three vias, the embodiment of the present invention can make the angle α of the connection line of at least three vias satisfy α>90°. The connection line of the vias refers to the connection line of the geometric centers of the vias. Fig.16 As shown, Fig.16 for Fig.14 Based on this arrangement, the multiple vias can be dispersed as much as possible in the area where the first capacitor C1 is located, which can improve the space utilization rate of the area where the first capacitor C1 is located, and is conducive to reducing the difficulty of setting the vias.

[0117] In another possible implementation, Fig.17 and Fig.18 As shown, Fig.17 An enlarged schematic diagram of another first connection portion OUT11 and a first capacitor C1 provided in an embodiment of the present invention, Fig.18 for Fig.17 In a cross-sectional view along B0-B0', the first connection portion OUT11 can also be electrically connected to the first electrode plate C11 of the first capacitor C1 through a via K00. Fig.17 and Fig.18 As shown, the first connection part OUT11 and the first sub-connection part OUT12 are in the same layer and are directly connected, and the first connection part OUT11 and the second sub-connection part OUT13 are in the same layer and are directly connected.

[0118] For example, in the embodiment of the present invention, the width of the first connection portion OUT11 in the first direction h11 may be greater than or equal to the line width of other parts of the first output line OUT1. The line width of other parts of the first output line OUT1 refers to the width of other parts of the first output line OUT1 except the first connection portion OUT11 in the direction perpendicular to the respective extension direction.

[0119] For example, Fig.12, Fig.14 and Fig.17 As shown, in the embodiment of the present invention, the width of the first connection portion OUT11 can be equal to the width of at least one of the main body portion OUT10, the first sub-connection portion OUT12 and the second sub-connection portion OUT13. In this case, the first connection portion OUT11 is a linear structure whose length in the extension direction is significantly greater than its width.

[0120] Or, if Fig. 9 , Fig.19 , Fig. 20 and Fig.21 As shown, Fig.19 for Fig. 9 A schematic diagram of the first output line in, Fig. 20 A schematic diagram of another first connecting portion and a first capacitor provided in an embodiment of the present invention, Fig.21 for Fig. 20 A schematic diagram of the first output line in the embodiment of the present invention can also make the first connection part OUT11 a planar structure, and the width of the first connection part OUT11 in the first direction h11 is greater than the line width of other parts of the first output line OUT1, such as the main body part OUT10, the first sub-connection part OUT12 and the second sub-connection part OUT13.

[0121] With this arrangement, in the region where the first capacitor C1 is located, the embodiment of the present invention can set the width of the first connection portion OUT11 in the first direction h11 as large as possible to reduce the resistance of the first connection portion OUT11, thereby reducing the overall resistance of the first output line OUT1 including the first connection portion OUT11. While reducing the signal delay of the first output signal transmitted by the first output line OUT1, the space in the region where the first capacitor C1 is located can be fully utilized.

[0122] Optional, such as Fig.19 and Fig.21 As shown, in the embodiment of the present invention, the shape of the orthographic projection of the first connection portion OUT11 on the plane where the substrate 1 is located can be set to be the same as the shape of the orthographic projection of at least one electrode plate of the first capacitor C1 on the plane where the substrate 1 is located.

[0123] It should be noted that the widths of different parts of the first connection portion OUT11 in the first direction h11 may be the same, or may be different. Fig.19 Assume that the widths of the two parts of the first connection portion OUT11 in the first direction h11 are W11 and W12 respectively, and the line width of the main body portion OUT10 is W2, and both W11 and W12 are greater than W2.

[0124] Optional, such as Fig. 9As shown, at least a portion of the main body OUT10 may be located in the source-drain metal layer M2 to reduce the resistance of the first output line OUT1 , thereby reducing the signal attenuation of the first output signal transmitted by the first output line OUT1 due to the voltage drop during the transmission process.

[0125] For example, Figure 3 As shown, the driving unit 20 further includes a first isolation transistor T11 ; the gate of the first isolation transistor T11 is connected to the second level signal terminal VGL, the first electrode is electrically connected to the first output terminal OUT1 , and the second electrode is electrically connected to the second output module 42 .

[0126] When the potential of the gate of the fourth output transistor T32 is coupled by the parasitic capacitance to the third level signal which is lower than the potential of the second level signal provided by the second level signal terminal VGL, the first isolation transistor T11 can be disconnected, thereby preventing the third level signal from being transmitted to the first output terminal OUT1, and further avoiding affecting the potential of the first output signal output by the first output terminal OUT1, which is beneficial to improving the stability of the first output signal. When the first output terminal OUT1 is electrically connected to the first input terminal IN1 of the other stage driving unit, the working stability of the other stage driving unit 20 can be improved.

[0127] like Figure 4 , Fig. 9 , Fig.11 and Fig.12 As shown, the first connection portion OUT11 is also used to connect the first electrode of the first isolation transistor T11 and the second electrode of the third output transistor T22. When the third output transistor T22 is turned on, the first level signal provided by the second level signal connection line VGL can be transmitted to the first electrode of the first isolation transistor T11 through the turned-on third output transistor T22 and the first connection portion OUT11.

[0128] Optional, such as Figure 4 , Fig. 9 , Fig.11 and Fig.12 As shown, the first isolation transistor T11 is located between the first output module 41 and the second output module 42 , so that the first isolation transistor T11 is connected to the first output module 41 and the second output module 42 respectively.

[0129] For example, Fig. 9 and Fig.12 As shown, the display panel also includes a second connecting portion 52, which connects the second electrode of the first isolation transistor T11 and the second output module 42; along the direction h2 perpendicular to the plane where the substrate 1 is located, the first output line OUT1 and the second connecting portion 52 do not overlap to reduce the coupling capacitance between the two.

[0130] Optional, such as Fig. 9 and Fig.12 As shown, along the first direction h11, the first output line OUT1 is at least partially located on the side of the second connection portion 52 away from the second output module 42, so that the first output line OUT1 is connected to the first input terminal IN1 of the next-stage driving unit 20, which is beneficial to shorten the length of the first output line OUT1 and reduce the delay of the signal transmitted by the first output line OUT1.

[0131] For example, Figure 3 As shown, the driving unit 20 further includes a third node N3, a third node writing unit 203 and a first processing module 21. The third node writing unit 203 is electrically connected to the third node N3, and the third node writing unit 203 is used to electrically connect the first input terminal IN1 and the third node N3 under the control of the first clock signal terminal CK; the first processing module 21 is electrically connected to the first node N1.

[0132] The first processing module 21 includes a second capacitor C2 electrically connected to the first node N1 and a first node writing unit 201; the first node writing unit 201 includes a first subunit 2011, and the first subunit 2011 is used to electrically connect the first level signal terminal VGH and the first node N1 under the control of the third node N3. Among them, the second capacitor C2 is used to electrically connect the second level signal terminal VGH and the first node N1, and the second capacitor C2 improves the stability of the potential of the first node N1.

[0133] When setting the first subunit 2011, illustratively, as Fig. 9 and Fig.12 As shown, along the first direction h11, the embodiment of the present invention can make the first subunit 2011 and the output module 4 be located on both sides of the second capacitor C2.

[0134] Optional, such as Fig. 9 and Fig.12 As shown, the display panel further includes a third connection portion 53, which connects the first subunit 2011 and the output module 4. Specifically, the third connection portion 53 can connect the output end of the first subunit 2011 and the gate of the first output transistor T21. The signal output by the output end of the first subunit 2011 can be transmitted to the gate of the first output transistor T21 through the third connection portion 53.

[0135] Optional, such as Fig. 9 and Fig. 22 As shown, Fig. 22 for Fig. 9In a cross-sectional schematic diagram along B3-B3', the third connection portion 53 includes a first sub-connection portion 531, and the first sub-connection portion 531 includes a first electrode plate C21 of the second capacitor C2. In other words, the first electrode plate C21 of the second capacitor C2 can be reused as the first sub-connection portion 531. Based on this arrangement, there is no need to additionally set a connection portion for connecting the first subunit 2011 and the output module 4, which is conducive to simplifying the structure of the drive unit 20 and further reducing the area of ​​the drive unit 20.

[0136] In the embodiment of the present invention, at least one of the first output transistor T21 and the second output transistor T31 comprises a top-bottom double-gate structure. Fig. 9 and Fig. 22 As an example, the first output transistor T21 and the second output transistor T31 both include a top-bottom double-gate structure.

[0137] like Fig. 22 As shown, the first output transistor T21 includes an active layer S21, and a top gate G212 and a bottom gate G211 located on both sides of the active layer S21 in a direction h2 perpendicular to the plane of the substrate 1. The second output transistor T31 includes an active layer S31, and a top gate G312 and a bottom gate G311 located on both sides of the active layer S31 in a direction h2 perpendicular to the plane of the substrate 1. The top-bottom double-gate structure can improve the carrier mobility and subthreshold characteristics of the device.

[0138] For example, Fig. 22 As shown, the semiconductor layer S includes the active layer S21 of the first output transistor T21 and the active layer S31 of the second output transistor T31. The display panel also includes a second gate metal layer M0, which is located on a side of the semiconductor layer S close to the substrate 1. The second gate metal layer M0 includes the bottom gate G211 of the first output transistor T21 and the bottom gate G311 of the second output transistor T31, and the first gate metal layer M1 includes the top gate G212 of the first output transistor T21 and the top gate G312 of the second output transistor T31.

[0139] Optional, such as Fig. 22 As shown, the display panel further includes a first bottom gate connection portion F11, a first top gate connection portion F12 and a first gate connection portion F10 which are arranged in different layers.

[0140] Among them, along the direction h2 perpendicular to the plane of the substrate 1, the first bottom gate connection portion F11 and the first top gate connection portion F12 do not at least partially overlap with the active layer S21 of the first output transistor T21; and the first bottom gate connection portion F11 and the first top gate connection portion F12 do not at least partially overlap with the active layer S31 of the second output transistor T31.

[0141] In the embodiment of the present invention, at least one of the top gate G212 of the first output transistor T21 and the top gate G312 of the second output transistor T31 is disposed in the same layer and connected to the first top gate connection portion F12, that is, the first gate metal layer M1 includes the first top gate connection portion F12.

[0142] At least one of the bottom gate G211 of the first output transistor T21 and the bottom gate G311 of the second output transistor T31 is disposed in the same layer and connected to the first bottom gate connection portion F11. That is, the second gate metal layer M0 includes the first bottom gate connection portion F11.

[0143] Optional, combined Fig.23 As shown, Fig.23 for Fig. 9 A schematic cross-sectional view along B4-B4', along a direction h2 perpendicular to the plane where the substrate 1 is located, the first gate connection portion F10 is located on a side of the first gate metal layer M1 away from the second gate metal layer M0, Fig.23 The source-drain metal layer M2 includes a first gate connection portion F10 as an example. One end of the first gate connection portion F10 is electrically connected to the first top gate connection portion F12 through a via K21, and the other end of the first gate connection portion F1 is electrically connected to the first bottom gate connection portion F11 through a via K22. Based on this arrangement, the top gate and the bottom gate of the first output transistor T21 are prevented from being directly connected through a via that penetrates the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the first output transistor T21, which is conducive to improving process reliability.

[0144] Optional, such as Fig. 9 As shown, along the first direction h11, the first gate connection portion F10 is located between the first output transistor T21 and the second output transistor T31. Based on this arrangement, the first gate connection portion F10 can be used to connect the top gate G212 and the bottom gate G211 of the first output transistor T21, and also used to connect the top gate G312 and the bottom gate G311 of the second output transistor T31, that is, the first gate connection portion F10 can be shared by the first output transistor T21 and the second output transistor T31, and the number of gate connection portions used to connect the top gate and the bottom gate can be reduced, which is conducive to simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0145] For example, Figure 3As shown, the first subunit 2011 includes a first transistor T1, whose gate is electrically connected to the third node N3, and whose first electrode and second electrode are electrically connected to the first level signal terminal VGH and the first node N1 respectively. When the driving unit 20 is working, under the control of the third node N3, the first transistor T1 is turned on, and the second level signal provided by the first level signal terminal VGH can be written into the first node N1 through the first transistor T1. Optionally, the first transistor T1 includes a P-type transistor.

[0146] For example, Fig. 9 As shown, the third connection portion 53 connects the second electrode of the first transistor T1 and the output module 4 .

[0147] Optional, such as Fig. 9 As shown, the first transistor T1 is located on a side of the second capacitor C2 close to the first level signal connection line VGH, so as to shorten the distance between the first electrode of the first transistor T1 and the first level signal connection line VGH and facilitate the connection between the two.

[0148] Optionally, the first transistor T1 comprises a top-bottom double-gate structure. Fig. 9 As shown, the display panel further includes a gate connection portion F01, and the gate connection portion F01 is used to connect the top gate and the bottom gate of the first transistor T1. Optionally, the gate connection portion F01 can be located in the source-drain metal layer M2. Based on this arrangement, it is avoided that the top gate and the bottom gate of the first transistor T1 are directly connected through a via hole penetrating the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the first transistor T1, which is conducive to improving process reliability.

[0149] For example, Fig. 9 As shown, the gate connection portion F01 may be located between the second capacitor C2 and the first level signal connection line VGH.

[0150] Optional, such as Fig. 9 and Fig.12 As shown, along the second direction h12, the second capacitor C2 and the first capacitor C1 at least partially overlap. Along the second direction h12, the second capacitor C2 is located on the side of the first capacitor C1 close to the first level signal connection line VGH to shorten the distance between the second capacitor C2 and the first level signal connection line VGH, facilitating the connection between the two.

[0151] For example, Figure 3As shown, the driving unit 20 also includes a fourth node N4; the first processing module 21 also includes a fourth node writing unit 204 and a third capacitor C3; the fourth node writing unit 204 is used to electrically connect the second level signal terminal VGL and the fourth node N4 under the control of the first clock signal terminal CK; and, under the control of the third node N3, electrically connect the first clock signal terminal CK and the fourth node N4.

[0152] like Figure 3 As shown, in addition to the above-mentioned first subunit 2011, the first node writing unit 201 also includes a second subunit 2012. The second subunit 2012 is used to electrically connect the second clock signal terminal CKB and the first node N1 under the control of the fourth node N4.

[0153] like Figure 3 As shown, the first plate C31 of the third capacitor C3 is electrically connected to the fourth node N4; the second plate C32 of the third capacitor C3 is electrically connected to the second subunit 2012.

[0154] Optional, such as Fig.24 As shown, Fig.24 for Figure 4 An enlarged schematic diagram of the middle area E3 shows that along the first direction h11, at least part of the fourth node writing unit 204 and at least part of the second subunit 2012 are located on both sides of the third capacitor C3.

[0155] Wherein, along the first direction h11, the third capacitor C3 is located at the second capacitor C2 away from the first output transistor ( Fig.24 At least part of the fourth node writing unit 204 is located on a side of the third capacitor C3 away from the first output transistor, and at least part of the second subunit 2012 is located on a side of the third capacitor C3 close to the first output transistor.

[0156] Optional, such as Fig.24 As shown, the display panel further includes a fourth connection portion 54 , and the fourth connection portion 54 connects the fourth node writing unit 204 and the second sub-unit 2012 .

[0157] For example, Fig.24 and Fig.25 As shown, Fig.25 for Fig.24 In a cross-sectional view along B5-B5', the fourth connection portion 54 includes a second sub-connection portion 541, and the second sub-connection portion 541 includes a first electrode plate C31 of the third capacitor C3. Based on this arrangement, the first electrode plate C31 of the third capacitor C3 is reused as a connection structure connecting the fourth node writing unit 204 and the second sub-unit 2012, which is conducive to simplifying the structure of the driving unit 20.

[0158] For example, Figure 3 As shown, the second subunit 2012 includes a second transistor T2 and a third transistor T3; the gate of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode is electrically connected to the first electrode of the third transistor T3; the first electrode of the second transistor T2 and the gate of the third transistor T3 are both electrically connected to the second clock signal terminal CKB; the second electrode of the third transistor T3 is electrically connected to the first node N1.

[0159] For example, Fig.24 As shown, the display panel also includes a second clock signal connection line CKB, at least part of which extends along the first direction h11, and along the second direction h12, at least part of which is located on one side of the main body OUT10 of the second level signal connection line VGL close to the first output line OUT1.

[0160] Optionally, in the embodiment of the present invention, at least one of the second transistor T2 and the third transistor T3 may include a top-bottom double-gate structure to improve carrier mobility and subthreshold characteristics of the device.

[0161] Optional, combined Fig.26 and Fig. 27 As shown, Fig.26 for Fig.24 An enlarged schematic diagram of the middle area E4, Fig. 27 for Fig.26 A cross-sectional schematic diagram along B6-B6', the display panel also includes a second bottom gate connection portion F21, a second top gate connection portion F22 and a second gate connection portion F20; wherein, along a direction h2 perpendicular to the plane where the substrate 1 is located, the second top gate connection portion F22 and the second bottom gate connection portion F21 do not at least partially overlap with the active layer S2 of the second transistor T2.

[0162] In the embodiment of the present invention, the second bottom gate connection portion F21 is disposed in the same layer and connected to the bottom gate G21 of the second transistor T2, that is, the second gate metal layer M0 includes the second bottom gate connection portion F21. The second top gate connection portion F22 is disposed in the same layer and connected to the top gate G22 of the second transistor T2, that is, the first gate metal layer M1 includes the second top gate connection portion F22.

[0163] The second gate connection portion F20 is located on a side of the first gate metal layer M1 away from the second gate metal layer M0; Fig.26 and Fig. 27 The second gate connecting portion F20 is located in the source-drain metal layer M2 as an example.

[0164] like Fig.26 and Fig. 27As shown, one end of the second gate connection portion F20 is connected to the second top gate connection portion F22 through a via K31; the other end of the second gate connection portion F20 is connected to the second bottom gate connection portion F21 through a via K32. Based on this arrangement, the top gate and the bottom gate of the second transistor T2 are prevented from being directly connected through a via that penetrates the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the second transistor T2, which is conducive to improving process reliability.

[0165] like Fig.25 and Fig. 27 As shown, the first plate C31 of the third capacitor C3 is located on the first gate metal layer M1, and the second plate of the third capacitor C3 is located on the capacitor metal layer MC.

[0166] Optional, such as Fig. 27 As shown, the second top gate connection portion F22 includes a first electrode plate C31 of a third capacitor C3, that is, the first electrode plate C31 of the third capacitor C3 can be reused as a connection structure connecting the top gate G22 of the second transistor T2 and the second gate connection portion F20. Based on this arrangement, the space in the area where the third capacitor C3 is located can be fully utilized, which is beneficial to simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0167] For example, Fig.26 , Fig. 27 and Fig.28 As shown, Fig.28 for Fig.26 In a cross-sectional view along B7-B7', the display panel further includes a fifth connecting portion 55, which connects the second electrode C32 of the third capacitor C3, the first electrode of the third transistor T3, and the second electrode of the second transistor T2. Fig. 27 and Fig.28 As shown, the fifth connecting portion 55 is located at a side of the second electrode plate C32 of the third capacitor C3 away from the substrate 1 . Fig. 27 and Fig.28 The fifth connection portion 55 is located in the source-drain metal layer M2 as an example.

[0168] Optional, such as Fig. 27 As shown, in the embodiment of the present invention, the fifth connection portion 55 and the second gate connection portion F20 can be arranged in the same layer and spaced apart to avoid contact between the two. For example, the distance between the two can be set according to the process capability, which is not limited in the embodiment of the present invention.

[0169] Optional, such as Fig.29 and Fig.30 As shown, Fig.29 A schematic diagram of local wiring of another driving unit provided in an embodiment of the present invention, Fig.30 for Fig.29 In a cross-sectional schematic diagram along B8-B8', the fourth connection portion 54 further includes a third sub-connection portion 542. Along a direction h2 perpendicular to the plane where the substrate 1 is located, the third sub-connection portion 542 is located on a side of the third capacitor C3 away from the substrate 1. The third sub-connection portion 542 is connected to the first electrode plate C31 of the third capacitor C3 through at least two vias. The provision of the third sub-connection portion 542 can reduce the resistance of the fourth connection portion 54, thereby reducing signal delay.

[0170] Optional, such as Fig.31 As shown, Fig.31 for Fig.29 An enlarged schematic diagram of the source-drain metal layer in the middle region E5, the embodiment of the present invention can make the third sub-connection part 542 and the fifth connection part 55 in the same layer and spaced apart to avoid contact between the two. Fig.31 As shown, there is a distance m between the third sub-connection portion 542 and the fifth connection portion 55. By way of example, the distance between the two can be set according to the process capability, which is not limited in the embodiment of the present invention. Fig.31 The two are arranged in the same layer on the source-drain metal layer M2 as an illustration.

[0171] For example, Figure 3 As shown, the first processing module 21 further includes a second isolation transistor T12, the gate of the second isolation transistor T12 is electrically connected to the second level signal terminal VGL; the first electrode and the second electrode are electrically connected to the fourth node write unit 204 and the first electrode plate C31 of the third capacitor C3, respectively. The second isolation transistor T12 is used to be disconnected when the potential of the first electrode plate C31 of the third capacitor C3 is pulled down to a potential less than the first level signal, so as to isolate the connection between the fourth node write unit 204 and the first electrode plate C31 of the third capacitor C3, thereby improving the reliability of the transistor in the fourth node write unit 204.

[0172] For example, Fig.24 and Fig.29 As shown, along the second direction h12, the second isolation transistor T12 is located on the side of the second level signal connection line VGL close to the first level signal connection line VGH. Also, along the first direction h11, the second isolation transistor T12 is located on the side of the third capacitor C3 close to the fourth node writing unit 204.

[0173] like Fig.24 and Fig.29 As shown, the fourth connection portion 54 is electrically connected to the fourth node writing unit 204 through the second isolation transistor T12.

[0174] Optionally, the second isolation transistor T12 includes a top-bottom dual-gate structure. Fig.24 and Fig.29 As shown, the display panel also includes a gate connection portion F12, and the gate connection portion F12 is used to connect the top gate and the bottom gate of the second isolation transistor T12. Optionally, the gate connection portion F12 can be located in the source-drain metal layer M2. Based on this arrangement, it is avoided that the top gate and the bottom gate of the second isolation transistor T12 are directly connected through a via hole that penetrates the insulating layer between the two, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the second isolation transistor T12, which is conducive to improving process reliability.

[0175] Optional, such as Fig.24 , Fig.26 and Fig.29 As shown, the length of the third capacitor C3 in the second direction h12 is greater than or equal to the length in the first direction h11. Based on this setting, on the one hand, the area of ​​the third capacitor C3 can be set as large as possible to increase the driving capability of the driving unit 20. On the other hand, the space occupied by the driving unit 20 in the first direction h11 can also be saved, which is convenient for arranging more devices on both sides of the third capacitor C3 in the first direction h11.

[0176] Optional, such as Figure 3 As shown, the fourth node write unit 204 includes: a seventh transistor T7, a gate electrically connected to the first clock signal terminal CK, a first electrode electrically connected to the second level signal terminal VGL, and a second electrode electrically connected to the fourth node N4; an eighth transistor T8, a gate electrically connected to the third node N3, a first electrode electrically connected to the first clock signal terminal CK, and a second electrode electrically connected to the fourth node N4. Figure 3 As an example, the eighth transistor T8 includes a double-gate transistor.

[0177] like Fig.24 As shown, the display panel also includes a first clock signal connection line CK. Along the second direction h12, the first clock signal connection line CK is located between the first level signal connection line VGH and the second level signal connection line VGL. The seventh transistor T7 is located on the side of the eighth transistor T8 close to the second level signal connection line VGL to shorten the distance between the seventh transistor T7 and the second level signal connection line VGL, facilitating the connection between the first electrode of the seventh transistor T7 and the second level signal connection line VGL.

[0178] Optionally, at least one of the seventh transistor T7 and the eighth transistor T8 includes a top-bottom double-gate structure to improve carrier mobility and subthreshold characteristics of the device.

[0179] For example, Fig.24As shown, the display panel further includes a gate connection portion F7 and a gate connection portion F8, the gate connection portion F7 is used to connect the top gate and the bottom gate of the seventh transistor T7, and the gate connection portion F8 is used to connect the top gate and the bottom gate of the eighth transistor T8. Optionally, the gate connection portion F7 and the gate connection portion F8 can be located in the source-drain metal layer M2. Based on this arrangement, it is avoided that the top gate and the bottom gate of the seventh transistor T7 are directly connected through a via hole penetrating the insulating layer between the two, and it is avoided that the top gate and the bottom gate of the eighth transistor T8 are directly connected through a via hole penetrating the insulating layer between the two, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the two, which is conducive to improving process reliability.

[0180] Optional, such as Figure 3 As shown, the driving unit 20 further includes a second processing module 22, and the second processing module 22 is electrically connected to the second node N2.

[0181] like Figure 3 As shown, the second processing module 22 includes a fourth capacitor C4 and a third subunit 221, the first plate C41 of the fourth capacitor C4 and the third node writing unit 203 are electrically connected to the second node N2; the third subunit 221 is electrically connected to the second plate C42 of the fourth capacitor C4.

[0182] For example, Fig.24 and Fig.29 As shown, along the second direction h12, the fourth capacitor C4 is located between the second level signal connection line VGL and the main body OUT10 of the first output line OUT1. Moreover, the fourth capacitor C4 and the third capacitor C3 at least partially overlap in the second direction h12. And along the first direction h11, the fourth capacitor C4 is located on the side of the second clock signal connection line CKB away from the first capacitor C1.

[0183] Optional, such as Figure 4 As shown, along the first direction h11, the third node writing unit 203 and the first output module 41 are located on both sides of the fourth capacitor C4.

[0184] For example, Fig.32 and Fig.33 As shown, Fig.32 for Figure 4 An enlarged schematic diagram of the middle area E6, Fig.33 for Fig.32 A cross-sectional schematic diagram along B10-B10' shows that the display panel further includes a sixth connecting portion 56, and the sixth connecting portion 56 connects the third node writing unit and the first output module.

[0185] Optional, such as Fig.32 and Fig.33As shown, the sixth connection portion 56 includes a fourth sub-connection portion 561, and the fourth sub-connection portion 561 includes a first electrode plate C41 of a fourth capacitor C4. Based on this arrangement, the first electrode plate C41 of the fourth capacitor C4 can be reused as a part of the sixth connection portion 56, and the space in the area where the fourth capacitor C4 is located can be fully utilized, which is beneficial to reducing the occupied space of the driving unit 20 in the display panel.

[0186] Optional, such as Figure 3 As shown, the second node N2 includes a first subnode N21 and a second subnode N22 ; the first subnode N21 is electrically connected to the first plate C41 of the fourth capacitor C4 , and the second subnode N22 is electrically connected to the first output module 41 .

[0187] like Figure 3 As shown, the second processing module 22 also includes an adjusting transistor T40, the gate of the adjusting transistor T40 is electrically connected to the first subnode N21, and the first pole and the second pole are electrically connected to the first subnode N21 and the second subnode N22 respectively. When the potential of the first subnode N21 is less than the potential of the first level signal, for example, when the first subnode N21 is pulled down to the third level signal under the coupling effect of the fourth capacitor C4, the isolation transistor T40 is turned on, and the third level signal of the first subnode N21 can be written into the second subnode N22 through the isolation transistor T40. When the potential of the first subnode N21 is greater than or equal to the first level signal, the isolation transistor T40 is turned off, so that the second subnode N22 can maintain the third level signal. Based on this setting, the duration of the second subnode N22 being in the third level signal can be made longer than the duration of the first subnode N21 being in the third level signal, so that the third output transistor T22 can be stably turned on under the control of the second subnode N22.

[0188] Optional, such as Fig.32 As shown, along the first direction h11, the regulating transistor T40 is located on the side of the fourth capacitor C4 close to the third output transistor T22. Along the second direction h12, the regulating transistor T40 is located between the second level signal connection line VGL and the main body OUT10 of the first output line OUT1.

[0189] like Fig.32 As shown, the sixth connection portion 56 is electrically connected to the third output transistor T22 via the regulating transistor T40 .

[0190] Optional, such as Fig.32 and Fig.33 As shown, the regulating transistor T40 includes a top-bottom double-gate structure to improve the carrier mobility and subthreshold characteristics of the regulating transistor T40.

[0191] Combination Fig.34 As shown, Fig.34 for Fig.32 A schematic cross-sectional view along B11-B11', the display panel further includes a third gate connection portion F40, a third bottom gate connection portion F41 and a third top gate connection portion F42 arranged in different layers, wherein along a direction h2 perpendicular to the plane where the substrate 1 is located, the third bottom gate connection portion F41 and the third top gate connection portion F42 are both connected to the active layer ( Fig.34 not shown) at least partially do not overlap.

[0192] In the embodiment of the present invention, the bottom gate G401 of the regulating transistor T40 is disposed in the same layer and connected to the third bottom gate connection portion F41; that is, the second gate metal layer M0 includes the third bottom gate connection portion F41. The top gate G402 of the regulating transistor T40 is disposed in the same layer and connected to the third top gate connection portion F42; that is, the first gate metal layer M1 includes the third top gate connection portion F42.

[0193] The third gate connection portion F40 is located on a side of the first gate metal layer M1 away from the second gate metal layer M0. Fig.34 The source-drain metal layer M2 including the third gate connecting portion F40 is used as an example.

[0194] Optionally, one end of the third gate connection portion F40 is connected to the third bottom gate connection portion F41 through a via K52, and the other end of the third gate connection portion F40 is connected to the third top gate connection portion F42 through a via K51. Based on this arrangement, it is avoided that the top gate and the bottom gate of the regulating transistor T40 are directly connected through a via hole penetrating the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate of the regulating transistor T40, which is conducive to improving process reliability.

[0195] For example, Fig.32 As shown, along the first direction h11, the third gate connection portion F40 is located on the side of the fourth capacitor C4 away from the isolation transistor T40. Along the second direction h12, the third gate connection portion F40 is located between the second level signal connection line VGL and the second clock signal connection line CKB. Based on this arrangement, the space on the side of the fourth capacitor C4 away from the isolation transistor T40 can be fully utilized, which is conducive to reducing the difficulty of arranging the third gate connection portion F40.

[0196] Optional, such as Fig.33As shown, the third top gate connection portion F42 includes the first electrode plate C41 of the fourth capacitor C4. That is, the first electrode plate C41 of the fourth capacitor C4 can be reused as a connection structure connecting the top gate G402 of the regulating transistor T40 and the third gate connection portion F40. Based on this arrangement, the space in the area where the fourth capacitor C4 is located can be fully utilized, which is conducive to simplifying the structure of the driving unit 20 and reducing the occupied area of ​​the driving unit 20 in the display panel.

[0197] Optional, such as Figure 3 As shown, the second processing module 22 further includes a third isolation transistor T13, the gate of the third isolation transistor T13 is electrically connected to the second level signal terminal VGL, and the first electrode and the second electrode are electrically connected to the third node writing unit 203 and the second node N2 respectively. Figure 2 As shown, when the second node N2 is split into the first sub-node N21 and the second sub-node N22, the second electrode of the third isolation transistor T13 can be electrically connected to the first sub-node N21.

[0198] When the fourth capacitor C4 couples the potential of the first subnode N21 to a potential lower than the second level signal terminal VGL, for example, when the potential of the first subnode N21 is coupled to the third level signal, the third isolation transistor T13 is disconnected, which can prevent the third level signal of the first subnode N21 from affecting the reliability of the transistor in the third node write unit 203.

[0199] Optionally, the third isolation transistor T13 includes a P-type transistor.

[0200] like Fig.32 As shown, the sixth connection portion 56 is connected to the third node writing unit ( Fig.32 not shown) electrical connections.

[0201] Optional, such as Figure 3 As shown, the third node writing unit 203 includes a fourth transistor T4, a gate of which is electrically connected to the first clock signal terminal CK, a first electrode of which is electrically connected to the first input terminal IN1, and a second electrode of which is electrically connected to the third isolation transistor T13.

[0202] Optional, such as Figure 3 As shown, the third subunit 221 includes: a fifth transistor T5, a gate of which is electrically connected to the fourth node N4, a first electrode of which is electrically connected to the first level signal terminal VGH, and a second electrode of which is electrically connected to the second electrode plate C42 of the fourth capacitor C4; a sixth transistor T6, a gate of which is electrically connected to the first electrode plate C41 of the fourth capacitor C4, a first electrode of which is electrically connected to the second clock signal terminal CKB, and a second electrode of which is electrically connected to the second electrode plate C42 of the fourth capacitor C4.

[0203] Exemplarily, the fifth transistor T5 and the sixth transistor T6 include P-type transistors.

[0204] For example, Fig.24 and Fig.29 As shown, the sixth transistor T6 and the fourth capacitor C4 are arranged along the first direction h11, and the sixth transistor T6 is located on the side of the fourth capacitor C4 away from the regulating transistor T40. Along the second direction h12, the sixth transistor T6 is located between the second level signal connection line VGL and the second clock signal connection line CKB to shorten the distance between the sixth transistor T6 and the second clock signal connection line CKB, which is convenient for connecting the two.

[0205] Continue to refer to Fig.24 and Fig.29 As shown, the fifth transistor T5 and the sixth transistor T6 are arranged along the second direction h12, and, along the second direction h12, the fifth transistor T5 is located on the side of the sixth transistor T6 close to the first level signal connection line VGH, so as to shorten the distance between the first electrode of the fifth transistor T5 and the first level signal connection line VGH to facilitate the connection between the two.

[0206] For example, Fig.24 , Fig.29 and Fig.32 As shown, the gate of the sixth transistor T6 is connected to the gate of the third output transistor T22 through the first plate C41 of the fourth capacitor C4. That is, the first plate C41 of the fourth capacitor C4 can also be reused as a connecting portion between the gate of the sixth transistor T6 and the gate of the third output transistor T22. Based on this arrangement, the wiring structure of the driving unit 20 can be simplified, which is conducive to further reducing the area occupied by the driving unit 20 in the display panel.

[0207] Exemplarily, the fifth transistor T5 includes a top-bottom double-gate structure to improve carrier mobility and subthreshold characteristics of the fifth transistor T5.

[0208] like Fig.24 and Fig.29 As shown, the display panel further includes a gate connection portion F50, and the gate connection portion F50 connects the top gate and the bottom gate of the fifth transistor T5. Based on this arrangement, it is avoided that the top gate and the bottom gate of the fifth transistor T5 are directly connected through a via hole penetrating the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate, which is conducive to improving process reliability.

[0209] Exemplarily, the gate connection portion F50 and the third capacitor C3 are arranged along the first direction h11.

[0210] Optionally, the sixth transistor T6 includes a top-bottom double-gate structure to improve carrier mobility and subthreshold characteristics of the sixth transistor T6.

[0211] like Fig.24 , Fig.29 and Fig.32 As shown, the third gate connection portion F40 is also used to connect the top gate and the bottom gate of the sixth transistor T6. That is, the third gate connection portion F40 can be shared by the first regulating transistor T40 and the sixth transistor T6, which can reduce the number of gate connection portions used to connect the top gate and the bottom gate, which is conducive to simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0212] Optional, such as Figure 3 As shown, the driving unit 20 further includes a fourth isolation transistor T14, a gate of the fourth isolation transistor T14 is electrically connected to the second level signal terminal VGL, and a first electrode and a second electrode are electrically connected to the third node N3 and the second node N2 respectively.

[0213] like Fig. 22 , Fig.24 , Fig.29 and Fig.32 As shown, the fourth isolation transistor T14 includes a top-bottom double-gate structure to improve the carrier mobility and subthreshold characteristics of the fourth isolation transistor T14.

[0214] like Figure 3 , Fig. 22 , Fig.24 and Fig.29 As shown, the display panel further includes a gate connection portion F14, and the gate connection portion F14 is used to connect the top gate and the bottom gate of the fourth isolation transistor T14. Optionally, the fourth isolation transistor T14 can be located in the source-drain metal layer M2. Based on this arrangement, it is avoided that the top gate and the bottom gate of the fourth isolation transistor T14 are directly connected through a via hole penetrating the insulating layer therebetween, which can reduce the requirements for the etching process, and reduce the possibility of disconnection of the connection portion between the top gate and the bottom gate, which is conducive to improving process reliability.

[0215] Exemplarily, the first isolation transistor T11 may also include a top-bottom double-gate structure to improve the carrier mobility and subthreshold characteristics of the first isolation transistor T11.

[0216] Optionally, the gate connection portion F14 may also be connected to the bottom gate and the top gate of the first isolation transistor T11. Based on this arrangement, the gate connection portion F14 may be reused as a connection portion connecting the top gate and the bottom gate of the first isolation transistor T11, that is, the gate connection portion F14 may be shared by the fourth isolation transistor T14 and the first isolation transistor T11, and the number of gate connection portions used to connect the top gate and the bottom gate may be reduced, which is beneficial to simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0217] Optional, such as Figure 4 As shown, the length of the fourth capacitor C4 in the first direction h11 is greater than or equal to the length in the second direction h12. Based on this setting, on the one hand, the area of ​​the fourth capacitor C4 can be set as large as possible to increase the driving capability of the driving unit 20. On the other hand, the space occupied by the fourth capacitor C4 in the second direction h12 can also be reduced, so as to facilitate the arrangement of more devices on both sides of the fourth capacitor C4 in the second direction h12.

[0218] For example, Figure 4 As shown, along the second direction h12, the fourth capacitor C4 and the third capacitor C3 at least partially overlap.

[0219] For example, Figure 4 As shown, in the embodiment of the present invention, the fourth output transistor T32 and the third output transistor T31 can be arranged along the second direction h12, and the fourth output transistor T32 can be located at a side of the third output transistor T31 close to the first output line OUT1.

[0220] Optional, such as Figure 3 As shown, the second output module 42 also includes a fifth capacitor C5 electrically connected to the first control signal output terminal OUT2 and the gate of the fourth output transistor T32. In the process of outputting an enable level at the first output terminal OUT1 to control the conduction of the fourth output transistor T32, when the potential of the first control signal output terminal OUT2 jumps from a high-level signal to a low-level signal, under the action of the fifth capacitor C5, the potential of the gate of the fourth output transistor T32 will be coupled to a signal with a lower potential than the first-level signal provided by the second-level signal terminal VGL, thereby enhancing the conduction ability of the fourth output transistor T32.

[0221] Optional, such as Figure 4 As shown, the display panel further includes a first input line IN1, which is electrically connected to the first input terminal IN1 of the current stage driving unit 20. Exemplarily, along the second direction h12, at least a portion of the first input line IN1 is located on a side of the first clock signal connection line CK close to the first level signal connection line VGH.

[0222] Exemplarily, for any one of the 1st to N-1th driving units 20, the first output line OUT1 electrically connected to the first output terminal OUT1 of the corresponding driving unit 20 can be multiplexed as the first input line IN1 electrically connected to the first input terminal IN1 of the next driving unit 20. That is, one end of the first output line OUT1_i is connected to the first output terminal OUT1 of the driving unit 20_i, and the other end is connected to the first input terminal IN1 of the driving unit 20_i+1. Wherein, i is an integer, and 1≤i≤N-1.

[0223] Optional, such as Figure 2 As shown, the driving unit 20 includes at least two third node writing units 203, one of which is electrically connected to the first processing module 21; and the other is electrically connected to the second processing module 22. Based on this setting, the potential disturbance of the second node N2 can be prevented from affecting the working stability of the first processing module 21. Figure 3 203_1 and 203_2 are used to distinguish the third node write unit electrically connected to the first processing module 21 and the third node write unit electrically connected to the second processing module 22, and T4_1 and T4_2 are used to distinguish the fourth transistor electrically connected to the first processing module 21 and the fourth transistor electrically connected to the second processing module 22.

[0224] Optional, such as Figure 4 As shown, at least two third node writing units 203 are arranged adjacent to each other. The fourth transistor T4_1 and the fourth transistor T4_2 can be arranged adjacent to each other along the first direction h11. Based on this arrangement, the distance between the two fourth transistors and the first input line IN1 can be shortened, which facilitates the connection between the first input line IN1 and the two fourth transistors.

[0225] Optional, such as Figure 4 As shown, the display panel further includes a first control signal input line IN21, a second control signal input line IN22 and a first control signal output line OUT2, and the first control signal output line OUT2 is respectively connected to the first electrode of the fifth capacitor C5 and the second electrode of the fourth output transistor T32.

[0226] Optional, such as Figure 3 As shown, the driving unit 20 further includes a reset transistor T50, a gate of which is electrically connected to the reset control signal terminal RST, and a first electrode and a second electrode of which are electrically connected to the first level signal terminal VGH and the third node N3 respectively.

[0227] For example, Figure 4As shown, along the first direction h11, the reset transistor T50 is located between the fourth transistor T4 and the seventh transistor T7. Also, along the second direction h12, the reset transistor T50 is located between the fourth transistor T4 and the second level signal connection line VGL.

[0228] like Figure 4 As shown, the display panel further includes a reset control connection line RST. Along the second direction h12, the reset control connection line RST is located between the first clock signal connection line CK and the second level signal connection line VGL.

[0229] For example, Figure 4 As shown, the display panel further includes a third node connection line 6, which is located on a side of the first level signal connection line VGH close to the third capacitor C3. The third node connection line 6 is respectively connected to the second electrode of the fourth transistor T4_1, the gate of the eighth transistor T8 and the first electrode of the fourth isolation transistor T14. Optionally, the third node connection line 6 can be located in the first gate metal layer M1.

[0230] For example, Figure 4 As shown, the driving unit 20 includes a first area D1 and a second area D2 arranged along the second direction h12, the first area D1 includes at least part of the first processing module 21, and the second area D2 includes at least part of the second processing module 22. Based on this arrangement, the first processing module 21 and the second processing module 22 can be arranged in different areas as much as possible, which is conducive to increasing the distance between different structures in the first processing module 21 and the second processing module 22 and weakening the coupling.

[0231] like Figure 4 As shown, the first region D1 includes a first sub-region D11, a second sub-region D12 and a third sub-region D13 arranged along the first direction h11, and the third sub-region D13 is located on a side of the second sub-region D12 away from the first sub-region D11; the first sub-region D11 includes a third node writing unit 203 and a fourth node writing unit 204; the second sub-region D12 includes a third capacitor C3 and a second sub-unit 2012; and the third sub-region D13 includes a second capacitor C2 and a first sub-unit 2011. Based on this arrangement, it is beneficial to reduce the width of the driving unit 20 in the second direction h12.

[0232] For example, Figure 1 As shown, the display panel includes a display area AA, and the display area AA includes the above-mentioned pixel circuit 3. Optionally, as Figure 1 As shown, the embodiment of the present invention can set the driving unit 20 in the display area AA. Figure 1As shown, along the second direction h12, the embodiment of the present invention can make the driving unit 20 located between two adjacent circuit units 30, and the circuit unit 30 includes at least one pixel circuit 3. Figure 1 The circuit unit 30 includes three pixel circuits 3 as an example. Based on this arrangement, there is no need to set up an additional area for accommodating the driving circuit 2 outside the display area AA, and a borderless design of the display panel can be achieved. When multiple display panels are spliced ​​to form a large-screen display device with a larger size, the visibility of the splicing seam between two adjacent display panels can be weakened or even eliminated, which can improve the visual effect of the large-screen display device.

[0233] When the first output module 41 and the second output module 42 are set, for example, Figure 4 As shown, the embodiment of the present invention can arrange the first output module 41 and the second output module 42 along the first direction h11 to fully utilize the width of the space where the multiple pixel circuits 3 are located and reduce the length of the driving unit 20 in the second direction h12.

[0234] Optional, such as Figure 4 As shown, the length of the driving unit 20 in the first direction h11 is d1, and the length in the second direction h12 is d2, and d1>d2.

[0235] For example, Figure 4 As shown, the first input line IN1 includes a first extension portion IN11 extending along the second direction h12, and the second control signal input line IN22 includes a second extension portion IN221 extending along the second direction h12. The length of the driving unit 20 in the first direction h11 may be the distance between the first extension portion IN11 and the second extension portion IN221. The length of the driving unit 20 in the second direction h12 may be the distance between the first level signal connection line VGH and the main body OUT10 of the first output line OUT1 in the second direction h12.

[0236] For example, Figure 2 As shown, the display panel further includes a first clock line C1 and a second clock line C2, the first clock line C1 is electrically connected to the first clock signal terminal CK of the odd-numbered driving unit 20, and is electrically connected to the second clock signal terminal CKB of the even-numbered driving unit 20. The second clock line C1 is electrically connected to the second clock signal terminal CKB of the odd-numbered driving unit 20, and is electrically connected to the first clock signal terminal CK of the even-numbered driving unit 20.

[0237] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.35 As shown, Fig.35 A schematic diagram of a display device provided in an embodiment of the present invention, the display device includes the above-mentioned display panel 100.

[0238] For example, Fig.35 As shown, the display device includes a spliced ​​display device. The spliced ​​display device includes at least two display panels 100 described above, so as to be applicable to a large-screen display device with a display function, such as a frameless spliced ​​display device.

[0239] For example, this type of spliced ​​display device can be used in public information display (PID) scenarios such as stations and airports. When the spliced ​​display device includes the above-mentioned display panel 100, the area occupied by the driving circuit can be reduced, thereby achieving a seamless / borderless splicing effect of the spliced ​​display device.

[0240] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0241] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; a driving circuit and a first output line located on one side of the substrate; At least a portion of the first output line extends along a first direction; The driving circuit comprises a plurality of driving units arranged in cascade, and the plurality of driving units are arranged along a second direction; the second direction intersects with the first direction; The driving unit comprises a first output terminal; the first output line is connected to the first output terminal of the driving unit at the current stage; The driving unit includes an output module, the output module includes a first capacitor, and the first capacitor is electrically connected to the first output terminal. and, Along a direction perpendicular to a plane where the substrate is located, the first output line at least partially overlaps with at least one plate of the first capacitor.

2. The display panel according to claim 1, characterized in that: Also included is a pixel circuit, the pixel circuit receiving a first control signal; The driving unit further includes a first control signal output terminal, and the first control signal output terminal is used to output the first control signal under the control of the first output terminal.

3. The display panel according to claim 2, characterized in that: The output module includes a first output module and a second output module; The first output module electrically connects the output terminal and the first level signal terminal in response to a signal of the first node, and electrically connects the cascade signal output terminal and the second level signal terminal in response to a signal of the second node; The second output module electrically connects the first control signal output terminal and the first control signal input terminal in response to the signal of the first node; and electrically connects the first control signal output terminal and the second control signal input terminal in response to the signal of the first output terminal.

4. The display panel according to claim 3, characterized in that: The pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module, and the pulse width modulation module receives a frequency sweep signal; The first control signal includes the frequency sweep signal; The first control signal input terminal includes a constant signal terminal; The second control signal input terminal includes a frequency sweep input signal terminal.

5. The display panel according to claim 1, characterized in that: The first output line includes a first connection portion, which overlaps with at least one plate of the first capacitor along a direction perpendicular to the plane where the substrate is located; wherein the first connection portion is located on a side of at least one plate of the first capacitor away from the substrate.

6. The display panel according to claim 5, characterized in that: The first electrode plate of the first capacitor is electrically connected to the first output end, the first connecting portion is located on a side of the first electrode plate away from the substrate, and the first connecting portion is electrically connected to the first electrode plate through a hole.

7. The display panel according to claim 6, characterized in that: The first connecting portion is electrically connected to the first electrode plate through at least two via holes, and the two via holes are arranged at intervals.

8. The display panel according to claim 5, characterized in that: The first plate of the first capacitor is electrically connected to the first output terminal, the second plate of the first capacitor is electrically connected to the second level signal terminal, the first plate is located on a side of the second plate away from the substrate, and at least part of the first plate is reused as the first connecting portion.

9. The display panel according to claim 5, characterized in that: The width of the first connection portion in the first direction is greater than the line width of other parts of the output line.

10. The display panel according to claim 3, characterized in that: The driving unit further includes a first isolation transistor; The gate of the first isolation transistor is connected to the second level signal terminal, the first electrode is connected to the first output line, and the second electrode is electrically connected to the second output module.

11. The display panel according to claim 10, characterized in that: The display panel further includes a second connection portion, wherein the second connection portion connects a second electrode of the first isolation transistor and the second output module; Along a direction perpendicular to a plane where the substrate is located, the first output line and the second connecting portion do not overlap.

12. The display panel according to claim 11, characterized in that: Along the first direction, the first output line is at least partially located on a side of the second connecting portion away from the second output module.

13. The display panel according to claim 3, characterized in that: The driving unit further comprises: A first input terminal; The third node; A third node writing unit, used for electrically connecting the first input terminal and the third node under the control of the first clock signal terminal; A first processing module electrically connected to the first node, the first processing module includes a second capacitor and a first node writing unit; the first node writing unit includes a first subunit, and the first subunit is used to electrically connect the first level signal terminal and the first node under the control of the third node.

14. The display panel according to claim 13, characterized in that: The display panel further includes a third connection portion connecting the first subunit and the output module.

15. The display panel according to claim 14, characterized in that: The third connection portion includes a first sub-connection portion, and the first sub-connection portion includes a first plate of the second capacitor.

16. The display panel according to claim 14, characterized in that: The first output module comprises a first output transistor, a gate of which is electrically connected to the first node; The second output module comprises a second output transistor, a gate of which is electrically connected to the first node; At least one of the first output transistor and the second output transistor includes a top-bottom double gate structure.

17. The display panel according to claim 16, characterized in that: The display panel further includes a first gate connection portion, a first bottom gate connection portion and a first top gate connection portion which are arranged in different layers, wherein: A bottom gate of at least one of the first output transistor and the second output transistor is disposed in the same layer and connected to the first bottom gate connecting portion; A top gate of at least one of the first output transistor and the second output transistor is disposed in the same layer and connected to the first top gate connecting portion; One end of the first gate connection portion is electrically connected to the first bottom gate connection portion through a via hole, and the other end of the first gate connection portion is electrically connected to the first top gate connection portion through a via hole.

18. The display panel according to claim 14, characterized in that: The first subunit includes a first transistor, a gate of which is electrically connected to the third node, and a first electrode and a second electrode of which are electrically connected to the first level signal terminal and the first node respectively; The third connection portion connects the first transistor and the output module.

19. The display panel according to claim 13, characterized in that: Along the second direction, the second capacitor and the first capacitor at least partially overlap.

20. The display panel according to claim 13, characterized in that: The driving unit further includes a fourth node; The first processing module further includes a fourth node writing unit and a third capacitor; The fourth node writing unit is used to electrically connect the second level signal terminal and the fourth node under the control of the first clock signal terminal; and, under the control of the third node, electrically connect the first clock signal terminal and the fourth node; The first node writing unit further includes a second subunit, The first plate of the third capacitor is electrically connected to the fourth node; the second plate of the third capacitor is electrically connected to the second subunit; The second subunit is used to electrically connect a second clock signal terminal and the first node under the control of the fourth node.

21. The display panel according to claim 20, characterized in that: The display panel further includes a fourth connecting portion, The fourth connection portion connects the fourth node writing unit and the second sub-unit.

22. The display panel according to claim 21, characterized in that: The fourth connection portion includes a second sub-connection portion, and the second sub-connection portion includes a first plate of the third capacitor.

23. The display panel according to claim 20, characterized in that: The second subunit includes a second transistor and a third transistor; The gate of the second transistor is electrically connected to the fourth node, and the second electrode is electrically connected to the first electrode of the third transistor; the first electrode of the second transistor and the gate of the third transistor are both electrically connected to the second clock signal terminal; the second electrode of the third transistor is electrically connected to the first node.

24. The display panel according to claim 23, characterized in that: The second transistor comprises a top-bottom dual-gate structure; The display panel further includes a second gate connection portion, a second bottom gate connection portion and a second top gate connection portion arranged in different layers; wherein, The bottom gate of the second transistor is arranged in the same layer and connected to the second bottom gate connecting portion; The top gate of the second transistor is arranged in the same layer and connected to the second top gate connecting portion; One end of the second gate connection portion is connected to the second top gate connection portion through a via hole; the other end of the second gate connection portion is connected to the second bottom gate connection portion through a via hole.

25. The display panel according to claim 24, characterized in that: The second top gate connection includes a first plate of the third capacitor.

26. The display panel according to claim 24, characterized in that: The display panel further includes a fifth connection portion, wherein the fifth connection portion connects the second electrode plate of the third capacitor, the first electrode of the third transistor, and the second electrode of the second transistor; The fifth connecting portion is located at a side of the third capacitor away from the substrate.

27. The display panel according to claim 26, characterized in that: The fifth connection portion and the second gate connection portion are in the same layer and are spaced apart from each other.

28. The display panel according to claim 26, characterized in that: The fourth connection portion also includes a third sub-connection portion, which is located on a side of the third capacitor away from the substrate along a direction perpendicular to the plane where the substrate is located, and is connected to the first plate of the third capacitor through at least two vias.

29. The display panel according to claim 28, characterized in that: The third sub-connection portion and the fifth connection portion are in the same layer and are spaced apart.

30. The display panel according to claim 21, characterized in that: The first processing module further includes a second isolation transistor, The gate of the second isolation transistor is electrically connected to the second level signal terminal; The fourth connection portion is electrically connected to the fourth node writing unit through the second isolation transistor.

31. The display panel according to claim 20, characterized in that: A length of the third capacitor in the second direction is greater than or equal to a length of the third capacitor in the first direction.

32. The display panel according to claim 20, characterized in that: The driving unit further includes a second processing module, wherein the second processing module is electrically connected to the second node; The second processing module includes a fourth capacitor and a third subunit, The first plate of the fourth capacitor and the third node writing unit are electrically connected to the second node; The third subunit is electrically connected to the second plate of the fourth capacitor.

33. The display panel according to claim 32, characterized in that: The display panel further includes a sixth connection portion, wherein the sixth connection portion connects the third node writing unit and the first output module; The sixth connection portion includes a fourth sub-connection portion, and the fourth sub-connection portion includes a first plate of the fourth capacitor.

34. The display panel according to claim 33, characterized in that: The second node includes a first subnode and a second subnode; The first sub-node is electrically connected to the first plate of the fourth capacitor, and the second sub-node is electrically connected to the first output module; The second processing module further includes a regulating transistor electrically connected to the first sub-node and the second sub-node, wherein a gate of the regulating transistor is connected to the first sub-node; The sixth connection portion is electrically connected to the first output module through the regulating transistor.

35. The display panel according to claim 34, characterized in that: The regulating transistor comprises a top-bottom dual-gate structure; The display panel further includes a third gate connection portion, a third bottom gate connection portion and a third top gate connection portion arranged in different layers; wherein, The bottom gate of the regulating transistor is arranged in the same layer and connected to the third bottom gate connecting portion; The top gate of the regulating transistor is arranged in the same layer and connected to the third top gate connecting portion; One end of the third gate connection portion is connected to the third bottom gate connection portion through a via hole, and the other end of the third gate connection portion is connected to the third top gate connection portion through a via hole.

36. The display panel according to claim 35, characterized in that: The third top gate connection includes a first plate of the fourth capacitor.

37. The display panel according to claim 33, characterized in that: The second processing module further includes a third isolation transistor electrically connected between the third node writing unit and the second node, and a gate of the third isolation transistor is electrically connected to the second level signal terminal; The sixth connection portion is electrically connected to the third node writing unit through the third isolation transistor.

38. The display panel according to claim 37, characterized in that: The third node writing unit includes a fourth transistor, a gate of which is electrically connected to the first clock signal terminal, a first electrode of which is electrically connected to the first input terminal, and a second electrode of which is electrically connected to the third isolation transistor through the sixth connecting portion.

39. The display panel according to claim 33, characterized in that: The third subunit comprises: a fifth transistor, a gate electrically connected to the fourth node, a first electrode electrically connected to the first level signal terminal, and a second electrode electrically connected to the second plate of the fourth capacitor; a sixth transistor, a gate electrically connected to the first plate of the fourth capacitor, a first electrode electrically connected to the second clock signal terminal, and a second electrode electrically connected to the second plate of the fourth capacitor; The gate of the sixth transistor is connected to the first output module through the first plate of the fourth capacitor.

40. The display panel according to claim 32, characterized in that: A length of the fourth capacitor in the first direction is greater than or equal to a length in the second direction.

41. The display panel according to claim 32, characterized in that: Along the second direction, the fourth capacitor and the third capacitor at least partially overlap.

42. The display panel according to claim 32, characterized in that: The driving unit includes a first area and a second area arranged along the second direction, The first region includes at least a portion of the first processing module; The second region includes at least a portion of the second process module.

43. The display panel according to claim 42, characterized in that: The first region includes a first sub-region, a second sub-region and a third sub-region arranged along the first direction, and the third sub-region is located on a side of the second sub-region away from the first sub-region; The first sub-area includes the third node writing unit and the fourth node writing unit; The second sub-region includes the third capacitor and the second sub-unit; The third sub-region includes the second capacitor and the first sub-unit.

44. The display panel according to claim 13, characterized in that: The driving unit includes at least two third node writing units, one of which is electrically connected to the first processing module; and the other of which is electrically connected to the second processing module.

45. The display panel according to claim 44, characterized in that: At least two of the third node writing units are adjacently arranged.

46. ​​A display device, characterized in that: A display panel comprising any one of claims 1-45.

Images