Pixel driving circuit and driving method thereof, display panel and display device

Abstract

Some embodiments of the present disclosure provide a pixel driving circuit and a driving method thereof, a display panel and a display device, and relate to the technical field of display, and are used to solve the problem of residual image in the display field. The pixel driving circuit comprises a first light-emitting control sub-circuit, a first initialization sub-circuit, a driving sub-circuit and a second light-emitting control sub-circuit; the first light-emitting control sub-circuit is coupled with a first voltage signal end, a first node and a first light-emitting control end; the first initialization sub-circuit is coupled with an initialization signal end, a second node and a first scanning signal end; the driving sub-circuit is coupled with the first node, the second node and a third node; and the second light-emitting control sub-circuit is coupled with the third node, a light-emitting device, the first light-emitting control end and a second light-emitting control end. The time when the second light-emitting control signal jumps to the effective level is earlier than the time when the first light-emitting control signal jumps to the effective level. The pixel driving circuit provided by the embodiments of the present disclosure is used to drive the light-emitting device to emit light.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel driving circuit, a driving method thereof, a display panel and a display device. BACKGROUND

[0002] Currently, in the driving process of the pixel driving circuit in the display technology, due to the hysteresis effect of the driving transistor, when the corresponding display product switches from a black and white picture to a 48 gray scale picture after lighting the black and white picture for a period of time, a residual image is found, and then the residual image phenomenon disappears after a period of time, which is short-term residual image. In the currently used pixel driving circuit, the gate-source voltage VGS of the driving transistor in the initialization stage is different under different picture switching, which causes the short-term residual image phenomenon. SUMMARY

[0003] The purpose of some embodiments of the present disclosure is to provide a pixel driving circuit, a driving method thereof, a display panel and a display device, which can solve the problem of short-term residual image.

[0004] To achieve the above-mentioned purpose, some embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a pixel driving circuit is provided. The pixel driving circuit includes a first light emitting control sub-circuit, a first initialization sub-circuit, a driving sub-circuit and a second light emitting control sub-circuit. The first light emitting control sub-circuit is coupled with a first voltage signal terminal, a first node and a first light emitting control terminal; the first light emitting control sub-circuit is configured to be turned on in response to a first light emitting control signal from the first light emitting control terminal, and transmit a first voltage signal from the first voltage signal terminal to the first node; the first initialization sub-circuit is coupled with an initialization signal terminal, a second node and a first scan signal terminal; the first initialization sub-circuit is configured to be turned on in response to a first scan signal from the first scan signal terminal, and transmit an initialization signal from the initialization signal terminal to the second node; the driving sub-circuit is coupled with the first node, the second node and a third node; the driving sub-circuit is configured to be turned on in response to an electrical signal from the second node, and transmit an electrical signal from the first node to the third node; the second light emitting control sub-circuit is coupled with the third node, a light emitting device, the first light emitting control terminal and a second light emitting control terminal; the second light emitting control sub-circuit is configured to be turned on in response to the first light emitting control signal and a second light emitting control signal from the second light emitting control terminal, and transmit an electrical signal of the third node to the light emitting device; wherein the time when the second light emitting control signal jumps to an effective level is earlier than the time when the first light emitting control signal jumps to an effective level.

[0006] In the pixel driving circuit provided by the present disclosure, the first light-emitting control sub-circuit is configured to be turned on in response to the first light-emitting control signal from the first light-emitting control terminal and transmit the first voltage signal from the first voltage signal terminal to the first node. The first initialization sub-circuit is configured to be turned on in response to the first scanning signal from the first scanning signal terminal and transmit the initialization signal from the initialization signal terminal to the second node. The driving sub-circuit is configured to be turned on in response to the electrical signal from the second node and transmit the electrical signal from the first node to the third node. The second light-emitting control sub-circuit is configured to be turned on in response to the first light-emitting control signal and the second light-emitting control signal from the second light-emitting control terminal and transmit the electrical signal of the third node to the light-emitting device. The time when the second light-emitting control signal jumps to the effective level is earlier than the time when the first light-emitting control signal jumps to the effective level. When the first light-emitting control sub-circuit and the first initialization sub-circuit are turned on, the driving sub-circuit receives the first voltage signal transmitted by the first voltage signal terminal and the initialization signal transmitted by the initialization signal terminal. At this time, the gate-source voltage of the transistor in the driving sub-circuit is a fixed value, which can ensure that the starting state of the gate-source voltage of the transistor in the driving sub-circuit is consistent at each gray scale refresh, thereby avoiding the afterimage problem caused by different gray scale pictures.

[0007] In some embodiments, the second light-emitting control sub-circuit includes a first transistor and a second transistor; a first electrode of the first transistor is coupled with the third node, and a second electrode of the first transistor is coupled with the light-emitting device; a control electrode of the second transistor is coupled with the first light-emitting control terminal, a first electrode of the second transistor is coupled with the second light-emitting control terminal, and a second electrode of the second transistor is coupled with the control electrode of the first transistor.

[0008] In some embodiments, the channel width of the second transistor of the second light-emitting control sub-circuit is greater than the channel length.

[0009] In some embodiments, the first light-emitting control sub-circuit includes a third transistor, a control electrode of the third transistor is coupled with the first light-emitting control terminal, a first electrode of the third transistor is coupled with the first voltage signal terminal, and a second electrode of the third transistor is coupled with the first node; the driving sub-circuit includes a fourth transistor, a control electrode of the fourth transistor is coupled with the second node, a first electrode of the fourth transistor is coupled with the first node, and a second electrode of the fourth transistor is coupled with the third node; and the first initialization sub-circuit includes a fifth transistor, a control electrode of the fifth transistor is coupled with the first scanning signal terminal, a first electrode of the fifth transistor is coupled with the initialization signal terminal, and a second electrode of the fifth transistor is coupled with the second node.

[0010] In some embodiments, the first transistor of the first light emitting control sub-circuit has the same channel width-length ratio as the third transistor, and both have a channel width-length ratio greater than that of the fourth transistor; the light emitting device is an OLED light emitting device, and the fourth transistor of the driving sub-circuit has a channel width less than a channel length; or, the light emitting device is an MLED light emitting device, and the fourth transistor of the driving sub-circuit has a channel width greater than a channel length.

[0011] In some embodiments, the pixel driving circuit further comprises a second initialization sub-circuit, a data writing sub-circuit, and a compensation sub-circuit; the second initialization sub-circuit is coupled to the initialization signal terminal, the light emitting device, and the first scan signal terminal; the second initialization sub-circuit is configured to conduct in response to a first scan signal from the first scan signal terminal, and transmit an initialization signal from the initialization signal terminal to the light emitting device; the data writing sub-circuit is coupled to the second scan signal terminal, the data signal terminal, and the first node; the data writing sub-circuit is configured to conduct in response to a second scan signal from the second scan signal terminal, and transmit a data signal from the data signal terminal to the first node; the compensation sub-circuit is coupled to the second scan signal terminal, the second node, and the third node; the compensation sub-circuit is configured to conduct in response to the second scan signal from the second scan signal terminal, and transmit a voltage from the second node to the third node.

[0012] In some embodiments, the second initialization sub-circuit comprises a sixth transistor, a control electrode of the sixth transistor is coupled to the first scan signal terminal, a first electrode of the sixth transistor is coupled to the initialization signal terminal, and a second electrode of the sixth transistor is coupled to the fourth node; the data writing sub-circuit comprises a seventh transistor, a control electrode of the seventh transistor is coupled to the second scan signal terminal, a first electrode of the seventh transistor is coupled to the data signal terminal, and a second electrode of the seventh transistor is coupled to the first node; the compensation sub-circuit comprises an eighth transistor, a control electrode of the eighth transistor is coupled to the second scan signal terminal, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the third node.

[0013] In some embodiments, the channel width of the sixth transistor and the seventh transistor is greater than the channel length.

[0014] In some embodiments, the first scan signal transmitted by the first scan signal terminal is earlier than the second scan signal transmitted by the second scan signal terminal.

[0015] In some embodiments, the second light-emitting control signal and the first scan signal are inverse signals of each other, and / or the first light-emitting control signal and the second scan signal are inverse signals of each other.

[0016] In another aspect, a driving method of a pixel driving circuit is provided, including the pixel driving circuit according to any one of the above aspects. One frame period includes an initialization stage and a light-emitting stage. The driving method includes:

[0017] In the initialization stage, a first light-emitting control sub-circuit of the pixel driving circuit is turned on in response to a first light-emitting control signal from a first light-emitting control terminal, and a first voltage signal from a first voltage signal terminal is transmitted to the first node;

[0018] A first initialization sub-circuit of the pixel driving circuit is turned on in response to a first scan signal from a first scan signal terminal, and an initialization signal from an initialization signal terminal is transmitted to the second node;

[0019] In the light-emitting stage, the first light-emitting control sub-circuit is turned on in response to the first light-emitting control signal from the first light-emitting control terminal, and the second light-emitting control sub-circuit is turned on in response to the first light-emitting control signal and a second light-emitting control signal from a second light-emitting control terminal, to form a path between the first voltage signal terminal and the light-emitting device, and drive the light-emitting device to emit light.

[0020] In some embodiments, the pixel driving circuit further includes a data writing sub-circuit and a compensation sub-circuit, and one frame period further includes a data writing stage between the initialization stage and the light-emitting stage.

[0021] In the data writing stage, the data writing sub-circuit is turned on in response to a second scan signal from a second scan signal terminal, and a data signal from a data signal terminal is transmitted to the first node; the driving sub-circuit is turned on in response to an electrical signal from the second node, and the electrical signal from the first node is transmitted to the third node; and the compensation sub-circuit is turned on in response to the second scan signal from the second scan signal terminal, and the electrical signal from the third node is transmitted to the second node, to compensate the driving sub-circuit.

[0022] The driving method of the pixel driving circuit provided by the embodiments of the present disclosure can achieve the same beneficial effects as the pixel driving circuit described in the above embodiments, which will not be repeated here.

[0023] In yet another aspect, a display panel is provided, comprising a plurality of pixel driving circuits as described in any of the above aspects, and a gate driving circuit; the gate driving circuit comprises a plurality of cascaded shift register units, wherein an Nth shift register unit is electrically connected to a first scan signal terminal and a first light-emitting control signal terminal of the pixel driving circuit of the Nth row, and an N+1th shift register unit is electrically connected to a second scan signal terminal and a second light-emitting control signal terminal of the pixel driving circuit of the Nth row.

[0024] The display panel provided by the embodiments of the present disclosure can achieve the same beneficial effects as the pixel driving circuit provided by the above-mentioned embodiments, which will not be repeated here.

[0025] In some embodiments, the shift register unit comprises a scan signal generation circuit and an inverter; the scan signal generation circuit is electrically connected to the scan signal terminal; the scan signal generation circuit is configured to generate a scan signal and transmit it to the scan signal terminal; the inverter is electrically connected to the scan signal terminal and the light-emitting control signal terminal; the inverter is configured to invert the scan signal as a light-emitting control signal and transmit it to the light-emitting control signal terminal.

[0026] In yet another aspect, a display device is provided, comprising the display panel as described in any of the above aspects.

[0027] The display device provided by the embodiments of the present disclosure can achieve the same beneficial effects as the display panel provided by the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0029] In the drawings:

[0030] Figure 1 A structural diagram of a display device provided by the embodiments of the present disclosure is shown in the drawings;

[0031] Figure 2 A pixel arrangement diagram of a display panel provided by the embodiments of the present disclosure is shown in the drawings;

[0032] Figure 3 A pixel architecture diagram of a display panel provided by the embodiments of the present disclosure is shown in the drawings;

[0033] Figure 4A A structure diagram of a pixel driving circuit provided for some embodiments of the related art is provided.

[0034] Figure 4B A timing diagram of a pixel driving circuit provided for some embodiments of the related art is provided.

[0035] Figure 5A A structure diagram of a display panel in a picture display state provided for embodiments of the present disclosure is provided.

[0036] Figure 5B Another structure diagram of a display panel in a picture display state provided for embodiments of the present disclosure is provided.

[0037] Figure 5C Still another structure diagram of a display panel in a picture display state provided for embodiments of the present disclosure is provided.

[0038] Figure 6A A curve change diagram of current and gray scale voltage of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0039] Figure 6B A curve change diagram of current and gray scale voltage of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0040] Figure 7 A pixel driving circuit diagram provided for embodiments of the present disclosure is provided.

[0041] Figure 8 A timing control diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0042] Figure 9A A timing control diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0043] Figure 9B A timing control diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0044] Figure 9C A driving process diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0045] Figure 10A A timing control diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0046] Figure 10B A timing control diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0047] Figure 10C A driving process diagram of a pixel driving circuit provided for embodiments of the present disclosure is provided.

[0048] Figure 11A A timing control diagram of the pixel driving circuit provided by an embodiment of the present disclosure;

[0049] Figure 11B A timing control diagram of the pixel driving circuit provided by an embodiment of the present disclosure;

[0050] Figure 11C A driving process diagram of the pixel driving circuit provided by an embodiment of the present disclosure;

[0051] Figure 12 An equivalent circuit diagram of the shift register unit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0053] Unless otherwise required by context, the term “comprises” in the specification and claims is to be interpreted as open, inclusive, meaning “including but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example” or “some examples” are intended to mean that the particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0054] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of “a plurality of” is two or more.

[0055] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" as used herein encompasses the case where one or more intervening elements can exist. The embodiments disclosed herein are not necessarily limited to the details of the embodiments described.

[0056] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C," and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0057] "A and / or B" includes the following combinations: A alone, B alone, and a combination of A and B.

[0058] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to a determination" or "in response to a detection of," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" is, optionally, interpreted as meaning "upon a determination" or "in response to a determination" or "upon detecting [a stated condition or event]" or "in response to a detection of [a stated condition or event]," depending on the context.

[0059] The use of "adapted to" or "configured to," as used herein, means an open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0060] Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0061] As used herein, "about," "approximately," or "circa" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0062] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equal and approximately equal, where the acceptable deviation range for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0063] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features can be shown in the drawings. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, manufacturing or processing tolerances, variations from manufacturing to manufacturing, variations in the manufacturing process, and / or variations in materials. Thus, the exemplary embodiments are not to be construed as limited to the specific illustrative examples that are described herein but are to be construed broadly.

[0065] The transistor used in the circuit provided by the embodiments of the present application can be a thin film transistor, a field effect transistor (such as an oxide thin film transistor), or other switching devices with the same characteristics, and the embodiments of the present application are described by taking a thin film transistor as an example. Preferably, the thin film transistor used in the embodiments of the present application can be an oxide semiconductor transistor or a low temperature polysilicon (LTPS, Low Temperature Poly-silicon) thin film transistor.

[0066] In this embodiment, the coupling methods of the drain and source of each transistor can be interchanged. Therefore, in this embodiment, the drain and source of each transistor are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistor used in this embodiment can be an N-type transistor or a P-type transistor. In this embodiment, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example, meaning that the thin-film transistor is turned on when the control terminal signal is high. It is conceivable that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of protection of this invention.

[0067] In the circuits provided in the embodiments of this application, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0068] In the circuits provided in the embodiments of this application, all transistors are P-type transistors, as an example, for explanation.

[0069] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which, by way of example, can be any display device that displays either moving (e.g., video) or stationary (e.g., still images) text or images. More specifically, the display device of the embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0070] The aforementioned display device 1000 may be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, etc. The specific form of the aforementioned display device 1000 is not limited in the embodiments disclosed herein.

[0071] like Figure 1 As shown, the display device 1000 includes a display panel 100. For example... Figure 2 As shown, the display panel 100 includes a display area AA and a peripheral area BB located on at least one side of the display area AA.

[0072] The aforementioned display area AA includes multiple sub-pixels P. Each sub-pixel P is the smallest unit for displaying an image on the display panel 100. Each sub-pixel P can display a single color, such as red, green, or blue. By adjusting the brightness (grayscale) of different colored sub-pixels P, and through color combination and superposition, multiple colors can be displayed, thereby achieving full-color display of the display panel 100. For ease of explanation, the multiple sub-pixels P mentioned above are illustrated in a matrix arrangement. In this case, sub-pixels P arranged in a row along the horizontal direction X are called a row of sub-pixels, and sub-pixels P arranged in a row along the vertical direction Y are called a column of sub-pixels P. A row of sub-pixels P can be connected to one or more scan signal lines GL, a row of sub-pixels P can be connected to one or more light emission control signal lines EM, and a column of sub-pixels P can be connected to a data line DL. For example, as shown... Figure 3 As shown, one row of sub-pixels P is connected to two scan signal lines GL, one row of sub-pixels P is connected to the light emission control signal line EM, and one column of sub-pixels P is connected to one data line DL.

[0073] The sub-pixel P contains a light-emitting device L and a pixel driving circuit 10 for controlling the light-emitting device L to emit light.

[0074] The light-emitting device L can be an organic light-emitting diode (OLED), a micro organic light-emitting diode (Micro OLED), a quantum dot light emitting diode (QLED), a mini light-emitting diode (Mini LED), a micro light-emitting diode (Micro LED), or the like.

[0075] The pixel driving circuit 10 is disposed on the substrate of the display panel 100. The scan signal line GL connected with the sub-pixel P is used to transmit a scan signal to the pixel driving circuit 10 of the sub-pixel P; the light-emitting control signal line EM connected with the sub-pixel P is used to transmit a light-emitting control signal to the pixel driving circuit 10 of the sub-pixel P; and the data line DL connected with the sub-pixel P is used to transmit a data signal data to the pixel driving circuit 10 of the sub-pixel P, the data signal data being from a source driver S coupled with each data line DL.

[0076] It should be noted that the pixel driving circuit 10 includes a plurality of thin film transistors. The control electrode of each thin film transistor used in the pixel driving circuit 10 is the gate of the transistor, the first electrode is one of the source and the drain of the thin film transistor, and the second electrode is the other of the source and the drain of the thin film transistor. Since the source and the drain of the thin film transistor can be symmetrical in structure, the source and the drain of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be indistinguishable in structure. For example, in the case of a P-type transistor, the first electrode of the thin film transistor is the source and the second electrode is the drain; in the case of an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0077] Referring to Figure 4A In some related embodiments, for example, a 7T1C pixel driving circuit is usually composed of seven transistors and one capacitor, which is used to control the driving current of the light-emitting device. Referring to Figure 4B The driving process of the pixel driving circuit is as follows: one frame period includes an initialization stage t1, a data refresh and compensation stage t2, and a light-emitting stage t3. The 7T1C pixel driving circuit needs at least one set of light-emitting control driving units and one set of gate driving units to provide driving signals. In combination with Figure 4A and Figure 4BIn the prior art, the gate-source voltage state of the driving transistor is affected by the previous frame of picture when the gray scale of each frame is refreshed. Since the gray scale of the previous frame of picture is different, the driving transistor can be in different states in the initialization stage, which can cause the gate-source voltage state to be inconsistent. That is, after the previous frame of picture ends, the gate and source of the driving transistor can have residual charges, which can cause the gate-source voltage state to be inconsistent. This inconsistency can affect the driving current of the current frame, which can cause the previous frame of picture to be retained in the subsequent frame of picture, and the difference between the gate-source voltages cannot be completely eliminated.

[0078] Referring to Figure 5A , Figure 5B and Figure 5C , Figure 5A , H1 and H2 represent two different gray scale pictures, H1 corresponds to a white gray scale picture, and H2 corresponds to a black gray scale picture. When the picture is switched from high brightness to low brightness, for example, to a 48-level gray scale picture as shown in Figure 5B , the high brightness information of the previous frame of picture can be retained in the subsequent frame of picture, which can cause a temporary ghosting phenomenon, and the ghosting phenomenon can disappear until the picture as shown in Figure 5C . As shown in Figure 6A , in the gray scale transition process, Figure 6A , I represents an L0 gray scale, and III represents an L255 gray scale. When the two gray scale pictures change to an intermediate gray scale L48, L0 first changes from the I state to the II state, and L255 changes from the III state to the IV state, and then changes to the VI state. Due to the inconsistency between the gate-source voltages, the gray scale changes of the two gray scale pictures follow different paths, which can cause the gray scale change to be not smooth, and an obvious residual image state can be generated.

[0079] The inventors of the present application have found that, referring to Figure 6B , L0 and L255 are first unified to a state V, and then change to the intermediate state VI along the same path, which can improve the residual image. The state V is a fixed setting of the gate-source voltage before each frame of picture is refreshed, and the value of the state V is greater than the gate-source voltage of L255.

[0080] Based on this, the pixel driving circuit of the present application is introduced below. The pixel driving circuit can ensure that the gate-source voltage is a fixed value under the control of the timing signal, which can improve the above-mentioned residual image state, and can improve the display effect of the display device.

[0081] Referring to Figure 7Some embodiments of the present application provide a pixel driving circuit 10, which comprises a first light-emitting control sub-circuit 110, a first initialization sub-circuit 120, a driving sub-circuit 130 and a second light-emitting control sub-circuit 140. The first light-emitting control sub-circuit 110 is coupled with a first voltage signal terminal VDD, a first node N1 and a first light-emitting control terminal EM1; the first light-emitting control sub-circuit 110 is configured to be turned on in response to a first light-emitting control signal e1 from the first light-emitting control terminal EM1, and transmit a first voltage signal from the first voltage signal terminal VDD to the first node N1.

[0082] The first initialization sub-circuit 120 is coupled with an initialization signal terminal Vinit, a second node N2 and a first scan signal terminal GT1; the first initialization sub-circuit 120 is configured to be turned on in response to a first scan signal g1 from the first scan signal terminal GT1, and transmit an initialization signal from the initialization signal terminal Vinit to the second node N2.

[0083] The driving sub-circuit 130 is coupled with the first node N1, the second node N2 and a third node N3; the driving sub-circuit 130 is configured to be turned on in response to an electrical signal from the second node N2, and transmit the electrical signal from the first node N1 to the third node N3.

[0084] The second light-emitting control sub-circuit 140 is coupled with the third node N3, a light-emitting device L, the first light-emitting control terminal EM1 and a second light-emitting control terminal EM2; the second light-emitting control sub-circuit 140 is configured to be turned on in response to the first light-emitting control signal e1 and a second light-emitting control signal e2 from the second light-emitting control terminal EM2, and transmit the electrical signal of the third node N3 to the light-emitting device L; wherein the time when the second light-emitting control signal e2 jumps to a valid level is earlier than the time when the first light-emitting control signal e1 jumps to a valid level.

[0085] In the pixel driving circuit 10 provided in the present disclosure, the first light emitting control sub-circuit 110 is configured to be turned on in response to the first light emitting control signal e1 from the first light emitting control terminal EM1, and transmit the first voltage signal from the first voltage signal terminal VDD to the first node N1. The first initialization sub-circuit 120 is configured to be turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and transmit the initialization signal from the initialization signal terminal Vinit to the second node N2. The driving sub-circuit 130 is configured to be turned on in response to the electrical signal from the second node N2, and transmit the electrical signal from the first node N1 to the third node N3. The second light emitting control sub-circuit 140 is configured to be turned on in response to the first light emitting control signal e1 and the second light emitting control signal e2 from the second light emitting control terminal EM2, and transmit the electrical signal of the third node N3 to the light emitting device L. It should be understood that, in the T1 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level. In the T2 stage, the second light emitting control signal e2 is at the valid level, and the first light emitting control signal e1 is at the invalid level. In the T3 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level. Figure 8 It should be understood that, in the T1 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level. In the T2 stage, the second light emitting control signal e2 is at the valid level, and the first light emitting control signal e1 is at the invalid level. In the T3 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level. Figure 8 It should be understood that, in the T1 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level. In the T2 stage, the second light emitting control signal e2 is at the valid level, and the first light emitting control signal e1 is at the invalid level. In the T3 stage, the second light emitting control signal e2 is at the invalid level, and the first light emitting control signal e1 is at the valid level.

[0086] The valid level is the working level, for example, the transistor is a P-type transistor, the working level is the low level, and the non-working level is the high level. Of course, in the case of an N-type transistor, the working level is the high level, and the non-working level is the low level. The transistor in some embodiments of the present disclosure is taken as an example of a P-type transistor, that is, the valid level is the low level.

[0087] In some embodiments, asFigure 7 As shown in the figure, the second light emitting control sub-circuit 140 includes a first transistor M1 and a second transistor M2; a first electrode of the first transistor M1 is coupled with the third node N3, and a second electrode of the first transistor M1 is coupled with the light emitting device L; a control electrode of the second transistor M2 is coupled with the first light emitting control end EM1, a first electrode of the second transistor M2 is coupled with the second light emitting control end EM2, and a second electrode of the second transistor M2 is coupled with the control electrode of the first transistor M1.

[0088] Exemplarily, as Figure 7 shown in the figure, the second transistor M2 is turned on in response to the first light emitting control signal of the first light emitting control end EM1, can transmit the second light emitting control signal e2 of the second light emitting control end EM2 to the control electrode of the first transistor M1, the first transistor M1 is turned on in response to the second light emitting control signal e2, can transmit the electrical signal of the third node N3 to the light emitting device L, to realize light emitting.

[0089] In some embodiments, as Figure 7 shown in the figure, the first light emitting control sub-circuit 110 includes a third transistor M3, a control electrode of the third transistor M3 is coupled with the first light emitting control end EM1, a first electrode of the third transistor M3 is coupled with the first voltage signal end VDD, and a second electrode of the third transistor M3 is coupled with the first node N1; the driving sub-circuit 130 includes a fourth transistor M4, a control electrode of the fourth transistor M4 is coupled with the second node N2, a first electrode of the fourth transistor M4 is coupled with the first node N1, and a second electrode of the fourth transistor M4 is coupled with the third node N3; the first initialization sub-circuit 120 includes a fifth transistor M5, a control electrode of the fifth transistor M5 is coupled with the first scanning signal end GT1, a first electrode of the fifth transistor M5 is coupled with the initialization signal end, and a second electrode of the fifth transistor M5 is coupled with the second node.

[0090] Exemplarily, the third transistor M3 is turned on in response to the first light-emitting control signal e1 of the first light-emitting control end EM1, and can transmit the first voltage signal of the first voltage signal end VDD to the first node N1; the fifth transistor M5 is turned on in response to the first scanning signal g1 from the first scanning signal end GT1, and transmits the initialization signal from the initialization signal end Vinit to the second node N2; the fourth transistor M4 is turned on in response to the electrical signal of the second node N2, and transmits the electrical signal from the first node N1 to the third node N3. That is, the first electrode of the fourth transistor M4 receives the first voltage signal of the first voltage signal end VDD, the control electrode of the fourth transistor M4 receives the initialization signal of the initialization signal end Vinit, at this time, the voltage difference (i.e. gate-source voltage) between the control electrode and the first electrode of the fourth transistor M4 is the difference between the initialization signal and the first voltage signal, that is, a fixed value, so as to ensure that the starting state of the gate-source voltage of the fourth transistor M4 is consistent at each time of gray scale refreshing, so as to avoid the residual image problem caused by different gray scale pictures.

[0091] In some embodiments, continuing to refer to Figure 7 , the pixel driving circuit 10 further includes a second initialization sub-circuit 150, a data writing sub-circuit 160, and a compensation sub-circuit 170; the second initialization sub-circuit 150 is coupled with the initialization signal end Vinit, the light-emitting device L, and the first scanning signal end GT1; the second initialization sub-circuit 150 is configured to be turned on in response to the first scanning signal g1 from the first scanning signal end GT1, and transmit the initialization signal from the initialization signal end Vinit to the light-emitting device L.

[0092] The data writing sub-circuit 160 is coupled with the second scanning signal end GT2, the data signal end Data, and the first node N1; the data writing sub-circuit 160 is configured to be turned on in response to the second scanning signal g2 from the second scanning signal end GT2, and transmit the data signal from the data signal end Data to the first node N1.

[0093] The compensation sub-circuit 170 is coupled with the second scanning signal end GT2, the second node N2, and the third node N3; the compensation sub-circuit 170 is configured to be turned on in response to the second scanning signal g2 from the second scanning signal end GT2, and transmit the voltage from the second node N2 to the third node N3.

[0094] In some embodiments, the second initialization sub-circuit 150 includes a sixth transistor M6, a control electrode of the sixth transistor M6 is coupled with the first scan signal terminal GT1, a first electrode of the sixth transistor M6 is coupled with the initialization signal terminal Vinit, and a second electrode of the sixth transistor M6 is coupled with the fourth node N4; the data writing sub-circuit 160 includes a seventh transistor M7, a control electrode of the seventh transistor M7 is coupled with the second scan signal terminal GT2, a first electrode of the seventh transistor M7 is coupled with the data signal terminal Data, and a second electrode of the seventh transistor M7 is coupled with the first node N1; and the compensation sub-circuit 170 includes an eighth transistor M8, a control electrode of the eighth transistor M8 is coupled with the second scan signal terminal GT2, a first electrode of the eighth transistor M8 is coupled with the second node N2, and a second electrode of the eighth transistor M8 is coupled with the third node N3.

[0095] For example, the sixth transistor M6 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and transmits the initialization signal from the initialization signal terminal Vinit to the light emitting device L; the seventh transistor M7 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the data signal from the data signal terminal Data to the first node N1; and the eighth transistor M8 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the voltage from the second node N2 to the third node N3.

[0096] It should be noted that the control electrode of the fifth transistor M5 and the control electrode of the sixth transistor M6 are both coupled with the first scan signal terminal GT1, and the turn-on and turn-off time of the fifth transistor M5 can be the same as the turn-on and turn-off time of the sixth transistor M6 (at the same time, the sixth transistor M6 and the fifth transistor M5 are turned on or turned off at the same time), and the transistor types of the sixth transistor M6 and the fifth transistor M5 are the same (for example, the sixth transistor M6 and the fifth transistor M5 are both P-type transistors), so the sixth transistor M6 and the fifth transistor M5 can use the same scan signal line. Compared with using different signal lines to control the turn-on or turn-off of the sixth transistor M6 and the fifth transistor M5, by sharing the signal line, one scan signal line can be saved, the structure of the pixel driving circuit 10 is simplified, the power consumption of the pixel driving circuit 10 is reduced, and the thinning of the display device is facilitated.

[0097] Similarly, the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 are both coupled to the second scan signal terminal GT2, and the turn-on and turn-off time of the seventh transistor M7 can correspond to the same as the turn-on and turn-off time of the eighth transistor M8 (at the same time, the seventh transistor M7 and the eighth transistor M8 are turned on or turned off at the same time), and the transistor types of the two are the same (for example, the seventh transistor M7 and the eighth transistor M8 are both P-type transistors), so the seventh transistor M7 and the eighth transistor M8 can use the same scan signal line. Compared with using different signal lines to control the turn-on or turn-off of the seventh transistor M7 and the eighth transistor M8, by sharing the signal line, one scan signal line can be saved, the structure of the pixel driving circuit 10 is simplified, and the power consumption of the pixel driving circuit 10 is reduced, which is beneficial to realize the light and thin display device.

[0098] In some embodiments, as shown in Figure 7 and Figure 8 , the time of the first scan signal g1 transmitted by the first scan signal terminal GT1 is earlier than the time of the second scan signal g2 transmitted by the second scan signal terminal GT2.

[0099] It should be noted that according to the foregoing, the first scan signal terminal GT1 is used to couple the first initialization sub-circuit 120 and the second initialization sub-circuit 150, that is, in the initialization stage, the first initialization sub-circuit 120 and the second initialization sub-circuit 150 can both be turned on in response to the first scan signal of the first scan signal terminal GT1; and the second scan signal terminal GT2 is used to couple the data writing sub-circuit 160 and the compensation sub-circuit 170, that is, in the compensation stage, the data writing sub-circuit 160 and the compensation sub-circuit 170 can be turned on in response to the second scan signal g2 transmitted by the second scan signal terminal GT2, therefore, based on one frame period of the pixel driving circuit 10, the turn-on time of the first scan signal g1 and the second scan signal g2 is set to be different.

[0100] In some embodiments, referring to Figure 8 , the second light-emitting control signal e2 and the first scan signal g1 are inverse signals of each other, and / or the first light-emitting control signal e1 and the second scan signal g2 are inverse signals of each other.

[0101] It should be noted that, referring to Figure 8 and combining Figure 7, the second light emitting control signal e2 is used to control the turn-off of the first transistor M1, the first scan signal g1 is used to control the turn-on of the sixth transistor M6 and the fifth transistor M5, the sixth transistor M6 and the fifth transistor M5 need to be turned on in the initialization stage, and the second light emitting control signal e2 only needs to make the first transistor M1 turned on in the light emitting stage, therefore, in the same stage timing, the second light emitting control signal e2 and the first scan signal g1 are set as inverse signals of each other, that is, in the case that the second light emitting control signal e2 is at a high level, the first scan signal g1 is at a low level, and in the case that the second light emitting control signal e2 is at a low level, the first scan signal g1 is at a high level. For example, in the initialization stage, the second light emitting control signal e2 is at a high level, and the first scan signal g1 is at a low level, and in the light emitting stage, the second light emitting control signal e2 is at a low level, and the first scan signal g1 is at a high level.

[0102] Similarly, the first light emitting control signal e1 is used to control the turn-on of the second transistor M2, the second scan signal g2 is used to control the turn-on of the seventh transistor M7 and the eighth transistor M8, the seventh transistor M7 and the eighth transistor M8 need to be turned on in the compensation stage, and the first light emitting control signal e1 only needs to make the second transistor M2 turned on in the light emitting stage, therefore, in the same stage timing, the first light emitting control signal e1 and the second scan signal g2 are set as inverse signals of each other, that is, in the case that the first light emitting control signal e1 is at a high level, the second scan signal g2 is at a low level, and in the case that the first light emitting control signal e1 is at a low level, the second scan signal g2 is at a high level. For example, in the compensation stage, the first light emitting control signal e1 is at a high level, and the second scan signal g2 is at a low level, and in the light emitting stage, the first light emitting control signal e1 is at a low level, and the second scan signal g2 is at a high level.

[0103] In the pixel driving circuit 10 provided in the embodiments of the present disclosure, the first node N1, the second node N2, and the third node N3 to be mentioned below are not actual components, but are convergence points of electrical connection of related sub-circuits or electronic elements in the circuit diagram, that is, these nodes are nodes equivalent to convergence points of electrical connection of related sub-circuits or electronic elements in the circuit diagram.

[0104] The light emitting device L in the pixel driving circuit can be an OLED light emitting device, and can also be an MLED light emitting device. However, the driving current of the OLED light emitting device is in the order of nA, and the driving current of the MLED light emitting device is in the order of μA. Therefore, according to the difference in the current order of magnitude, and in the case that both are applied to the pixel driving circuit 10 corresponding to the embodiments of the present disclosure, the size relationship between the channel length and the channel width of the transistors in the corresponding pixel driving circuit 10 needs to be adjusted according to the type of the light emitting device, so as to ensure that the current in the pixel driving circuit 10 is matched with the light emitting device.

[0105] The size relationship between the channel length and the channel width of the transistors in the pixel driving circuit 10 will be specifically introduced below.

[0106] In some embodiments, referring to Figure 7 , the channel width of the second transistor M2 of the second light emitting control sub-circuit 140 is greater than the channel length.

[0107] In some embodiments, referring to Figure 7 , the channel width of the sixth transistor M6 and the seventh transistor M7 is greater than or equal to the channel length.

[0108] In some embodiments, referring to Figure 7 , the channel width-length ratio of the first transistor of the first light emitting control sub-circuit 110 and the channel width-length ratio of the third transistor are the same, and are greater than the channel width-length ratio of the fourth transistor.

[0109] It should be noted that in the case that the light emitting device L is an OLED light emitting device or an MLED light emitting device, the above-mentioned setting that the channel width of the second transistor M2 of the second light emitting control sub-circuit 140 is greater than the channel length, the channel width of the sixth transistor M6 and the seventh transistor M7 is greater than or equal to the channel length, and the channel width-length ratio of the first transistor of the first light emitting control sub-circuit 110 and the channel width-length ratio of the third transistor are the same and are greater than the channel width-length ratio of the fourth transistor can be used to adjust the corresponding current.

[0110] In other embodiments, the light emitting device L is an OLED light emitting device, and the channel width of the fourth transistor M4 of the driving sub-circuit 130 is less than the channel length; or, the light emitting device L is an MLED light emitting device, and the channel width of the fourth transistor M4 of the driving sub-circuit 130 is greater than the channel length.

[0111] It can be understood that the above-mentioned fourth transistor M4 adopts the above-mentioned setting when the type of the light emitting device L is different, which can ensure that the order of magnitude of the driving circuit is matched with the corresponding light emitting device L.

[0112] The pixel driving circuit 10 is based on the structure of any one of the above embodiments. As shown in Figure 7 , the pixel driving circuit 10 comprises a first light-emitting control sub-circuit 110, a first initialization sub-circuit 120, a driving sub-circuit 130, a second light-emitting control sub-circuit 140, a second initialization sub-circuit 150, a data writing sub-circuit 160 and a compensation sub-circuit 170. Some embodiments of the present disclosure provide a driving method of the pixel driving circuit 10.

[0113] As shown in Figure 8 , one frame period of the pixel driving circuit 10 comprises an initialization stage T1, a data writing stage T2 and a light-emitting stage T3.

[0114] In some embodiments, referring to Figure 9A , Figure 9B and Figure 9C , in the initialization stage T1, the first light-emitting control sub-circuit 110 of the pixel driving circuit 10 is turned on in response to the first light-emitting control signal e1 from the first light-emitting control end EM1, and transmits the first voltage signal from the first voltage signal end VDD to the first node N1; the first initialization sub-circuit 120 of the pixel driving circuit 10 is turned on in response to the first scanning signal g1 from the first scanning signal end GT1, and transmits the initialization signal from the initialization signal end Vinit to the second node N2.

[0115] In the light-emitting stage, referring to Figure 10A , Figure 10B and Figure 10C , in the data writing stage T2, the data writing sub-circuit 160 is turned on in response to the second scanning signal g2 from the second scanning signal end GT2, and transmits the data signal from the data signal end Data to the first node N1; the driving sub-circuit 130 is turned on in response to the electrical signal from the second node N2, and transmits the electrical signal from the first node N1 to the third node N3; the compensation sub-circuit 170 is turned on in response to the second scanning signal g2 from the second scanning signal end GT2, and transmits the electrical signal from the third node N3 to the second node N2, so as to compensate the driving sub-circuit.

[0116] In some embodiments, referring to Figure 11A , Figure 11B and Figure 11C , the first light-emitting control sub-circuit 110 is turned on in response to the first light-emitting control signal e1 from EM1, and the second light-emitting control sub-circuit 140 is turned on in response to the first light-emitting control signal e1 and the second light-emitting control signal e2 from the second light-emitting control end EM2, so as to form a path between the first voltage signal end VDD and the light-emitting device L, and drive the light-emitting device L to emit light.

[0117] For example, the following will be described in combination withFigure 9A - Figure 11C right Figure 7 The specific operation of the pixel driving circuit 10 shown will be described in detail. In the following description, the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 in the pixel driving circuit 10 are P-type thin-film transistors. The first voltage signal transmitted at the first voltage signal terminal VDD is a high-level voltage, the second voltage signal transmitted at the second voltage signal terminal VSS is a low-level voltage, and the initialization signal at the initialization signal terminal Vinit is a low-level voltage, as illustrated in the following description. Those skilled in the art should understand that in the above-described pixel driving circuit 10, when the line between the first voltage signal terminal VDD and the second voltage signal terminal VSS is connected, the light-emitting device L emits light.

[0118] For example, in the description below, "0" represents a low level and "1" represents a high level.

[0119] like Figure 9A and Figure 9B As shown, during the initialization phase T1, e1 = 0, g1 = 0, e2 = 1, g2 = 1.

[0120] In this case, refer to Figure 9C The third transistor M3 is turned on in response to the first light-emitting control signal e1 from the first light-emitting control terminal EM1, transmitting the first voltage signal from the first voltage signal terminal VDD to the first node N1; the fifth transistor M5 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, transmitting the initialization signal from the initialization signal terminal Vinit to the second node N2. At the same time, the second transistor M2 is also turned on in response to the first light-emitting control signal e1 from the first light-emitting control terminal EM1, but the first transistor M1 is turned off in response to the second light-emitting control signal e2 from the second light-emitting control terminal EM2. Therefore, the line between the first voltage terminal VDD and the second voltage terminal VSS is open, and the light-emitting device L does not emit light. It should be noted that the first electrode of the fourth transistor M4 receives the first voltage signal from the first voltage signal terminal VDD, and the control electrode of the fourth transistor M4 receives the initialization signal from the initialization signal terminal Vinit. At this time, the voltage difference between the control electrode and the first electrode of the fourth transistor M4 (i.e., the gate-source voltage) is the difference between the initialization signal and the first voltage signal, which is a fixed value. This ensures that the initial state of the gate-source voltage of the fourth transistor M4 remains consistent each time grayscale is refreshed, so as to avoid the image retention problem caused by different grayscale images.

[0121] In the data writing phase T2, such as Figure 10A As shown, e1 = 0, g1 = 1, e2 = 1, g2 = 0, or as... Figure 10BAs shown, e1=1, g1=1, e2=1, g2=0.

[0122] In this case, referring to Figure 10C , the seventh transistor M7 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the data signal from the data signal terminal Data to the first node N1; the fourth transistor T4 is turned on in response to the electrical signal from the second node N2, and transmits the electrical signal from the first node N1 to the third node N3; the eighth transistor M8 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the electrical signal from the third node N3 to the second node N2, so as to compensate the driving sub-circuit 130.

[0123] According to the above, since the second scan signal terminal GT2 is connected to the seventh transistor M7 and the eighth transistor M8 at the same time, that is, the seventh transistor M7 and the eighth transistor M8 are turned on at the same time under the control of the second scan signal g2 from the second scan signal terminal GT2, since Figure 10A and Figure 10B the second scan signal g2 in the two stages is low, therefore Figure 10C the pixel driving circuit 10 shown in Figure 10A and Figure 10B is capable of realizing data writing under the control of the timing shown in

[0124] In the light-emitting stage T3, as shown in Figure 11A and Figure 11B , e1=0, g1=0, e2=1, g2=1.

[0125] Referring to Figure 11C , under the timing shown in Figure 11A and Figure 11B , the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all turned off, the second transistor M2 is turned on in response to the first light-emitting control signal e1 from EM1, and the first transistor M1 is turned on in response to the second light-emitting control signal e2 from the second light-emitting control terminal EM2, so as to form a path between the first voltage signal terminal VDD and the light-emitting device L, and drive the light-emitting device L to emit light.

[0126] In the display panel 100 provided in some embodiments of the present disclosure, as shown in Figure 3 , the display panel 100 comprises a plurality of pixel driving circuits 10 described in any of the above embodiments, and a gate driving circuit 20. The beneficial effects that can be achieved by the display panel 100 provided in the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the pixel driving circuit 10 provided in the above embodiments, and will not be described here.

[0127] The gate drive circuit 20 includes a plurality of cascaded shift register units 201, wherein an Nth shift register unit 201 is electrically connected to the first scan signal terminal GT1 and the first light-emitting control signal terminal EM1 of the Nth row of pixel drive circuits 10, and an N+1th shift register unit is electrically connected to the second scan signal terminal GT2 and the second light-emitting control signal terminal EM2 of the Nth row of pixel drive circuits.

[0128] In some embodiments, with reference to Figure 12 , the shift register unit 201 includes a scan signal generation circuit 30 and an inverter 40. The scan signal generation circuit 30 is electrically connected to the scan signal terminal, and is configured to generate a scan signal and transmit it to the scan signal terminal. The inverter 40 is electrically connected to the scan signal terminal and the light-emitting control signal terminal, and is configured to invert the scan signal and transmit it to the light-emitting control signal terminal as a light-emitting control signal.

[0129] It should be noted that the scan signal terminal includes the first scan signal terminal GT1 and the second scan signal terminal GT2, and the light-emitting control signal terminal includes the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2.

[0130] In some embodiments, in the same shift register unit 201, when the scan signal generation circuit 30 generates the first scan signal terminal GT1, since the first scan signal terminal GT1 and the second light-emitting control signal e2 are inverse signals of each other, the scan signal terminal connected to the inverter 40 transmits the first scan signal terminal GT1, and the light-emitting control signal terminal connected to the inverter 40 is the second light-emitting control signal terminal EM2, which transmits the second light-emitting control signal e2. Similarly, when the scan signal generation circuit 30 generates the second scan signal terminal GT2, since the second scan signal g2 and the first light-emitting control signal e1 are inverse signals of each other, the scan signal terminal connected to the inverter 40 is the second scan signal terminal GT2, which transmits the second scan signal g2, and the light-emitting control signal terminal connected to the inverter 40 is the first light-emitting control signal terminal EM1, which transmits the second light-emitting control signal e2.

[0131] In the display device 1000 provided in some embodiments of the present disclosure, as shown in Figure 1 and Figure 2 , the display device 1000 includes the display panel 100 described in any of the above embodiments. The beneficial effects that can be achieved by the display device 1000 provided in the embodiments of the present disclosure are the same as those that can be achieved by the display panel 100 provided in the above embodiments, and will not be repeated here.

[0132] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, characterized by comprising: The pixel driving circuit is used for connecting a light emitting device, and comprises: a first light emitting control sub-circuit, coupled with a first voltage signal terminal, a first node and a first light emitting control terminal; the first light emitting control sub-circuit is configured to be turned on in response to a first light emitting control signal from the first light emitting control terminal, and transmit a first voltage signal from the first voltage signal terminal to the first node; a first initialization sub-circuit, coupled with an initialization signal terminal, a second node and a first scan signal terminal; the first initialization sub-circuit is configured to be turned on in response to a first scan signal from the first scan signal terminal, and transmit an initialization signal from the initialization signal terminal to the second node; a driving sub-circuit, coupled with the first node, the second node and a third node; the driving sub-circuit is configured to be turned on in response to an electrical signal from the second node, and transmit an electrical signal from the first node to the third node; a second light emitting control sub-circuit, coupled with the third node, the light emitting device, the first light emitting control terminal and a second light emitting control terminal; the second light emitting control sub-circuit is configured to be turned on in response to the first light emitting control signal and a second light emitting control signal from the second light emitting control terminal, and transmit the electrical signal of the third node to the light emitting device; wherein a time when the second light emitting control signal jumps to a valid level is earlier than a time when the first light emitting control signal jumps to the valid level; the second light emitting control sub-circuit comprises: a first transistor, a first electrode of the first transistor being coupled with the third node, and a second electrode of the first transistor being coupled with the light emitting device; a second transistor, a control electrode of the second transistor being coupled with the first light emitting control terminal, a first electrode of the second transistor being coupled with the second light emitting control terminal, and a second electrode of the second transistor being coupled with a control electrode of the first transistor.

2. The pixel driving circuit according to claim 1, characterized in that, A channel width of the second transistor of the second light emitting control sub-circuit is greater than a channel length.

3. The pixel driving circuit according to claim 1 or 2, characterized in that the first light emitting control sub-circuit comprises a third transistor, a control electrode of the third transistor being coupled with the first light emitting control terminal, a first electrode of the third transistor being coupled with the first voltage signal terminal, and a second electrode of the third transistor being coupled with the first node; the driving sub-circuit comprises a fourth transistor, a control electrode of the fourth transistor being coupled with the second node, a first electrode of the fourth transistor being coupled with the first node, and a second electrode of the fourth transistor being coupled with the third node; the first initialization sub-circuit comprises a fifth transistor, a control electrode of the fifth transistor being coupled with the first scan signal terminal, a first electrode of the fifth transistor being coupled with the initialization signal terminal, and a second electrode of the fifth transistor being coupled with the second node.

4. The pixel driving circuit according to claim 3, characterized in that a channel width-length ratio of the first transistor is same as a channel width-length ratio of the third transistor, and both are greater than a channel width-length ratio of the fourth transistor. The light-emitting device is an OLED light-emitting device, and a channel width of the fourth transistor of the driving sub-circuit is less than a channel length. The light-emitting device is an MLED light-emitting device, and a channel width of the fourth transistor of the driving sub-circuit is greater than a channel length.

5. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises: a second initialization sub-circuit coupled with the initialization signal terminal, the light-emitting device and a first scan signal terminal; the second initialization sub-circuit is configured to conduct in response to a first scan signal from the first scan signal terminal, and transmit an initialization signal from the initialization signal terminal to the light-emitting device; a data writing sub-circuit coupled with a second scan signal terminal, a data signal terminal and the first node; the data writing sub-circuit is configured to conduct in response to a second scan signal from the second scan signal terminal, and transmit a data signal from the data signal terminal to the first node; a compensation sub-circuit coupled with the second scan signal terminal, the second node and the third node; the compensation sub-circuit is configured to conduct in response to the second scan signal from the second scan signal terminal, and transmit a voltage from the second node to the third node.

6. The pixel driving circuit according to claim 5, wherein the second initialization sub-circuit comprises a sixth transistor, a control electrode of the sixth transistor is coupled with the first scan signal terminal, a first electrode of the sixth transistor is coupled with the initialization signal terminal, and a second electrode of the sixth transistor is coupled with the light-emitting device; the data writing sub-circuit comprises a seventh transistor, a control electrode of the seventh transistor is coupled with the second scan signal terminal, a first electrode of the seventh transistor is coupled with the data signal terminal, and a second electrode of the seventh transistor is coupled with the first node; the compensation sub-circuit comprises an eighth transistor, a control electrode of the eighth transistor is coupled with the second scan signal terminal, a first electrode of the eighth transistor is coupled with the second node, and a second electrode of the eighth transistor is coupled with the third node.

7. The pixel driving circuit according to claim 6, wherein a channel width of the sixth transistor and the seventh transistor is greater than a channel length.

8. The pixel driving circuit according to any one of claims 5-7, wherein a time of a first scan signal transmitted by the first scan signal terminal is earlier than a time of a second scan signal transmitted by the second scan signal terminal.

9. The pixel driving circuit of claim 8, wherein, the second light-emitting control signal and the first scan signal are inverse signals of each other, and / or the first light-emitting control signal and the second scan signal are inverse signals of each other.

10. A driving method of a pixel driving circuit, characterized by, application to the pixel driving circuit according to any one of claims 1-9; a frame period comprises an initialization stage and a light-emitting stage; the driving method comprises: in the initialization stage, the first light-emitting control sub-circuit of the pixel driving circuit conducts in response to a first light-emitting control signal from the first light-emitting control terminal, and transmits a first voltage signal from the first voltage signal terminal to the first node; The first initialization sub-circuit of the pixel driving circuit is turned on in response to a first scan signal from the first scan signal terminal, and transmits an initialization signal from the initialization signal terminal to the second node; In the light emitting stage, The first light emitting control sub-circuit is turned on in response to a first light emitting control signal from the first light emitting control terminal, and the second light emitting control sub-circuit is turned on in response to the first light emitting control signal and a second light emitting control signal from the second light emitting control terminal, so as to form a path between the first voltage signal terminal and the light emitting device, and drive the light emitting device to emit light.

11. The driving method of the pixel driving circuit according to claim 10, wherein The pixel driving circuit further comprises a data writing sub-circuit and a compensation sub-circuit; one frame period further comprises a data writing stage between the initialization stage and the light emitting stage; In the data writing stage, The data writing sub-circuit is turned on in response to a second scan signal from the second scan signal terminal, and transmits a data signal from the data signal terminal to the first node; The driving sub-circuit is turned on in response to an electrical signal from the second node, and transmits an electrical signal from the first node to the third node; The compensation sub-circuit is turned on in response to a second scan signal from the second scan signal terminal, and transmits an electrical signal from the third node to the second node, so as to compensate the driving sub-circuit.

12. A display panel, characterized by The display panel comprises a plurality of pixel driving circuits as claimed in any one of claims 1-9, and a gate driving circuit; The gate driving circuit comprises a plurality of cascaded shift register units, wherein, The Nth shift register unit is electrically connected to the first scan signal terminal and the first light emitting control signal terminal of the Nth row of pixel driving circuits, and the N+1th shift register unit is electrically connected to the second scan signal terminal and the second light emitting control signal terminal of the Nth row of pixel driving circuits.

13. The display panel of claim 12, wherein, The shift register unit comprises: A scan signal generation circuit electrically connected to the scan signal terminal; the scan signal generation circuit is configured to generate a scan signal and transmit it to the scan signal terminal; An inverter electrically connected to the scan signal terminal and the light emitting control signal terminal; the inverter is configured to invert the scan signal as a light emitting control signal and transmit it to the light emitting control signal terminal.

14. A display device comprising: The display panel comprises: The display panel of claim 12 or 13.

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