Display device and driving method thereof

Abstract

The invention relates to a display device and a driving method thereof. A display device includes a display panel having a display area including a plurality of sub-pixels. At least one sub-pixel of the plurality of sub-pixels may include: a driving transistor having a first electrode connected to a first power supply line configured to receive a first power supply voltage; a first switching transistor connected to the data line and having a gate electrode configured to receive a first scan signal; a second switching transistor connected between the gate electrode of the driving transistor and the second electrode and having a gate electrode configured to receive a second scan signal; and a third switching transistor connected to the gate electrode of the driving transistor and having a gate electrode configured to receive a light emission control signal.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof. Background Art

[0002] In addition to being used as a display screen for a monitor or television, the display device is widely used as a display screen for a laptop computer, a tablet computer, a smart phone, a portable display device, and a portable information device. Recently, there is an increasing demand for large display devices for large electronic devices such as automobiles.

[0003] Such a large display device has a plurality of display areas, and a method capable of freely adjusting the ratio of each display area according to a user's request or a display image will be required. Summary of the invention

[0004] Accordingly, the present disclosure is directed to a display device and a method of driving the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0005] An object of the present disclosure is to provide a display device in which the ratio of a plurality of display areas can be adjusted and the response speed can be improved.

[0006] In addition to the objects of the present disclosure described above, those skilled in the art can clearly understand additional objects and features of the present disclosure from the following description of the present disclosure.

[0007] To achieve these methods and other advantages of the present disclosure, as implemented and broadly described herein, a display device may include a display panel having a display area including a plurality of sub-pixels, at least one of the plurality of sub-pixels including: a driving transistor having a first electrode connected to a first power line configured to receive a first power supply voltage; a first switching transistor connected to a data line and having a gate electrode configured to receive a first scanning signal; a second switching transistor connected between the gate electrode and the second electrode of the driving transistor and having a gate electrode configured to receive a second scanning signal; and a third switching transistor connected to the gate electrode of the driving transistor and having a gate electrode configured to receive a light emitting control signal.

[0008] According to another aspect of the present disclosure, a display device may include a display panel, the display panel includes a plurality of sub-pixels, at least one of the plurality of sub-pixels includes: a first switching transistor having a gate electrode configured to receive a first scanning signal, a first electrode connected to a data line, and a second electrode connected to a first node; a driving transistor having a gate electrode connected to a second node, a first electrode connected to a first power line configured to receive a first power supply voltage, and a second electrode connected to a third node; a second switching transistor having a gate electrode configured to receive a second scanning signal, a first electrode connected to the second node, and a second electrode connected to the third node; a third switching transistor having a gate electrode configured to receive a light-emitting control signal, a first electrode connected to the first node, and a second electrode connected to an initialization voltage line configured to receive an initialization voltage; a storage capacitor connected between the first node and the second node; and at least one light-emitting element connected between the third node and a second power line configured to receive a second power supply voltage.

[0009] Additional features and aspects of the present disclosure will be set forth in the following description, and in part will become apparent from the description, or may be learned by the practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and obtained by the structures indicated in the written description or structures derivable therefrom, as well as the attached claims and drawings.

[0010] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are given by way of example and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate example embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0012] Figure 1 is a schematic diagram illustrating a configuration of a display device according to an exemplary embodiment of the present disclosure;

[0013] Figure 2A and Figure 2B is a diagram illustrating various forms in which the ratio of the first display area and the second display area can be changed in a display device according to an exemplary embodiment of the present disclosure;

[0014] Figure 3 is a circuit diagram illustrating an example sub-pixel of a display device according to an example embodiment of the present disclosure;

[0015] Figure 4is a diagram illustrating a driving waveform of an example sub-pixel of a display device according to an example embodiment of the present disclosure;

[0016] Figure 5 is a diagram illustrating circuit driving of an exemplary sub-pixel of a display device in a first period according to an exemplary embodiment of the present disclosure;

[0017] Figure 6 is a diagram illustrating circuit driving of an exemplary sub-pixel of a display device in a second period according to an exemplary embodiment of the present disclosure;

[0018] Figure 7 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a third period according to an example embodiment of the present disclosure;

[0019] Figure 8 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a fourth period according to an example embodiment of the present disclosure;

[0020] Fig. 9 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a fifth period according to an example embodiment of the present disclosure;

[0021] Fig.10 is a diagram illustrating a driving waveform of an example sub-pixel of a display device according to another example embodiment of the present disclosure;

[0022] Fig.11 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a sixth period according to an example embodiment of the present disclosure; and

[0023] Fig.12 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a seventh period according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The advantages and features of the present disclosure and methods for implementing the same will become clear with reference to the example embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. Instead, these example embodiments are provided so that the present disclosure will be sufficiently thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0025] The shapes, sizes, areas, lengths, thicknesses, ratios, angles, quantities, etc. illustrated in the drawings describing various exemplary embodiments of the present disclosure are given by way of example only. Therefore, the present disclosure is not limited to the details illustrated in the drawings. Unless otherwise specified, similar reference numerals generally refer to similar elements throughout the specification.

[0026] In the following description, when a detailed description of related known functions or configurations may unnecessarily obscure aspects of the present disclosure, the detailed description of such known functions or configurations may be omitted or may be briefly discussed.

[0027] When terms such as "includes," "having," and "comprising" are used, one or more other elements may be added unless the term is used with a more restrictive term such as "only." Elements described in the singular may include plural elements, and vice versa, unless the context clearly indicates otherwise.

[0028] When interpreting an element, although there is no explicit description on the error range or tolerance range, the element should be interpreted as including the error range or tolerance range.

[0029] When the positional relationship between two elements is described using terms such as "on," "above," "below," "adjacent," etc., one or more other elements may be located between the two elements, unless the terms are used with more restrictive terms such as "immediately" or "directly."

[0030] When using terms such as "after", "subsequently", "next", "before", etc. to describe a temporal relationship, it can include non-sequential or non-continuous situations unless it is used with a more restrictive term such as "immediately" or "directly".

[0031] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms because they are not used to define the specific essence, order, sequence, precedence, or quantity of such elements. These terms are only used to refer to an element that is separated from another element. For example, a first element may be referred to as a second element, and a second element may be similarly referred to as a first element without departing from the scope of the present disclosure.

[0032] The features of the various embodiments of the present disclosure may be partially or completely connected or combined with each other, and may be operated, linked or driven together in various ways as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in association with each other.

[0033] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a schematic diagram illustrating a configuration of a display device according to an exemplary embodiment of the present disclosure.

[0035] The display device according to example embodiments may be an electroluminescent display device such as an organic light emitting diode (OLED) display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode (OLED) display device.

[0036] like Figure 1 As shown, a display device according to an example embodiment may include a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, a level shifter 500, a gamma voltage generator 600, and a power management circuit 700. In this case, the data driver 300, the timing controller 400, the level shifter 500, and the gamma voltage generator 600 may be integrated into a display driver.

[0037] The display panel 100 may be a flat display panel, or may be a flexible display panel whose shape may be modified such as a foldable display panel, a bendable display panel, a rollable display panel, or a stretchable display panel.

[0038] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

[0039] The display area DA may include a plurality of sub-pixels SP arranged in a matrix. The sub-pixel matrix provided in the display area DA may include a plurality of row lines and a plurality of column lines respectively connected to the plurality of sub-pixels SP.

[0040] Each sub-pixel SP may be any one of a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, a blue sub-pixel for emitting blue light, and a white sub-pixel for emitting white light. In addition, a unit pixel may include at least two sub-pixels SP.

[0041] The display area DA may include a plurality of signal lines connected to each sub-pixel SP. The plurality of signal lines may include a plurality of gate lines 12, 14 and 16, a data line 22, a plurality of power lines 24, 32 and 34, and a plurality of mode control lines 42 and 44.

[0042] The plurality of gate lines 12, 14, and 16 may include first and second scan lines 12 and 14 and a light emission control line 16. Each of the first and second scan lines 12 and 14 may provide a first scan signal SCAN1 and a second scan signal SCAN2 provided from the gate driver 200 to each corresponding sub-pixel SP, and the light emission control line 16 may provide a light emission control signal EM provided from the gate driver 200 to each corresponding sub-pixel SP.

[0043] The data line 22 may provide the data voltage Vdata provided from the data driver 300 to each corresponding sub-pixel SP.

[0044] The plurality of power lines 24, 32, and 34 may include an initialization voltage line 24, a first power line 32, and a second power line 34. The initialization voltage line 24 may provide an initialization voltage Vref provided from the power management circuit 700 to each corresponding sub-pixel SP, the first power line 32 may provide a high potential power voltage EVDD to each corresponding sub-pixel SP, and the second power line 34 may provide a low potential power voltage EVSS to each corresponding sub-pixel SP.

[0045] The plurality of mode control lines 42 and 44 may include a first mode control line 42 and a second mode control line 44. The first mode control line 42 may provide a first mode control signal SH provided from the data driver 300 or a separate mode controller (not shown) to each corresponding sub-pixel SP, and the second mode control line 44 may provide a second mode control signal PR provided from the data driver 300 or a separate mode controller to each corresponding sub-pixel SP.

[0046] The display device or display panel 100 can selectively drive the first light emitting element and the second light emitting element of each sub-pixel SP through a plurality of mode control signals SH and PR. Therefore, the display area DA can be driven by being divided into a plurality of areas, and the proportion or size of each of the plurality of areas can be freely adjusted in the first direction X and the second direction Y.

[0047] The gate driver 200 may be disposed in the non-display area NDA. The gate driver 200 may include a scan driver 210 and a light emission control driver 220. The scan driver 210 may provide a first scan signal SCAN1 and a second scan signal SCAN2 to the first scan line 12 and the second scan line 14, respectively, and the light emission control driver 220 may provide a light emission control signal EM to the light emission control line 16.

[0048] Each of the scan driver 210 and the light emission control driver 220 may operate by receiving a plurality of gate control signals provided by the timing controller 400 through the level shifter 500 .

[0049] The data driver 300 may convert digital data provided together with the data control signal from the timing controller 400 into an analog data signal and provide the data voltage Vdata to the data line 22 of the display panel 100. The data driver 300 may subdivide a plurality of reference gamma voltages provided from the gamma voltage generator 600 and convert the digital data into an analog data voltage by using the subdivided gamma voltages.

[0050] In addition, the data driver 300 may generate a plurality of mode control signals SH and PR, and respectively provide the generated mode control signals SH and PR to a plurality of mode control lines 42 and 44 of the display panel 100. Alternatively, the plurality of mode control signals SH and PR may be generated by a mode controller (not shown) separate from the data driver 300, and provided to the display panel 100 through a circuit film on which the data driver IC is packaged.

[0051] The timing controller 400 may control the gate driver 200 and the data driver 300 by using a timing control signal provided from a host system and timing setting information stored therein.

[0052] The timing controller 400 may generate a plurality of gate control signals for controlling the driving timing of the gate driver 200 and provide them to the gate driver 200. Alternatively, the timing controller 400 may generate a control signal for timing control and provide the control signal to the level shifter 500, so that the level shifter 500 may generate a plurality of gate control signals and provide the gate control signals to the gate driver 200.

[0053] The timing controller 400 may generate a plurality of data control signals for controlling the driving timing of the data driver 300, and provide the generated data control signals to the data driver 300. Alternatively, the timing controller 400 may perform various image processing including image quality correction, degradation correction, and illumination correction for power consumption reduction by receiving input image data, and may provide the image-processed data to the data driver 300.

[0054] The level shifter 500 may generate a plurality of gate control signals by level-shifting or logic-processing a control signal for timing control provided from the timing controller 400 and provide the generated gate control signals to the scan driver 210 and the light emission control driver 220 .

[0055] The gamma voltage generator 600 may generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and provide the generated reference gamma voltages to the data driver 300 .

[0056] The power management circuit 700 can generate and provide a plurality of driving voltages for the operation of all circuit elements of the display device by using the input voltage. For example, the power management circuit 700 can generate a first power voltage EVDD, a second power voltage EVSS, and an initialization voltage Vref, and provide the generated voltages to the display panel 100. In addition, the power management circuit 700 can generate and provide various driving voltages for the operation of the gate driver 200, the data driver 300, the timing controller 400, the level shifter 500, and the gamma voltage generator 600.

[0057] Figure 2A and Figure 2B 2 is a diagram illustrating various forms in which the ratio of the first display area DA1 and the second display area DA2 may be changed in the display device according to an exemplary embodiment of the present disclosure.

[0058] like Figure 2A and Figure 2B As shown, the display area DA of the display panel 100 may include a first display area DA1 and a second display area DA2. The first display area DA1 may be a first mode (SH) area according to a first mode control signal SH, and the second display area DA2 may be a second mode (PR) area according to a second mode control signal PR. For example, the first mode (SH) area may be a shared mode area, and the second mode (PR) area may be a privacy mode area.

[0059] exist Figure 2A and Figure 2B In the embodiment, the first direction X can be expressed as a left-right direction, a horizontal direction, a parallel direction, or an X-axis direction. In addition, the second direction Y is a direction perpendicular to the first direction X, and can be expressed as an up-down direction, a vertical direction, a perpendicular direction, or a Y-axis direction.

[0060] like Figure 2A As shown, the first display area DA1 may be an area extending from the left end and the upper end of the display area DA along the first direction X and the second direction Y, and the second display area DA2 may be an area from the entire display area DA excluding the first display area DA1. In addition, the first display area DA1 may extend to the right end of the display area DA in the first direction X. In addition, the first display area DA1 may extend to the lower end of the display area DA in the second direction Y.

[0061] like Figure 2BAs shown, the second display area DA2 may be an area extending from the right end and the lower end of the display area DA along the first direction X and the second direction Y, and the first display area DA1 may be an area of ​​the entire display area DA that does not include the second display area DA2. In addition, the second display area DA2 may extend to the left end of the display area DA in the first direction X. In addition, the second display area DA2 may extend to the upper end of the display area DA in the second direction Y.

[0062] Apart from Figure 2A and Figure 2B In addition to the illustrated example, the ratio and size of the first display area DA1 and the second display area DA2 may be changed in various forms along the first direction X and the second direction Y.

[0063] Figure 3 is a circuit diagram illustrating one example sub-pixel SP of a display device according to an example embodiment of the present disclosure.

[0064] One subpixel SP may include a plurality of transistors DT and T1 to T7, a plurality of light emitting elements EL1 and EL2, and a storage capacitor Cst. The plurality of transistors DT and T1 to T7 may include a driving transistor DT and first to seventh switching transistors T1 to T7.

[0065] Each of the plurality of transistors DT and T1 to T7 of each sub-pixel SP includes a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode can be changed according to the direction of the voltage and current applied to the gate electrode instead of being fixed, one of the source electrode and the drain electrode can be represented as a first electrode, and the other can be represented as a second electrode.

[0066] The plurality of light emitting elements EL1 and EL2 may include a first light emitting element EL1 and a second light emitting element EL2. The first light emitting element EL1 may include an anode connected to the sixth switching transistor T6 and a cathode supplied with a second power supply voltage EVSS from the second power supply line 34. In addition, the second light emitting element EL2 may include an anode connected to the seventh switching transistor T7 and a cathode supplied with a second power supply voltage EVSS from the second power supply line 34.

[0067] The first light emitting element EL1 can be provided with a driving current from the driving transistor DT through the sixth switching transistor T6, and the second light emitting element EL2 can be provided with a driving current from the driving transistor DT through the seventh switching transistor T7. Therefore, the first light emitting element EL1 and the second light emitting element EL2 can emit light with brightness proportional to the current value of the driving current.

[0068] A first electrode of the driving transistor DT may be connected to a first power line 32 for providing a first power voltage EVDD. As described above, the first power voltage EVDD may be provided from the power management circuit 700. A second electrode of the driving transistor DT may be connected to first electrodes of the sixth switching transistor T6 and the seventh switching transistor T7. The driving transistor DT may drive the first light emitting element EL1 through the sixth switching transistor T6, and may drive the second light emitting element EL2 through the seventh switching transistor T7.

[0069] The driving transistor DT may control the light emission intensities of the first light emitting element EL1 and the second light emitting element EL2 through the sixth switching transistor T6 and the seventh switching transistor T7 , respectively, by controlling the driving current Ids according to the driving voltage Vgs of the driving transistor DT.

[0070] The storage capacitor Cst may be connected between the gate electrode and the second electrode of the driving transistor DT to charge the driving voltage Vgs corresponding to the data voltage Vdata. During the non-emission period, the storage capacitor Cst may maintain the charged driving voltage Vgs and provide it to the driving transistor DT.

[0071] The first switching transistor T1 may operate according to a first scan signal SCAN1 applied through the first scan line 12. In addition, the first switching transistor T1 may provide a data voltage Vdata provided through the data line 22 to the first electrode of the storage capacitor Cst.

[0072] The second switching transistor T2 may operate according to the second scan signal SCAN2 applied through the second scan line 14. In addition, the second switching transistor T2 may charge the storage capacitor Cst to the threshold voltage Vth of the driving transistor DT.

[0073] The third switching transistor T3 may operate according to the light emission control signal EM. The third switching transistor T3 may provide an initialization voltage Vref provided through the initialization voltage line 24 to the first electrode of the storage capacitor Cst.

[0074] The fourth and fifth switching transistors T4 and T5 may operate according to the second scan signal SCAN2 and may provide the initialization voltage Vref provided through the initialization voltage line 24 to the anodes of the first and second light emitting elements EL1 and EL2, respectively.

[0075] The sixth switching transistor T6 and the seventh switching transistor T7 may be operated according to the first mode control signal SH and the second mode control signal PR. The first electrodes of the sixth switching transistor T6 and the seventh switching transistor T7 may be connected to the driving transistor DT, and the second electrodes of the sixth switching transistor T6 and the seventh switching transistor T7 may be connected to the first light emitting element EL1 and the second light emitting element EL2, respectively.

[0076] The first mode control signal SH and the second mode control signal PR may be provided from the data driver 300 or the mode controller (not shown). When each sub-pixel SP operates in the first mode SH, the first mode control signal SH may be activated by a gate-on voltage, and the second mode control signal PR may be deactivated by a gate-off voltage. In addition, when each sub-pixel SP operates in the second mode PR, the first mode control signal SH may be deactivated by a gate-off voltage, and the second mode control signal PR may be activated by a gate-on voltage.

[0077] Figure 4 1 is a diagram illustrating a driving waveform of an example sub-pixel SP of a display device according to an example embodiment of the present disclosure. Each sub-pixel SP may be driven by being divided into a first period t1 to a fifth period t5. The first period t1 to the fifth period t5 may be continuous without overlapping each other. Figures 5 to 9 The driving process of the sub-pixel SP is described in detail.

[0078] Figure 5 1 is a diagram illustrating a circuit driving of an exemplary sub-pixel of a display device according to an exemplary embodiment of the present disclosure in a first period t1. The first period t1 may be referred to as an initial period.

[0079] At the first period t1, the light emitting control signal EM of the low voltage state is applied so that the third switching transistor T3 may be turned on. Therefore, the initialization voltage Vref applied to the initialization voltage line 24 may be applied to the first node n1.

[0080] The second scan signal SCAN2 in a low voltage state is applied so that the second switch transistor T2, the fourth switch transistor T4 and the fifth switch transistor T5 can be turned on. In addition, the second mode control signal PR in a low voltage state is applied so that the seventh switch transistor T7 can be turned on. Therefore, the initialization voltage Vref applied to the initialization voltage line 24 can be applied to the second node n2 and the third node n3.

[0081] In this case, since the first terminal and the second terminal of the storage capacitor Cst are connected to the first node n1 and the second node n2, the first terminal and the second terminal of the storage capacitor Cst can be initialized to the initialization voltage Vref. In addition, since the gate electrode and the second electrode of the driving transistor DT are respectively connected to the second node n2 and the third node n3, each of the gate electrode and the second electrode of the driving transistor DT can be initialized to the initialization voltage Vref.

[0082] The initialization voltage Vref may be selected within a voltage range sufficiently lower than the driving voltage of the first light emitting element EL1 and the second light emitting element EL2, and may be set to a voltage equal to or lower than the voltage of the second power supply voltage EVSS. For example, the potential difference between the initialization voltage Vref applied to the anodes of the first light emitting element EL1 and the second light emitting element EL2 and the second power supply voltage EVSS applied to the cathodes may be lower than the threshold voltages of the first light emitting element EL1 and the second light emitting element EL2. Therefore, since no current flows to the second light emitting element EL2 even if the seventh switching transistor T7 is turned on during the first period t1, the first light emitting element EL1 and the second light emitting element EL2 may not emit light.

[0083] In addition, although Figure 5 The seventh switching transistor T7 is shown turned on by applying the second mode control signal PR in a low voltage state, but the sixth switching transistor T6 may be turned on and used by applying the first mode control signal SH in a low voltage state.

[0084] Figure 6 2 is a diagram illustrating a circuit driving of an exemplary subpixel of a display device according to an exemplary embodiment of the present disclosure in a second period t2. The second period t2 may be referred to as an on-bias stress (OBS) period. The OBS period may be a period in which a bias voltage is directly applied to the driving transistor DT.

[0085] At the second period t2, the light emitting control signal EM may maintain a low voltage state, and the second scan signal SCAN2 and the second mode control signal PR may change from a low voltage state to a high voltage state. Therefore, the third switch transistor T3 may maintain a turned-on state, and the second switch transistor T2, the fourth switch transistor T4, the fifth switch transistor T5, and the seventh switch transistor T7 may change from a turned-on state to a turned-off state.

[0086] In addition, the driving transistor DT turned on in the first period t1 may remain in the turned-on state even in the second period t2. In this case, since the second switch transistor T2, the fourth switch transistor T4, the fifth switch transistor T5, the sixth switch transistor T6 and the seventh switch transistor T7 are all in the cut-off state, the third node n3 may be in an open state. For example, the second electrode of the driving transistor DT connected to the third node n3 may also be in an open state. In this case, since the first electrode of the driving transistor DT is in a state where the first power supply voltage EVDD is applied, the second electrode of the driving transistor DT may be changed from the initialization voltage Vref to the first power supply voltage EVDD. For example, the voltage of the second electrode of the driving transistor DT may be increased.

[0087] Therefore, compared with the case where the initialization voltage Vref is applied to the third node n3 at the first period t1, the first power voltage EVDD having a voltage greater than the initialization voltage Vref may be applied to the third node n3 at the second period t2. Therefore, the OBS effect may be improved at the second period t2 compared with the first period t1.

[0088] Specifically, due to the hysteresis characteristics of the driving transistor DT, the threshold voltage Vth of the driving transistor DT can be changed by the value of the gate-source voltage Vgs of the driving transistor DT. However, by applying the first power supply voltage EVDD to the first electrode and the second electrode of the driving transistor DT during the second period t2, the gate-source voltage Vgs of the driving transistor DT can be biased to a specific voltage, and the source-drain current Ids can flow to the driving transistor DT.

[0089] Therefore, in the exemplary embodiment of the present disclosure, the bias voltage can be applied to the driving transistor DT through the existing first power voltage EVDD without forming a power supply for additionally applying a voltage. As a result, the exemplary embodiment of the present disclosure can reduce the hysteresis of the driving transistor DT.

[0090] Figure 7 2 is a diagram illustrating circuit driving of an exemplary sub-pixel of a display device according to an exemplary embodiment of the present disclosure in a third period t3. The third period t3 may be referred to as a sampling period.

[0091] At the third period t3, the light emitting control signal EM can be changed from a low voltage state to a high voltage state, and the second scan signal SCAN2 can be changed from a high voltage state to a low voltage state. Therefore, the third switch transistor T3 can be changed from a conducting state to a cut-off state, and the second switch transistor T2, the fourth switch transistor T4, and the fifth switch transistor T5 can be changed from a cut-off state to a conducting state.

[0092] The third switching transistor T3 may be changed to a cut-off state, and the driving transistor DT may be in a diode connection state. For example, the gate electrode and the second electrode of the driving transistor DT are connected to each other, and the driving transistor DT may operate like a diode. In this case, at the third period t3, the source-drain current Ids may flow to the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are in a diode connection state, the voltage of the second node n2 may be increased by the current flowing from the source electrode to the drain electrode until the gate-source voltage Vgs of the driving transistor DT reaches the threshold voltage Vth. For example, during the third period t3, the voltage of the second node n2 may be charged with a voltage EVDD-|Vth| corresponding to the difference between the first power supply voltage EVDD and the threshold voltage Vth of the driving transistor DT. For example, the threshold voltage Vth of the driving transistor DT may be sampled. In addition, since the gate-source voltage Vgs of the driving transistor DT increases until it reaches the threshold voltage Vth, the driving transistor DT may be cut off.

[0093] Figure 8 2 is a diagram illustrating circuit driving of an exemplary sub-pixel of a display device according to an exemplary embodiment of the present disclosure in a fourth period t4. The fourth period t4 may be referred to as a data period.

[0094] At the fourth period t4, the first scan signal SCAN1 may be changed from a high voltage state to a low voltage state. Therefore, the first switch transistor T1 may be changed from an off state to an on state. In addition, the third switch transistor T3 may remain in an off state, and the second switch transistor T2, the fourth switch transistor T4, and the fifth switch transistor T5 may remain in an on state.

[0095] In addition, the driving transistor DT may be maintained in the off state. Therefore, the voltage of the second node n2 may maintain the difference voltage EVDD-|Vth| between the first power supply voltage EVDD and the threshold voltage Vth.

[0096] Since the first switching transistor T1 is turned on, the data voltage Vdata may be applied to the first electrode of the storage capacitor Cst. Therefore, the storage capacitor Cst may store a voltage EVDD-|Vth|-Vdata corresponding to a difference between the data voltage Vdata and the difference voltage EVDD-|Vth|.

[0097] Fig. 9 2 is a diagram illustrating a circuit driving of an exemplary sub-pixel of a display device according to an exemplary embodiment of the present disclosure in a fifth period t5. The fifth period t5 may be referred to as a light emitting period.

[0098] At the fifth period t5, the first scan signal SCAN1 and the second scan signal SCAN2 can be changed from a low voltage state to a high voltage state, and the light emission control signal EM and the second mode control signal PR can be changed from a high voltage state to a low voltage state. Therefore, the first switch transistor T1, the second switch transistor T2, the fourth switch transistor T4 and the fifth switch transistor T5 can be changed from a conducting state to a cut-off state. In addition, the third switch transistor T3 and the seventh switch transistor T7 can be changed from a cut-off state to a conducting state.

[0099] Since the third switch transistor T3 is turned on, the second electrode of the storage capacitor Cst can be connected to the gate electrode of the drive transistor DT. Therefore, the drive transistor DT can be turned on so that the source-drain current (or drive current) Ids can flow. In addition, since the seventh switch transistor T7 is turned on, the source-drain current Ids can flow to the second light-emitting element EL2 through the seventh switch transistor T7. Therefore, the second light-emitting element EL2 can emit light.

[0100] In addition, although Fig. 9 It is disclosed that the second light emitting element EL2 emits light based on the driving current Ids flowing through the seventh switching transistor T7, but the first light emitting element EL1 can emit light based on the driving current Ids flowing through the sixth switching transistor T6 by applying the first mode control signal SH in a low voltage state to turn on the sixth switching transistor T6.

[0101] In this case, since the second electrode of the driving transistor DT is applied with the first power supply voltage EVDD through the second period t2, the second electrode of the driving transistor DT may be at the first power supply voltage EVDD even in the fifth period t5. Therefore, when the sixth switching transistor T6 or the seventh switching transistor T7 is turned on, the amount of time for charging the anode of the first light emitting element EL1 or the second light emitting element EL2 may be reduced compared to the state in which the second electrode of the driving transistor DT is at the initialization voltage Vref. As a result, according to the exemplary embodiment of the present disclosure, since the light emitting element may be driven in the state in which the second electrode of the driving transistor DT is at the first power supply voltage EVDD, the response speed of the sub-pixel SP may be improved.

[0102] Fig.10 is a diagram illustrating a driving waveform of a sub-pixel of a display device according to another example embodiment of the present disclosure.

[0103] and Figure 4 In contrast, the sixth period t6 and the seventh period t7 may be additionally performed between the first period t1 and the second period t2. The sixth period t6 and the seventh period t7 may be continuously performed between the first period t1 and the second period t2 without overlapping.

[0104] Fig.11 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a sixth period t6 according to an example embodiment of the present disclosure.

[0105] At the sixth period t6, the first scan signal SCAN1 and the second scan signal SCAN2 may be maintained in the state of the first period t1, and the light emitting control signal EM and the second mode control signal PR may be changed from a low voltage state to a high voltage state. Therefore, the third switching transistor T3 and the seventh switching transistor T7 may be changed from a turn-on state to a turn-off state. As a result, the gate electrode of the driving transistor DT may be disconnected from the initialization voltage line 24 for providing the initialization voltage Vref, and the second electrode of the driving transistor DT may be disconnected from the second light emitting element EL2.

[0106] Fig.12 is a diagram illustrating circuit driving of an example sub-pixel of a display device in a seventh period t7 according to an example embodiment of the present disclosure.

[0107] At the seventh period t7, the second scan signal SCAN2 may be changed from a low voltage state to a high voltage state. Therefore, the second switch transistor T2, the fourth switch transistor T4, and the fifth switch transistor T5 may be changed from an on state to an off state. As a result, the gate electrode of the drive transistor DT may be disconnected from the second electrode of the drive transistor DT, and the anodes of the first light emitting element EL1 and the second light emitting element EL2 may be disconnected from the initialization voltage line 24 for providing the initialization voltage Vref.

[0108] That is, in another example embodiment of the present disclosure, the switch transistor connected to each electrode of the driving transistor DT may be sequentially turned off through the sixth period t6 and the seventh period t7. Therefore, after the sixth period t6 and the seventh period t7, when the light emitting control signal EM is applied again in the second period t2 to turn on the third switching transistor T3, the initialization voltage line 24 for providing the initialization voltage Vref may be more stably connected to the gate electrode of the driving transistor DT through the third switching transistor T3. As a result, the sub-pixel SP may be driven more stably.

[0109] According to the exemplary embodiments of the present disclosure, the following advantageous effects can be obtained.

[0110] According to an example embodiment of the present disclosure, a turn-on bias voltage may be applied to a driving transistor by a high potential power supply voltage, so that a response speed of a sub-pixel may be increased.

[0111] It will be apparent to those skilled in the art that the present disclosure is not limited to the above-described example embodiments and the accompanying drawings, and that various substitutions, modifications, and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the above example embodiments of the present disclosure are provided for illustrative purposes and are not intended to limit the scope or technical concept of the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims and their equivalents, and the present disclosure is intended to cover all modifications and variations of the present disclosure that fall within the scope of the claims and their equivalents.

[0112] CROSS-REFERENCE TO RELATED APPLICATIONS

[0113] This application claims the benefit of Korean Patent Application No. 10-2023-0150957, filed on November 3, 2023, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: A display panel having a display area including a plurality of sub-pixels, at least one sub-pixel of the plurality of sub-pixels comprising: a drive transistor having a first electrode connected to a first power line configured to receive a first power voltage; a first switching transistor connected to the data line and having a gate electrode configured to receive a first scan signal; a second switching transistor connected between the gate electrode and the second electrode of the driving transistor and having a gate electrode configured to receive a second scanning signal; and A third switching transistor is connected to the gate electrode of the driving transistor and has a gate electrode configured to receive a light emitting control signal.

2. The display device according to claim 1, wherein: The at least one sub-pixel among the plurality of sub-pixels further comprises: a fourth switching transistor and a fifth switching transistor, each of the fourth switching transistor and the fifth switching transistor having a gate electrode configured to receive the second scanning signal; a sixth switching transistor and a seventh switching transistor, each of which has a first electrode connected to the second electrode of the driving transistor; a storage capacitor connected between the first switching transistor and the gate electrode of the driving transistor; a first light emitting element connected to the second electrode of the sixth switch transistor; and A second light emitting element is connected to the second electrode of the seventh switch transistor.

3. The display device according to claim 2, wherein: The sixth switch transistor has a gate electrode configured to receive a first mode signal, and the seventh switch transistor has a gate electrode configured to receive a second mode signal, and The first light emitting element and the second light emitting element are configured not to emit light at the same time.

4. The display device according to claim 2, wherein: The fourth switching transistor has a first electrode connected to the third switching transistor and a second electrode connected to the sixth switching transistor, and The fifth switching transistor has a first electrode connected to the third switching transistor and a second electrode connected to the seventh switching transistor.

5. The display device according to claim 1, wherein: The at least one sub-pixel among the plurality of sub-pixels further comprises: a storage capacitor connected between the first switching transistor and the gate electrode of the driving transistor; and a light emitting element connected between the second electrode of the driving transistor and a second power supply line configured to receive a second power supply voltage, The at least one sub-pixel among the plurality of sub-pixels is configured to be driven in a first period to a fifth period, During the first period, the first switching transistor is configured to be in an off state, and the second switching transistor and the third switching transistor are configured to be in an on state to initialize the voltage stored in the storage capacitor, During a second period after the first period, the second electrode of the driving transistor is configured to be in an open state, During a third period after the second period, the threshold voltage of the driving transistor is configured to be sampled, During a fourth period after the third period, the first switch transistor is configured to be in a turned-on state to apply the data voltage on the data line to the storage capacitor, and During a fifth period after the fourth period, the light emitting element is configured to emit light.

6. The display device according to claim 1, wherein: The third switching transistor is connected between the gate electrode of the driving transistor and an initialization voltage line configured to receive an initialization voltage, and During a first period, the second switching transistor and the third switching transistor are configured to be in a turned-on state to apply the initialization voltage to the gate electrode and the second electrode of the driving transistor.

7. The display device according to claim 6, wherein: During a second period following said first period: The third switching transistor is configured to be in the on-state, and the second switching transistor is configured to be in the off-state, and The voltage at the second electrode of the driving transistor is configured to increase from the initialization voltage.

8. The display device according to claim 7, wherein: During the second period: The first electrode of the driving transistor is configured to receive the first power supply voltage, and The voltage at the second electrode of the driving transistor is configured to increase to be equal to the first power supply voltage.

9. The display device according to claim 7, wherein: During a third period following the second period: The third switching transistor is configured to be in the off state, and the second switching transistor is configured to be in the on state.

10. The display device according to claim 9, wherein: During a fourth period subsequent to the third period: The second switching transistor is configured to be in the on state, and The first switching transistor is configured to be in the on-state so that the data voltage applied to the data line is applied to the gate electrode of the driving transistor through the first switching transistor.

11. The display device according to claim 10, wherein: The at least one sub-pixel among the plurality of sub-pixels further comprises: a fourth switching transistor or a fifth switching transistor, the fourth switching transistor or the fifth switching transistor having a gate electrode configured to receive the second scanning signal; and a sixth switching transistor or a seventh switching transistor, the sixth switching transistor or the seventh switching transistor having a first electrode connected to the second electrode of the driving transistor, and During a fifth time period after the fourth time period, the first switching transistor and the second switching transistor are configured to be in the off state, and the sixth switching transistor and one of the seventh switching transistors connected to the second electrode of the driving transistor and the third switching transistor are configured to be in the on state.

12. The display device according to claim 11, wherein: At least one of the plurality of sub-pixels further includes a first light emitting element connected to the second electrode of the sixth switch transistor or a second light emitting element connected to the second electrode of the seventh switch transistor, and During the fifth period, the first light emitting element or the second light emitting element is configured to emit light.

13. The display device according to claim 7, wherein: During a sixth period after the first period and before the second period, the first switching transistor is configured to be in the off state, the second switching transistor is configured to be in the on state, and the third switching transistor is configured to be in the off state.

14. The display device according to claim 13, wherein: During a seventh period after the sixth period and before the second period, the first switching transistor is configured to be in the off state, the second switching transistor is configured to be in the off state, and the third switching transistor is configured to be in the off state.

15. A display device, comprising: The display panel comprises a plurality of sub-pixels, and at least one sub-pixel among the plurality of sub-pixels comprises: a first switching transistor having a gate electrode configured to receive a first scan signal, a first electrode connected to the data line, and a second electrode connected to the first node; a driving transistor having a gate electrode connected to the second node, a first electrode connected to a first power line configured to receive a first power supply voltage, and a second electrode connected to a third node; a second switching transistor having a gate electrode configured to receive a second scan signal, a first electrode connected to the second node, and a second electrode connected to the third node; a third switch transistor having a gate electrode configured to receive a light emission control signal, a first electrode connected to the first node, and a second electrode connected to an initialization voltage line configured to receive an initialization voltage; a storage capacitor connected between the first node and the second node; and At least one light emitting element is connected between the third node and a second power line configured to receive a second power voltage.

16. The display device according to claim 15, wherein: During a first period, the first scan signal is configured to be at a gate-off voltage, the second scan signal is configured to be at a gate-on voltage, and the light emission control signal is configured to be at a gate-on voltage, and During a second period after the first period, the first scan signal is configured to be at the gate-off voltage, the second scan signal is configured to be at the gate-off voltage, and the light emission control signal is configured to be at the gate-on voltage.

17. The display device according to claim 16, wherein: During a third period after the second period, the first scan signal is configured to be at the gate-off voltage, the second scan signal is configured to be at the gate-on voltage, and the light emission control signal is configured to be at the gate-off voltage, During a fourth period after the third period, the first scan signal is configured to be at a gate-on voltage, the second scan signal is configured to be at the gate-on voltage, and the light emission control signal is configured to be at the gate-off voltage, and During a fifth period after the fourth period, the first scan signal is configured to be at the gate-off voltage, the second scan signal is configured to be at the gate-off voltage, and the light emission control signal is configured to be at the gate-on voltage.

18. The display device according to claim 16, wherein: During a sixth period after the first period and before the second period, the first scan signal is configured to be at the gate-off voltage, the second scan signal is configured to be at the gate-on voltage, and the light emission control signal is configured to be at the gate-off voltage.

19. The display device according to claim 18, wherein: During a seventh period after the sixth period and before the second period, the first scan signal is configured to be at the gate-off voltage, the second scan signal is configured to be at the gate-off voltage, and the light emitting control signal is configured to be at the gate-off voltage.

20. The display device according to claim 15, wherein: The at least one sub-pixel among the plurality of sub-pixels further comprises: a fourth switching transistor having a gate electrode configured to receive the second scan signal, the first electrode connected to the initialization voltage line, and a second electrode connected to an anode of a first light emitting element among the at least one light emitting element; a fifth switching transistor having a gate electrode configured to receive the second scan signal, the first electrode connected to the initialization voltage line, and a second electrode connected to an anode of a second light emitting element among the at least one light emitting element; a sixth switching transistor having a gate electrode configured to receive a first mode signal, a first electrode connected to the third node, and a second electrode connected to the anode of the first light emitting element; and A seventh switch transistor has a gate electrode configured to receive a second mode signal, a first electrode connected to the third node, and a second electrode connected to the anode of the second light emitting element.

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