Display panel and display device

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a display panel and display equipment. The display panel comprises 2N rows of scanning lines; in the M columns of data lines, the (3i-2) th column of data lines is electrically connected with the (3i + 1) th column of data lines, the (3i-1) th column of data lines is electrically connected with the (3i + 2) th column of data lines, and the (3i) th column of data lines is electrically connected with the (3i + 3) th column of data lines; each pixel circuit comprises a pixel unit and a control unit, in the n row of pixel circuit, the control ends of the control units in the (3i-2) column, the (3i-1) column and the (3i-i) column are respectively connected with the (2n-1) row of scanning line, and the control ends of the control units in the (3i + 1) column, the (3i + 2) column and the (3i + 3) column are respectively connected with the (2n) row of scanning line; or the control ends of the control units in the (3i-2) th column, the (3i-1) th column and the (3i) th column are respectively connected with the (2n-1) th row of scanning lines, and the control ends of the control units in the (3i + 1) th column, the (3i + 2) th column and the (3i + 3) th column are respectively connected with the (2n-1) th row of scanning lines; by controlling the opening mode of the scanning lines, two horizontal pixels can be merged.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and in particular relates to a display panel and a display device. Background Art

[0002] The display industry is now pursuing higher and higher refresh rates. Recently, a technology has emerged that uses low refresh drives to display high refresh rates, called HSR (Hardware Super Resulation). For example, a 4K×2K UHD (Ultra High Definition) 60Hz display can be displayed at 4K×1K UHD 120Hz by adjusting the timing; however, in related technologies, the refresh rate is doubled by merging two rows into one row of pixels by changing the charging timing, and the merging of two columns of pixels cannot be achieved. Summary of the invention

[0003] The present application provides a display panel and a display device, which solves the problem that the display panel cannot realize the merging of two columns of pixels.

[0004] In a first aspect, the present application provides a display panel, the display panel comprising: 2N rows of scan lines; M columns of data lines, the 3i-2 column data line is electrically connected to the 3i+1 column data line, the 3i-1 column data line is electrically connected to the 3i+2 column data line, and the 3i column data line is electrically connected to the 3i+3 column data line; N rows × M columns of pixel circuits, each pixel circuit comprising a pixel unit and a control unit, the control unit comprising a control terminal, a first connection terminal and a second connection terminal; the first connection terminal of each control unit is electrically connected to the data line of the corresponding column, and the second connection terminal of each control unit is connected to the input terminal of the corresponding pixel unit; the control The unit is used to charge the pixel unit through the data signal on the data line when it is in the on state; in the nth row pixel circuit: the control ends of the 3i-2nd column, 3i-1st column and 3ith column control units are respectively connected to the 2n-1th row scan line, and the control ends of the 3i+1st column, 3i+2nd column and 3i+3rd column control units are respectively connected to the 2nth row scan line; or the control ends of the 3i-2nd column, 3i-1st column and 3ith column control units are respectively connected to the 2nth row scan line, and the control ends of the 3i+1st column, 3i+2nd column and 3i+3rd column control units are respectively connected to the 2n-1th row scan line; wherein, n=[1,2,…,N],where N and M are both positive integers greater than 1.

[0005] Optionally, the pixel units in the 3m-2th column and the 3m+1th column are first color sub-pixels, the pixel units in the 3m-1th column and the 3m+2th column are second color sub-pixels, and the pixel units in the 3mth column and the 3m+3th column are third color sub-pixels; wherein,

[0006] Optionally, the control unit includes: a switch transistor, a gate of the switch transistor serves as a control terminal of the control unit, a first terminal of the switch transistor is connected to the data line, and a second terminal of the switch transistor is connected to the pixel unit.

[0007] Optionally, the pixel unit includes: a liquid crystal capacitor, a pixel electrode of the liquid crystal capacitor is connected to the second end of the switching transistor; or, the pixel unit includes: a storage capacitor, a driving transistor and a light-emitting diode; the first end of the storage capacitor is connected to the second connection end of the control unit, the second end of the storage capacitor is connected to the power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is grounded.

[0008] Optionally, when the pixel unit includes a liquid crystal capacitor, N rows of scan lines are turned on row by row.

[0009] Optionally, when the pixel unit includes a light emitting diode, the scanning lines are turned on row by row in the order of the 4n-3rd scanning line, the 4n-2nd scanning line, the 4n-1th scanning line and the 4nth scanning line.

[0010] Optionally, the 2n-1th row of scan lines and the 2nth row of scan lines are turned on simultaneously, and the 2n-1th row of scan lines and the 2n+1th row of scan lines are turned on row by row.

[0011] Optionally, the 4n-3th scan line and the 4n-1th scan line are turned on simultaneously, the 4n-2th scan line and the 4nth scan line are turned on simultaneously, and the 4n-3th scan line and the 4n-2th scan line are turned on row by row.

[0012] Optionally, the 4n-3rd scan line, the 4n-2nd scan line, the 4n-1th scan line and the 4nth scan line are turned on simultaneously, and the 4n-3rd scan line and the 4n+1th scan line are turned on row by row.

[0013] In a second aspect, the present application provides a display device, comprising: a gate drive circuit for outputting a scan signal; a source drive circuit for outputting a data signal; and a display panel, wherein the scan line of the display panel is connected to the gate drive circuit, and the data line of the display panel is connected to the source drive circuit.

[0014] The technical solution provided by this application has at least the following beneficial effects:

[0015] 1. The present application electrically connects the 3i-2 column data line with the 3i+1 column data line, the 3i-1 column data line with the 3i+2 column data line, and the 3i column data line with the 3i+3 column data line, and connects three sub-pixels in adjacent pixels to different scan lines in units of pixels, and controls the opening mode of the scan lines to achieve horizontal merging of two pixels, that is, to achieve merged drive of two columns of display.

[0016] 2. The present application can also charge two rows of sub-pixels of two columns of pixel units at the same time by controlling the opening mode of the scan lines, thereby realizing a driving mode of merging two columns of pixels and two rows of pixels, which can increase the refresh rate by 4 times and is compatible with high-definition resolution in high-refresh mode and high-refresh mode in high-definition resolution, greatly improving product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0018] Figure 1 Shown is a schematic structural diagram of a display panel in the related art;

[0019] Figure 2 Shown is a schematic structural diagram of a display panel provided in an embodiment of the present application.

[0020] Figure 3 Shown are circuit schematic diagrams of two pixel circuits provided in embodiments of the present application.

[0021] Figure 4 Shown is a circuit diagram of a display panel provided in an embodiment of the present application.

[0022] Figure 5 The figure shows a first driving timing diagram provided in an embodiment of the present application.

[0023] Figure 6 The figure shows a second driving timing diagram provided in an embodiment of the present application.

[0024] Figure 7 The third driving timing diagram provided in the embodiment of the present application is shown.

[0025] Figure 8 The fourth driving timing diagram provided in the embodiment of the present application is shown.

[0026] Fig. 9Shown is a schematic diagram of an application of a display panel provided in an embodiment of the present application in a liquid crystal screen.

[0027] Fig.10 The fifth driving timing diagram provided in the embodiment of the present application is shown.

[0028] Fig.11 Shown is a schematic diagram of application of another display panel provided in an embodiment of the present application in a liquid crystal screen.

[0029] Description of reference numerals:

[0030] 100, display panel; 110, scan line; 120, data line; 130, pixel circuit; 131, control unit; 132, pixel unit; T1, switching transistor; T2, driving transistor; Cc, storage capacitor; Cs, pixel capacitor; Ct, energy storage capacitor; OLED, light emitting diode. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0032] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0033] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0034] The display industry is pursuing higher and higher refresh rates. Recently, a technology called HSR (Hardware Super Resulation) has emerged to drive high refresh rates with low refresh rates. For example, a 4K×2K UHD (Ultra High Definition) 60Hz display can be displayed as a 4K×1K UHD 120Hz display by adjusting the timing. Another example is a 4K×2K UHD 120Hz display can be displayed as a 4K×1K UHD 240Hz display by adjusting the timing. Because the total amount of data displayed is the same, the specifications of the driving components are the same. The refresh rate is doubled only by adjusting the timing. Of course, the resolution is halved. End customers can freely switch between these two display states through the remote control.

[0035] The driver receives display data one sub-pixel at a time, and in sequence. Then each sub-pixel in a row is processed by its own internal data channel, converted into grayscale voltage and reaches its own output port. Taking UHD as an example, Figure 1 As shown: merge the first column of red and the second column of red, TCON sends the first column of red data, then TCON copies the first column of red data and sends it again, it will be given to the second column of red, however, the purpose is to increase the refresh rate (the refresh rate is doubled after the horizontal pixel is merged), after the copy, the amount of data for a horizontal row to be sent by TCON is still the same as that of UHD, but the refresh rate is doubled, the time for a row is halved, TCON cannot send so much data, it is not feasible. If TCON sends the first column of red data, and then TCON directly sends the third column of red data, it can be found that all Driver chips receive data in sequence, the third column of red data will be given to the second column of red, and an error will also be displayed, so the existing Driver chip does not support merging two columns of pixels into one column of pixels.

[0036] Furthermore, a display panel in the existing industry can only achieve compatibility between 4K×2K×60Hz and 4K×1K×120Hz, and cannot achieve compatibility between 4K×2K×60Hz, 4K×1K×120Hz, 2K×2K×120Hz, and 2K×1K×240Hz. It is also impossible to increase the refresh rate while also involving 4K changes in 4K×2K×60Hz.

[0037] In order to solve the above problems, the present application provides a display panel, which specifically includes the following embodiments:

[0038] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application; Figure 2As shown, the display panel 100 includes: 2N rows of scan lines 110, M columns of data lines 120, and array-arranged pixel circuits 130; wherein the number of columns of the pixel circuits 130 is M, and the number of rows is N; that is, the number of columns of the pixel circuits 130 in the display panel 100 is the same as the number of data lines 120, and the number of rows of the pixel circuits 130 is half of the scan lines 110. Figure 2 The scan lines 110 and data lines 120 in FIG. 1 cross but are not connected. Figure 2 In the figure, G1, G2, G3, G4, G5 and G6 represent the first row of scan line 110, the second row of scan line 110, the third row of scan line 110, the fourth row of scan line 110, the fifth row of scan line 110 and the sixth row of scan line 110 respectively, and S1, S2, ..., S6 represent the first column of data line 120, the second column of data line 120, ..., the sixth column of data line 120 respectively.

[0039] In one embodiment, each pixel circuit 130 includes a pixel unit 132 and a control unit 131. The control unit 131 is used to input the data signal on the data line 120 into the pixel unit 132 when it is in a conductive state, thereby charging the pixel unit 132 through the data signal on the data line 120; on the contrary, when the control unit 131 is in a disconnected state (i.e., a non-conductive state), the data signal on the data line 120 cannot be input into the pixel unit 132, thereby not charging the pixel unit 132; it should be noted that the display panel 100 can be a liquid crystal display (LCD) or an OLED (Organic Light-Emitting Diode) display; when the display panel 100 is a liquid crystal display, the pixel unit 132 includes liquid crystal molecules; when the display panel 100 is an OLED display, the pixel unit 132 includes a light-emitting diode.

[0040] like Figure 2 As shown, the control unit 131 includes a control end, a first connection end and a second connection end; the first connection end of each control unit 131 is electrically connected to the data line 120 of the corresponding column, and the second connection end of each control unit 131 is connected to the input end of the corresponding pixel unit.

[0041] In this embodiment, the 3i-2nd column data line is electrically connected to the 3i+1st column data line, the 3i-1st column data line is electrically connected to the 3i+2nd column data line, the 3ith column data line is electrically connected to the 3i+3rd column data line, That is to say: i takes an odd value; when i=1, the data line in the 1st column is connected to the data line in the 4th column, the data line in the 2nd column is connected to the data line in the 5th column, and the data line in the 3rd column is connected to the data line in the 6th column; when i=3, the data line in the 7th column is connected to the data line in the 10th column, the data line in the 8th column is connected to the data line in the 11th column, and the data line in the 9th column is connected to the data line in the 12th column; and so on. The connection relationship will not be repeated here.

[0042] like Figure 2 As shown, in the nth row pixel circuit 130: the control ends of the 3i-2th column, 3i-1th column and 3ith column control units are respectively connected to the 2n-1th row scan line, and the control ends of the 3i+1th column, 3i+2th column and 3i+3th column control units are respectively connected to the 2nth row scan line.

[0043] It should be noted that n and i in this embodiment are variables, N and M are constants, the value range of variable n is 1 to N, and the value range of variable i is 1 to For odd values ​​between , N and M are both positive integers greater than 1.

[0044] For example, for the first row of pixel circuits 130, the control ends of the first column control unit 131, the second column control unit 131, the third column control unit 131, the seventh column control unit 131, the eighth column control unit 131, the ninth column control unit 131, the thirteenth column control unit 131, the fourteenth column control unit 131, the fifteenth column control unit 131... are respectively connected to the first row of scan lines 110, and the control ends of the fourth column control unit 131, the fifth column control unit 131, the sixth column control unit 131, the tenth column control unit 131, the eleventh column control unit 131, the twelfth column control unit 131... are respectively connected to the second row of scan lines 110.

[0045] In another embodiment of the present application, in the n-th row pixel circuit 130: the control ends of the 3i-2nd column, 3i-1st column and 3i-th column control units are respectively connected to the 2n-1th row scan line, and the control ends of the 3i+1st column, 3i+2nd column and 3i+3rd column control units are respectively connected to the 2nth row scan line; the control connection mode of the control unit of this embodiment and the scan line is the same as Figure 2On the contrary, for example: for the 1st row of pixel circuits 130, the control ends of the 1st column control unit 131, the 2nd column control unit 131, the 3rd column control unit 131, the 7th column control unit 131, the 8th column control unit 131, the 9th column control unit 131, the 13th column control unit 131, the 14th column control unit 131, the 15th column control unit 131... are respectively connected to the 2nd row of scan lines 110, and the control ends of the 4th column control unit 131, the 5th column control unit 131, the 6th column control unit 131, the 10th column control unit 131, the 11th column control unit 131, the 12th column control unit 131... are respectively connected to the 1st row of scan lines 110.

[0046] In one embodiment, the pixel units in the 3m-2th column and the 3m+1th column are first color sub-pixels, the pixel units in the 3m-1th column and the 3m+2th column are second color sub-pixels, and the pixel units in the 3mth column and the 3m+3th column are third color sub-pixels; wherein,

[0047] It should be noted that in the above embodiments, color mixing is performed between two adjacent rows of pixels. In order to prevent the problem of color mixing of pixels of different colors, the colors of the pixel units in the same column are the same; the first color sub-pixel, the second color sub-pixel and the third color sub-pixel represent red sub-pixels, green sub-pixels and blue sub-pixels respectively.

[0048] In one embodiment of the present application, Figure 3 As shown, the control unit 131 includes: a switch transistor T1, a gate of the switch transistor serves as a control terminal of the control unit 131, a first terminal of the switch transistor T1 is connected to the data line 120, and a second terminal of the switch transistor T1 is connected to the pixel unit.

[0049] Figure 3 3a is a circuit diagram of the first pixel unit provided in an embodiment of the present application, wherein the pixel unit 132 includes: a storage capacitor Cc, a driving transistor T2 and a light-emitting diode OLED, wherein the first end of the storage capacitor Cc is connected to the output end Vo of the control unit 131, and the second end of the storage capacitor Cc is connected to the power supply end VDD; the control end of the driving transistor T2 is connected to the first end of the storage capacitor Cc, and the first end of the driving transistor T2 is connected to the second end of the storage capacitor Cc; the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T2, and the cathode of the light-emitting diode OLED is grounded VSS.

[0050] In this embodiment, when the switch transistor T1 is in the on state, the storage capacitor Cc is charged by the data signal on the data line 120, and under the effect of the driving voltage output by the power supply end, the driving transistor T2 outputs a corresponding driving current to drive the light emitting diode OLED to emit light.

[0051] Figure 3 3b is a circuit diagram of the second pixel unit provided in an embodiment of the present application, wherein the pixel unit 132 includes: a liquid crystal capacitor, wherein the pixel electrode of the liquid crystal capacitor is connected to the second end of the switching transistor T1; wherein the liquid crystal capacitor Cs is generally formed by a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode, and data signals of different sizes are applied to the pixel electrode to rotate the liquid crystal molecules to different angles, thereby realizing brightness adjustment of the pixel unit 132.

[0052] In this embodiment, the pixel unit 132 further includes an energy storage capacitor Ct, and the pixel electrode of the energy storage capacitor Ct is connected to the second end of the switch transistor T1 to maintain the charging voltage.

[0053] Figure 4 The figure shows a circuit diagram of a display panel provided in an embodiment of the present application. This embodiment takes the 2T1C OLED application as an example. The specific driving methods include:

[0054] (1) The first driving mode: N rows of scan lines are turned on row by row; the driving timing diagram is as follows Figure 5 As shown, the horizontal scan lines are turned on row by row, first G1 is turned on, S1 charges the sub-pixels in the first column, then G2 is turned on, S4 charges the sub-pixels in the fourth column, and the same is true for other rows and columns; at a resolution such as UHD, the new DRD driving architecture provided in this embodiment reduces the number of Driver chips by half (UHD generally has 12 Driver chips, and DRD has 6 chips, which is half the number), and can display 4K×2K×60Hz.

[0055] (2) The second driving mode: the 2n-1 scan line and the 2n scan line are turned on at the same time, and the 2n-1 scan line and the 2n+1 scan line are turned on line by line. The specific driving timing diagram is as follows: Figure 6 As shown, G1G2 is turned on at the same time, and the first row of sub-pixels in the 1st and 4th columns are charged at the same time. Then G3G4 is turned on at the same time, and the second row of sub-pixels in the 1st and 4th columns are charged at the same time. The same is true for other rows and columns. This architecture can realize the horizontal merging of two pixels only by controlling the scan line opening method, and cleverly transfers the row merging originally achieved by GateLine control to column merging, thereby realizing DLS driving mode (two-column pixel merging), which is compatible with 4K×2K×60Hz and 2K×2K×120Hz displays at UHD resolution.

[0056] (3) The third driving mode: the 4n-3rd scan line and the 4n-1st scan line are turned on at the same time, the 4n-2nd scan line and the 4nth scan line are turned on at the same time, and the 4n-3rd scan line and the 4n-2nd scan line are turned on line by line. The specific driving timing diagram is as follows: Figure 7As shown, when n=1, G1G3 is turned on at the same time, and the sub-pixels in the 1st row and the 2nd row of the 1st column are charged at the same time, and then G2G4 is turned on at the same time, and the sub-pixels in the 1st row and the 2nd row of the 1st column are charged, and the same is true for other rows and columns, thereby realizing the DLG driving mode (two rows of pixels are merged); it is compatible with the display of 4K×2K×60Hz and 4K×1K×120Hz at UHD resolution.

[0057] (4) The fourth driving mode: the 4n-3rd scan line, the 4n-2nd scan line, the 4n-1th scan line and the 4nth scan line are turned on at the same time, and the 4n-3rd scan line and the 4n+1th scan line are turned on line by line. The specific driving timing diagram is as follows: Figure 8 As shown, when n=1, G1, G2, G3, and G4 are turned on at the same time, and the first two rows of sub-pixels in the 1st column and the 4th column are charged at the same time; when the 4 scan lines are turned on at the same time, two of the scan lines realize the horizontal merging of two rows, and the row merging originally controlled by the other two scan lines is cleverly transferred to the column merging by this architecture, thereby realizing the DLG and DLS driving modes at the same time; at UHD resolution, the driving architecture of this embodiment supports DLG&S mode (two rows and two columns of pixels are merged at the same time), which can display 4K×2K×60Hz (UHD) and 2K×1K×240Hz (FHD) compatibility; special Timing, four rows are turned on at the same time, which can increase the refresh rate by four times, and has ultra-high refresh but no cost increase, and can use existing driver chips in the industry, with strong universality and low implementation difficulty.

[0058] It can be seen that in this embodiment, under UHD resolution (4K×2K×60Hz working mode), the DRD driving architecture (2G1D) is adopted, that is, S1 charges two columns of sub-pixels in sequence, and the charging time of each row is as follows: Figure 1 The normal architecture (1G1D) is half of that, but when it enters FHD resolution (2K×1K×240Hz working mode), the charging time of each row will be the same as Figure 1 The common architecture (1G1D) is the same as FHD, which ensures sufficient charging time and no charging problems. For laptops or MNT monitors, UHD resolution can be used for daily office work and watching movies, and FHD (Full High Definition) resolution 240Hz high refresh mode can be used for e-sports games.

[0059] Fig. 9 The figure shows a schematic diagram of an application of a display panel provided by an embodiment of the present application in a liquid crystal screen. The gray scale of the liquid crystal screen is divided into positive and negative. First, in the high-definition display mode, if you want to charge Fig. 9Effect, turn on G1, G3, G5, G7, G9... in sequence, charge all the pixels in the first column of a frame, then turn on G2, G4, G6, G8, G10... in sequence, charge all the pixels in the fourth column of a frame, S1 output only needs to switch the positive and negative polarity once in a frame, but the computer host and TV signal source transmit display data line by line, so the driver chip needs to store a frame of data before executing, which is not supported by the current general chip, and the cost of supporting it is very high; if Figure 5 The timing is turned on row by row, and the polarity will be reversed sub-pixel by sub-pixel, resulting in higher power consumption (but for a 27-inch UHD 60Hz MNT, which is small in size and has a low refresh rate, the power consumption will not be too high and is acceptable).

[0060] The optimized driving mode is to turn on the scanning line in the order of the 4n-3rd row, the 4n-2nd row, the 4n-1st row and the 4nth row, such as Fig.10 As shown, G1, G3, G2, G4, G6, G8, G5, G7 are cycled, S1 polarity will be ++----++ cycle, connected together it is ++----++++----++++----++......, 4 positive and 4 negative are switched once, power consumption will be lower, display data only needs to store two lines, which is supported by current general chips. It should be understood that if driven by G1, G3, G5, G7, G2, G4, G6, G8, display data needs to be stored in four lines, which is not supported by current general chips (maximum 2 lines). Horizontal polarity can only be +-+-+--+-+-+ (S1 and S2, S3 and S4 output polarity at the same time must be opposite), discontinuous but balanced, there is such a 6-column inversion display.

[0061] In high refresh display mode, Figure 6 , Figure 7 and Figure 8 The driving timing shown can also be applied to LCD display. The S1 polarity does not switch in one frame, and the power consumption is low. The charging result is as follows Fig.11 , the horizontal polarity is also discontinuous but balanced between positive and negative every 12 columns.

[0062] In summary, the display panel provided by the present application has at least the following beneficial effects:

[0063] 1. The present application electrically connects the 3i-2 column data line with the 3i+1 column data line, the 3i-1 column data line with the 3i+2 column data line, and the 3i column data line with the 3i+3 column data line, and connects three sub-pixels in adjacent pixels to different scan lines in units of pixels, and controls the opening mode of the scan lines to achieve horizontal merging of two pixels, that is, to achieve merged drive of two columns of display.

[0064] 2. This application controls the 4n-3rd, 4n-2nd, 4n-1st and 4nth scanning lines to be turned on at the same time, and charges the two rows of sub-pixels of the two columns of pixel units at the same time, thereby realizing the driving mode of merging two columns of pixels and two rows of pixels, which can increase the refresh rate by 4 times and is compatible with high-definition resolution in high refresh mode and high refresh mode under high-definition resolution.

[0065] In one embodiment, the present application provides a display device, which includes: a gate driving circuit, a gate driving circuit and a display panel shown in the above embodiment; the gate driving circuit is used to output a scanning signal; the source driving circuit is used to output a data signal; the scanning line of the display panel is connected to the gate driving circuit, and the data line of the display panel is connected to the source driving circuit.

[0066] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0067] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0068] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A display panel, characterized in that: The display panel comprises: 2N scan lines; M columns of data lines, the 3i-2 column data line is electrically connected to the 3i+1 column data line, the 3i-1 column data line is electrically connected to the 3i+2 column data line, and the 3i column data line is electrically connected to the 3i+3 column data line; N rows×M columns of pixel circuits, each pixel circuit comprising a pixel unit and a control unit, the control unit comprising a control terminal, a first connection terminal and a second connection terminal; the first connection terminal of each control unit is electrically connected to a data line of a corresponding column, and the second connection terminal of each control unit is connected to an input terminal of a corresponding pixel unit; the control unit is used to charge the pixel unit through a data signal on the data line when in a conducting state; In the pixel circuit of the nth row: the control ends of the control units of the 3i-2th column, the 3i-1th column and the 3ith column are respectively connected to the scan line of the 2n-1th row, and the control ends of the control units of the 3i+1th column, the 3i+2th column and the 3i+3th column are respectively connected to the scan line of the 2nth row; or the control ends of the control units of the 3i-2th column, the 3i-1th column and the 3ith column are respectively connected to the scan line of the 2nth row, and the control ends of the control units of the 3i+1th column, the 3i+2th column and the 3i+3th column are respectively connected to the scan line of the 2n-1th row; in, n=[1,2,…,N],where N and M are both positive integers greater than 1.

2. The display panel according to claim 1, characterized in that: The pixel units in the 3m-2th column and the 3m+1th column are first color sub-pixels, the pixel units in the 3m-1th column and the 3m+2th column are second color sub-pixels, and the pixel units in the 3mth column and the 3m+3th column are third color sub-pixels; wherein, 3. The display panel according to claim 1, characterized in that: The control unit comprises: A switching transistor, wherein a gate of the switching transistor serves as a control terminal of the control unit, a first terminal of the switching transistor is connected to the data line, and a second terminal of the switching transistor is connected to the pixel unit.

4. The display panel according to claim 3, characterized in that: The pixel unit comprises: A liquid crystal capacitor, wherein a pixel electrode of the liquid crystal capacitor is connected to the second end of the switch transistor; Or, the pixel unit includes: a storage capacitor, a driving transistor and a light-emitting diode; the first end of the storage capacitor is connected to the second connection end of the control unit, the second end of the storage capacitor is connected to the power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is grounded.

5. The display panel according to claim 4, characterized in that: When the pixel unit includes a liquid crystal capacitor, N rows of scan lines are turned on row by row.

6. The display panel according to claim 4, characterized in that: When the pixel unit includes a light emitting diode, the 4n-3rd scan line, the 4n-2nd scan line, the 4n-1st scan line and the 4nth scan line are turned on row by row in the order.

7. The display panel according to claim 4, characterized in that: The 2n-1th scan line and the 2nth scan line are turned on simultaneously, and the 2n-1th scan line and the 2n+1th scan line are turned on line by line.

8. The display panel according to claim 4, characterized in that: The 4n-3rd scan line and the 4n-1th scan line are turned on simultaneously, the 4n-2nd scan line and the 4nth scan line are turned on simultaneously, and the 4n-3rd scan line and the 4n-2nd scan line are turned on line by line.

9. The display panel according to claim 4, characterized in that: The 4n-3rd scan line, the 4n-2nd scan line, the 4n-1th scan line and the 4nth scan line are turned on simultaneously, and the 4n-3rd scan line and the 4n+1th scan line are turned on line by line.

10. A display device, characterized in that: The display device comprises: A gate driving circuit, used for outputting a scanning signal; A source driving circuit, used for outputting a data signal; The display panel according to any one of claims 1 to 9, wherein the scan lines of the display panel are connected to the gate drive circuit, and the data lines of the display panel are connected to the source drive circuit.

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