Memory device, memory system, and method of operating memory device

Abstract

A memory device, a memory system, and a method of operating the memory device are disclosed. The memory device includes: a memory cell array including a plurality of memory cells respectively connected to a plurality of bit lines; a first multiplexer including a plurality of transistors connected to the plurality of bit lines; a reference circuit generating a reference current; the decoding circuit transmits the reference current to the first multiplexer; and a control logic circuit connected to the reference circuit and the decoding circuit. The control logic circuit controls the decoding circuit to apply a reference current to a transistor connected to each of at least two bit lines among the plurality of bit lines such that the first current flows through the at least two bit lines.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0151744 filed on November 6, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to a memory device and a method of operating the memory device, and in particular, to a method of programming a memory array in the memory device using a plurality of bit lines and a memory device for performing the method. Background Art

[0003] In the event that a defect occurs inside a semiconductor memory device, the semiconductor memory device may fail. Therefore, a test may be performed to detect whether a defect has occurred in the semiconductor memory device and to identify the cause of the defect.

[0004] However, the NOR flash memory has a structure that allows data bits corresponding to a single word to be stored in a single programming operation.

[0005] This results in an increase in the time required to program or store data in memory cells to test the semiconductor device. In addition, as the individual test time for the semiconductor memory device increases, the overall productivity of the semiconductor memory device may decrease. Summary of the invention

[0006] One or more disclosed aspects provide a memory device for simultaneously storing data in memory cells connected to different bit lines.

[0007] According to one aspect of the disclosure, a memory device is provided, comprising: a memory cell array, comprising a plurality of memory cells respectively connected to a plurality of bit lines; a first multiplexer, comprising a plurality of transistors connected to the plurality of bit lines; a reference circuit, configured to generate a reference current; a decoding circuit, configured to transmit the reference current to the first multiplexer; and a control logic circuit, configured to: control the decoding circuit to apply the reference current to at least two transistors among the plurality of transistors in the first multiplexer, the at least two transistors being respectively connected to at least two bit lines among the plurality of bit lines.

[0008] According to another aspect of the disclosure, a memory system is provided, the memory system comprising: a memory device; and a memory controller configured to control the memory device, wherein the memory device comprises: a memory cell array comprising a plurality of memory cells respectively connected to a plurality of bit lines; a plurality of multiplexers, each multiplexer comprising a plurality of transistors, the plurality of transistors being connected to each of a specific number of bit lines among the plurality of bit lines; a reference circuit configured to generate a reference current; a decoding circuit configured to transmit the reference current to the plurality of multiplexers; and a control logic circuit configured to apply the reference current to at least two transistors in a first multiplexer among the plurality of multiplexers based on a control signal transmitted from the memory controller.

[0009] According to another aspect of the disclosure, a method for operating a memory device is provided, the method comprising: receiving a first input related to the operation of the memory device; generating a reference current; transmitting the reference current to a decoding circuit based on the first input; and controlling the decoding circuit to apply the reference current to at least two transistors among a plurality of transistors in a first multiplexer, the at least two transistors being respectively connected to at least two bit lines among a plurality of bit lines of a memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram of a memory device according to example embodiments.

[0012] Figure 2 is a block diagram of a memory device according to example embodiments.

[0013] Figure 3 is a circuit diagram illustrating a configuration of a first multiplexer according to example embodiments.

[0014] Figure 4 is a circuit diagram illustrating a configuration of a decoding circuit according to an example embodiment.

[0015] Figure 5 is a block diagram of a memory device according to example embodiments.

[0016] Figure 6 is a flowchart illustrating a method of controlling a memory device according to example embodiments.

[0017] Figure 7 is a flow chart illustrating an operation of a control logic circuit controlling a decoding circuit to apply a reference current to a multiplexer according to an example embodiment.

[0018] Figure 8is a block diagram of a computing system including a memory device according to an example embodiment.

[0019] Fig. 9 is a block diagram of a memory system including a memory device according to example embodiments. DETAILED DESCRIPTION

[0020] The embodiments herein and the various features and advantageous details of the embodiments are explained more fully with reference to the non-limiting embodiments shown in the drawings and described in detail in the following description. Descriptions of known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments herein. The examples used herein are intended only to facilitate understanding of the manner in which the embodiments herein may be practiced, and further enable those skilled in the art to practice the embodiments herein. Therefore, the examples should not be construed as limiting the scope of the embodiments herein.

[0021] Figure 1 is a block diagram of a memory device according to example embodiments.

[0022] Reference Figure 1 According to example embodiments, the memory device 100 may include a memory cell array 110, a row decoder 120, a control logic circuit 150, a reference circuit 121, a decoding circuit 122, and a plurality of multiplexers MUX1, MUX2 to MUXn (where n is a positive integer). However, the disclosure is not limited thereto, and thus, according to another embodiment, the memory device 100 may include Figure 1 In some embodiments, Figure 1 One or more of the components shown in FIG. 1 may be omitted or combined with other components of the memory device 100 .

[0023] According to example embodiments, the memory device 100 may include a memory cell array 110 including a plurality of memory cells (MCs).

[0024] For example, the memory cell array 110 may include a plurality of memory cells arranged in a matrix of rows and columns. The plurality of memory cells may be connected to a plurality of word lines WL1 to WLn and a plurality of bit lines BL, respectively. Figure 1 It is shown that the number of multiplexers MUX is equal to the number of word lines WL (e.g., WLn and MUXn), but the disclosure is not limited thereto. Thus, according to another embodiment, the number of word lines WL may be the number m of the plurality of word lines WL1 to WLm, where m is a positive integer different from n. According to another embodiment, the number of multiplexers may be the number p of the plurality of multiplexers MUX1, MUX2 to MUXp, where p is a positive integer different from n.

[0025] According to example embodiments, the memory cell array 110 may include a plurality of volatile memory cells or a plurality of nonvolatile memory cells.

[0026] For example, the volatile memory may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), thyristor RAM (TRAM), zero capacitor RAM (Z-RAM), or two transistor RAM (TTRAM).

[0027] In addition, the non-volatile memory may include, but is not limited to, electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate memory (NFGM), holographic memory, molecular electronic memory device, or insulator resistance change memory.

[0028] According to example embodiments, the memory cell array 110 may be referred to as an embedded flash memory (eFlash memory). However, the disclosure is not limited thereto, and thus, in some example cases, the memory device 100 may be referred to as an eFlash memory.

[0029] The memory cell array 110 may include a plurality of cell strings. For example, the memory cell array 110 may include a plurality of cell strings connected to each of a plurality of bit lines BL.

[0030] In one example embodiment, a plurality of memory cells may be arranged in a two-dimensional plane. For example, a plurality of memory cells may be implemented in a two-dimensional plane. However, the disclosure is not limited thereto, and thus, according to another example embodiment, a plurality of memory cells may be arranged (or implemented) in a three-dimensional manner. For example, a plurality of memory cells may be arranged in layers in a vertical direction.

[0031] Each of the plurality of memory cells may include a plurality of nonvolatile memory cells.

[0032] For example, the memory cell array 110 may include a plurality of nonvolatile memory cells connected in parallel. Therefore, the memory cell array 110 according to example embodiments may be referred to as a NOR flash memory.

[0033] In an example embodiment, the memory device 100 may include a plurality of multiplexers MUX1 to MUXn (where n is a positive integer) connected to the plurality of bit lines BL, respectively.

[0034] For example, the memory device 100 may include a plurality of multiplexers MUX1 to MUXn, and the plurality of multiplexers MUX1 to MUXn are respectively connected to 16 bit lines.

[0035] Each of the plurality of multiplexers MUX1 to MUXn may output a current flowing through at least a portion of a plurality of connected bit lines.

[0036] For example, each of the plurality of multiplexers MUX1 to MUXn may output a current received through at least a portion of the plurality of connected bit lines based on a signal transmitted from the decoding circuit 122 .

[0037] According to example embodiments, each of the multiplexers MUX1 to MUXn may include a plurality of transistors connected to a plurality of bit lines.

[0038] For example, the first multiplexer MUX1 may include 16 transistors, and the 16 transistors are respectively connected to the first to sixteenth bit lines. However, the disclosure is not limited thereto, and as such, the number of transistors and the number of bit lines may be different from 16. The first multiplexer MUX1 may output a current received through at least a portion of the first to sixteenth bit lines.

[0039] In an example embodiment, the memory device 100 may include a reference circuit 121 configured to generate a reference current IREF.

[0040] For example, the reference circuit 121 may generate a reference current IREF having a value. The value may be a predetermined value. For example, the reference circuit 121 may generate a reference current IREF having a value equal to a natural number multiple of a first current required to store data in a memory cell connected to a single bit line.

[0041] For example, the reference circuit 121 may have, for example, a current mirror structure or a current mirror circuit.

[0042] According to example embodiments, the memory device 100 may include a row decoder 120 configured to select at least a portion of a plurality of word lines WL1 to WLn.

[0043] For example, the row decoder 120 may select at least a portion of the plurality of word lines WL1 to WLn by decoding the row address XADD and activating corresponding word lines among the word lines WL1 to WLn. In one example case where the word lines are activated, a high power supply voltage higher than the power supply voltage VDD may be applied to the gate of the access transistor of the memory cell. For example, the word lines may be activated in a word line enable operation.

[0044] The memory device 100 may include a decoding circuit 122 configured to select at least a portion of the plurality of bit lines BL. For example, the decoding circuit 122 may select at least a portion of the plurality of bit lines BL by transmitting a reference current IREF to at least a portion of the multiplexers MUX1 to MUXn. For example, the reference current IREF may be generated by the reference circuit 121.

[0045] In an example embodiment, the decoding circuit 122 may decode the column address YADD to activate at least a portion of the plurality of bit lines BL.

[0046] For example, the decoding circuit 122 may decode the column address YADD to generate a column selection signal for selecting at least a portion of the bit lines BL. For example, the column selection signal may be implemented in the form of a digital code, but example embodiments are not limited thereto.

[0047] Furthermore, the decoding circuit 122 may transmit the reference current IREF generated by the reference circuit 121 to at least a portion of the plurality of multiplexers MUX1 to MUXn.

[0048] For example, the decoding circuit 122 may transmit the reference current IREF to at least a portion of the plurality of bit lines connected to the plurality of multiplexers MUX1 to MUXn based on a column selection signal generated by decoding the column address YADD.

[0049] In another embodiment, the decoding circuit 122 may transmit the reference current IREF to at least a portion of the plurality of transistors “respectively connected to a plurality of bit lines” in each of the plurality of multiplexers MUX1 to MUXn based on the column selection signal generated by decoding the column address YADD. That is, the decoding circuit 122 may transmit the reference current IREF to at least a portion of the plurality of transistors in each of the plurality of multiplexers MUX1 to MUXn based on the column selection signal generated by decoding the column address YADD. However, the disclosure is not limited thereto, and in this manner, the decoding circuit 122 may transmit the reference current IREF to at least a portion of the plurality of transistors in one or more of the plurality of multiplexers MUX1 to MUXn.

[0050] Furthermore, the memory device 100 may include a control logic circuit 150 connected to the row decoder 120 , the decoding circuit 122 , and the reference circuit 121 .

[0051] The control logic circuit 150 according to an example embodiment may receive a command, an address, or write data from a processor or a memory controller. The control logic circuit 150 may generate various control signals (e.g., XADD and YADD) corresponding to an access operation (such as a program operation or a read operation) to the memory cell array 110 based on the command and the address.

[0052] The control logic circuit 150 may execute, for example, software, a program, or an instruction set to control one or more other components (e.g., the decoding circuit 122 and / or the reference circuit 121) of the memory device 100, and perform various data processing or operations. The control logic circuit 150 may include a central processing unit or a microprocessor, and may control the overall operation of the memory device 100. According to an embodiment, the following operations performed by the memory device 100 may be understood to be performed under the control of the control logic circuit 150. However, the disclosure is not limited thereto, and as such, one or more operations performed by the memory device 100 may be based on another manner.

[0053] In an example embodiment, the control logic circuit 150 may include an algorithm for controlling at least a portion of the reference circuit 121 and the decoding circuit 122. For example, the algorithm may be a software code programmed inside the control logic circuit 150. For example, the algorithm may be a hardware code hard-coded inside the control logic circuit 150, but example embodiments are not limited thereto.

[0054] In an example embodiment, the control logic circuit 150 may transmit the reference current IREF generated by the reference circuit 121 to the decoding circuit 122 based on an algorithm. In addition, the control logic circuit 150 may apply the reference current IREF to at least a portion of the multiplexers MUX1 to MUXn through the decoding circuit 122 based on an algorithm.

[0055] In an example embodiment, the control logic circuit 150 may apply the reference current IREF to at least two transistors among the plurality of transistors included in each of the plurality of multiplexers MUX1 to MUXn through the decoding circuit 122 .

[0056] The operation of the control logic circuit 150 applying the reference current IREF to the transistor can be understood as the operation of the control logic circuit 150 applying a voltage exceeding the threshold voltage of each transistor to the gate electrode of each of the at least two transistors. For example, the control logic circuit 150 applies a voltage to the gate electrode of each of the at least two transistors based on the reference current IREF.

[0057] For example, the control logic circuit 150 may apply the reference current IREF to at least two transistors included in a specific multiplexer so that a first current flows through at least two bit lines among a plurality of bit lines connected to the multiplexer. The first current may be a predetermined current.

[0058] In one example embodiment, the control logic circuit 150 may apply the reference current IREF to the alternately arranged transistors among the transistors in each multiplexer. According to an embodiment, the pattern in which the transistors are alternately arranged may represent an arrangement of transistors in the multiplexer with every other transistor. However, the disclosure is not limited thereto, and thus, according to another embodiment, the control logic circuit 150 may apply the reference current IREF to the transistors in the multiplexer based on different patterns. For example, the control logic circuit 150 may apply the reference current IREF to every three transistors in the multiplexer.

[0059] For example, the control logic circuit 150 may apply the reference current IREF to the transistor "connected to the first bit line, the third bit line, the fifth bit line, the seventh bit line, the ninth bit line, the eleventh bit line, the thirteenth bit line and the fifteenth bit line" among the first bit line to the sixteenth bit line connected to the first multiplexer MUX1, so that the first current flows to the first bit line, the third bit line, the fifth bit line, the seventh bit line, the ninth bit line, the eleventh bit line, the thirteenth bit line and the fifteenth bit line.

[0060] In this case, since the control logic circuit 150 applies the reference current IREF to at least two transistors included in the first multiplexer MUX1 , data may be programmed (or stored) in a memory cell connected to a bit line to which the reference current IREF is applied.

[0061] Referring to the above configuration, according to example embodiments, the control logic circuit 150 may apply the reference current IREF to at least two transistors included in the multiplexer. In this case, the first current may flow through the bit line connected to the transistor to which the reference current IREF is applied.

[0062] Therefore, the control logic circuit 150 may control the multiplexer so that current having the same value flows through a plurality of bit lines regardless of a resistance (eg, line resistance) value of each bit line.

[0063] In addition, the control logic circuit 150 may store data in memory cells connected to different bit lines at the same time. In an example embodiment, the control logic circuit 150 may store data in memory cells connected to at least one word line selected by the row decoder 120 and at least two bit lines through which the first current flows. In an example embodiment, when the reference current IREF is applied, the control logic circuit 150 may store data in memory cells connected to at least one word line selected by the row decoder 120 and a bit line through which the first current flows, the bit line through which the first current flows being connected to the at least two transistors in the first multiplexer.

[0064] As a result, the above configuration may allow the memory device 100 to reduce the time required to store data in the memory cell array 110 .

[0065] For example, the memory device 100 may reduce the time required to store data in the memory cell array 110 in order to test the memory device 100 .

[0066] Figure 2 is a block diagram of a memory device according to an example embodiment, and Figure 3 is a circuit diagram illustrating a configuration of a first multiplexer according to example embodiments.

[0067] Reference Figure 2 and Figure 3 According to example embodiments, a memory device 100A may include a memory cell array 110 , a control logic circuit 150 , a reference circuit 121 , a decoding circuit 122 , and a first multiplexer MUX1 .

[0068] The memory device 100A may further include an output transistor TRO connected to the first multiplexer MUX1.

[0069] Figure 2 The memory device 100A shown in FIG. 1 may be understood as Figure 1 1. Therefore, the same or substantially the same elements have been denoted by the same reference numerals, and redundant descriptions will be omitted. However, the disclosure is not limited thereto, and as such, other elements or components may be included in the memory device 100A.

[0070] In an example embodiment, the memory device 100A may include a first multiplexer MUX1 connected to a plurality of bit lines BL1 to BL16. The first multiplexer MUX1 may include a plurality of transistors TR1 to TR16 connected to the plurality of bit lines BL1 to BL16.

[0071] In an example embodiment, the control logic circuit 150 may transmit the reference current IREF to the decoding circuit 122. For example, the control logic circuit 150 may control the reference circuit 121 to output the reference current IREF to the decoding circuit 122.

[0072] For example, the control logic circuit 150 may transmit the reference current IREF to the decoding circuit 122 based on a first input related to the operation mode of the memory device 100A. For example, the control logic circuit 150 may transmit the reference current IREF generated by the reference circuit 121 to the decoding circuit 122 in response to a first input for the memory device 100A to operate in the first mode.

[0073] The first mode may be understood as an operation of inputting predetermined data to at least a portion of a plurality of memory cells included in the memory cell array 110 and reading data from the memory cells to determine whether the memory device 100 operates in a normal manner.

[0074] For example, in a state where the reference current IREF generated by the reference circuit 121 is applied to the output transistor TRO, the control logic circuit 150 may control the reference circuit 121 to transmit the reference current IREF generated by the reference circuit 121 to the decoding circuit 122 in response to the first input.

[0075] For example, the control logic circuit 150 may control an electrical path between the reference circuit 121 and the decoding circuit 122 in response to the first input to transfer the reference current IREF from the reference circuit 121 to the decoding circuit 122 .

[0076] In addition, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to the first multiplexer MUX1 .

[0077] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the plurality of transistors TR1 to TR16 included in the first multiplexer MUX1 .

[0078] The control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the transistors TR1 to TR16 so that the first current flows to at least two bit lines among the plurality of bit lines BL1 to BL16 .

[0079] In an example embodiment, the decoding circuit 122 may transmit the reference current IREF generated by the reference circuit 121 to the first multiplexer MUX1 .

[0080] The decoding circuit 122 may decode the column address YADD transmitted from the control logic circuit 150 to generate a column selection signal.

[0081] In addition, the decoding circuit 122 may apply the reference current IREF to at least two transistors selected in the first multiplexer MUX1 according to the column selection signal.

[0082] For example, the decoding circuit 122 may apply the reference current IREF to the first to eighth transistors TR1 to TR8 selected in the first multiplexer MUX1 according to the column selection signal generated based on the column address YADD.

[0083] For example, the decoding circuit 122 may apply the reference current IREF to the first transistor TR1, the third transistor TR3, the fifth transistor TR5, the seventh transistor TR7, the ninth transistor TR9, the eleventh transistor TR11, the thirteenth transistor TR13 and the fifteenth transistor TR15 alternately arranged in the first multiplexer MUX1 according to the column selection signal.

[0084] Reference Figure 2 and Figure 3 , the control logic circuit 150 may apply the reference current IREF to the alternately arranged transistors among the transistors TR1 to TR16 included in the first multiplexer MUX1 through the decoding circuit 122 .

[0085] In an example embodiment, the operation of the control logic circuit 150 or the decoding circuit 122 applying the reference current IREF to the transistors may be understood as the operation of the control logic circuit 150 applying a voltage exceeding the threshold voltage of each transistor to the gate electrode of each transistor using the reference current IREF.

[0086] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to the first transistor TR1 , the third transistor TR3 , the fifth transistor TR5 , the seventh transistor TR7 , the ninth transistor TR9 , the eleventh transistor TR11 , the thirteenth transistor TR13 , and the fifteenth transistor TR15 .

[0087] Therefore, the first current I1 may flow through the first, third, fifth, seventh, ninth, BL9, eleventh, BL11, thirteenth, and fifteenth bit lines BL15 connected to transistors to which the reference current IREF is applied.

[0088] In this case, data may be programmed or stored in a memory cell connected to a bit line through which the first current I1 flows.

[0089] In an example case where data is stored in a memory cell connected to a second bit line BL2, a fourth bit line BL4, a sixth bit line BL6, an eighth bit line BL8, a tenth bit line BL10, a twelfth bit line BL12, a fourteenth bit line BL14 and a sixteenth bit line BL16, the control logic circuit 150 may apply a reference current IREF to the second transistor TR2, the fourth transistor TR4, the sixth transistor TR6, the eighth transistor TR8, the tenth transistor TR10, the twelfth transistor TR12, the fourteenth transistor TR14 and the sixteenth transistor TR16.

[0090] Therefore, the first current I1 may flow through the second bit line BL2, the fourth bit line BL4, the sixth bit line BL6, the eighth bit line BL8, the tenth bit line BL10, the twelfth bit line BL12, the fourteenth bit line BL14 and the sixteenth bit line BL16 connected to the transistor to which the reference current IREF is applied.

[0091] In an example embodiment, the control logic circuit 150 may apply the reference current IREF to the plurality of transistors TR1 to TR16 included in the first multiplexer MUX1 through the decoding circuit 122 .

[0092] Therefore, the first current I1 may flow through the plurality of bit lines BL1 to BL16 connected to the transistors to which the reference current IREF is applied.

[0093] As a result, the control logic circuit 150 may simultaneously program data in memory cells connected to each of the plurality of bit lines BL1 to BL16 .

[0094] According to example embodiments, the first multiplexer MUX1 may output a current equal to a product of the first current I1 and the number of transistors to which the reference current IREF is applied based on the reference current IREF being applied to the first multiplexer MUX1 .

[0095] For example, refer to Figure 3 In response to the reference current IREF being applied to eight transistors TR1, TR3, TR5, TR7, TR9, TR11, TR13 and TR15 among the plurality of transistors TR1 to TR16, the first multiplexer MUX1 may output a current equal to the product of the first current I1 and “8” (8×I1).

[0096] In addition, the current output from the first multiplexer MUX1 may be output to the outside of the memory device 100A through the output transistor TRO.

[0097] For example, the control logic circuit 150 may apply a voltage greater than or equal to a threshold voltage of the output transistor TRO, such as the power supply voltage VDD, to the gate electrode of the output transistor TRO.

[0098] Referring to the above configuration, the control logic circuit 150 according to example embodiments may apply the reference current IREF to a plurality of transistors included in the first multiplexer MUX1 so that currents having the same value (eg, the first current I1 ) flow through a plurality of bit lines.

[0099] The plurality of bit lines BL1 to BL16 may have internal resistances (or inherent resistances) R1 , R2 to R15 , R16 , respectively.

[0100] Therefore, the control logic circuit 150 according to example embodiments may control the reference circuit 121 and / or the decoding circuit 122 so that a designated current flows through a plurality of bit lines regardless of the corresponding resistances R1 , R2 to R15 , R16 of the bit lines.

[0101] As a result, the memory device 100A according to example embodiments may significantly reduce an influence caused by a resistance value of each bit line in a case where data is programmed in a memory cell through a plurality of bit lines.

[0102] In addition, the control logic circuit 150 may apply the reference current IREF to the first multiplexer MUX1 to simultaneously program data in memory cells connected to different bit lines.

[0103] As a result, the memory device 100A according to example embodiments may reduce the time required to store data in the memory cell array 110 .

[0104] For example, the memory device 100A according to example embodiments may reduce the time required to store data in the memory cell array 110 in order to test the memory device 100A.

[0105] Figure 4 is a circuit diagram illustrating a configuration of a decoding circuit according to an example embodiment.

[0106] Reference Figure 4 , the decoding circuit 122 according to example embodiments may include a driver circuit 411 and a transmission circuit 412 .

[0107] Figure 4 The decoding circuit 122 shown in FIG. 1 can be understood as Figure 1 An example of the decoding circuit 122 is shown in FIG.

[0108] According to example embodiments, the decoding circuit 122 may include a driver circuit 411 and a transmission circuit 412. The driver circuit 411 may include a digital logic 420. However, the disclosure is not limited thereto, and as such, the decoding circuit 122 may include other elements or components.

[0109] The driver circuit 411 may decode the column address YADD transmitted from the control logic circuit 150. For example, the driver circuit 411 may decode the column address YADD using the digital logic 420. According to an embodiment, the driver circuit 411 may generate a column selection signal Ysel based on a result of decoding the column address YADD.

[0110] The column selection signal Ysel may include information on at least two transistors among a plurality of transistors included in the first multiplexer MUX1 .

[0111] For example, the column selection signal Ysel may be implemented in the form of a digital code.

[0112] Therefore, the column selection signal Ysel may be referred to as a first digital code for controlling the logic circuit 150 to apply the reference current IREF to at least two transistors included in the first multiplexer MUX1 .

[0113] According to example embodiments, the driver circuit 411 may include a plurality of driver transistors DT1 , DT2 , and DT3 .

[0114] For example, the driver circuit 411 may include a first driver transistor DT1 connected to a power supply voltage VDD, a second driver transistor DT2 connected to ground, and a third driver transistor DT3 connected between the first driver transistor DT1 and the second driver transistor DT2.

[0115] According to an embodiment, the digital logic 420 , the first to third driver transistors DT1 to DT3 may be implemented as standard cells, but the disclosure is not limited thereto.

[0116] According to example embodiments, the control logic circuit 150 may output the column selection signal Ysel generated from the digital logic 420 to the output terminal OT.

[0117] For example, the control logic circuit 150 may turn off the first driver transistor DT1 and the second driver transistor DT2 based on a first input for the memory device 100 to operate in the first mode.

[0118] Furthermore, the control logic circuit 150 may turn on the third driver transistor DT3 based on the first input for the memory device 100 to operate in the first mode.

[0119] The first mode may be understood as an operation of inputting predetermined data to a plurality of memory cells included in the memory cell array 110 and reading data from the memory cells to determine whether the memory device 100 operates normally.

[0120] Thus, for example, the first mode may be referred to as a test mode.

[0121] For example, the control logic circuit 150 may control the decoding circuit 122 to output the column selection signal Ysel generated by the digital logic 420 to the output terminal OT through the third driver transistor DT3 .

[0122] According to example embodiments, the decoding circuit 122 may include a transmission circuit 412 configured to transmit the reference current IREF from the reference circuit 121 to the first multiplexer MUX1 .

[0123] In an example embodiment, the control logic circuit 150 may turn on the transmission circuit 412 in response to the first input for the memory device 100 to operate in the first mode. This may allow the transmission circuit 412 to transmit the reference current IREF transmitted from the reference circuit 121 to the first multiplexer MUX1.

[0124] For example, the control logic circuit 150 may turn on a transistor (TT1 or TT2) included in the transmission circuit 412 in response to the first input. In this case, the reference current IREF generated by the reference circuit 121 may be transmitted to the output terminal OT of the decoding circuit 122 through the transmission circuit 412. According to an embodiment, the output terminal may include a plurality of terminals. For example, the output terminal may include one or more terminals corresponding to the electrical line from the driver circuit 411 and one or more terminals corresponding to the electrical line from the transmission circuit 412. However, the disclosure is not limited thereto, and in this way, the column selection signal Ysel and the reference current IREF may be alternately output through the output terminal OT.

[0125] In an example embodiment, the control logic circuit 150 may turn on the third driver transistor DT3 and the transmission circuit 412 in response to the first input. In addition, the control logic circuit 150 may turn off the first driver transistor DT1 and the second driver transistor DT2 in response to the first input.

[0126] The control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the plurality of transistors included in the first multiplexer MUX1 .

[0127] For example, the control logic circuit 150 may apply the reference current IREF transmitted through the transmission circuit 412 to at least two transistors of the first multiplexer MUX1 selected by the “column selection signal Ysel generated by the digital logic 420 ”.

[0128] Therefore, the control logic circuit 150 may simultaneously program (or store) data in memory cells connected to different bit lines using bit lines connected to a plurality of transistors to which the reference current IREF is applied.

[0129] Referring to the above configuration, according to example embodiments, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors included in the first multiplexer MUX1. In this case, the first current may flow through the bit line connected to the transistor to which the reference current IREF is applied.

[0130] Furthermore, the control logic circuit 150 may simultaneously store data in memory cells connected to different bit lines using the plurality of bit lines through which the first current flows.

[0131] Therefore, the above configuration may allow the memory device 100 according to example embodiments to reduce the time required to store data in the memory cell array 110 .

[0132] For example, the memory device 100 may reduce the time required to store data in the memory cell array 110 in order to test the memory device 100 .

[0133] In an example embodiment, the control logic circuit 150 may turn off the third driver transistor DT3 and the transfer circuit 412 based on the second input for the memory device 100 to operate in the second mode. In addition, the control logic circuit 150 may turn on the first and second driver transistors DT1 and DT2 based on the second input.

[0134] For example, the second mode may be referred to as an operating mode.

[0135] The control logic circuit 150 may output a second digital code for applying a voltage greater than or equal to the threshold voltage to one of the transistors TR1 to TR16 included in the first multiplexer MUX1 using the digital logic 420 .

[0136] Furthermore, the control logic circuit 150 may apply the reference current IREF generated by the reference circuit 121 to the output transistor TRO based on the second input.

[0137] The control logic circuit 150 may transmit the second digital code for turning on one of the transistors TR1 to TR16 to the first multiplexer MUX1 through the decoding circuit 122 .

[0138] This may allow the control logic circuit 150 to store data in the memory cell connected to the bit line “connected to the transistor that is turned on”.

[0139] With reference to the above configuration, the control logic circuit 150 may control the decoding circuit 122 so that the memory device 100 operates in different modes.

[0140] According to an embodiment, the control logic circuit 150 may control the decoding circuit 122 so that the memory device 100 operates in a first mode of simultaneously storing data in memory cells connected to different bit lines connected to the first multiplexer MUX1 .

[0141] According to another embodiment, the control logic circuit 150 may control the decoding circuit 122 so that the memory device 100 operates in the second mode of storing data in memory cells connected to a single bit line connected to the first multiplexer MUX1 .

[0142] Through the above configuration, the memory device 100 according to example embodiments may operate in different modes using a single decoding circuit 122. Therefore, the memory device 100 may reduce the area of ​​circuits required to operate in different modes.

[0143] Figure 5 is a block diagram of a memory device according to example embodiments.

[0144] Reference Figure 5 , a memory device 100B according to example embodiments may include a memory cell array 110, a control logic circuit 150, a reference circuit 121, a decoding circuit 122, and a plurality of multiplexers MUX1 to MUXn. However, the disclosure is not limited thereto, and as such, the memory device 100B may include other components.

[0145] Figure 5 The memory device 100B shown in FIG. 1 may be understood as Figure 1 Therefore, the same or substantially the same elements have been denoted by the same reference numerals, and redundant descriptions will be omitted.

[0146] In an example embodiment, the memory device 100B may include a plurality of multiplexers MUX1 to MUXn, each of which is connected to a plurality of bit lines.

[0147] Furthermore, each of the multiplexers MUX1 to MUXn may include a plurality of transistors, which are respectively connected to a plurality of bit lines.

[0148] In an example embodiment, the control logic circuit 150 may transmit the reference current IREF output from the reference circuit 121 to the decoding circuit 122 .

[0149] For example, the control logic circuit 150 may transmit the reference current IREF generated by the reference circuit 121 to the decoding circuit 122 in response to a first input for the memory device 100B to operate in the first mode.

[0150] For example, in a state where the reference current IREF generated by the reference circuit 121 is applied to the output transistor TRO, the control logic circuit 150 may control the reference circuit 121 to transmit the reference current IREF from the reference circuit 121 to the decoding circuit 122 in response to the first input.

[0151] In addition, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least a portion of the plurality of multiplexers MUX1 to MUXn.

[0152] The operation of the control logic circuit 150 (or the decoding circuit 122 ) applying the reference current IREF to the transistors may be understood as the operation of the control logic circuit 150 applying a voltage exceeding the threshold voltage of each transistor to the gate electrode of each transistor.

[0153] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the plurality of transistors included in each of the plurality of multiplexers MUX1 to MUXn.

[0154] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the plurality of transistors TR1 to TR16 included in the first multiplexer MUX1 .

[0155] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors among the plurality of transistors TR1 to TR16 included in the first multiplexer MUX1 so that the first current flows through at least two bit lines among the plurality of bit lines BL1 to BL16 .

[0156] In an example embodiment, the decoding circuit 122 may transmit the reference current IREF generated by the reference circuit 121 to each of the plurality of multiplexers MUX1 to MUXn.

[0157] The decoding circuit 122 may decode the column address YADD transmitted from the control logic circuit 150 to generate a column selection signal.

[0158] In addition, the decoding circuit 122 may apply the reference current IREF to at least two transistors selected from each of the plurality of multiplexers MUX1 to MUXn according to the column selection signal.

[0159] For example, the control logic circuit 150 may apply the reference current IREF to alternately arranged transistors among a plurality of transistors included in each of the plurality of multiplexers MUX1 to MUXn through the decoding circuit 122 .

[0160] For example, the decoding circuit 122 may apply the reference current IREF to the first to eighth transistors TR1 to TR8 selected from the first multiplexer MUX1 according to the column selection signal generated based on the column address YADD.

[0161] Therefore, the first current I1 may flow through the bit line connected to the transistor to which the reference current IREF is applied.

[0162] Furthermore, data may be programmed or stored in a memory cell connected to a bit line through which the first current I1 flows.

[0163] As a result, the control logic circuit 150 may simultaneously program or store data in memory cells connected to different bit lines using a plurality of bit lines connected to each of the plurality of multiplexers MUX1 to MUXn.

[0164] Furthermore, each of the plurality of multiplexers MUX1 to MUXn may output a current equal to a product of the first current I1 and the number of transistors to which the reference current IREF is applied among the plurality of transistors in response to the reference current IREF being applied.

[0165] For example, refer to Figure 3 and Figure 5 In response to the reference current IREF being applied to eight transistors TR1, TR3, TR5, TR7, TR9, TR11, TR13 and TR15 of the plurality of transistors TR1 to TR16, the first multiplexer MUX1 may output a current equal to the product of the first current I1 and “8” (8×I1).

[0166] Referring to the above configuration, the control logic circuit 150 according to example embodiments may apply the reference current IREF to a plurality of transistors included in each of a plurality of multiplexers MUX1 to MUXn so that currents having the same value (eg, the first current I1 ) flow through a plurality of bit lines.

[0167] As a result, the control logic circuit 150 may apply the reference current IREF to each of the plurality of multiplexers MUX1 to MUXn to simultaneously program or store data in memory cells connected to different bit lines.

[0168] This may allow the memory device 100B according to example embodiments to reduce the time required to store data in the memory cell array 110 .

[0169] For example, the memory device 100B can reduce the time required to store data in the memory cell array 110 in order to test the memory device 100B.

[0170] Figure 6 is a flowchart illustrating a method of controlling a memory device according to example embodiments.

[0171] Reference Figure 6 According to example embodiments, the memory device 100 or the control logic circuit 150 may perform an operation for applying the reference current IREF to a plurality of transistors so that the first current I1 flows through a plurality of bit lines.

[0172] Therefore, the control logic circuit 150 can use multiple bit lines to simultaneously program or store data in memory cells connected to different bit lines.

[0173] In operation S10, the method may include receiving a first input related to the operation of the memory device. For example, the control logic circuit 150 according to example embodiments may receive a first input for the memory device 100 to operate in a first mode.

[0174] For example, the first mode may be understood as an operation of inputting predetermined data to a plurality of memory cells included in the memory cell array 110 and reading data from the memory cells to determine whether the memory device 100 operates normally.

[0175] For example, the control logic circuit 150 may receive a first input for the memory device 100 to operate in the first mode through a memory controller or an interface.

[0176] In operation S20 , the method may include transmitting a reference current to the decoding circuit. For example, the control logic circuit 150 may transmit the reference current IREF generated by the reference circuit 121 to the decoding circuit 122 .

[0177] For example, the control logic circuit 150 may control the reference circuit 121 so that the reference current IREF generated by the reference circuit 121 is transmitted or sent to the decoding circuit 122 .

[0178] The control logic circuit 150 may control at least one electrical path connected to the reference circuit 121 so that the reference current IREF generated by the reference circuit 121 is transmitted or sent to the decoding circuit 122 .

[0179] For example, the control logic circuit 150 may turn on at least one switch connected between the reference circuit 121 and the decoding circuit 122 in response to the first input.

[0180] In operation S30, the method may include applying a reference current to at least two transistors connected to at least two bit lines. For example, the control logic circuit 150 may apply a reference current IREF to at least two transistors connected to at least two bit lines.

[0181] For example, the control logic circuit 150 may apply the reference current IREF to transistors connected to at least two bit lines so that the first current I1 flows through the at least two bit lines connected to the first multiplexer MUX1 .

[0182] The control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors “connected to at least two or more bit lines connected to the first multiplexer MUX1 ” so that the first current I1 flows through the at least two bit lines.

[0183] For example, the control logic circuit 150 may control the decoding circuit 122 to apply the reference current IREF to at least two transistors alternately arranged among the plurality of transistors included in the first multiplexer MUX1 .

[0184] Since the reference current IREF is applied to at least two transistors, the first current I1 may flow through a bit line connected to each of the transistors to which the reference current IREF is applied.

[0185] Furthermore, when the first current I1 flows through the bit line, data may be stored in a memory cell “connected to the bit line through which the first current I1 flows” in the memory cell array 110 .

[0186] Referring to the above configuration, the control logic circuit 150 according to example embodiments may apply the reference current IREF to at least two transistors included in the multiplexer. In this case, the first current I1 may flow through a bit line connected to the transistor to which the reference current IREF is applied.

[0187] This may allow the control logic circuit 150 to simultaneously store data in memory cells connected to different bit lines using the plurality of bit lines through which the first current I1 flows, respectively.

[0188] Therefore, through the above configuration, the memory device 100 according to example embodiments may reduce the time required to store data in the memory cell array 110 .

[0189] For example, the memory device 100 may reduce the time required to store data in the memory cell array 110 in order to test the memory device 100 .

[0190] Figure 7 is a flow chart illustrating an operation of a control logic circuit controlling a decoding circuit to apply a reference current to a multiplexer according to an example embodiment.

[0191] Reference Figure 6 and Figure 7 , the memory device 100 (or the control logic circuit 150 ) according to example embodiments may apply the reference current IREF to at least two transistors of the multiplexer based on a digital code.

[0192] In operation S31 , the method may include outputting a digital code. For example, the control logic circuit 150 may output a digital code including information related to a transistor.

[0193] For example, the control logic circuit 150 may control the driver circuit 411 of the decoding circuit 122 to output a digital code including information on at least two transistors.

[0194] For example, refer to Figure 4 and Figure 7, the control logic circuit 150 can transmit the column address YADD to the driver circuit 411 of the decoding circuit 122.

[0195] Driver circuit 411 may decode column address YADD using digital logic 420 .

[0196] In addition, the driver circuit 411 may decode the column address YADD to generate a column selection signal Ysel. The column selection signal Ysel may be generated in the form of a digital code. Therefore, the column selection signal Ysel may be referred to as a digital code.

[0197] In an example embodiment, the control logic circuit 150 may generate a first digital code for selecting at least two transistors among a plurality of transistors included in the first multiplexer MUX1 in response to a first input allowing the memory device 100 to operate in the first mode.

[0198] In one example embodiment, the control logic circuit 150 may generate a second digital code for selecting a single transistor among a plurality of transistors included in the first multiplexer MUX1 in response to a second input that allows the memory device 100 to operate in the second mode.

[0199] In operation S32 , the method may include applying a reference current IREF to at least two transistors selected based on the digital code. For example, the control logic circuit 150 according to example embodiments may apply the reference current IREF to at least two transistors selected based on the first digital code.

[0200] For example, the control logic circuit 150 may apply the reference current IREF to at least two transistors selected based on the first digital code among the plurality of transistors included in the first multiplexer MUX1 .

[0201] Referring to the above configuration, the control logic circuit 150 according to example embodiments may apply the reference current IREF to at least two transistors included in the multiplexer. In this case, the first current I1 may flow through a bit line connected to the transistor to which the reference current IREF is applied.

[0202] Therefore, the control logic circuit 150 can simultaneously store data in memory cells connected to different bit lines using the plurality of bit lines through which the first current I1 flows, respectively.

[0203] Therefore, through the above configuration, the memory device 100 can reduce the time required to store data in the memory cell array 110 .

[0204] For example, the memory device 100 may reduce the time required to store data in the memory cell array 110 in order to test the memory device 100 .

[0205] Figure 8 is a block diagram of a computing system including a memory device according to an example embodiment.

[0206] Reference Figure 8 , the computing system 80 may include a central processing unit (CPU) 810 , an input / output (I / O) device 820 , an interface 830 , a power supply 840 , and a memory system 800 .

[0207] The CPU 810, the I / O device 820, the interface 830, the power supply 840, and the memory system 800 may be coupled to each other via a bus 860. The bus 860 may be understood as a path through which data is exchanged between various components of the computing system 80. For example, pieces of data may be moved to and / or from various components of the computing system 80 via the bus 860.

[0208] In an example embodiment, the CPU 810 may include a single core or multiple cores for processing data. For example, the CPU 810 may include a single core processor or a multi-core processor (such as a dual core processor, a quad core processor, or a hexa core processor). The CPU 810 may also include various hardware devices. For example, the CPU 810 may include, but is not limited to, an intellectual property (IP) core, an internal or external cache memory.

[0209] In an example embodiment, the I / O device 820 may include one or more input devices (such as a keyboard or a touch screen) and / or one or more output devices (such as a speaker or a display device).

[0210] In an example embodiment, the interface 830 may be a communication interface. For example, the interface may be implemented by circuits and electronic components. The interface 830 may perform wireless communication or wired communication with an external device. For example, the interface 830 may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile communication, memory card communication, universal serial bus (USB) communication, etc. However, the disclosure is not limited thereto, and as such, the interface 830 may perform other types of communication.

[0211] In one example embodiment, the memory system 800 may store data processed by the CPU 810 or operate as a working memory of the CPU 810. The memory system 800 may include a memory device 801 and a memory controller 802.

[0212] The memory device 801 can be understood as Figure 1 An example of a memory device 100 is shown in FIG.

[0213] In an example embodiment, the memory device 801 may receive an input for controlling a mode of the memory device 801 through the I / O device 820 or the interface 830 .

[0214] For example, the memory device 801 may receive an input for the memory device 801 to operate in the first mode from a user through an input device such as a keyboard or a touch screen.

[0215] In another example, the memory device 801 may receive an input for the memory device 801 to operate in the first mode from an external device through the interface 830 .

[0216] For example, the memory device 801 may receive an input for the memory device 801 to operate in the second mode from a user through an input device such as a keyboard or a touch screen.

[0217] According to example embodiments, the memory device 801 may simultaneously program or store data in memory cells connected to different bit lines using a plurality of bit lines based on a first input.

[0218] For example, memory device 801 can use multiple bit lines to simultaneously program or store data in memory cells connected to different bit lines in response to a first input. This can allow memory device 801 to reduce the time required to store data in memory cells in order to test the operation of memory device 801 or memory system 800.

[0219] In an example embodiment, the power supply 840 may convert externally input power and supply the converted power to at least a portion of each component of the computing system 80 (eg, the CPU 810 or the I / O device 820 ).

[0220] The computing system 80 may also include a nonvolatile memory device. For example, the nonvolatile memory device may include, but is not limited to, various nonvolatile memory devices such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0221] In an example embodiment, computing system 80 may be referred to as any computing system such as a mobile phone, smart phone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation system, etc.

[0222] Fig. 9 is a block diagram of a memory system including a memory device according to example embodiments.

[0223] Reference Fig. 9 , the memory system 800 may include a memory device 801 and a memory controller 802 .

[0224] In an example embodiment, the memory controller 802 may be configured to control the memory device 801. For example, the memory controller 802 may be configured to control one or more operations of the memory device 801.

[0225] The memory controller 802 may access the memory device 801 based on a request from the host. The memory controller 802 may access the memory device 801 in response to a request from the host. For example, the memory controller 802 may program data in the memory device 801 or read data from the memory device 801.

[0226] For example, the memory controller 802 may provide a command CMD and / or an address ADDR to the memory device 801 and exchange data DQ with the memory device 801. The memory controller 802 may be configured to execute firmware to control the memory device 801.

[0227] In an example embodiment, the memory device 801 may be configured to store data. For example, the memory device 801 may include an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistive change memory.

[0228] The memory device 801 can be understood as Figure 1 An example of a memory device 100 is shown in FIG.

[0229] In an example embodiment, the memory device 801 may simultaneously program (or store) data in memory cells connected to different bit lines using a plurality of bit lines under the control of the memory controller 802 .

[0230] For example, the control logic circuit 150 of the memory device 801 may simultaneously program (or store) data in memory cells connected to a plurality of bit lines based on control signals (eg, commands CMD and / or addresses ADDR) transmitted from the memory controller 802 .

[0231] This may allow the memory device 801 to reduce the time required to store data in memory cells in order to test the operation of the memory device 801 (or memory system 800 ).

[0232] As described above, the control logic circuit 150 according to example embodiments may apply the reference current IREF to at least two transistors included in the multiplexer. In this case, the first current may flow through the bit line connected to the transistor to which the reference current IREF is applied.

[0233] This may allow the control logic circuit 150 to use multiple bit lines to simultaneously store data in memory cells connected to different bit lines.

[0234] Therefore, the memory device 100 can reduce the time required to store data in the memory cell array 110. For example, the memory device 100 can reduce the time required to store data in the memory cell array 110 in order to test the memory device 100. That is, the time required to store data in the memory cell array 110 can be reduced.

[0235] Furthermore, the control logic circuit 150 may control the multiplexer so that current having the same value flows through a plurality of bit lines regardless of resistance (eg, line resistance) values ​​of the bit lines.

[0236] This may allow the memory device 100 to significantly reduce an influence caused by a resistance value of each bit line in a case where data is programmed or stored in a memory cell through a plurality of bit lines.

[0237] As described above, a memory device according to example embodiments may simultaneously store data in memory cells connected to different bit lines using a reference current.

[0238] Therefore, the memory device can reduce the time required to store data in the memory cell array.

[0239] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: A memory cell array including a plurality of memory cells respectively connected to a plurality of bit lines; a first multiplexer comprising a plurality of transistors connected to the plurality of bit lines; a reference circuit configured to generate a reference current; a decoding circuit configured to transmit the reference current to the first multiplexer; as well as The control logic circuit is configured as follows: The decoding circuit is controlled to apply a reference current to at least two transistors among the plurality of transistors in the first multiplexer, the at least two transistors being respectively connected to at least two bit lines among the plurality of bit lines.

2. The memory device of claim 1, wherein: The decoding circuit includes: driver circuitry, including digital logic; and a transmission circuit configured to transmit the reference current to the first multiplexer, and The control logic circuit is configured to apply the reference current to the first multiplexer through the transmission circuit based on the digital code output by the digital logic.

3. The memory device of claim 2, wherein: The control logic circuit is configured to transmit a reference current to the decoding circuit based on a first input associated with a first operating mode of the memory device.

4. The memory device as claimed in claim 3, in, The driver circuit includes: a first driver transistor connected to a power supply; a second driver transistor connected to ground; and a third driver transistor connected between the first driver transistor and the second driver transistor, and Wherein, the control logic circuit is configured as: Based on the first input, the third driver transistor and the transmission circuit are turned on, the first driver transistor and the second driver transistor are turned off, and the digital logic is controlled to output a first digital code to apply a reference current to the at least two transistors in the first multiplexer.

5. The memory device of claim 4, wherein: The control logic circuit is configured to: turn off the third driver transistor and the transmission circuit based on a second input associated with a second operating mode of the memory device; The first driver transistor and the second driver transistor are turned on; and the digital logic is controlled to output a second digital code to apply a voltage greater than or equal to a threshold voltage to a single transistor among the plurality of transistors in the first multiplexer.

6. The memory device of claim 1, further comprising: a row decoder connected to the control logic circuit, the row decoder being configured to select at least one word line, The control logic circuit is configured to store data in a memory cell connected to the at least one word line and the at least two bit lines through which the first current flows.

7. The memory device of claim 6, wherein: The first multiplexer is configured to output a current equal to a product of the first current and the number of transistors to which the reference current is applied among the plurality of transistors based on the reference current being applied to the first multiplexer.

8. The memory device of claim 2, wherein: The control logic circuit is configured to: provide the column address to the decoding circuit, and The driver circuit is configured to decode the column address through digital logic and generate a digital code.

9. The memory device of claim 5, further comprising: The output transistor is connected to the first multiplexer, The control logic circuit is configured to apply a reference current to the output transistor based on the second input.

10. The memory device of claim 1, wherein: The control logic circuit is configured to apply a reference current to alternately arranged transistors among the plurality of transistors included in the first multiplexer.

11. A memory system comprising: Memory device; as well as a memory controller configured to control the memory device, Wherein, the memory device comprises: A memory cell array including a plurality of memory cells respectively connected to a plurality of bit lines; a plurality of multiplexers, each multiplexer comprising a plurality of transistors, the plurality of transistors being connected to the plurality of bit lines; a reference circuit configured to generate a reference current; a decoding circuit configured to transmit a reference current to the plurality of multiplexers; and The control logic circuit is configured to apply a reference current to at least two transistors in a first multiplexer among the plurality of multiplexers based on a control signal transmitted from the memory controller.

12. The memory system of claim 11, further comprising: a row decoder connected to the control logic circuit, the row decoder being configured to select at least one word line, The control logic circuit is configured to store data in a memory cell connected to the at least one word line and a bit line through which the first current flows when a reference current is applied, and the bit line through which the first current flows is connected to the at least two transistors in the first multiplexer.

13. The memory system of claim 12, wherein: The decoding circuit includes: driver circuitry, including digital logic; and a transmission circuit configured to transmit the reference current to the first multiplexer, and The control logic circuit is configured to apply a reference current to the at least two transistors through the transmission circuit based on a digital code output by the digital logic.

14. The memory system of claim 13, in, The driver circuit includes: a first driver transistor connected to a power supply; a second driver transistor connected to ground; and a third driver transistor connected between the first driver transistor and the second driver transistor, and Wherein, the control logic circuit is configured to: turn on the third driver transistor and the transmission circuit based on a first input related to a first operating mode of the memory device; turn off the first driver transistor and the second driver transistor; and control the digital logic to output a first digital code to apply a reference current to the at least two transistors in the first multiplexer.

15. The memory system of claim 14, wherein: The control logic circuit is configured to transmit a reference current to the decoding circuit based on the first input.

16. The memory system of claim 12, wherein: The first multiplexer is configured to output a current equal to a product of the first current and the number of transistors to which the reference current is applied among the plurality of transistors based on the reference current being applied to the first multiplexer.

17. The memory system of claim 11, wherein: The control logic circuit is configured to apply a reference current to alternately arranged transistors among the plurality of transistors in the first multiplexer.

18. A method of operating a memory device, comprising: receiving a first input related to operation of the memory device; generating a reference current; transmitting a reference current to a decoding circuit based on the first input; as well as The decoding circuit is controlled to apply a reference current to at least two transistors among a plurality of transistors in the first multiplexer, the at least two transistors being respectively connected to at least two bit lines among a plurality of bit lines of the memory cell array.

19. The method of claim 18, wherein: The steps of controlling the decoding circuit include: controlling a driver circuit of the decoding circuit to output a digital code including information related to the at least two transistors; and A reference current is applied to the at least two transistors based on a digital code.

20. The method of claim 18, wherein: The steps of controlling the decoding circuit include: A reference current is applied to alternately arranged transistors among the plurality of transistors in the first multiplexer.

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