Memory device, control logic circuit and operating method thereof

Abstract

A memory device includes a memory array configured to store data and a peripheral circuit coupled to the memory array, the peripheral circuit including control logic circuitry to control operation of the peripheral circuit. The control logic circuitry includes a master control circuit and at least one first sub-control circuit, and the master control circuit and the first sub-control circuit interact through first trigger signals and first indication signals. The master control circuit and the first sub-control circuit interact through asynchronous control logic without a global clock signal.

Description

Technical Field

[0001] This disclosure relates to memory devices, control logic circuits, and their operation. Background Technology

[0002] Memory devices such as flash memory are low-cost, high-density, non-volatile solid-state storage media that can be electrically erased and reprogrammed. The peripheral circuitry of a memory device typically includes various register circuits and corresponding control logic circuits, which interact with the main control digital circuitry via global clocks and bus protocols to operate the memory device. However, the wiring on these global clocks and buses is very long, consuming power in the clock and bus circuitry. Summary of the Invention

[0003] In one aspect, a memory device is disclosed. The memory device includes a memory array configured to store data and peripheral circuitry coupled to the memory array. The peripheral circuitry includes control logic circuitry to control the operation of the peripheral circuitry. The control logic circuitry includes a main control circuitry and at least one first sub-control circuitry, and the main control circuitry and the first sub-control circuitry interact via a first trigger signal and a first indication signal.

[0004] In some implementations, the main control circuit and the first sub-control circuit do not require a global clock signal, but interact through asynchronous control logic.

[0005] In some embodiments, the first sub-control circuit includes an asynchronous control circuit configured to receive the first trigger signal from the main control circuit and generate a local clock signal; and a state machine circuit configured to receive the local clock signal and generate the first indication signal.

[0006] In some embodiments, the asynchronous control circuit includes a first XOR gate, which includes a first input, a second input, and a first output, wherein the first input is configured to receive the first trigger signal, and the first output is configured to output the local clock signal; a trigger circuit, which includes an enable terminal coupled to the first output of the first XOR gate, a second output, and a data terminal coupled to the second output; and a first delay element disposed between the second input of the first XOR gate and the second output of the trigger circuit.

[0007] In some embodiments, the trigger circuit includes a D flip-flop. In some embodiments, the asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the trigger circuit.

[0008] In some embodiments, the state machine circuit includes at least one state, the at least one state being triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a third output configured to output a next signal when the state is switched, and an indication output.

[0009] In some embodiments, the indication output is configured to output the first indication signal when the state in the state machine circuit is switched.

[0010] In some embodiments, the memory device further includes a second XOR gate and a second delay element, the second XOR gate including a third input terminal and a fourth input terminal configured to receive the first trigger signal, and a fourth output terminal coupled to the asynchronous control circuit; the second delay element is disposed between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

[0011] In some embodiments, the fourth output of the second XOR gate is coupled to the first input of the first XOR gate. In some embodiments, the first delay element includes at least one inverter, and the second delay element includes at least one inverter.

[0012] In some embodiments, the control logic circuit further includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact via a second trigger signal and a second indication signal. In some embodiments, the first sub-control circuit and the second sub-control circuit operate independently.

[0013] In some embodiments, the main control circuit is configured to output the first trigger signal and the second trigger signal respectively, and to receive the first indication signal and the second indication signal respectively.

[0014] In another aspect, a control logic circuit for controlling the operation of peripheral circuitry of a memory device is disclosed. The control logic circuit includes a main control circuit and at least one first sub-control circuit, which interact with each other via a first trigger signal and a first indication signal. The sub-control circuit includes an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal; and a state machine circuit configured to receive the local clock signal and generate the first indication signal.

[0015] In some embodiments, the asynchronous control circuit includes a first XOR gate, which includes a first input, a second input, and a first output, wherein the first input is configured to receive the first trigger signal, and the first output is configured to output the local clock signal; a trigger circuit, which includes an enable terminal coupled to the first output of the first XOR gate, a second output, and a data terminal coupled to the second output; and a first delay element disposed between the second input of the first XOR gate and the second output of the trigger circuit.

[0016] In some embodiments, the trigger circuit includes a D flip-flop. In some embodiments, the asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the trigger circuit.

[0017] In some embodiments, the state machine circuit includes at least one state, the at least one state being triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a third output configured to output a next signal when the state is switched, and an indication output.

[0018] In some embodiments, the indication output is configured to output the first indication signal when the state in the state machine circuit is switched.

[0019] In some embodiments, the memory device further includes a second XOR gate and a second delay element, the second XOR gate including a third input terminal and a fourth input terminal configured to receive the first trigger signal, and a fourth output terminal coupled to the asynchronous control circuit; the second delay element is disposed between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

[0020] In some embodiments, the fourth output of the second XOR gate is coupled to the first input of the first XOR gate. In some embodiments, the first delay element includes at least one inverter, and the second delay element includes at least one inverter.

[0021] In some embodiments, the control logic circuit further includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact via a second trigger signal and a second indication signal. In some embodiments, the first sub-control circuit and the second sub-control circuit operate independently.

[0022] In some embodiments, the main control circuit is configured to output the first trigger signal and the second trigger signal respectively, and to receive the first indication signal and the second indication signal respectively.

[0023] In another aspect, a method for operating the peripheral circuitry of a memory device is disclosed. A trigger signal is generated by a main control circuit, the trigger signal is received by a sub-control circuit, a local clock signal is generated in the sub-control circuit, a state machine circuit in the sub-control circuit is triggered by the local clock signal, an indication signal is generated by the sub-control circuit, and the indication signal is sent to the main control circuit.

[0024] In some implementations, the trigger signal and the first delay signal are combined to generate a request signal, and the request signal is sent to the asynchronous control circuit.

[0025] In some implementations, the request signal and the second delay signal are combined to generate the local clock signal.

[0026] In some embodiments, the flip-flop circuit is triggered by the local clock signal to generate a flip-flop output signal, and the flip-flop output signal is delayed to generate the second delayed signal. In some embodiments, the flip-flop output signal is delayed by a delay element.

[0027] In some implementations, at least one state is defined in the state machine circuit, and the states in the state machine circuit are switched sequentially when the local clock signal is received.

[0028] In some implementations, a next state signal is generated when the state in the state machine circuit is switched, and the next state signal is delayed to generate a first delay signal.

[0029] In some implementations, the indication signal is generated when the state in the state machine circuit is switched, and the indication signal is sent to the main control circuit to indicate that the interaction between the main control circuit and the sub-control circuit is complete.

[0030] In another aspect, a method for operating a control logic circuit is disclosed. The control logic circuit includes a main control circuit and at least one sub-control circuit. A trigger signal from the main control circuit is received by the sub-control circuit. A local clock signal is generated in the sub-control circuit in response to receiving the trigger signal. A state machine circuit in the sub-control circuit is triggered by the local clock signal. An indication signal is generated by the sub-control circuit and the indication signal is sent to the main control circuit.

[0031] In some implementations, the trigger signal and the first delay signal are combined to generate a request signal, and the request signal is sent to the asynchronous control circuit.

[0032] In some implementations, the request signal and the second delay signal are combined to generate the local clock signal.

[0033] In some embodiments, the flip-flop circuit is triggered by the local clock signal to generate a flip-flop output signal, and the flip-flop output signal is delayed to generate the second delayed signal. In some embodiments, the flip-flop output signal is delayed by a delay element.

[0034] In some implementations, at least one state is defined in the state machine circuit, and the states in the state machine circuit are switched sequentially when the local clock signal is received.

[0035] In some implementations, a next state signal is generated when the state in the state machine circuit is switched, and the next state signal is delayed to generate a first delay signal.

[0036] In some implementations, the indication signal is generated when the state in the state machine circuit is switched, and the indication signal is sent to the main control circuit to indicate that the interaction between the main control circuit and the sub-control circuit is complete. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0038] Figure 1A A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0039] Figure 1B A schematic circuit diagram of a memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0040] Figure 2 A block diagram of an exemplary control logic circuit, including a main control circuit and several register circuits, is shown according to some aspects of this disclosure.

[0041] Figure 3 A block diagram of an exemplary click element of an asynchronous control circuit according to some aspects of this disclosure is shown.

[0042] Figure 4 A block diagram of an exemplary control logic circuit including a main control circuit and several sub-control circuits according to some aspects of this disclosure is shown.

[0043] Figure 5 A block diagram of an exemplary sub-control circuit according to some aspects of this disclosure is shown.

[0044] Figure 6 A block diagram of an exemplary asynchronous control circuit according to some aspects of this disclosure is shown.

[0045] Figure 7 Timing diagrams of exemplary control logic circuits according to some aspects of this disclosure are shown.

[0046] Figure 8 A flowchart illustrating an exemplary method for operating the peripheral circuitry of a memory device according to some aspects of this disclosure is shown.

[0047] Figure 9 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0048] Figure 10A An illustration of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0049] Figure 10B An illustration of an exemplary solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0050] Various aspects of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0051] Although specific configurations and arrangements have been discussed, it should be understood that they are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be employed in a wide variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0052] Generally, terms should be understood at least in part by their use in context. For example, at least in part, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part, depending on the context, terms such as "a," "an," or "the" may be understood to convey either singular or plural usage. Furthermore, the term "based on" may not necessarily be intended to convey an exclusive set of factors; instead, it may allow for additional factors that are not explicitly described, again at least in part depending on the context.

[0053] Figure 1A A block diagram of an exemplary memory device 100, including a memory cell array 102 and peripheral circuitry, is shown according to some aspects of this disclosure. In some embodiments, the peripheral circuitry includes a page buffer / sensor amplifier 104, a column decoder / bit line driver 106, a row decoder / word line driver 108, a voltage generator 110, control logic 112, a register 114, an interface 116, and a data bus 118. It should be understood that other peripheral circuitry, not shown in FIG1, may also be included.

[0054] Page buffer / sensor amplifier 104 can be configured to read data from memory cell array 102 and program (write) data to memory cell array 102 according to control signals from control logic 112. In one embodiment, page buffer / sensor amplifier 104 can store a page of programming data (write data) to be programmed into a page of memory cell array 102. In another example, page buffer / sensor amplifier 104 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another embodiment, page buffer / sensor amplifier 104 can also sense a low-power signal representing a data bit stored in the memory cell from the bit line during a read operation and amplify the small voltage swing to a recognizable logic level. Column decoder / bit line driver 106 can be configured to be controlled by control logic 112 according to control signals from control logic 112 and to select one or more NAND memory strings by applying a bit line voltage generated by voltage generator 110.

[0055] The row decoder / word line driver 108 can be configured to be controlled by control logic 112 according to control signals from control logic 112, and to select / deselect blocks of memory cell array 102 and to select / deselect word lines. The row decoder / word line driver 108 can be further configured to drive word lines using word line voltages generated by voltage generator 110. Voltage generator 110 can be configured to be controlled by control logic 112 according to control signals from control logic 112, and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to memory cell array 102.

[0056] Control logic 112 may be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit by generating and sending various control signals. As detailed below, control logic 112 may include a main control unit or main control circuit to communicate or interact with several sub-control units or sub-control circuits.

[0057] Interface 116 can be coupled to control logic 112 and acts as an instruction fetcher / buffer and instruction decoder, thereby decoding instructions received from the memory controller and forwarding the decoded instructions to control logic 112. Interface 116 can also buffer status information received from control logic 112 and forward it to the memory controller. Interface 116 can be coupled to column decoder / bit line driver 106 via data bus 118 and further acts as a data input / output (I / O) interface and data buffer, thereby buffering and forwarding data to and from memory cell array 102.

[0058] Figure 1B A schematic circuit diagram of a memory device 150 including peripheral circuitry according to some aspects of the present disclosure is shown. The memory device 150 may include a memory cell array 151 and peripheral circuitry 152 coupled to the memory cell array 151. A memory device 100 may be an example of the memory device 150, wherein the memory cell array 151 and at least the peripheral circuitry 152 may be included in peripheral circuitry 104.

[0059] The memory cell array 151 may be a NAND flash memory cell array, wherein the memory cells 156 are provided in the form of an array of NAND memory strings 138. In some embodiments, each NAND memory string 158 includes a plurality of memory cells 156 connected in series. Each memory cell 156 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 156. Each memory cell 156 may be a "floating gate" type memory cell including a floating gate transistor, or it may be a "charge trap" type memory cell including a charge trap transistor.

[0060] In some implementations, each memory cell 156 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell 156 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC may be capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal memory values. In one example, if each MLC stores two bits of data, then the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used as the erase state.

[0061] like Figure 1B As shown, each NAND memory string 158 may include a source select gate (SSG) transistor 160 at its source end and a drain select gate (DSG) transistor 162 at its drain end. The SSG transistor 160 and DSG transistor 162 may be configured to activate the selected NAND memory string 158 (column of the array) during read and program operations. In some embodiments, each SSG transistor 160 of each NAND memory string 158 within the same memory block 154 is coupled to, for example, ground via the same source line (SL) 164 (e.g., a common SL). According to some embodiments, the DSG transistor 162 of each NAND memory string 158 is coupled to a corresponding bit line 166, enabling data to be read from or programmed onto the bit line 166 via an output bus (not shown). In some implementations, each NAND memory string 158 is configured to be selected or deselected by applying a selected voltage (e.g., exceeding the threshold voltage of the DSG transistor 162) or a deselected voltage (e.g., 0V) to the corresponding DSG transistor 162 via one or more DSG lines 163 and / or by applying a selected voltage (e.g., exceeding the threshold voltage of the SSG transistor 160) or a deselected voltage (e.g., 0V) to the corresponding SSG transistor 160 via one or more SSG lines 165.

[0062] like Figure 1B As shown, NAND memory strings 158 can be organized into multiple blocks 154, each of which may have a common source line 164. In some implementations, each block 154 is the basic data unit for erase operations; for example, all memory cells 156 on the same block 154 are erased simultaneously. Memory cells 156 of adjacent NAND memory strings 158 can be coupled via word lines 168, which select which row of memory cells 166 is affected by read and program operations.

[0063] Peripheral circuitry 152 can be coupled to memory cell array 151 via bit line 166, word line 168, source line 164, SSG line 165, and DSG line 163. As described above, peripheral circuitry 152 may include any suitable circuitry for facilitating the operation of memory cell array 151, which applies voltage and / or current signals to each target memory cell 156 via word line 168, source line 164, SSG line 165, and DSG line 163 via bit line 166 and senses voltage and / or current signals from each target memory cell 156, thereby facilitating said operation. Peripheral circuitry 152 may include various types of peripheral circuitry formed using CMOS technology.

[0064] Figure 2 A block diagram of an exemplary control logic circuit 200, including a main control circuit 202 and several logic circuits 204, is shown according to some aspects of this disclosure. In some embodiments of the memory device design, the main control circuit 202 may be located at the center of the chip, with numerous other circuits, such as the logic circuits 204 and their corresponding control circuits, distributed throughout various regions of the chip. In some embodiments, the logic circuits 204 may include register circuitry and associated control logic circuitry. In some embodiments, the main control circuit 202 and the logic circuits 204 may be located in… Figure 1A The control logic 112 is located within the main control circuitry. In some embodiments, the main control circuitry 202 and logic circuitry 204 may be placed within the control logic 112 to communicate with or control the register 114, column decoder / bitline driver 106, and row decoder / wordline driver 108. In some embodiments, these circuits interact with the main control circuitry 202, which relies on a global clock and bus protocol 206. Due to the large area of ​​the memory device, the wiring on the global clock and bus is long; in some embodiments, the power consumption on the global clock and bus is almost equal to the power consumption of the main digital circuitry itself.

[0065] This disclosure provides a simplified asynchronous circuit handshake protocol for generating a local clock signal, which replaces the original digital global clock and bus in the memory device, thus completely saving power consumption on the global clock and bus.

[0066] Figure 3 A block diagram of an exemplary click element 300 for an asynchronous circuit according to some aspects of this disclosure is shown. Asynchronous circuits (clockless or self-timing circuits) are sequential digital logic circuits that do not require a global clock circuit or signal generator to synchronize their components. Instead, components are driven by a handshake circuit that instructs the completion of a set of instructions. Asynchronous circuitry is a method for designing clockless digital systems. In a process called handshake between circuit sections that send and receive data, local signaling replaces global synchronization by exchanging request (req) and acknowledgment (ack) signals. Besides eliminating clock skew, other potential advantages of asynchronous systems include average-case performance, lower power consumption, and robustness. The handshake is accomplished by a simple data transmission protocol. In some embodiments, the handshake circuit or handshake protocol can be performed by the click element 300, which uses request signals (Ri, Ro) and acknowledgment signals (Ai, Ao) to facilitate communication between the main control circuit and registers, such as... Figure 3 As shown.

[0067] Figure 4A block diagram of an exemplary control logic circuit 400, including a main control circuit 402 and several sub-control circuits 404, is shown according to some aspects of this disclosure. In some embodiments, the main control circuit 402 and the sub-control circuits 404 may be placed in... Figure 1A The control logic 112 is located within this logic. In some embodiments, the main control circuit 402 and the sub-control circuit 404 may be placed within the control logic 112 to communicate with or control the register 114, the column decoder / bitline driver 106, and the row decoder / wordline driver 108. For example... Figure 4 As shown, without the need for a global clock signal, the main control circuit 402 and the sub-control circuit 404 interact or communicate via a trigger signal (request signal) "go" and an indication signal (acknowledgment signal) "done". In some embodiments, the main control circuit 402 may send a "go" signal to the sub-control circuit 404 to indicate the start of data transmission, and the sub-control circuit 404 may send a "done" signal back to the main control circuit 402 to indicate the completion of data transmission.

[0068] In some implementations, the control logic circuit 400 may include a main control circuit 402 and several different sub-control circuits 404. The trigger signal "go" and the indication signal "done" between the main control circuit 402 and the different sub-control circuits 404 can be operated independently. In other words, the main control circuit 402 outputs trigger signals to the different sub-control circuits 404 respectively, and receives indication signals from the different sub-control circuits 404 respectively.

[0069] By using this handshake protocol, a local clock signal is generated in the sub-control circuit 404 to replace the global clock and bus in the memory device, thereby completely eliminating the power consumption on the global clock and bus.

[0070] Figure 5 A block diagram of an exemplary sub-control circuit 404 according to some aspects of this disclosure is shown. In some embodiments, the sub-control circuit 404 may include an asynchronous control circuit 506 and a state machine circuit 508. In some embodiments, the asynchronous control circuit 506 may be a click element that receives a trigger signal 502 “go” generated by the main control circuit 402. In some embodiments, the asynchronous control circuit 506 may generate a local clock signal “fire” and provide the local clock signal “fire” to the state machine circuit 508.

[0071] In some embodiments, the state machine circuit 508 may include at least one state triggered by a local clock signal "fire" to switch states. In some embodiments, the state machine circuit 508 may have a local clock input "clk" that receives the local clock signal "fire" from the asynchronous control circuit 506. In some embodiments, the number of states in the state machine circuit 508 may be predefined based on the actual application, and the number of states is not limited. In some embodiments, each time a state in the state machine circuit 508 is switched to the next state, the state machine circuit 508 may output a signal "next" at its output to indicate the state switch. In some embodiments, when all states defined in the state machine circuit 508 have been completely switched, the state machine circuit 508 may output an indication signal 504 "done" at another output to indicate that data transmission is complete, and send the indication signal "done" back to the main control circuit 402.

[0072] In some embodiments, the sub-control circuit 404 may further include a delay element 510 and an XOR gate 512. In some embodiments, the XOR gate 512 may include an input receiving a trigger signal 502 "go" generated by the main control circuit 402 and another input receiving a signal "next_dly" delayed by the delay element 510. The delay element 510 is positioned between the input of the XOR gate 512 and the output of the output signal "next" from the state machine circuit 508. In some embodiments, the delay element 510 may be an inverter to delay the signal "next" by a predefined time. In some embodiments, the predefined time of the delay element 510 may be used to define the low-level duration of the local clock signal "fire".

[0073] In some implementations, the XOR gate 512 can combine the delayed signal "next_dly" delayed by the delay element 510 with the trigger signal "go" to generate a request signal, and the request signal is provided to the asynchronous control circuit 506 as the trigger signal "in_req".

[0074] Figure 6 A block diagram of an asynchronous control circuit 506 according to some aspects of this disclosure is shown. Figure 6As shown, the asynchronous control circuit 506 may include an XOR gate 602, a flip-flop circuit 604, and a delay element 606. The XOR gate 602 may include an input that receives a trigger signal "in_req" from the trigger signal 502 "go". The XOR gate 602 may include another input that receives a signal "pul_gen" from the delay element 606, and the XOR gate 602 combines the trigger signal "in_req" and the signal "pul_gen" to generate a local clock signal "fire" at the output of the XOR gate 602. In some embodiments, the flip-flop circuit 604 may include an enable terminal coupled to the output of the XOR gate 602, and may also provide the local clock signal "fire" to enable the flip-flop circuit 604.

[0075] In some embodiments, the trigger circuit 604 may be a D flip-flop. In some embodiments, the trigger circuit 604 may include an output terminal coupled to the data terminal of the trigger circuit 604 via an inverter 608. In some embodiments, a delay element 606 is disposed between the input terminal of the XOR gate 602 and the output terminal of the trigger circuit 604 to delay the output signal of the trigger circuit 604 by a predefined time. In some embodiments, the delay element 606 may be an inverter to delay the output signal of the trigger circuit 604 by a predefined time. In some embodiments, the predefined time of the delay element 606 may be used to define the high-level time of the local clock signal "fire".

[0076] Figure 7 A timing diagram 700 of an exemplary control logic circuit according to some aspects of this disclosure is shown, and Figure 8 A flowchart illustrating an exemplary method 800 for operating peripheral circuitry of a memory device according to some aspects of this disclosure is shown. To better describe this disclosure, [further details will be provided]. Figure 7 The timing diagram and Figure 8 Method 800 will be discussed together with this method. It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the examples. Figure 7 and Figure 8 The execution is performed in the order shown.

[0077] like Figure 7 as well as Figure 8As shown in operations 802 and 804, at time "t0", a trigger signal "go" is generated by the main control circuit 402, and the trigger signal "go" is received by the sub-control circuit 404. In some embodiments, the trigger signal "go" and the delay signal "next_dly" are combined to generate a request signal "in req", and the request signal "in req" is input to the input of the asynchronous control circuit 506.

[0078] like Figure 7 and Figure 8 As shown in operation 806, at time "t1", a local clock signal "fire" is generated in sub-control circuit 404. In some embodiments, the local clock signal "fire" is generated in asynchronous control circuit 506. In some embodiments, the request signal "in req" is combined with the delay signal "pul_gen" to generate the local clock signal "fire". In some embodiments, trigger circuit 604 is triggered by the local clock signal "fire" to generate a trigger output signal, and the trigger output signal is provided to delay element 606 to generate a delay signal "pul_gen" that is fed back to XOR gate 602.

[0079] like Figure 7 As shown, at time "t2", when the delay signal "pul_gen" is high, the XOR gate 602 can combine the delay signal "pul_gen" with the request signal "in req" to pull down the local clock signal "fire". In other words, the predefined time of the delay element 606 can be used to define the high-level time of the local clock signal "fire".

[0080] After generating the local clock signal "fire", the local clock signal "fire" is provided to the state machine circuit 508 as a clock signal to switch the states in the state machine circuit 508. For example... Figure 7 and Figure 8 As shown in operation 808, at time "t1", the state machine circuit 508 in the sub-control circuit 404 is triggered by the local clock signal "fire". In some embodiments, the state machine circuit 508 may include one or more predefined states based on different applications. Upon receiving the local clock signal, the state machine circuit 508 is switched sequentially.

[0081] In some implementations, each time a state in state machine circuit 508 is switched to the next state, state machine circuit 508 can output a signal "next" to indicate the state switch. The signal "next" is provided to delay element 510 to generate a delayed signal "next_dly" at time "t3". Then, the delayed signal "next_dly" is provided to XOR gate 512 to be combined with the trigger signal "go" to generate the trigger signal "in_req", and XOR gate 602 can combine the delayed signal "pul_gen" and the request signal "in req" to pull up the local clock signal "fire". In other words, the predefined time of delay element 510 can be used to define the low-level time of the local clock signal "fire".

[0082] In some implementations, when all states defined in the state machine circuit 508 have been sequentially and completely switched over, the state machine circuit 508 can output an indication signal 504 "done" at another output terminal to indicate that data transmission is complete, and send the indication signal "done" back to the main control circuit 402. For example... Figure 7 as well as Figure 8 As shown in operation 810, at time "t4", the sub-control circuit 404 generates an indication signal "done" and sends it to the main control circuit 402.

[0083] By using this handshake protocol, a local clock signal is generated in the sub-control circuit 404 to replace the global clock and bus in the memory device, thereby completely eliminating the power consumption on the global clock and bus.

[0084] Figure 9 A block diagram of an exemplary system 900 having a memory device according to some aspects of this disclosure is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device having memory located therein. Figure 9 As shown, system 900 may include host 908 and memory system 902, the memory system 902 having one or more memory devices 904 and a memory controller 906. Host 908 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 908 may be configured to send or receive data to or from memory device 904.

[0085] Memory device 904 can be any memory device disclosed in this disclosure, such as memory device 100. As detailed above, memory device 904 can have a controlled, predefined discharge current during a bit-line discharge operation. According to some embodiments, memory controller 906, such as the control logic circuit 400 described above, is coupled to memory device 904 and host 908 and is configured to control memory device 904. Memory controller 906 can manage data stored in memory device 904 and communicate with host 908. For example, memory controller 906 can be coupled to memory device 904 (e.g., memory device 100 described above), and memory controller 906 can be configured to control the operation of memory cells via peripheral devices.

[0086] In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 906 can be configured to control the operation of the memory device 904, such as read, erase, and program operations. The memory controller 906 can also be configured to manage various functions related to data stored in or to be stored in the memory device 904, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 906 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 904. The memory controller 906 may also perform any other appropriate functions, such as formatting the memory device 904. The memory controller 906 may communicate with an external device (e.g., the host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with an external device via at least one of various interface protocols such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0087] The memory controller 906 and one or more memory devices 904 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 902 can be implemented and packaged into different types of end electronic products. Figure 10A In one example shown, the memory controller 906 and a single memory device 904 can be integrated into the memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1002 may further include a connection between the memory card 1002 and a host computer (e.g., Figure 9 The memory card connector 1004 is coupled to the host 908 in the system. In such a way... Figure 10B In another example shown, a memory controller 906 and multiple memory devices 904 may be integrated into an SSD 1006. The SSD 1006 may further include interfaces for connecting the SSD 1006 to a host computer (e.g., Figure 9 The SSD connector 1008 is coupled to the host 908 in the memory card 1002. In some embodiments, the storage capacity and / or operating speed of the SSD 1006 is higher than that of the memory card 1002.

[0088] The descriptions of specific implementation methods described above can be easily modified and / or adapted for various applications. Therefore, based on the teachings and guidelines provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed implementation methods and equivalents.

[0089] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the following claims and their equivalents.

Claims

1. A memory device, comprising: A memory array configured to store data; Peripheral circuitry, coupled to the memory array and including control logic circuitry to control the operation of the peripheral circuitry. The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact through a first trigger signal and a first indication signal. The first sub-control circuit includes: An asynchronous control circuit, configured to receive the first trigger signal from the main control circuit and generate a local clock signal; and A state machine circuit configured to receive the local clock signal and generate the first indication signal, wherein the state machine circuit includes at least one state, the at least one state being triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a first output configured to output a next signal when switching the state, and an indication output. A first XOR gate, comprising a first input terminal configured to receive the first trigger signal, a second input terminal, and a second output terminal coupled to the asynchronous control circuit; and A first delay element is disposed between the second input terminal of the first XOR gate and the first output terminal of the state machine circuit.

2. The memory device according to claim 1, wherein, The main control circuit and the first sub-control circuit do not require a global clock signal, but interact through asynchronous control logic.

3. The memory device according to claim 1, wherein, The asynchronous control circuit includes: The second XOR gate includes a third input, a fourth input, and a third output, wherein the third input is configured to receive an output signal from the second output, and the third output is configured to output the local clock signal. A trigger circuit, comprising an enable terminal coupled to the third output terminal of the second XOR gate, a fourth output terminal, and a data terminal coupled to the fourth output terminal; and The second delay element is disposed between the fourth input terminal of the second XOR gate and the fourth output terminal of the flip-flop circuit.

4. The memory device according to claim 3, wherein, The trigger circuit includes a D flip-flop.

5. The memory device according to claim 3, wherein, The asynchronous control circuit also includes an inverter between the data terminal and the fourth output terminal of the trigger circuit.

6. The memory device according to claim 1, wherein, The indicator output terminal is configured to output the first indicator signal when the state in the state machine circuit is switched.

7. The memory device according to claim 3, wherein, The second output of the first XOR gate is coupled to the third input of the second XOR gate.

8. The memory device according to claim 3, wherein, The first delay element includes at least one inverter, and the second delay element includes at least one inverter.

9. The memory device according to claim 1, wherein, The control logic circuit further includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact through a second trigger signal and a second indication signal.

10. The memory device according to claim 9, wherein, The first sub-control circuit and the second sub-control circuit operate independently.

11. The memory device according to claim 10, wherein, The main control circuit is configured to output the first trigger signal and the second trigger signal respectively, and to receive the first indication signal and the second indication signal respectively.

12. A control logic circuit for controlling the operation of peripheral circuits of a memory device, comprising: A main control circuit and at least one first sub-control circuit, the main control circuit and the at least one sub-control circuit interacting with each other via a first trigger signal and a first indication signal; The sub-control circuit includes: An asynchronous control circuit, configured to receive the first trigger signal and generate a local clock signal; and A state machine circuit configured to receive the local clock signal and generate the first indication signal, wherein the state machine circuit includes at least one state, the at least one state being triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a first output configured to output a next signal when switching the state, and an indication output. A first XOR gate, comprising a first input terminal configured to receive the first trigger signal, a second input terminal, and a second output terminal coupled to the asynchronous control circuit; and A first delay element is disposed between the second input terminal of the first XOR gate and the first output terminal of the state machine circuit.

13. The control logic circuit according to claim 12, wherein, The asynchronous control circuit includes: The second XOR gate includes a third input, a fourth input, and a third output, wherein the third input is configured to receive an output signal from the second output, and the third output is configured to output the local clock signal. A trigger circuit, comprising an enable terminal coupled to the third output terminal of the second XOR gate, a fourth output terminal, and a data terminal coupled to the fourth output terminal; and The second delay element is disposed between the fourth input terminal of the second XOR gate and the fourth output terminal of the flip-flop circuit.

14. The control logic circuit according to claim 13, wherein, The trigger circuit includes a D flip-flop.

15. The control logic circuit according to claim 13, wherein, The asynchronous control circuit also includes an inverter between the data terminal and the fourth output terminal of the trigger circuit.

16. The control logic circuit according to claim 12, wherein, The indicator output terminal is configured to output the first indicator signal when the state in the state machine circuit is switched.

17. The control logic circuit according to claim 13, wherein, The second output of the first XOR gate is coupled to the third input of the second XOR gate.

18. The control logic circuit according to claim 13, wherein, The first delay element includes at least one inverter, and the second delay element includes at least one inverter.

19. The control logic circuit according to claim 12, further comprising a second sub-control circuit, wherein, The main control circuit and the second sub-control circuit interact via a second trigger signal and a second indication signal.

20. The control logic circuit according to claim 19, wherein, The first sub-control circuit and the second sub-control circuit operate independently.

21. The control logic circuit according to claim 20, wherein, The main control circuit is configured to output the first trigger signal and the second trigger signal respectively, and to receive the first indication signal and the second indication signal respectively.

22. A method for operating peripheral circuitry of a memory device, comprising: The trigger signal is generated by the main control circuit; The trigger signal is received by the sub-control circuit; A local clock signal is generated in the sub-control circuit; The state machine circuit is triggered in the sub-control circuit by the local clock signal; as well as The sub-control circuit generates an indication signal and sends the indication signal to the main control circuit. The trigger signal received by the sub-control circuit includes: The trigger signal and a first delayed signal, which delays the output signal of the state machine circuit, are combined to generate a request signal; and The request signal is sent to the asynchronous control circuit of the sub-control circuit.

23. The method according to claim 22, wherein, Generating the local clock signal in the sub-control circuit includes: The request signal and the second delay signal are combined to generate the local clock signal.

24. The method of claim 23, further comprising: The local clock signal triggers the flip-flop circuit to generate the flip-flop output signal; as well as The output signal of the trigger is delayed to generate the second delayed signal.

25. The method according to claim 24, wherein, Delaying the output signal of the trigger to generate the second delayed signal includes: The output signal of the trigger is delayed by a delay element.

26. The method according to claim 22, wherein, The state machine circuit is triggered in the sub-control circuit by the local clock signal, including: At least one state is defined in the state machine circuit; and When the local clock signal is received, the states in the state machine circuit are switched sequentially.

27. The method of claim 26, further comprising: When the state in the state machine circuit is switched, the next state signal is generated; as well as The next state signal is delayed to generate the first delayed signal.

28. The method according to claim 27, wherein, Generating the indication signal by the sub-control circuit and sending the indication signal to the main control circuit includes: When the state in the state machine circuit is switched, the indication signal is generated; and The indication signal is sent to the main control circuit to indicate the completion of the interaction between the main control circuit and the sub-control circuit.

29. A method for operating a control logic circuit, wherein, The control logic circuit includes a main control circuit and at least one sub-control circuit, including: The sub-control circuit receives a trigger signal from the main control circuit; In response to receiving the trigger signal, a local clock signal is generated in the sub-control circuit; The state machine circuit is triggered in the sub-control circuit by the local clock signal; and The sub-control circuit generates an indication signal and sends the indication signal to the main control circuit. The sub-control circuit receiving the trigger signal from the main control circuit includes: The trigger signal and a first delayed signal, which delays the output signal of the state machine circuit, are combined to generate a request signal; and The request signal is sent to the asynchronous control circuit of the sub-control circuit.

30. The method according to claim 29, wherein, In response to receiving the trigger signal, generating the local clock signal in the sub-control circuit includes: The request signal and the second delay signal are combined to generate the local clock signal.

31. The method of claim 30, further comprising: The local clock signal triggers the flip-flop circuit to generate the flip-flop output signal; as well as The output signal of the trigger is delayed to generate the second delayed signal.

32. The method according to claim 31, wherein, Delaying the output signal of the trigger to generate the second delayed signal includes: The output signal of the trigger is delayed by a delay element.

33. The method according to claim 29, wherein, The state machine circuit is triggered in the sub-control circuit by the local clock signal, including: At least one state is defined in the state machine circuit; and When the local clock signal is received, the states in the state machine circuit are switched sequentially.

34. The method of claim 33, further comprising: When the state in the state machine circuit is switched, the next state signal is generated; as well as The next state signal is delayed to generate the first delayed signal.

35. The method according to claim 34, wherein, Generating the indication signal by the sub-control circuit and sending the indication signal to the main control circuit includes: When the state in the state machine circuit is switched, the indication signal is generated; and The indication signal is sent to the main control circuit to indicate the completion of the interaction between the main control circuit and the sub-control circuit.

36. A memory system, comprising: Memory controller; as well as A memory device, coupled to the memory controller, includes: A memory array configured to store data; Peripheral circuitry, coupled to the memory array and including control logic circuitry to control the operation of the peripheral circuitry. The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact via a first trigger signal and a first indication signal. The first sub-control circuit includes: An asynchronous control circuit, configured to receive the first trigger signal from the main control circuit and generate a local clock signal; and A state machine circuit configured to receive the local clock signal and generate the first indication signal, wherein the state machine circuit includes at least one state, the at least one state being triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input configured to receive the local clock signal, a first output configured to output a next signal when switching the state, and an indication output. A first XOR gate, comprising a first input terminal configured to receive the first trigger signal, a second input terminal, and a second output terminal coupled to the asynchronous control circuit; and A first delay element is disposed between the second input terminal of the first XOR gate and the first output terminal of the state machine circuit.

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