Memory device, operating method thereof, and memory system

Abstract

The invention provides a memory device, an operation method thereof and a memory system. The memory device comprises a peripheral circuit and a memory array coupled with the peripheral circuit; the storage array comprises a conductive wire; the peripheral circuit comprises a discharge circuit coupled with the conductive wire, and the discharge circuit comprises a first sub-discharge circuit and a second sub-discharge circuit; wherein the first sub-discharge circuit is configured to discharge an operation voltage on the conductive wire to a first voltage in response to a power-down signal; the second sub-discharge circuit is configured to discharge the first voltage to a second voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device and an operating method thereof, and a memory system. Background Art

[0002] Memory devices are memory devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable programming and erasing speed and retention characteristics.

[0003] During the use of the memory device, a sudden power failure may occur. How to reduce the negative impact of the sudden power failure on the memory device has become a problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory device, the memory device comprising a peripheral circuit and a memory array coupled to the peripheral circuit; the memory array comprises a conductive line; the peripheral circuit comprises a discharge circuit coupled to the conductive line, the discharge circuit comprises a first sub-discharge circuit and a second sub-discharge circuit; wherein,

[0007] The first sub-discharging circuit is configured to discharge the operating voltage on the conductive line to a first voltage in response to a power-off signal;

[0008] The second sub-discharging circuit is configured to discharge the first voltage to a second voltage.

[0009] In an optional embodiment, the first sub-discharge circuit includes a current mirror circuit; the current mirror circuit includes a constant current source, a first transistor, a second transistor and a first switch; the first end of the first transistor and the first end of the second transistor are both connected to the ground voltage; the control end and the second end of the first transistor are both connected to the constant current source; the second end of the second transistor is coupled to the conductive line; the first end of the first switch is connected to the control end of the first transistor, and the second end of the first switch is connected to the control end of the second transistor.

[0010] In an optional implementation, the first sub-discharge circuit further includes a third transistor; the second end of the third transistor is connected to the conductive line, the first end of the third transistor is connected to the second end of the second transistor; and the control end of the third transistor is connected to the ground voltage.

[0011] In an optional embodiment, the second sub-discharge circuit includes a fourth transistor and a second switch; the second end of the fourth transistor is connected to the conductive line, and the first end of the fourth transistor is connected to the ground voltage; the first end of the second switch is connected to the control end of the fourth transistor, and the second end of the second switch receives the first control voltage.

[0012] In an optional embodiment, the second sub-discharge circuit includes the third transistor, a fifth transistor and a third switch; the first end of the fifth transistor is connected to the first end of the third transistor, and the second end of the fifth transistor is connected to the ground voltage; the first end of the third switch is connected to the control end of the fifth transistor, and the second end of the third switch receives a second control voltage.

[0013] In an optional embodiment, the second sub-discharge circuit includes the third transistor, the second transistor and a capacitor; the first plate of the capacitor is connected to the second end of the first switch and the control end of the second transistor; the second plate of the capacitor is connected to the ground voltage.

[0014] In an optional implementation, the conductive line includes a source line and / or a bit line.

[0015] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0016] At least one memory device according to any one of the above embodiments;

[0017] A memory controller is coupled to the at least one memory device and is configured to control the memory device.

[0018] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory device, wherein the memory device comprises a memory array and a discharge circuit coupled to a conductive line in the memory array, wherein the discharge circuit comprises a first sub-discharge circuit and a second sub-discharge circuit; the operating method comprises:

[0019] In response to a power-off signal, discharging the operating voltage on the conductive line to a first voltage through the first sub-discharging circuit;

[0020] The first voltage is discharged to a second voltage through the second sub-discharging circuit.

[0021] In an optional implementation, the first sub-discharging circuit includes a current mirror circuit and a third transistor; the current mirror circuit includes a first transistor, a second transistor and a first switch; the first switch is located between a control terminal of the first transistor and a control terminal of the second transistor; and discharging the operating voltage to the first voltage through the first sub-discharging circuit includes:

[0022] In response to the power-off signal, the first switch is closed, and the operating voltage is discharged to the first voltage through the third transistor and the current mirror circuit; the first voltage is higher than the ground voltage.

[0023] In an optional implementation, the second sub-discharging circuit includes a fourth transistor and a second switch connected to the control terminal of the fourth transistor; discharging the first voltage to a second voltage through the second sub-discharging circuit includes:

[0024] The first switch is opened and the second switch is closed, so that the fourth transistor is turned on by the first control voltage and the first voltage is discharged to the second voltage through the fourth transistor.

[0025] In an optional implementation, the second sub-discharging circuit includes the third transistor, the fifth transistor, and a third switch connected to the control terminal of the fifth transistor; discharging the first voltage to the second voltage through the second sub-discharging circuit includes:

[0026] The first switch is opened and the third switch is closed to turn on the fifth transistor through a second control voltage, and the first voltage is discharged to the second voltage through the third transistor and the fifth transistor.

[0027] In an optional implementation, the second sub-discharge circuit includes the third transistor, the second transistor and a capacitor; the first plate and the second plate of the capacitor are respectively connected to the control terminal of the second transistor and the ground voltage; and discharging the first voltage to the second voltage through the second sub-discharge circuit includes:

[0028] The first switch is turned off, and the first voltage is discharged to the second voltage through the third transistor and the second transistor.

[0029] In the technical solution provided by the present disclosure, the memory device includes a discharge circuit coupled to a conductive line. When the memory device suddenly loses power, the first sub-discharge circuit in the discharge circuit can discharge the operating voltage on the conductive line to a first voltage in response to a power-off signal, and the second sub-discharge circuit can discharge the first voltage to a second voltage. On the one hand, the first sub-discharge circuit includes a current mirror circuit, which can control the discharge current, thereby reducing the instantaneous discharge speed of the high voltage, and avoiding the coupling effect caused by the excessively fast instantaneous discharge speed that causes other circuit elements in the memory device to be damaged; on the other hand, when the voltage is reduced to the point where the normal operation of the current mirror circuit cannot be maintained, the second sub-discharge circuit can continue to be used to discharge in a faster discharge mode or a discharge mode similar to that of the first sub-discharge circuit, so that the higher operating voltage on the conductive line can be discharged to a lower voltage, thereby avoiding the higher operating voltage from causing damage to the circuit elements in the memory device, and reducing the negative impact of sudden power failure on the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for an embodiment of the present disclosure;

[0032] Figure 3 A schematic diagram of an exemplary solid state drive having a memory system provided for an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present disclosure;

[0035] Figure 6 A circuit diagram of a discharge circuit provided for a specific example of the present disclosure;

[0036] Figure 7 A voltage curve 1 on a conductive line provided by an embodiment of the present disclosure;

[0037] Figure 8 A circuit diagram of a discharge circuit provided for another specific example of the present disclosure Figure 1 ;

[0038] Fig. 9 A circuit diagram of a discharge circuit provided for another specific example of the present disclosure Figure 2 ;

[0039] Fig.10 A second voltage curve on a conductive line provided in an embodiment of the present disclosure;

[0040] Fig.11 A discharge circuit provided for another specific example of the present disclosure Figure 1 ;

[0041] Fig.12 A discharge circuit provided for another specific example of the present disclosure Figure 2 ;

[0042] Fig.13 A flowchart of an operating method of a memory device provided in an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0043] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0045] In the drawings, like reference numerals refer to like elements throughout.

[0046] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system including a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking the memory system including a three-dimensional NAND memory as an example.

[0049] Figure 1 Schematic diagram of an exemplary system with a memory system provided for an embodiment of the present disclosure. In the embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , the system 100 may include a host device 101 and a memory system 102, and the memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to the memory system 102 or receive data from the memory system 102.

[0050] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101, and is configured to control the memory device 103. The memory controller 104 can manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (Compact Flash Card, CFC), a universal serial bus (Universal Serial BUS, USB) flash drive, or in other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as a solid state drive or an embedded multimedia card (EmbeddedMulti-MediaCard, eMMC).

[0051] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0052] In such Figure 2 In one example shown in , the memory controller 104 and the single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1 The host device 101 in the embodiment of the present invention is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD203 is greater than the storage capacity and / or operating speed of memory card 201.

[0053] Figure 4A circuit diagram of an exemplary memory device 300 including peripheral circuits provided for an embodiment of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 103 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0054] In some embodiments, each memory cell 305 is a single level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0055] like Figure 4As shown in , each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled through a common source line (CSL) 310. In other words, all memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data can be read or written from the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0056] like Figure 4 As shown in , the memory string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or programming operation.

[0057] In some embodiments, the peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for implementing operations on the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology.

[0058] Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, a control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0059] The page buffer / sense amplifier 401 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic 405. In one example, the page buffer / sense amplifier 401 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 401 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 401 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 402 can be configured to be controlled by the control logic 405, and select one or more memory strings by applying a bit line voltage generated from the voltage generator 404.

[0060] The row decoder / word line driver 403 may be configured to be controlled by the control logic 405 and to select / deselect a memory block of the memory array 301 and to select / deselect a word line of the memory block. The row decoder / word line driver 408 may also be configured to drive a word line using a word line voltage generated from the voltage generator 404. In some embodiments, the row decoder / word line driver 403 may also select / deselect and drive a lower selection line and an upper selection line. As described in detail below, the row decoder / word line driver 403 is configured to perform a programming operation on a memory cell coupled to (one or more) selected word lines. The voltage generator 404 may be configured to be controlled by the control logic 405 and to generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0061] The control logic 405 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 406 may be coupled to the control logic 405, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The flash memory interface 407 may be coupled to the control logic 405, and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic 405, and to buffer status information received from the control logic 405 and relay them to the memory controller. The flash memory interface 407 may also be coupled to the column decoder / bit line driver 402 via the data bus 408, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 301 or relay or buffer data from the storage array 301.

[0062] For the above-mentioned memory device, when performing programming operation, reading operation or erasing operation, a higher operating voltage may be required. However, as the integration of the memory device is further improved, the size of the circuit elements in the memory device is further reduced, and the voltage resistance of the circuit elements is reduced accordingly. When the memory device suddenly loses power, the higher operating voltage may damage the circuit elements in the memory device, thereby causing the performance of the memory device to decrease after power is restored, or even to be unable to continue normal operation. Therefore, how to reduce the negative impact of sudden power failure on the memory device has become a problem that needs to be solved urgently. In this regard, the present disclosure proposes the following implementation methods.

[0063] The present disclosure provides a memory device, which includes a peripheral circuit and a memory array coupled to the peripheral circuit; the memory array includes a conductive line, the peripheral circuit includes a discharge circuit coupled to the conductive line, the discharge circuit includes a first sub-discharge circuit and a second sub-discharge circuit; wherein the first sub-discharge circuit is configured to discharge an operating voltage on the conductive line to a first voltage in response to a power-off signal; and the second sub-discharge circuit is configured to discharge the first voltage to a second voltage.

[0064] In some specific examples, such as Figure 4 As shown, the conductive line may be a source line 310, a bit line 311, a word line 312, or other conductive lines that need to withstand a higher operating voltage during the operation of the memory device. For example, when performing an erase operation on the memory array through a gate induced drain leakage (GIDL) erase mechanism, it is necessary to apply an erase voltage to both the source line 310 and the bit line 311, and the erase voltage may reach more than 20V; when performing a read operation on the memory array, it is necessary to apply a higher turn-on voltage to the unselected word line 312; when performing a programming operation on the memory array, it is necessary to apply a higher programming voltage to the selected word line 312. When the memory device suddenly loses power, if these operating voltages cannot be discharged in time, they may cause damage to the circuit elements in the memory device.

[0065] In the embodiment of the present disclosure, the discharge circuit coupled to the conductive line in the memory array can discharge the operating voltage on the conductive line through the first sub-discharge circuit and the second sub-discharge circuit in response to the power-off signal, so that when a sudden power failure occurs, the higher operating voltage can be discharged to the lower second voltage in time, thereby preventing the higher operating voltage from damaging the circuit elements in the memory device and reducing the negative impact of the sudden power failure on the memory device. Below, the memory device including the discharge circuit provided by the present disclosure will be described in detail with reference to specific examples.

[0066] Figure 6 A circuit diagram of a discharge circuit provided for a specific example of the present disclosure is shown in FIG. Figure 6 As shown, two ends of the discharge circuit 500 are coupled to the conductive line and the ground voltage VSS respectively, and the discharge circuit 500 includes a first sub-discharge circuit 501 and a second sub-discharge circuit 502 .

[0067] The first sub-discharge circuit 501 includes a current mirror circuit, which includes a first transistor Q1, a second transistor Q2, a constant current source I and a first switch S1. The first end of the first transistor Q1 and the first end of the second transistor Q2 are both connected to the ground voltage VSS; the control end and the second end of the first transistor Q1 are both connected to the constant current source I; the second end of the second transistor Q2 is coupled to the conductive line; the first end of the first switch S1 is connected to the control end of the first transistor Q1, and the second end of the first switch S1 is connected to the control end of the second transistor Q2.

[0068] The first sub-discharging circuit 501 further includes a third transistor Q3; a second end of the third transistor Q3 is connected to the conductive line, a first end of the third transistor Q3 is connected to the second end of the second transistor Q2; and a control end of the third transistor Q3 is connected to the ground voltage VSS.

[0069] The second sub-discharging circuit 502 includes a fourth transistor Q4 and a second switch S2; the second end of the fourth transistor Q4 is connected to the conductive line, and the first end of the fourth transistor Q4 is connected to the ground voltage VSS; the first end of the second switch S2 is connected to the control end of the fourth transistor Q4, and the second end of the second switch S2 receives the first control voltage.

[0070] In some specific examples, the first transistor Q1 , the second transistor Q2 , the third transistor Q3 , and the fourth transistor Q4 are all NMOS transistors.

[0071] In the embodiment of the present disclosure, when the first switch S1 is closed and the second switch S2 is opened, the voltage on the conductive line can be discharged through the first sub-discharge circuit 501, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I; when the first switch S1 is opened and the second switch S2 is closed, the first control voltage can turn on the fourth transistor Q4, and the voltage on the conductive line can be discharged through the second sub-discharge circuit 502, and the magnitude of the discharge current is jointly determined by the magnitude of the voltage on the conductive line and the on-resistance of the fourth transistor Q4.

[0072] In some embodiments, the peripheral circuit further includes control logic, which can be configured to: in response to a power-off signal, close the first switch S1 so that the first sub-discharge circuit 501 discharges the operating voltage on the conductive line to the first voltage; open the first switch S1 and close the second switch S2 so that the second sub-discharge circuit 502 discharges the voltage on the conductive line from the first voltage to the second voltage.

[0073] In some specific examples, the peripheral circuit may further include a power-off detection unit, which may be coupled to the power supply voltage VDD and the control logic of the memory device. When the power-off detection unit detects that the power supply voltage VDD is lower than a preset voltage within a certain period of time and the maintenance time exceeds a preset time length, the power-off detection unit may determine that a sudden power failure occurs in the memory device and may send a power-off signal to the control logic.

[0074] In a specific example, Figure 7 5 is a voltage curve on a conductive line of a memory device including a discharge circuit 500. In the operation execution phase before the first discharge phase T1, the voltage on the conductive line gradually rises from the ground voltage VSS to the operating voltage. Here, the conductive line may be a source line or a bit line, and the operating voltage may be an erase voltage, which may be 22.5V.

[0075] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 501 can discharge the operating voltage to the first voltage. Since the operating voltage is relatively high, the discharge current can be controlled by discharging through the current mirror circuit in the first sub-discharge circuit 501, thereby reducing the instantaneous discharge speed of the high voltage and avoiding the coupling effect caused by the excessively fast instantaneous discharge speed, which may cause damage to other circuit elements in the memory device.

[0076] The first sub-discharge circuit 501 can only discharge the erase voltage to the first voltage. This is because after a sudden power failure occurs, the working time of the constant current source I is limited. After the operating voltage is discharged to the first voltage, the power supply voltage connected to the constant current source I is already low and cannot continue to maintain the operation of the current mirror circuit. The first voltage is still higher than the ground voltage VSS, which may still cause damage to the circuit elements.

[0077] In some specific examples, the first voltage may range from 1 V to 2 V. In a specific example, the first voltage may be 1.65V.

[0078] In the second discharge stage T2, the second sub-discharge circuit 502 can continue to discharge the first voltage to the second voltage, where the second voltage can be the ground voltage VSS, such as 0 V. Since the first voltage is lower than the erase voltage, it can be discharged to the second voltage at a faster discharge speed through the fourth transistor Q4 in the second sub-discharge circuit 502.

[0079] In the embodiment of the present disclosure, the first sub-discharge circuit 501 in the discharge circuit can discharge the operating voltage on the conductive line to the first voltage, and the second sub-discharge circuit 502 can continue to discharge the first voltage to the second voltage, so that when a sudden power failure occurs in the memory device, the higher operating voltage on the conductive line can be discharged to the ground voltage VSS, thereby preventing the higher operating voltage from damaging the circuit elements in the memory device and reducing the negative impact of the sudden power failure on the memory device.

[0080] Figure 8 and Fig. 9 A circuit diagram of a discharge circuit provided for another specific example of the present disclosure is shown in FIG. Figure 8 and Fig. 9 As shown, two ends of the discharge circuit 600 are coupled to the conductive line and the ground voltage VSS respectively, and the discharge circuit 600 includes a first sub-discharge circuit 601 and a second sub-discharge circuit 602 .

[0081] The first sub-discharge circuit 601 includes a current mirror circuit and a third transistor Q3. The current mirror circuit includes a first transistor Q1, a second transistor Q2, a constant current source I and a first switch S1. The first end of the first transistor Q1 and the first end of the second transistor Q2 are both connected to the ground voltage VSS; the control end and the second end of the first transistor Q1 are both connected to the constant current source I; the second end of the second transistor Q2 is coupled to the conductive line; the first end of the first switch S1 is connected to the control end of the first transistor Q1, and the second end of the first switch S1 is connected to the control end of the second transistor Q2; the second end of the third transistor Q3 is connected to the conductive line, and the first end of the third transistor Q3 is connected to the second end of the second transistor Q2; the control end of the third transistor Q3 is connected to the ground voltage VSS.

[0082] The second sub-discharge circuit 602 includes a third transistor Q3, a fifth transistor Q5 and a third switch S3; the first end of the fifth transistor Q5 is connected to the first end of the third transistor Q3, and the second end of the fifth transistor Q5 is connected to the ground voltage VSS; the first end of the third switch S3 is connected to the control end of the fifth transistor Q5, and the second end of the third switch S3 receives the second control voltage.

[0083] In some specific examples, the first transistor Q1 , the second transistor Q2 , and the third transistor Q3 are all NMOS transistors, and the fifth transistor Q5 is a PMOS transistor.

[0084] In the embodiment of the present disclosure, when the first switch S1 is closed and the third switch S3 is opened, the voltage on the conductive line can be discharged through the first sub-discharge circuit 601, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I; when the first switch S1 is opened and the third switch S3 is closed, the second control voltage can turn on the fifth transistor Q5, and the voltage on the conductive line can be discharged through the second sub-discharge circuit 602, and the magnitude of the discharge current is jointly determined by the magnitude of the voltage on the conductive line, the on-resistance of the third transistor Q3 and the on-resistance of the fifth transistor Q5.

[0085] In the embodiment of the present disclosure, the control logic can be configured to: in response to a power-off signal, close the first switch S1 so that the first sub-discharge circuit 601 discharges the operating voltage on the conductive line to the first voltage; open the first switch S1 and close the third switch S3 so that the second sub-discharge circuit 602 discharges the voltage on the conductive line from the first voltage to the second voltage.

[0086] In a specific example, Fig.10 6 is a voltage curve on a conductive line of a memory device including a discharge circuit 600. In the operation execution phase before the first discharge phase T1, the voltage on the conductive line gradually rises from the ground voltage VSS to the operating voltage. Here, the conductive line may be a source line or a bit line, and the operating voltage may be an erase voltage, which may be 22.5V.

[0087] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 601 can discharge the operating voltage to the first voltage. Since the operating voltage is relatively high, the discharge current can be controlled by discharging through the current mirror circuit in the first sub-discharge circuit 601, thereby reducing the instantaneous discharge speed of the high voltage and avoiding the coupling effect caused by the excessively fast instantaneous discharge speed, which may cause damage to other circuit elements in the memory device.

[0088] After the first sub-discharge circuit 601 discharges the operating voltage to the first voltage, the power supply voltage connected to the constant current source I is already low, and the operation of the current mirror circuit cannot be continued. In the second discharge stage T2, the second sub-discharge circuit 602 can continue to discharge the first voltage to the second voltage, where the second voltage can be the ground voltage VSS, such as 0 V. Here, the second sub-discharge circuit 602 can maintain a discharge speed that is almost the same as that of the first sub-discharge circuit 601.

[0089] In the embodiment of the present disclosure, the fifth transistor Q5 is turned on by the second control voltage in the second discharge stage T2. Since the fifth transistor Q5 is a PMOS transistor, only a small gate voltage is required to turn it on, thereby further improving the reliability of the discharge circuit in the low-voltage discharge section. That is, when the voltage in the memory device has dropped to a lower level, the conduction of the fifth transistor Q5 can still be maintained, so that the first voltage can be further discharged to the second voltage.

[0090] Fig.11 and Fig.12 A circuit diagram of a discharge circuit provided for another specific example of the present disclosure is as follows: Fig.11 and Fig.12 As shown, two ends of the discharge circuit 700 are coupled to the conductive line and the ground voltage VSS respectively, and the discharge circuit 700 includes a first sub-discharge circuit 701 and a second sub-discharge circuit 702 .

[0091] The first sub-discharge circuit 701 includes a current mirror circuit and a third transistor Q3. The current mirror circuit includes a first transistor Q1, a second transistor Q2, a constant current source I and a first switch S1. The first end of the first transistor Q1 and the first end of the second transistor Q2 are both connected to the ground voltage VSS; the control end and the second end of the first transistor Q1 are both connected to the constant current source I; the second end of the second transistor Q2 is coupled to the conductive line; the first end of the first switch S1 is connected to the control end of the first transistor Q1, and the second end of the first switch S1 is connected to the control end of the second transistor Q2; the second end of the third transistor Q3 is connected to the conductive line, and the first end of the third transistor Q3 is connected to the second end of the second transistor Q2; the control end of the third transistor Q3 is connected to the ground voltage VSS.

[0092] The second sub-discharging circuit 702 includes a third transistor Q3, a second transistor Q2 and a capacitor C; a first plate of the capacitor C is connected to the second end of the first switch S1 and the control end of the second transistor Q2, and a second plate of the capacitor C is connected to the ground voltage VSS.

[0093] In some specific examples, the first transistor Q1 , the second transistor Q2 , and the third transistor Q3 are all NMOS transistors.

[0094] In some embodiments, the control logic can be configured to: in response to a power-off signal, close the first switch S1 so that the first sub-discharge circuit 701 discharges the operating voltage on the conductive line to the first voltage; and open the first switch S1 so that the second sub-discharge circuit 702 discharges the voltage on the conductive line from the first voltage to the second voltage.

[0095] In the embodiment of the present disclosure, when the first switch S1 is closed, the voltage on the conductive line can be discharged through the first sub-discharge circuit 701, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I. At the same time, the constant current source I can charge the capacitor C; when the first switch S1 is disconnected, the voltage on the first plate of the capacitor C can maintain the gate voltage of the second transistor Q2, and the voltage on the conductive line is discharged through the second sub-discharge circuit 702.

[0096] Return to reference Fig.10 For the memory device including the discharge circuit 700, the voltage curve on the conductive line when a sudden power failure occurs during the operation execution is similar to that of the memory device including the discharge circuit 600. In the operation execution stage before the first discharge stage T1, the voltage on the conductive line gradually rises from the ground voltage VSS to the operation voltage.

[0097] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 701 can discharge the operating voltage to the first voltage. Since the operating voltage is relatively high, the discharge current can be controlled by discharging through the current mirror circuit in the first sub-discharge circuit 701, thereby reducing the instantaneous discharge speed of the high voltage and avoiding the coupling effect caused by the excessively fast instantaneous discharge speed, which may cause damage to other circuit elements in the memory device.

[0098] After the first sub-discharge circuit 701 discharges the operating voltage to the first voltage, the power supply voltage connected to the constant current source I is already low, and the operation of the current mirror circuit cannot be maintained. In the second discharge stage T2, the second sub-discharge circuit 702 can continue to discharge the first voltage to the second voltage, and the second voltage can be the ground voltage VSS, such as 0 V. Here, the second sub-discharge circuit 702 can maintain a discharge speed that is almost the same as that of the first sub-discharge circuit 701.

[0099] In the embodiment of the present disclosure, when the voltage drops to a level that makes it impossible to maintain the operation of the current mirror circuit, the voltage on the first plate of the capacitor C can continue to maintain the voltage on the control terminal of the second transistor Q2, thereby allowing the second transistor Q2 to continue to remain in the on state, and the second sub-discharge circuit 702 can continue to discharge the voltage on the conductive line to the second voltage, so that when a sudden power failure occurs in the memory device, the higher operating voltage on the conductive line can be discharged to the ground voltage VSS, thereby preventing the higher operating voltage from damaging the circuit elements in the memory device and reducing the negative impact of the sudden power failure on the memory device.

[0100] In addition, combined with reference Figure 6 , Fig. 9 and Fig.12Compared with the discharge circuit 500 and the discharge circuit 600 , the discharge circuit 700 occupies a smaller circuit area, which is more conducive to the miniaturization of the memory device.

[0101] In some embodiments, the memory device may include one or more discharge circuits of the discharge circuit 500, the discharge circuit 600, and the discharge circuit 700.

[0102] In some embodiments, there may be multiple discharge circuits coupled to the same conductive line, that is, the operating voltage on the same conductive line may be discharged through multiple discharge circuits to further reduce the negative impact of sudden power failure on the memory device and improve the reliability of the memory device.

[0103] Based on the concept similar to the above-mentioned memory device, the present disclosure also provides a memory system, which includes: at least one memory device in any of the above-mentioned embodiments; a memory controller coupled to the at least one memory device and configured to control the memory device. For the specific composition and function implementation of the memory system, please refer to the above description of Figures 1 to 5 For the sake of brevity, the description is not repeated here.

[0104] The present disclosure also provides an operating method of a memory device. Fig.13 The present disclosure provides a flow chart of the operation method of the memory device, as shown in Fig.13 As shown, the operating method of the memory device includes the following steps:

[0105] Step S10: in response to a power-off signal, discharging the operating voltage on the conductive line to a first voltage through the first sub-discharging circuit;

[0106] Step S20: discharging the first voltage to a second voltage through the second sub-discharging circuit.

[0107] In some embodiments, a memory device includes a memory array and a discharge circuit coupled to a conductive line in the memory array, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit.

[0108] In some embodiments, the conductive line may be a source line, a bit line or a word line. Before executing step S10, the memory device operation method further includes: applying an operating voltage to the conductive line, for example, applying an erase voltage to the source line and the bit line, or applying a turn-on voltage or a programming voltage to the word line.

[0109] In some embodiments, reference Figure 6 , Figure 8 and Fig.11The first sub-discharging circuit includes a current mirror circuit and a third transistor Q3, and the current mirror circuit includes a first transistor Q1, a second transistor Q2, and a first switch S1 located between a control terminal of the first transistor Q1 and a control terminal of the second transistor Q2. The specific process of performing step S10 includes: in response to the power-off signal, closing the first switch S1, and discharging the operating voltage on the conductive line to a first voltage through the third transistor Q3 and the current mirror circuit, and the first voltage is higher than the ground voltage VSS.

[0110] In a specific example, referring to Figure 6 The discharge circuit 500 coupled to the conductive line includes a first sub-discharge circuit 501 and a second sub-discharge circuit 502, and the second sub-discharge circuit 502 includes a fourth transistor Q4 and a second switch S2 connected to the control terminal of the fourth transistor Q4. The specific process of performing step S20 includes: opening the first switch S1 and closing the second switch S2 to turn on the fourth transistor Q4 through the first control voltage, and discharging the first voltage to the second voltage through the fourth transistor Q4.

[0111] In another specific example, referring to Figure 8 and Fig. 9 The discharge circuit 600 includes a first sub-discharge circuit 601 and a second sub-discharge circuit 602, and the second sub-discharge circuit 602 includes a third transistor Q3, a fifth transistor Q5, and a third switch S3 connected to the control terminal of the fifth transistor Q5. The specific process of performing step S20 includes: disconnecting the first switch S1 and closing the third switch S3 to turn on the fifth transistor Q5 through the second control voltage, and discharging the first voltage to the second voltage through the third transistor Q3 and the fifth transistor Q5.

[0112] In another specific example, referring to Fig.11 and Fig.12 The discharge circuit 700 coupled to the conductive line includes a first sub-discharge circuit 701 and a second sub-discharge circuit 702. The second sub-discharge circuit 702 includes a third transistor Q3, a second transistor Q2 and a capacitor C. The first plate and the second plate of the capacitor C are respectively connected to the control terminal of the second transistor Q2 and the ground voltage VSS. The specific process of performing step S20 includes: disconnecting the first switch S1, and discharging the first voltage to the second voltage through the third transistor Q3 and the second transistor Q2.

[0113] In the embodiment of the present disclosure, after a sudden power failure occurs in the memory device, the current mirror circuit in the first sub-discharge circuit can be used to discharge first, and the magnitude of the discharge current can be controlled, so that the instantaneous discharge speed of the high voltage can be reduced, and the coupling effect caused by the excessively fast instantaneous discharge speed can be avoided to cause other circuit elements in the memory device to be damaged. When the voltage on the conductive line drops to the first voltage, the current mirror circuit in the first sub-discharge circuit cannot continue to work, and the second sub-discharge circuit including the fourth transistor Q4, the second sub-discharge circuit including the third transistor Q3 and the fifth transistor Q5, or the second sub-discharge circuit including the third transistor Q3, the second transistor Q2 and the capacitor C can continue to discharge, so as to discharge the first voltage to the second voltage, and the second voltage can be the ground voltage VSS of 0V, so that the higher operating voltage on the conductive line can be discharged to a lower voltage, so as to avoid the higher operating voltage from causing damage to the circuit elements in the memory device, and reduce the negative impact of the sudden power failure on the memory device.

[0114] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0115] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: The memory device comprises a peripheral circuit and a memory array coupled to the peripheral circuit; the memory array comprises a conductive line; the peripheral circuit comprises a discharge circuit coupled to the conductive line, the discharge circuit comprises a first sub-discharge circuit and a second sub-discharge circuit; wherein, The first sub-discharging circuit is configured to discharge the operating voltage on the conductive line to a first voltage in response to a power-off signal; The second sub-discharging circuit is configured to discharge the first voltage to a second voltage.

2. The memory device according to claim 1, wherein: The first sub-discharge circuit includes a current mirror circuit; the current mirror circuit includes a constant current source, a first transistor, a second transistor and a first switch; the first end of the first transistor and the first end of the second transistor are both connected to the ground voltage; the control end and the second end of the first transistor are both connected to the constant current source; the second end of the second transistor is coupled to the conductive line; the first end of the first switch is connected to the control end of the first transistor, and the second end of the first switch is connected to the control end of the second transistor.

3. The memory device according to claim 2, wherein: The first sub-discharging circuit further includes a third transistor; the second end of the third transistor is connected to the conductive line, the first end of the third transistor is connected to the second end of the second transistor; and the control end of the third transistor is connected to the ground voltage.

4. The memory device according to claim 3, wherein: The second sub-discharge circuit includes a fourth transistor and a second switch; the second end of the fourth transistor is connected to the conductive line, and the first end of the fourth transistor is connected to the ground voltage; the first end of the second switch is connected to the control end of the fourth transistor, and the second end of the second switch receives a first control voltage.

5. The memory device according to claim 3, wherein: The second sub-discharge circuit includes the third transistor, a fifth transistor and a third switch; the first end of the fifth transistor is connected to the first end of the third transistor, and the second end of the fifth transistor is connected to the ground voltage; the first end of the third switch is connected to the control end of the fifth transistor, and the second end of the third switch receives a second control voltage.

6. The memory device according to claim 3, wherein: The second sub-discharging circuit includes the third transistor, the second transistor and a capacitor; the first plate of the capacitor is connected to the second end of the first switch and the control end of the second transistor; The second plate of the capacitor is connected to the ground voltage.

7. The memory device according to claim 1, wherein: The conductive lines include source lines and / or bit lines.

8. A memory system, characterized in that: include: at least one memory device as claimed in any one of claims 1 to 7; A memory controller is coupled to the at least one memory device and is configured to control the memory device.

9. A method for operating a memory device, characterized in that: The memory device includes a memory array and a discharge circuit coupled to a conductive line in the memory array, the discharge circuit includes a first sub-discharge circuit and a second sub-discharge circuit; the operating method includes: In response to a power-off signal, discharging the operating voltage on the conductive line to a first voltage through the first sub-discharging circuit; The first voltage is discharged to a second voltage through the second sub-discharging circuit.

10. The method for operating a memory device according to claim 9, wherein: The first sub-discharging circuit includes a current mirror circuit and a third transistor; the current mirror circuit includes a first transistor, a second transistor and a first switch; the first switch is located between the control end of the first transistor and the control end of the second transistor; The step of discharging the operating voltage to a first voltage through the first sub-discharging circuit includes: In response to the power-off signal, closing the first switch, and discharging the operating voltage to the first voltage through the third transistor and the current mirror circuit; The first voltage is higher than a ground voltage.

11. The method for operating a memory device according to claim 10, wherein: The second sub-discharging circuit includes a fourth transistor and a second switch connected to the control terminal of the fourth transistor; The step of discharging the first voltage to a second voltage through the second sub-discharging circuit includes: The first switch is opened and the second switch is closed, so that the fourth transistor is turned on by the first control voltage and the first voltage is discharged to the second voltage through the fourth transistor.

12. The method for operating a memory device according to claim 10, wherein: The second sub-discharging circuit includes the third transistor, the fifth transistor and a third switch connected to the control terminal of the fifth transistor; The step of discharging the first voltage to a second voltage through the second sub-discharging circuit includes: The first switch is opened and the third switch is closed to turn on the fifth transistor through a second control voltage, and the first voltage is discharged to the second voltage through the third transistor and the fifth transistor.

13. The method for operating a memory device according to claim 10, wherein: The second sub-discharging circuit comprises the third transistor, the second transistor and a capacitor; the first plate and the second plate of the capacitor are respectively connected to the control terminal of the second transistor and the ground voltage; The step of discharging the first voltage to a second voltage through the second sub-discharging circuit includes: The first switch is turned off, and the first voltage is discharged to the second voltage through the third transistor and the second transistor.

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