Memory circuit and operation method thereof

Abstract

A memory circuit and an operating method thereof, the memory circuit comprising: a memory array comprising a plurality of memory cells, the plurality of memory cells being disposed over a plurality of word lines and along a bit line; and a controller operatively coupled to the memory array and including an RC detector. The RC detector is configured to advance a timing of lowering a first tracking signal after a second tracking signal transitions to rise and before a third tracking signal transitions to rise. The first tracking signal is conducted through a first tracking wire, the second tracking signal is provided to be conducted through a second tracking wire, and the third tracking signal is conducted through the second tracking wire.

Description

Technical Field

[0001] The present disclosure relates to a memory circuit and a method for operating the memory circuit. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. Primarily, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array including a plurality of memory cells; and a controller operatively coupled to the memory array and including an RC detector. The RC detector is used to adjust the timing of a falling edge of a first tracking signal based on a rising edge of a second tracking signal and a rising edge of a third tracking signal.

[0004] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array including a plurality of memory cells, the plurality of memory cells being arranged above a plurality of word lines and along bit lines; and a controller operatively coupled to the memory array and including an RC detector. The RC detector is used to advance a timing at which a first tracking signal falls after a second tracking signal transitions to rise and before a third tracking signal transitions to rise. The first tracking signal is conducted through a first tracking connection, the second tracking signal is provided to be conducted through a second tracking connection, and the third tracking signal is conducted through the second tracking connection.

[0005] In another aspect of the present disclosure, a method of operating a memory circuit is disclosed. The method includes turning on a first transistor by a first tracking signal provided to be transmitted through a tracking word line, and turning on a second transistor by a second tracking signal transmitted through the tracking word line. The method includes advancing a timing of pulling down a voltage level present on a tracking bit line. The method includes turning off the second transistor by the second tracking signal transmitted through the tracking word line. The method includes generating an enable signal to cause a word line signal to fall in response to a voltage level on the tracking bit line falling to a threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1An example block diagram of a memory device including a memory controller for adjusting a pulse width of a word line signal according to some embodiments is shown;

[0008] Figure 2 FIG. 1 is a diagram illustrating a method according to some embodiments of the present invention. Figure 1 A schematic diagram of nominal memory cells and tracking cells of a memory device;

[0009] Figure 3 FIG. 1 is a diagram illustrating a method according to some embodiments of the present invention. Figure 1 A block diagram of the memory controller;

[0010] Figure 4 FIG. 1 is a diagram illustrating a method according to some embodiments of the present invention. Figure 1 Schematic diagram of the RC detector of the memory controller;

[0011] Figure 5 and Figure 6 According to some embodiments, Figure 1 The waveforms of various signals when the memory device is operated under high voltage / temperature conditions and low pressure / temperature conditions;

[0012] Figure 7 An example flow chart of a method for operating a memory device according to some embodiments is illustrated.

[0013]

Explanation of symbols

[0014] 100:Memory device or circuit

[0015] 105:Memory Controller

[0016] 120:Memory array

[0017] 125: Storage circuit or memory unit

[0018] 130: Tracking column

[0019] 135:Tracking Unit

[0020] 140: dummy unit

[0021] 145:Tracing the Word Line

[0022] 150: Tracing the Bit Line

[0023] 160: word line driver / controller

[0024] 170: Input / Output (I / O) Circuit

[0025] 310: Clock Generator

[0026] 311: Clock signal

[0027] 313: Clock pulse

[0028] 315: Tracking word line (TRKWL) signal

[0029] 317:TRKWL_RET signal

[0030] 319: Tracking bit line (TRKBL) signal

[0031] 320: Pulse generator

[0032] 330:RC Detector

[0033] 700: Method

[0034] 710: Operation

[0035] 720: Operation

[0036] 730: Operation

[0037] 740: Operation DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0039] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "top," "bottom," and the like may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0040] A static random access memory (SRAM) device is a type of volatile semiconductor memory that uses a bistable circuit that does not need to be refreshed to store data bits. An SRAM cell may be referred to as a bit cell or a memory cell because an SRAM cell stores one bit of information represented by the logic state of two cross-coupled inverters. A memory array includes a plurality of bit cells arranged in rows and columns. Each bit cell in the memory array typically includes a connection to a supply voltage and a reference voltage. Logic signals on the bit lines control reading from and writing to the bit cells, with word lines controlling the connection of the bit lines to the inverters. Word lines may be coupled to bit cells in rows of a memory array, with different word lines provided for different rows.

[0041] Each successive bit cell along a bit line or word line has a characteristic input capacitance, and each conductor leg between bit cells has a resistance, resulting in a signal propagation delay. The delay is longer for bit cells that are farther along the signal path than other bit cells, which begin at the source of memory addressing and control signals, such as the outputs of address decoding gates and wiring drivers coupled at the edge of the memory array. The delay affects the time required to access a bit cell and limits the maximum frequency at which the memory can operate. For example, the time it takes to access an SRAM cell for a read / write operation can be attributed to variations in several factors, including the relative position of the accessed bit cells within the SRAM array. Reliable estimates of SRAM timing characteristics are important to ensure consistency of system components and high system performance.

[0042] In this regard, various techniques have been proposed to provide timing tracking functionality for accurate and efficient monitoring of SRAM devices. Timing tracking enables determination of the time at which a bit cell ends a read or write operation. For example, a tracking word line is typically modified or otherwise recruited from an existing word line of a memory array to track or mimic the propagation time of a signal transmitted through a normal word line of the memory array, and a tracking bit line that is typically modified or otherwise recruited from a memory array to track or mimic the propagation time of a signal transmitted through a normal bit line of the memory array may not accurately track the propagation time. The signal transmitted through the tracking bit line is typically responsive to the signal transmitted through the tracking word line.

[0043] With the trend toward even shrinking feature sizes (e.g., smaller and / or thinner conductor legs), RC delays in memory arrays are thus increased, which disadvantageously slows down signals traveling through tracking word lines. Again, signals traveling through tracking bit lines cannot accurately track propagation times. Such problems may become more pronounced when memory devices are operated under certain conditions (e.g., at high voltages and / or high temperatures). Thus, existing timing tracking techniques or corresponding circuits for SRAM devices have not been entirely satisfactory in certain aspects.

[0044] The present disclosure provides various embodiments of a memory device including a controller and at least one memory array operatively coupled to each other. In various embodiments, the controller may adjust the timing of a tracking bit line signal based on an operating condition of the memory device. For example, the controller may include an RC detector that may advance the timing of a tracking signal (sometimes referred to as a "TRKBL signal") transmitted through a tracking bit line to fall based on the operating condition of the memory device. In some embodiments, the RC detector may include: a first transistor gated by a signal (sometimes referred to as a "TRKWL signal") that is provided to be transmitted through a tracking word line; and a second transistor gated by another signal (sometimes referred to as a "TRKWL_RET signal") that is transmitted through the tracking word line and returned from the tracking word line. In addition, the first transistor and the second transistor are connected in series to the tracking bit line, wherein a voltage at one of the source / drain terminals of the first transistor is maintained at a nearly constant level. Under certain operating conditions (e.g., high voltage and / or high temperature), the TRKWL signal can cause the first transistor to conduct a higher current, thereby advancing the timing of pulling down the TRKBL signal, for example, before the TRKWL_RET signal returns from the tracking word line. Thus, the RC delay faced by conventional memory devices when operating under high voltage / temperature conditions can be compensated. In other words, even in the case of RC delay, the advanced timing provided by the presently disclosed RC detector can compensate for this delay.

[0045] Figure 1 FIG. 1 is a block diagram of a memory device or circuit 100 according to various embodiments. Figure 1 The memory device 100 in FIG. 1 is simplified for illustrative purposes, and thus it should be understood that the memory device 100 may include any of a variety of other elements while remaining within the scope of the present disclosure.

[0046] As shown, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 configured in a two-dimensional array or a three-dimensional array. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). According to the electrical signals passing through the word lines WL and the bit lines BL, the memory controller 105 may write data to the memory array 120 or read data from the memory array 120. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the WL signal transmitted through the corresponding confirmation word line WL based on the physical distance between the confirmation word line and the memory controller 105, which will be discussed in further detail below. In other embodiments, the memory device 100 includes a pulse width of a WL signal transmitted through the confirmation word line WL compared to the physical distance between the confirmation word line and the memory controller 105. Figure 1 More, fewer or different elements may be shown.

[0047] The memory array 120 is a hardware element for storing data. In one embodiment, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 includes word lines WL0...WLJ each extending in a first direction (e.g., X direction), and bit lines BL0...BLK each extending in a second direction (e.g., Y direction). In some embodiments, the memory array 120 may be referred to as having a plurality of columns and a plurality of rows, wherein each of the columns corresponds to a respective one of the bit lines BL, and each of the rows corresponds to a respective one of the word lines WL. That is, the memory array 120 may include K columns and J rows of memory cells 125. The word lines WL and the bit lines BL may each be a conductive metal or a conductive rail. Each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and may be operated according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL, BLB of one or more memory cells 125 coupled to a group of memory cells 125, and these memory cells 125 are arranged along a second direction (e.g., the Y direction). The bit lines BL, BLB can receive and / or provide different signals. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is embodied as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array 120 includes additional wiring (e.g., selection wiring, reference wiring, reference control wiring, power rails, etc.).

[0048] In addition to memory cells 125 for storing data (which are sometimes referred to as nominal memory cells), memory array 120 may include one or more tracking columns 130 disposed adjacent to or integrated into memory array 120, such as Figure 1 . The tracking columns 130 may each include a plurality of tracking cells 135 and a plurality of dummy cells 140. The tracking cells 135 and the dummy cells 140 may be configured in any respective number, wherein the total number of tracking cells 135 and the dummy cells 140 is equal to the number of rows (J), while remaining within the scope of the present disclosure. For example, the number of tracking cells 135 may be selected to simulate a worst-case condition in a write and / or read operation.

[0049] In addition, the tracking column 130 may include at least one tracking word line 145 and at least one tracking bit line 150, wherein the tracking word line 145 is connected to each of the tracking cells 135, and the tracking bit line 150 is connected to each of the tracking cells 135 and the dummy cells 140. The tracking word line 145 and the tracking bit line 150 are used to respectively conduct the TRKWL_RET signal and the TRKBL signal mentioned above, which will be discussed in further detail below. By conducting the TRKWL_RET and TRKBL signals, the tracking word line 145 and the tracking bit line 150 can respectively emulate the signal routing delay in the functional memory array (e.g., 120) of the read or write operation at the far edge.

[0050] For example, tracking word line 145 may include a first horizontal portion extending along a row of memory array 120, a second horizontal portion also extending along a row of memory array 120, and a vertical portion extending along a column of memory array 120. The length of each of the first and second horizontal portions of tracking word line 145 may be approximately equal to the width of memory array 120 (e.g., based on the width of memory array 120). Figure 1 The length of the vertical portion of the tracking word line 145 may be approximately equal to the height of the memory array (e.g., according to the orientation of the memory array in FIG. 1 ), and the length of the vertical portion of the tracking word line 145 may be approximately equal to the height of the memory array (e.g., according to the orientation of the memory array in FIG. 1 ). Figure 1 The orientation of the memory array in the memory controller 105 is the distance from the farthest tracking unit 135). For example, in Figure 1, a first portion of tracking word line 145 may extend (e.g., physically) from memory controller 105 to a middle portion of memory array 120, and a second portion of tracking word line 145 may return (e.g., physically) from a midpoint of memory array 120 to memory controller 105. Thus, the sum of the lengths of the first and second portions of tracking word line 145 may be equal to the length of each of word lines WL, such that metal wiring delays for accessing a cell at the upper right corner of memory array 120, such as delays from a signal entry at the lower left portion that propagates horizontally and vertically over a path distance equal to the length of the path from one corner to the diagonal corner, are emulated.

[0051] Generally, the tracking cells 135 do not function as the (nominal) memory cells 125 function in terms of storing data and supporting read / write operations. Specifically, the tracking cells 135 may initially be a subset of the nominal memory cells 125, but be recruited or repurposed for timing tracking. For example, the tracking cells 135 are bit cells having fixed logic values ​​that are configured and coupled to each other so as to respond in a predictable manner when addressed by a test or tracking signal. A non-limiting implementation of the tracking cells 135, along with a non-limiting implementation of the nominal memory cells 125, is described below in Figure 2 . The dummy cell 140 allows the capacitive and resistive environment to be closely matched for accurate modeling of the environment of the nominal memory cell. Typically the traced bit line has a propagation delay that determines the signal carried, i.e., two factors of the series resistance and parallel capacitance. The dummy cell 140 has a real capacitive load and emulates the capacitance of the bit line BL coupled to the nominal memory cell. If the dummy cell 140 is not provided, the length of the traced bit line will effectively appear shorter than the nominal bit line BL that the traced bit line is intended to emulate, which will have reduced resistance and capacitance and may cause the trace circuit to determine that a read or write operation is prematurely terminated.

[0052] The memory controller 105 is a hardware component that controls various operations of the memory array 120, such as reading data bits from the memory cells 125, writing data bits to the memory cells 125, implementing a tracking scheme for the respective timings of the read / write operations, adjusting the tracking timings of the read / write operations, etc. In various embodiments, the memory controller 105 may include a plurality of circuits, each of which may be embodied as a logic circuit, an analog circuit, or a combination thereof to perform such operations.

[0053] For example, the memory controller 105 may include a clock generator, a pulse generator, and an RC detector. The clock generator may receive or generate a clock signal, and provide the clock signal of the pulse generator to generate a plurality of clock pulses. The pulse generator may rely on the clock pulse to control (e.g., pull up and / or pull down) a plurality of control signals (e.g., TRKWL signal, TRIG signal, SAE signal). The RC detector may provide the TRKWL signal to be transmitted through the tracking word line 145 and receive the TRKWL_RET signal transmitted through the tracking word line 145. Based on the operating conditions of the memory device 100 (e.g., high voltage conditions or low voltage conditions), the RC detector may selectively adjust the transition timing of the TRKBL signal. The selectively adjusted TRKBL signal may be further received by the pulse generator, which causes the clock pulse to be adjusted. Such adjusted clock pulses may be used to adjust the transition timing of the TRIG signal and / or the SAE signal, which may advantageously read and / or write the margin of the memory device 100. Details of these circuit elements of memory controller 105 will be described in detail below. Figure 3 Further discussion.

[0054] In some embodiments, the memory device 100 may further include various other circuit elements, such as a word line driver / controller 160, an input / output (I / O) circuit 170, etc., each of which may be embodied as a logic circuit, an analog circuit, or a combination thereof. The word line driver 160 may provide a voltage or current that is transmitted through one or more word lines WL of the memory array 120. This voltage / current may sometimes be referred to as a WL signal. The I / O circuit 170 may sense a voltage or current that is transmitted through one or more bit lines BL of the memory array 120. For example, the I / O circuit 170 may include a plurality of sense amplifiers, each of which is operatively coupled to one or more of the bit lines BL within the memory array 120. These sense amplifiers may be activated by a sense amplifier enable (SAE) signal, which is pulled up by a TRIG (trigger) signal. After the SAE signal is pulled up to a certain voltage level, the WL signal may be pulled low. In other words, the memory controller 105 can utilize the adjusted timing of the SAE signal to adjust the pulse width of the WL signal based on the operating conditions of the memory device 100. Advantageously, various performances of the memory device 100 (eg, power consumption, RC delay, etc.) can be improved.

[0055] Figure 2 Schematic diagrams illustrating example implementations of nominal memory cells 125 and tracking cells 135 according to various embodiments. In general, tracking cells 135 may have the same structure as nominal memory cells 125, but may be operationally configured differently. Figure 2In FIG. 1 , the nominal memory cell 125 is implemented as a six-transistor (6T) static random access memory (SRAM) cell consisting of six transistors, and thus the tracking cell 135 may also have six transistors.

[0056] like Figure 2 As shown in FIG. 1 , a nominal memory cell 125 includes a pair of access transistors PG1 and PG2 biased by a word line WL and providing access to a first and second cross-coupled inverter, respectively. The "PG" in PG1 and PG2 may be referred to as a "pass gate" because when the WL signal at the gate terminal of transistor PG becomes true, PG passes the bit line signal to the node of the cross-coupled inverters. The first inverter includes a pull-up PMOS transistor PU1 and a pull-down NMOS transistor PD1, and the second inverter includes a pull-up PMOS transistor PU2 and a pull-down NMOS transistor PD2. Transistors PG1 and PG2 are coupled to a first bit line BL ("bit line") and a second bit line BLB ("bit line bar" or bit line complement), respectively. This configuration is referred to as a six-transistor (6T) configuration. During standby mode, WL has not yet been asserted, and access transistors PG1 and PG2 disconnect the memory cell 125 from the bit lines BL and BLB. The cross-coupled inverters are coupled between power supplies (VDD and VSS) and reinforce each other to maintain one of two possible logic states, where the stored data bit is at one of the nodes (node ​​Q) between the inverters and the complement of the bit is at the other node (node ​​QB) between the inverters. For a read operation, BL and BLB are precharged to a high logic state and WL is asserted. The stored data bit at node Q is transferred to BL and the data bit at node QB is transferred to BLB. For a write operation, when WL is asserted, the value to be written is provided at BL and the complement of the value is provided at BLB. Although a 6T SRAM cell is described herein, other types of memory cells may be used, including memory types other than SRAM and other types of SRAM configurations other than 6T, such as an eight-transistor (8T) configuration or a ten-transistor (10T) configuration.

[0057] In such a memory configuration of the nominal memory cells 125, one or more of the nominal memory cells 125 may alternatively be recruited or pre-configured as a tracking cell 135 to execute a tracking scheme. The tracking scheme may generally follow the following steps: (1) the transistors in at least one storage node of the tracking cell 135 are maintained in a conductive (or non-conductive) condition characteristic of their condition at a predetermined logic state (e.g., forced to a condition representing a logic high), the transistors being switched to an opposite conductive (or non-conductive) condition by a TRKBL signal conducted through a route that otherwise serves as the tracking bit line 150 in the memory array 120; (2) the word lines are similarly decoupled from the normal (nominal) cell array and coupled to a conductive route (originally used as a bit line in an adjacent nominal cell), such as the tracking word line 145 to carry the TRKWL signal; and (3) when the TRKWL signal turns on a transistor (such as the PG transistor and the PD transistor of the tracking cell 135 in the SRAM example), a current from the tracking bit line 150 to VSS is generated and can be detected to stop and / or read a timer that was started when the TRKBL signal was generated. In this way, representative time delays to and from the tracking unit 135 provide a basis for inferring delays along the path, such as measurements in an SRAM. The tracking scheme and corresponding configurations as described above are also applicable to 8T and 10T configurations.

[0058] Still viewing Figure 2 , tracking cell 135 is substantially similar to nominal memory cell 125, but has modifications to certain elements applied for tracking functionality. For example, tracking cell 135 may include two NMOS PG transistors (PG3 and PG4), two PMOS PU transistors (PU3 and PU4), and two NMOS PD transistors (PD3 and PD4). The PG4 transistor is coupled to a floating node, as represented by FLOAT, and has a gate coupled to a corresponding nominal word line WL, which may extend from memory array 120 (e.g., coupled to one or more of memory cells 125). Word line WL is not accessed due to the floating node being disabled. In Figure 2 In the illustrated example of FIG. 1 , the PU-PD pair on the right side (PU4 and PD4) do not have drain terminals connected to each other. This disconnection prevents current from flowing from VDD (the node is tied high to force the state of the inverter formed by the PU-PD pair on the left side, i.e., PU3 and PD3) to the nominal bit line BL (of the memory array 120) through the PG4 transistor when the nominal word line WL has a logic high state. In other embodiments, the drain terminals of the PU-PD pair on the right side (PU4 and PD4) can be connected to each other.

[0059] In addition, the PG3 transistor has a gate terminal connected to the tracking word line 145 to receive the TRKWL signal, and a drain terminal connected to the tracking bit line 150 to present the TRKBL signal. Generally speaking, when a tracking scheme is implemented, the tracking bit line 150 may first be precharged to a logic high voltage value, such as VDD, via a control transistor (not shown) having its gate connected to the tracking word line 145. Next, TRKWL conducted through the tracking word line 145 may be pulled up (to a high logic state), which may turn off the control transistor (when implemented as a PMOS transistor), thereby decoupling the tracking bit line 150 from VDD. As a result, the PG3 transistor is turned on, and the PD3 transistor is maintained in an "on" state by connecting its gate to VDD, thereby allowing current to flow from the tracking bit line 150 to ground (VSS). Therefore, the overvoltage at the tracking bit line 150 begins to discharge to ground, and the pulled-down tracking bit line 150 is coupled (eg, fed back to the TRKBL signal) to the memory controller 105 ( Figure 1 ). The pulled low TRKBL signal arriving at the memory controller 105 can be measured for timing tracking, since the read / write operation emulated in the functional SRAM (e.g., the nominal memory cell 125) has been completed. In addition, the memory controller 105 can use the pulled low TRKBL signal to stimulate (e.g., pull up) the TRIG signal, which in turn pulls up the SAE signal. The pulled up SAE signal can cause the WL signal to be pulled low, which determines the pulse width of the WL signal.

[0060] Figure 3 FIG. 1 shows a memory controller 105 according to various embodiments. Figure 1 ), the memory controller 105 can adjust the timing of the falling edge of the TRKBL signal based on the operating conditions of the memory device 100. Therefore, the memory controller 105 can use the adjusted timing of the TRKBL signal to shorten the pulse width of the WL signal transmitted through the confirmed word line WL. Figure 3 , the memory controller 105 is simplified for illustrative purposes, and thus it should be understood that the memory controller 105 may include any of a variety of other elements while remaining within the scope of the present disclosure.

[0061] As shown in the figure, the memory controller 105 includes a clock generator 310, a pulse generator 320 and an RC detector 330. The clock generator 310 can receive a clock signal 311 and provide a plurality of clock pulses 313 based on the clock signal 311. In some embodiments, at least one transition edge of the clock pulse 313 can follow the clock signal 311. For example, when the clock signal 311 rises, the clock pulse 313 also rises. In other words, the rising edge of the clock pulse 313 follows the rising edge of the clock signal 311. The clock generator 310 can provide the clock pulse 313 to the pulse generator 320. In addition, the clock generator 310 can provide the clock pulse 313 to drive other circuit elements of the memory device 100, such as the word line driver 160 ( Figure 1 ).

[0062] After receiving the clock pulse 313, the pulse generator 320 may generate a tracking word line (TRKWL) signal 315 that is transmitted through the tracking word line 145 and further provide the TRKWL signal 315 to the RC detector 330. The TRKWL signal 315 may be used to turn on or otherwise activate the tracking unit 135. In some embodiments, at least one transition edge of the TRKWL signal 315 may follow the clock pulse 313. For example, when the clock pulse 313 is pulled up, the TRKWL signal 315 is also pulled up. In other words, the rising edge of the TRKWL signal 315 follows the rising edge of the clock pulse 313. In addition, the TRKWL signal 315 is provided by the RC detector 330 to be transmitted through the (first and second) horizontal portions of the tracking word line 145. In other words, at Figure 1 In the illustrative embodiment of FIG. 1 , TRKWL signal 315 is fed into a first horizontal portion of tracking word line 145 from its start, which is approximately aligned with one edge of memory array 120. TRKWL signal 315 then flows through the first and second horizontal portions of tracking word line 145 and returns as TRKWL_RET signal 317. In some embodiments, TRKWL_RET signal 317 may further flow through a vertical portion of tracking word line 145 to activate (e.g., turn on) tracking cell 135 ( Figure 1 ). After the tracking unit 135 is activated, the tracking bit line (TRKBL) signal 319 conducted through the tracking bit line 150 that has been precharged to a high logic state (e.g., VDD) may begin to pull low. According to various embodiments of the present disclosure, the timing of the TRKBL signal 319 being pulled low to a certain voltage level may correspond to the end timing of the corresponding tracking scheme.

[0063] As will be discussed below, the RC detector 330 includes at least two transistors gated by the TRKWL signal 315 and the TRKWL_RET signal 317, respectively. In addition, these two transistors are connected in series to each other and are further coupled to the tracking bit line 150. Due to the different timing of the rising edges of the TRKWL signal 315 and the TRKWL_RET signal 317, which can sometimes be used as an index for monitoring the operating condition of the memory device 100, these two transistors may not be turned on at the same time. In other words, a time window may be present, for example, after the transistor gated by the TRKWL signal 315 is turned on and before the transistor gated by the TRKWL_RET signal 317 is turned on. In various embodiments of the present disclosure, the RC detector 330 may utilize this time window to advance the pull-down of the TRKBL signal 319 after detecting or otherwise identifying a certain operating condition of the memory device 100.

[0064] Figure 4 A schematic diagram of a portion of the RC detector 330 and the pulse generator 320 is shown according to various embodiments. Figure 4 The schematic diagram of is simplified for illustrative purposes, and thus it should be understood that RC detector 330 and pulse generator 320 may each include any of a variety of other elements while remaining within the scope of the present disclosure.

[0065] As shown, the RC detector 330 includes transistors M1, M2, and M3 connected in series to each other, and further coupled between ground and the tracking bit line 150. The pulse generator 320 includes transistors M4 and M5 configured as inverters. In some embodiments, the transistors M1, M2, and M4 are each implemented as an n-type metal-oxide-semiconductor field-effect-transistor (MOSFET), and the transistors M3 and M5 are each implemented as a p-type MOSFET. However, it should be understood that the transistors M1 to M5 can each be embodied as any of a variety of other transistors while remaining within the scope of the present disclosure.

[0066] Specifically, transistor M1 is configured as a diode connection, for example, where the gate terminal and the drain terminal are connected to each other, and its source terminal is connected to ground. Transistor M2 is used to be gated by TRKWL signal 315, for example, by coupling the gate terminal to the first horizontal portion of the tracking word line 145. Transistor M2 has its drain terminal and source terminal connected to transistor M3 and transistor M2, respectively. Transistor M3 is used to be gated by TRKWL_RET signal 317, for example, by coupling the gate terminal to the second horizontal portion of the tracking word line 145. Transistor M3 has its drain terminal and source terminal connected to transistor M2 and tracking bit line 150, respectively. Transistors M4 and M5 configured as inverters have gates that are normally coupled to tracking bit line 150 (to receive TRKBL signal 319) and drain terminals that are connected to the control pin to output the TRIG signal. In other words, the inverter formed by transistors M4 and M5 can logically invert the TRKBL signal 319 to the TRIG signal.

[0067] To advance the pull-down of the TRKBL signal, the operation of the RC detector 330 is briefly illustrated as follows. For example, the common node "A" connecting transistors M1 and M2 can be maintained at a substantially constant level via the diode-connected transistor M1. The voltage level present at node A is approximately the same as the threshold voltage of transistor M1 (e.g., approximately 400 millivolts). Therefore, when the TRKWL signal has a logic high state and is at a higher voltage level (e.g., when the memory device 100 is operating under high voltage / temperature conditions), transistor M2 can be turned on to conduct more current to advance the timing of pulling the TRKBL signal low. This can occur before the TRKWL_RET signal returns from the tracking word line 145 (i.e., remains in a logic low state). In other words, when transistor M3 pulls the TRKBL signal low, transistor M3 remains turned on until the TRKWL_RET signal returns to a logic high state. Therefore, it can be understood that the TRKBL signal can be pulled low before the TRKWL_RET signal returns, which advantageously solves the RC delay problem commonly faced by existing memory devices. In some embodiments, such advantages can be better understood when the memory device 100 is under high voltage / temperature conditions.

[0068] Figure 5 and Figure 6 Some of these signals generated or adjusted by the RC detector 330 are shown in accordance with various embodiments of the present disclosure. For example, Figure 5 FIG. 3 shows waveforms of the TRKWL signal 315 , the TRKWL_RET signal 317 , the TRKBL signal 319 , and the TRIG signal when the memory device operates under the first condition, and FIG. Figure 6The waveforms of these signals are shown when the memory device operates under a second condition. In some embodiments, the first condition may correspond to a high voltage and / or high temperature operating condition (e.g., where the TRKWL signal is set to a higher voltage level), and the second condition may correspond to a low voltage and / or low temperature operating condition (e.g., where the TRKWL signal is set to a lower voltage level).

[0069] First see Figure 5 , when the TRKWL signal is set and pulled high, transistor M2 is activated. Assuming that the voltage at node A is maintained at a substantially constant level via diode-connected transistor M1 and the TRKWL signal is pulled up to a higher voltage level (e.g., above about 0.7 volts), transistor M2 conducts a higher current to pull the TRKBL signal low in advance. In comparison, the waveform of TRKBL presented by a memory device that does not include the disclosed RC detector 330 is shown as a dotted line, while the waveform of the TRKBL signal adjusted by the RC detector 330 is shown as a solid line. As shown, the timing of the start of the TRKBL signal falling is advanced. Furthermore, when compared to the TRIG signal (dotted line) generated by a conventional memory device, the timing of the TRIG signal rising can be advanced based on adjusting the TRKBL signal (solid line). Next, refer to Figure 6 , the TRKWL signal is pulled up to a lower voltage level (e.g., below about 0.6 volts), transistor M2 still conducts current, but it may not pull the TRKBL signal low in advance. Therefore, the timing of the falling edge of TRKBL presented by the RC detector 330 and the conventional memory device, respectively, may be similar, which in turn makes the timing of the rising edge of the respective TRIG signal similar.

[0070] Figure 7 1 is a flow chart illustrating an example method 700 for adjusting a pulse width of a WL signal transmitted through a validation word line WL based on an operating condition of a corresponding memory device according to various embodiments of the present disclosure. The method 700 may be executed to operate the memory device 100 ( Figure 1 ) and therefore, in the following discussion of the operations of method 700, may be reused Figures 1 to 6 Reference numbers used in the method 700 are noted. Note that the method 700 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be performed in the method 700. Figure 7 The method 700 is provided before, during, and after, and some other operations may be described herein only briefly.

[0071] The method 700 begins with operation 710 of turning on a first transistor of the RC detector by a first tracking signal provided to be conducted via a tracking word line, and turning on a second transistor of the RC detector by a second tracking signal conducted via the tracking word line. For example, the first transistor and the second transistor may be the transistors shown in FIG. Figure 4145. In some embodiments, transistor M2 is gated by a TRKWL signal that is provided to flow through at least the first and second horizontal portions of tracking word line 145, and transistor M3 is gated by a TRKWL_RET signal that is a signal that is conducted through the first and second horizontal portions of tracking word line 145. Thus, TRKWL_RET may mimic the RC delay of a nominal word line. In other words, the TRKWL_RET signal may follow the TRKWL signal with a time offset / window (e.g., delay). This time window may vary depending on the operating conditions of memory device 100. For example, this time window becomes larger when memory device 100 operates at high voltage / temperature conditions, and becomes smaller when memory device 100 operates at low voltage / temperature conditions.

[0072] The method 700 proceeds to operation 720 to advance the timing of pulling down the voltage level present on the tracking bit line. Continuing with the above example, after being turned on by pulling up the TRKWL signal, the (first) transistor M2 may begin pulling down the voltage present on the tracking bit line 150 (i.e., the TRKBL signal), and does not need to wait until the TRKWL_RET signal returns from the tracking word line 145. In addition, before the TRKWL_RET signal returns (has a logic high state), the (second) transistor M3 may remain enabled to enable the (first) transistor M2 to pull down the TRKBL signal. In other words, the timing of the TRKBL signal falling may be advantageously advanced.

[0073] The method 700 proceeds to operation 730 where the second transistor is turned off by the second tracking signal conducted through the tracking word line. Still by the same example, after the TRKWL_RET signal is transmitted back from the horizontal portion of the tracking word line 145 (having a logic high state), the (second) transistor M3 can be turned off. Thus, the conduction path extending from the tracking bit line through the transistors M3 and M2 and to ground is disconnected, thereby stopping the discontinuation of the TRKBL signal.

[0074] The method 700 proceeds to the following operation 740: In response to the voltage level on the tracking bit line falling to the threshold value, an enable signal is generated to cause the word line signal to fall. Still by the same example, after the TRKBL signal falls to a certain voltage level, the pulse generator 320 can stimulate the TRIG signal with a logic high state, thereby causing the SAE signal to rise. After the SAE signal rises to a certain voltage level, the WL signal can start to fall. Therefore, the pulse width of the WL signal can be adjusted.

[0075] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array including a plurality of memory cells; and a controller operatively coupled to the memory array and including an RC detector. The RC detector is used to adjust the timing of a falling edge of a first tracking signal based on a rising edge of a second tracking signal and a rising edge of a third tracking signal.

[0076] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array including a plurality of memory cells, the plurality of memory cells being arranged over a plurality of lines and along a bit line; and a controller operatively coupled to the memory array and including an RC detector. The RC detector is used to advance a timing of a first tracking signal falling after a second tracking signal transitions to rising and before a third tracking signal transitions to rising. The first tracking signal is conducted through a first tracking connection, the second tracking signal is provided to be conducted through a second tracking connection, and the third tracking signal is conducted through the second tracking connection.

[0077] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes turning on a first transistor by a first tracking signal provided to be transmitted through a tracking word line, and turning on a second transistor by a second tracking signal transmitted through the tracking word line. The method includes advancing a timing of pulling down a voltage level present on a tracking bit line. The method includes turning off the second transistor by the second tracking signal transmitted through the tracking word line. The method includes generating an enable signal to cause a word line signal to drop in response to the voltage level on the tracking bit line dropping to a threshold value.

[0078] In some embodiments, the first tracking signal is conducted through the first tracking.

[0079] In some embodiments, the first tracing signal is conducted through a first tracing wire, the second tracing signal is provided to be conducted through a second tracing wire, and the third tracing signal is conducted through the second tracing wire.

[0080] In some embodiments, the second tracking line has a first portion extending from a first edge of the memory array to a midpoint of the memory array along a first lateral direction and a second portion extending from the midpoint of the memory array to the first edge of the memory array along the first lateral direction, and the first tracking line extends from the second edge of the memory array to a third edge of the memory array along a second lateral direction perpendicular to the first lateral direction.

[0081] In some embodiments, a plurality of memory cells are arranged above a plurality of word lines and along a bit line, and wherein the second tracking connection has a first portion and a second portion, the first portion and the second portion each having a length equal to half the length of the plurality of word lines, and the first tracking connection has a length approximately equal to the length of the bit line.

[0082] In some embodiments, the RC detector includes: a first transistor connected via a diode; a second transistor; and a third transistor. The first transistor to the third transistor are serially coupled to each other.

[0083] In some embodiments, the second transistor is gated by a second tracking signal, and the third transistor is gated by a third tracking signal.

[0084] In some embodiments, the second transistor and the third transistor have opposite conductivity types.

[0085] In some embodiments, the first transistor has one of its multiple source / drain terminals coupled to ground, and the third transistor has one of its multiple source / drain terminals coupled to the first tracking signal.

[0086] In some embodiments, the diode-connected first transistor is used to maintain a voltage level at the first source / drain terminal of the second transistor that is approximately equal to a threshold voltage of the first transistor, thereby advancing the timing of the falling edge of the first tracking signal when the memory array operates under a high voltage condition.

[0087] In some embodiments, the second source / drain terminal of the second transistor is connected to the first source / drain terminal of the third transistor, wherein the second source / drain terminal of the third transistor is used to receive the first tracking signal.

[0088] In some embodiments, the second tracking wiring is used to emulate each of the plurality of word lines, and the first tracking wiring is used to emulate the bit line.

[0089] In some embodiments, the RC detector includes: a first transistor connected via a diode; a second transistor; and a third transistor. The first transistor to the third transistor are serially coupled to each other.

[0090] In some embodiments, the second transistor is gated by a second tracking signal, and the third transistor is gated by a third tracking signal.

[0091] In some embodiments, the second transistor and the third transistor have opposite conductivity types.

[0092] In some embodiments, the first transistor has one of its multiple source / drain terminals coupled to ground, and the third transistor has one of its multiple source / drain terminals coupled to the first tracking signal.

[0093] In some embodiments, the diode-connected first transistor is configured to pull down a voltage level at the first source / drain terminal of the second transistor closer to ground based on an operating condition of the memory array, thereby advancing the timing of a falling edge of the first tracking signal.

[0094] In some embodiments, the second source / drain terminal of the second transistor is connected to the first source / drain terminal of the third transistor, wherein the second source / drain terminal of the third transistor is used to receive the first tracking signal.

[0095] In some embodiments, the method further comprises the following steps: in response to the first tracking signal having a certain voltage level, turning on the first transistor, wherein the drain terminal of the first transistor is coupled to the tracking bit line maintained at a substantially constant voltage level and the source terminal thereof, so as to advance the voltage level on the tracking bit line before the second transistor is turned off.

[0096] As used herein, the terms "about" and "approximately" generally indicate a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may indicate a value of a given quantity that varies within 10% to 30% of the value (e.g., within +10%, ±20%, or ±30% of the value).

[0097] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, characterized in that: Include: a memory array comprising a plurality of memory cells; and a controller operatively coupled to the memory array and comprising an RC detector; The RC detector is used to adjust a timing of a falling edge of a first tracking signal based on a rising edge of a second tracking signal and a rising edge of a third tracking signal.

2. The memory circuit according to claim 1, wherein: The first tracking signal is conducted through a first tracking connection, the second tracking signal is provided to be conducted through a second tracking connection, and the third tracking signal is conducted through the second tracking connection.

3. The memory circuit according to claim 2, wherein: The second tracking line has a first portion extending from a first edge of the memory array to a midpoint of the memory array along a first lateral direction and a second portion extending from the midpoint of the memory array to the first edge of the memory array along the first lateral direction, and the first tracking line extends from a second edge of the memory array to a third edge of the memory array along a second lateral direction perpendicular to the first lateral direction.

4. The memory circuit according to claim 2, wherein: The plurality of memory cells are arranged above a plurality of word lines and along a bit line, and the second tracking connection has a first portion and a second portion, each of the first portion and the second portion having a length equal to half a length of the plurality of word lines, and the first tracking connection has a length approximately equal to a length of the bit line.

5. A memory circuit, characterized in that: Include: a memory array comprising a plurality of memory cells arranged above a plurality of word lines and along a bit line; and a controller operatively coupled to the memory array and comprising an RC detector; wherein the RC detector is used to advance a timing of a first tracking signal falling after a second tracking signal transitions to a rising state and before a third tracking signal transitions to a rising state; The first tracking signal is conducted through a first tracking connection, the second tracking signal is provided to be conducted through a second tracking connection, and the third tracking signal is conducted through the second tracking connection.

6. The memory circuit according to claim 5, wherein: The RC detector includes: a first transistor connected via a diode; a second transistor; and a third transistor; The first transistor to the third transistor are coupled to each other in series.

7. The memory circuit according to claim 6, wherein: The first transistor has one of its multiple source / drain terminals coupled to the ground, and the third transistor has one of its multiple source / drain terminals coupled to the first tracking signal.

8. The memory circuit according to claim 6, wherein: The diode-connected first transistor is used to pull down a voltage level at a first source / drain terminal of the second transistor closer to ground based on an operating condition of the memory array, thereby advancing the timing of the falling edge of the first tracking signal.

9. A method for operating a memory circuit, characterized in that: The following steps are involved: A first transistor is turned on by a first tracking signal provided to conduct through a tracking word line, and a second transistor is turned on by a second tracking signal conducted through the tracking word line; Advancing a timing of pulling down a voltage level present on a tracking bit line; turning off the second transistor by the second tracking signal conducted through the tracking word line; and In response to the voltage level on the tracking bit line falling to a threshold value, an enable signal is generated to cause a word line signal to fall.

10. The method according to claim 9, characterized in that Further comprising the following steps: In response to the first tracking signal having a certain voltage level, the first transistor is turned on, wherein the drain terminal is coupled to the tracking bit line maintained at a substantially constant voltage level and the source terminal is coupled to advance the voltage level on the tracking bit line before the second transistor is turned off.

Images