Method for trimming eflash parameters

Abstract

The application provides a trimming method of eFlash parameters, comprising the following steps: S1: collecting a vector set of initial trimming values, a vector set of high-voltage start-up modes of built-in self-test and a vector set of erase and write operation modes to form a file in HEX format; S2: transmitting a built-in self-test instruction set by using the file in HEX format; S3: starting high-voltage of built-in self-test, and testing analog parameters in a default state by a parameter test module; S4: correcting a trimming value of an SRAM address; S5: starting high-voltage of built-in self-test, and measuring analog parameters corresponding to the SRAM address by the parameter test module; S6: repeating S4-S5 to complete measurement of analog parameters of all SRAM addresses, and if a difference between a measured value and a corresponding trimming value is out of a preset range, the measured value of the address is erased, and the trimming value is written into the address.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for adjusting eFlash parameters. Background Technology

[0002] During the manufacturing process of eFlash, due to the inherent variability in its manufacturing process, the consistency of key parameters cannot be guaranteed. Therefore, during eFlash manufacturing, multiple ranges are typically designed for each key parameter. Then, during subsequent eFlash testing, the range closest to the target parameter is determined from these multiple ranges and adjusted accordingly. This adjustment is crucial, directly impacting the product's basic functionality, yield, and reliability. The adjustment of eFlash parameters primarily involves analog parameters. Taking NORD eFlash as an example, there are more than ten analog adjustment items, such as word line erase voltage VWLE, control gate erase voltage VCGE, bit line write voltage VBLP, control gate write low voltage VCGLP, control gate write high voltage VCGHP, word line read voltage VWLR, control gate read voltage VCGR, memory cell reference current RCELL, bandgap reference voltage VREF, low dropout linear regulator output voltage VLDO, and byte write operation current IDP, among other analog parameters.

[0003] The existing eFlash parameter tuning method includes the following steps: Step S1: Set the initial value of the trim bit. Step S2: Load test vector set 1 to load the initial trim value. Step S3: Configure the parameter test (PMU) module. Step S4: Load test vector set 2 to enter the BIST (Built In Self Test) high-voltage on-state mode. Step S5: Load test vector set 3 to enter erase and write operation modes. Step S6: The PMU performs analog measurements. Step S7: Load test vector set 4 to exit test mode. Step S8: Change the value of the trim bit, and repeat steps S2 to S7 until all parameters are tuned.

[0004] However, existing technologies load vector sets too many times, and each reloading wastes a lot of time. Summary of the Invention

[0005] The purpose of this invention is to provide a method for adjusting eFlash parameters, which can reduce the adjustment time.

[0006] To achieve the above objectives, the present invention provides a method for adjusting eFlash parameters, comprising:

[0007] Step S1: Combine the vector set of the adjusted initial values, the vector set of the built-in self-test high voltage on mode, and the vector set of the erase and write operation modes to form a HEX format file.

[0008] Step S2: Use HEX format files to transmit the built-in self-test instruction set to achieve the initial value setting of the adjustment, the high voltage activation of the built-in self-test, and the erase and write operations.

[0009] Step S3: Enable the built-in self-test high voltage and test the simulated parameters in the default state using the parameter test module;

[0010] Step S4: Correct the adjustment value of the SRAM address;

[0011] Step S5: Activate the built-in self-test high voltage and use the parameter test module to measure the analog parameters corresponding to the SRAM address.

[0012] Step S6: Repeat steps S4 to S5 to complete the measurement of the analog parameters of all SRAM addresses. If the difference between the measured value and the corresponding adjustment value is outside the preset range, the measured value of the address is erased and the adjustment value is written to the address to adjust the analog parameters of the address.

[0013] Optionally, in the method for adjusting the eFlash parameters, step S1 further includes: loading a HEX format file into a data cache storage.

[0014] Optionally, in the method for adjusting the eFlash parameters, the method for correcting the adjustment value of the SRAM address includes:

[0015] Increment the SRAM address by 1;

[0016] Set the adjustment value corresponding to this address.

[0017] Optionally, in the method for adjusting the eFlash parameters, the SRAM address is represented by a hexadecimal number.

[0018] Optionally, in the method for adjusting the eFlash parameters, in step S6, a test machine is used to measure the analog parameters of all SRAM addresses.

[0019] Optionally, in the method for adjusting the eFlash parameters, if the difference is within a preset range, the analog parameters of the address are not adjusted.

[0020] Optionally, in the method for adjusting the eFlash parameters, if the difference between the measured value obtained by the parameter testing module from the simulated parameters in the default state and the initial value for adjustment is outside a preset range, then the simulated parameters in the default state are adjusted.

[0021] Optionally, in the method for adjusting the eFlash parameters, the initial value for adjustment is a set value.

[0022] Optionally, in the method for adjusting the eFlash parameters, the analog parameters include: word line erase voltage, control gate erase voltage, bit line write voltage, control gate write low voltage, control gate write high voltage, word line read voltage, control gate read voltage, memory cell reference current, bandgap reference voltage, low dropout Zener diode output voltage, and byte write operation current.

[0023] Optionally, in the eFlash parameter adjustment method, the different simulation parameters include a vector set of different initial values ​​for adjustment, a vector set of the built-in self-test high-voltage start-up mode, and a vector set of erase and write operation modes.

[0024] The method for adjusting eFlash parameters provided by this invention includes: Step S1: Combining the vector set of the initial adjustment value, the vector set of the built-in self-test high-voltage activation mode, and the vector set of the erase and write operation modes to form a HEX format file; Step S2: Using the HEX format file to transmit the instruction set of the built-in self-test, thereby realizing the setting of the initial adjustment value, the activation of the built-in self-test high voltage, and the erase and write operations; Step S3: Activating the built-in self-test high voltage, and the parameter test module tests the simulated parameters in the default state; Step S4: Correcting the adjustment value of the SRAM address; Step S5: Activating the built-in self-test high voltage, and the parameter test module measures the simulated parameters corresponding to the SRAM address; Step S6: Repeating steps S4 to S5 to complete the measurement of the simulated parameters of all SRAM addresses. If the difference between the measured value and the corresponding adjustment value is outside a preset range, the measured value of that address is erased, and the adjustment value is written to that address to adjust the simulated parameters of that address. This invention combines all vector sets into a single HEX format file, eliminating the need for frequent loading of the test vector set, thus reducing tuning time and improving tuning efficiency. Furthermore, the fast SRAM processing speed allows for tuning of all simulation parameters through changes in SRAM addresses, further reducing tuning time and improving tuning efficiency. Attached Figure Description

[0025] Figure 1 This is a flowchart of the method for adjusting eFlash parameters according to an embodiment of the present invention. Detailed Implementation

[0026] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0027] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0028] Please refer to Figure 1 This invention provides a method for adjusting eFlash parameters, comprising:

[0029] Step S1: Combine the vector set of the adjusted initial values, the vector set of the built-in self-test high voltage on mode, and the vector set of the erase and write operation modes to form a HEX format file.

[0030] Step S2: Use HEX format files to transmit the built-in self-test instruction set to achieve the initial value setting of the adjustment, the high voltage activation of the built-in self-test, and the erase and write operations.

[0031] Step S3: Enable the built-in self-test high voltage and test the simulated parameters in the default state using the parameter test module;

[0032] Step S4: Correct the adjustment value of the SRAM address;

[0033] Step S5: Activate the built-in self-test high voltage and use the parameter test module to measure the analog parameters corresponding to the SRAM address.

[0034] Step S6: Repeat steps S4 to S5 to complete the measurement of the analog parameters of all SRAM addresses. If the difference between the measured value and the corresponding adjustment value is outside the preset range, the measured value of the address is erased and the adjustment value is written to the address to adjust the analog parameters of the address.

[0035] In step S1, after combining the vector set of the initial values ​​to be adjusted, the vector set of the built-in self-test high-voltage on-mode, and the vector set of erase and write operation modes to form a HEX format file, the process further includes loading the HEX format file into the data cache memory (DBM). This allows the HEX format file to be called directly, and the corresponding actions can be completed according to the instructions contained in the HEX format file, without frequently loading the vector set, thus reducing adjustment time.

[0036] The method for correcting the SRAM address adjustment value includes: incrementing the SRAM address by 1; and setting the corresponding adjustment value for that address. The SRAM address is represented in hexadecimal numbers. The SRAM address is incremented by 1 starting from 0x00, thus traversing all addresses. Each increment of 1 is equivalent to changing the address, after which the analog parameters of that address can be measured and adjusted.

[0037] In step S6, a test machine is used to measure the simulated parameters of all SRAM addresses. For example, the following program is one method for implementing measurement and adjustment. Here, TPEWriteDbmData(TPE_PG, bit width, address, data) is the adjustment parameter. 0Xc5, 0XCD, and 0XD5 are the addresses.

[0038] RESULT vee_trim_all_dbm_c()

[0039] {

[0040] UINT dbm_vee = 0x00;

[0041] for(dbm_vee=0x00; dbm_vee<=0xf0; dbm_vee+=0x10)

[0042] {

[0043] TPEWriteDbmData(TPR_PG1,8,0xC5,dbm_vee);

[0044] TPEWriteDbmData(TPR_PG1,8,0xCD,dbm_vee);

[0045] TPEWriteDbmData(TPR_PG1,8,0xD5,dbm_vee);

[0046] TPERunTest("meas_vee_debug")

[0047] TPERunTest("meas_vee_debug")

[0048] TPEGetPmuMeasurement(&pmu_data);

[0049] Rt_printf("VEP 0x%02X:%5.3f\n",dbm_vee,pmu_data.value);

[0050] }

[0051] Return PASS;

[0052] }

[0053] TPEWriteDbmData(TPE_PG, bit width, address, data);

[0054] In this embodiment of the invention, if the difference is within a preset range, the simulated parameters of that address are not adjusted. The preset range is set and can be determined according to specific circumstances. If the difference between the measured value obtained by the initial parameter testing module from the simulated parameters in the default state and the initial value for adjustment is outside the preset range, then the simulated parameters in the default state are adjusted. The initial value for adjustment is a set value.

[0055] The simulation parameters in this embodiment of the invention include: word line erase voltage VWLE, control gate erase voltage VCGE, bit line write voltage VBLP, control gate write low voltage VCGLP, control gate write high voltage VCGHP, word line read voltage VWLR, control gate read voltage VCGR, memory cell reference current RCELL, bandgap reference voltage VREF, low dropout linear regulator output voltage VLDO, and byte write operation current IDP. The above simulation parameters are only a part of the total; other adjustment parameters may exist in other embodiments of the invention. Different simulation parameters include vector sets of different initial adjustment values, vector sets of high-voltage on-state modes with built-in self-test, and vector sets of erase and write operation modes. That is, the eFlash parameter adjustment method of this embodiment can be used to adjust the VWLE parameter, and also to adjust the VCGE parameter. The preset range or adjustment value of the difference involved in the adjustment process can be determined according to the actual situation.

[0056] Finally, taking the SST structure as an example, two analog quantities (16 levels) were sampled. The experimental and verification results are shown in the table below. ALPG represents the existing technology method, and DBM represents the method of this invention embodiment. VEP and VEE are two different tuning parameters. It can be seen that for VEP tuning, the tuning time of the existing technology is 3.450s, while that of this invention embodiment is 1.083s. Therefore, the tuning time of this invention embodiment is reduced compared to the existing technology. Specifically, it is reduced by 68.61%, thus improving efficiency by 318.56%. For VEE tuning, the tuning time of the existing technology is 3.250s, while that of this invention embodiment is 1.117s. Therefore, the tuning time of this invention embodiment is reduced compared to the existing technology. Specifically, it is reduced by 65.63%, thus improving efficiency by 290.96%.

[0057]

[0058] In summary, the eFlash parameter adjustment method provided in this embodiment of the invention includes: Step S1: Combining the vector set of the initial adjustment value, the vector set of the built-in self-test high-voltage activation mode, and the vector set of the erase and write operation modes to form a HEX format file; Step S2: Using the HEX format file to transmit the built-in self-test instruction set to realize the initial adjustment value setting, the activation of the built-in self-test high voltage, and the erase and write operations; Step S3: Activating the built-in self-test high voltage, and the parameter test module tests the simulated parameters in the default state; Step S4: Correcting the adjustment value of the SRAM address; Step S5: Activating the built-in self-test high voltage, and the parameter test module measures the simulated parameters corresponding to the SRAM address; Step S6: Repeating steps S4 to S5 to complete the measurement of the simulated parameters of all SRAM addresses. If the difference between the measured value and the corresponding adjustment value is outside the preset range, the measured value of that address is erased, and the adjustment value is written to that address to adjust the simulated parameters of that address. This invention combines all vector sets into a single HEX format file, eliminating the need for frequent loading of the test vector set, thus reducing tuning time and improving tuning efficiency. Furthermore, the fast SRAM processing speed allows for tuning of all simulation parameters through changes in SRAM addresses, further reducing tuning time and improving tuning efficiency.

[0059] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for adjusting eFlash parameters, characterized in that, include: Step S1: Combine the vector set of the adjusted initial values, the vector set of the built-in self-test high voltage on mode, and the vector set of the erase and write operation modes to form a HEX format file. Step S2: Use HEX format files to transmit the built-in self-test instruction set to achieve the initial value setting of the adjustment, the high voltage activation of the built-in self-test, and the erase and write operations. Step S3: Enable the built-in self-test high voltage and test the simulated parameters in the default state using the parameter test module; Step S4: Correct the adjustment value of the SRAM address; Step S5: Activate the built-in self-test high voltage, and the parameter test module measures the analog parameters corresponding to the SRAM address; Step S6: Repeat steps S4 to S5 to complete the measurement of the analog parameters of all SRAM addresses. If the difference between the measured value and the corresponding adjustment value is outside the preset range, the measured value of the address is erased and the adjustment value is written to the address to adjust the analog parameters of the address.

2. The method for adjusting eFlash parameters as described in claim 1, characterized in that, Step S1 also includes loading the HEX format file into the data cache storage.

3. The method for adjusting eFlash parameters as described in claim 1, characterized in that, Methods for correcting SRAM address adjustment values ​​include: Increment the SRAM address by 1; Set the adjustment value corresponding to this address.

4. The method for adjusting eFlash parameters as described in claim 1, characterized in that, The SRAM address is represented in hexadecimal numbers.

5. The method for adjusting eFlash parameters as described in claim 1, characterized in that, In step S6, a test machine is used to measure the simulated parameters of all SRAM addresses.

6. The method for adjusting eFlash parameters as described in claim 1, characterized in that, If the difference is within a preset range, the analog parameters of that address will not be adjusted.

7. The method for adjusting eFlash parameters as described in claim 1, characterized in that, If the difference between the measured value obtained by the parameter testing module from the simulated parameters in the default state and the adjusted initial value is outside the preset range, then the simulated parameters in the default state will be adjusted.

8. The method for adjusting eFlash parameters as described in claim 1, characterized in that, The initial value for the adjustment is a set value.

9. The method for adjusting eFlash parameters as described in claim 1, characterized in that, The simulation parameters include: word line erase voltage, control gate erase voltage, bit line write voltage, control gate write voltage, word line read voltage, control gate read voltage, reference voltage, low dropout regulated output voltage, and programming current.

10. The method for adjusting eFlash parameters as described in claim 9, characterized in that, Different simulation parameters include a vector set of different adjusted initial values, a vector set of the built-in self-test high-voltage on-mode, and a vector set of erase and write operation modes.

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