Top die backside marking for memory systems

Abstract

The invention relates to a top die backside mark for a memory system. One or more alignment marks may be added to a backside of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment mark may be formed on the top memory die during a manufacturing process of the multi-layer memory device. Various semiconductor manufacturing techniques are used to describe the operations of forming the alignment marks. Operations are also disclosed that use the alignment marks to modify placement of the top memory die to reduce alignment offsets in the manufacturing process of subsequent memory dies.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 929,394, filed by Li et al. on October 28, 2024, entitled “TOP DIE BACK-SIDE MARKING FOR MEMORY SYSTEMS,” and U.S. provisional patent application No. 63 / 547,316, filed by Li et al. on November 3, 2023, entitled “TOP DIE BACK-SIDE MARKING FOR MEMORY SYSTEMS,” each of which is assigned to its assignee, and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to top die backside marking for memory systems. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, which are typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access the stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Some memory devices may include multiple layers of memory dies, which include memory cells for storing information. A memory device can be formed by stacking memory dies together during a manufacturing process. Summary of the invention

[0005] Describe a method. The method may include: aligning a first memory die with a second memory die, the first memory die including: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die including a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die so that it contacts the second pad of the second memory die; aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die including a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die positions the third pillar of the third memory die so that it contacts the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer; and bonding the third memory die to the first memory die to form a multi-layer semiconductor device.

[0006] A method is described. The method may include: bonding a memory die to a carrier die, the memory die including a silicon layer and one or more pillars positioned on a first side of the silicon layer; identifying a first position of a first alignment mark on the first side of the silicon layer; forming one or more second alignment marks at a plurality of locations on a second side of the silicon layer based at least in part on identifying the first position of the first alignment mark, wherein the first alignment mark and the one or more second alignment marks can be used to align the memory die as a top die in a multi-layer semiconductor device; and debonding the memory die from the carrier die.

[0007] A method is described. The method may include: aligning a first memory die with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die comprising a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die so that it contacts the second pad of the second memory die; aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die The first memory die is aligned, the third memory die includes a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein the third memory die is aligned at least in part based on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die so that it contacts the first pad of the first memory die; the third memory die is bonded together with the first memory die to form a multi-layer semiconductor device; an alignment offset between the third memory die and the first memory die is determined at least in part based on the one or more marks; and one or more alignment procedures of the second multi-layer semiconductor device are adjusted at least in part based on the alignment offset.

[0008] An apparatus is described. The apparatus may include: a first memory die aligned with a second memory die, the first memory die including: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled with the first pillar and the first pad, the second memory die including a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein the first memory die has the first pillar of the first memory die in contact with the second pad of the second memory die; and a third memory die aligned with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die including a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein the third memory die contacts the third pillar of the third memory die with the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer; wherein the third memory die is bonded together with the first memory die to form a multilayer semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting top die backside marking for a memory system according to examples as disclosed herein is shown.

[0010] Figure 2 A side elevation view of a memory device supporting top die backside marking for a memory system is shown according to examples as disclosed herein.

[0011] Figure 3 Shown is a side elevation view of a system supporting top die backside marking for a memory system according to examples as disclosed herein.

[0012] Figure 4 Shown are side elevation and top plan views of a top memory die supporting top die backside marking for a memory system according to examples as disclosed herein.

[0013] Figure 5 An example of steps in a manufacturing process supporting top die backside marking for a memory system is shown according to examples as disclosed herein.

[0014] Figure 6 An example of a manufacturing process supporting top die backside marking for a memory system according to examples as disclosed herein is shown.

[0015] Figure 7 Shown is a side elevation view of a memory device supporting top die backside marking for a memory system according to examples as disclosed herein.

[0016] Figures 8 to 11 A flow chart illustrating one or several methods of supporting top die backside marking for a memory system according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0017] As part of the manufacturing process, a multi-layer memory device can be formed by stacking individual memory dies on top of each other. The stacking process uses accurate alignment of the memory dies so that when the memory dies are bonded together, components such as through-silicon vias (TSVs) are coupled to each other in different layers. For example, various alignment techniques can be used to align the pillars of a first memory die with the pads of a second memory die below the first memory die. Many memory dies include components that can be detected on a first side (e.g., bottom) of the memory die and a second side (e.g., top) of the memory die. For example, if the memory die includes TSVs, it can be observed on the first side and the second side. However, in a multi-layer memory device, the second side of the top memory die (e.g., the final memory die added to the stack of memory dies) may be blank (e.g., substantially no markings present on the second side of other memory dies). Therefore, it may be challenging to align the top memory die with the stack of memory dies below so that the pillars on the first side of the top memory die are connected to the pads of the memory die immediately below. Misalignment of the top memory die may cause failure of the entire multi-layer memory device. Additionally, this misalignment may reduce the yield of memory devices during the manufacturing process.

[0018] Techniques for adding one or more alignment marks to a second side of a top memory die in a stack of memory dies are described. The one or more alignment marks may be used to align the position of the top memory die relative to the position of the memory die below the top memory die. The one or more alignment marks may be formed on the top memory die during a manufacturing process. Operations for forming the one or more alignment marks are described using various semiconductor manufacturing techniques (e.g., photolithography, etching, etc.). The multi-layer memory device may be inspected after the manufacturing process to identify any alignment offset associated with the top memory die. Operations for modifying the placement of the top memory die as part of a subsequent manufacturing operation to reduce or eliminate alignment offsets during the manufacturing process of subsequent memory dies using the one or more alignment marks are also disclosed. By reducing misalignment of the top memory die, the yield of the memory device during the manufacturing process may be improved.

[0019] In About Figure 1 Features of the present disclosure are illustrated and described in the context of systems and architectures. Figures 2 to 8 Features of the present disclosure are further illustrated and described in the context of a manufacturing process for a top die backside marking of a memory system of Figures 9 to 11 These and other features of the present disclosure are further illustrated by and described with reference to a flowchart associated with a manufacturing process for a top die backside marking of a memory system of the present invention.

[0020] Figure 1An example of a system 100 that supports top die backside marking for a memory system according to examples as disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smart phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling the host system 105 with the memory system 110 (e.g., to support a communication coupling). The system 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0021] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to perform processes, any one or more of which may be referred to as a processor 125 or included in the processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC or components thereof, among other examples.

[0022] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as a host system controller 120 or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functions described herein may be implemented by the processor 125 or may be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as a host.

[0023] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. The memory system 110 can be configured for operation with different types of host systems 105, and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory device 145 to the host system 105, or receive a refresh command indicating that the memory system 110 is to refresh data stored in the memory device 145, as well as other types of commands and operations.

[0024] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions that support the memory system 110 to perform various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some examples, the memory system controller 140 may control the operation of the memory system 110 in cooperation with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof. Although examples of the memory system controller 140 are illustrated as separate components of the memory system 110, in some examples, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, the one or more local controllers 150, or any combination thereof.

[0025] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), each of which is operable to store data (e.g., as one or more memory bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, or NOR memory cells and NAND memory cells, or any combination thereof.

[0026] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some examples, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some examples, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some examples, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access addresses of the memory array 155, a sensing component for sensing states of memory cells of the memory array 155, a writing component for writing states to memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0027] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be examples of conductive input or output points of devices of the system 100, and terminals may operate as part of a channel 115. To support communication via channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating received signals, or an encoder for encoding or modulating signals to be transmitted, as well as other components that support signaling via channel 115, which may be included in corresponding interface portions of the corresponding systems.

[0028] The channels 115 may be dedicated to conveying one or more types of information, and the channels 115 may include unidirectional channels, bidirectional channels, or both. For example, the channels 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, the channels 115 may be configured to provide power from one system to another (e.g., from the host system 105 to the memory system 110 according to a regulated voltage). In some examples, at least a subset of the channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard), which may support configuration operations of the host system 105 and the memory system 110 and interaction between the host system 105 and the memory system 110.

[0029] As described herein, a multi-layer semiconductor device may be formed by stacking a plurality of memory dies (e.g., memory array 155) on top of one another. For example, a first memory die may be aligned with and positioned on a second memory die such that a first pillar of the first memory die contacts a second pad of the second memory die. A third memory die may be aligned with and positioned on a first memory die such that a third pillar of the first memory die contacts a first pad of the first memory die. According to the described example, the third memory die includes one or more markings on a second surface facing away from the first memory die. The third memory die is then bonded together with the first memory die to form a multi-layer semiconductor device. In some examples, a multi-layer semiconductor device may be used as a memory device 145 in a memory system 110.

[0030] In some examples, one or more marks may be formed on the second surface of the third memory die before alignment with the first memory die using a different manufacturing process. In some examples, a post-bonding inspection may be performed on the multi-layer semiconductor device to detect an alignment offset between the third memory die and the second memory die. The alignment offset may be used to adjust one or more alignment procedures during a subsequent manufacturing process of the multi-layer semiconductor device. The described process may be used to improve the alignment of the third memory die with the second memory die, thereby reducing the failure rate of the multi-layer semiconductor device produced by the manufacturing process. In addition, the yield associated with the manufacturing process may be improved, thereby reducing costs.

[0031] In addition to applicability in systems as described herein, techniques for top die backside marking of memory systems may also be implemented to improve the sustainability of various electronic devices and systems. As the use of electronic devices becomes more widespread, the energy usage and environmental impact associated with the production of electronic devices and device operation are also increasing. In addition, waste associated with the disposal of electronic devices may also be harmful for a variety of reasons. Implementation of the techniques described herein may reduce the impacts associated with electronic devices by improving the alignment of individual layers when producing multi-layer semiconductor devices, which may reduce product failure rates during quality testing associated with the manufacturing process, reduce materials used in the production of electronic devices, improve the yield associated with the manufacturing process of producing electronic devices, and other advantages.

[0032] Figure 2 An example of a memory device 200 supporting top die backside marking for a memory system according to examples as disclosed herein is shown. The memory device 200 can be an example of a multi-layer semiconductor device including one or more first memory dies 210 (e.g., core memory dies), second memory dies 220 (e.g., initial memory dies), and top memory die 230 (e.g., top memory die). Although Figure 2 2 , three first memory dies 210 - a, 210 - b, 210 - c are shown, but other examples may include more or fewer first memory dies 210 (e.g., 2, 4, 8, 16, etc.). The multi-layer semiconductor memory device may be an example of a high bandwidth memory (HBM) and the host system 105 may be configured to communicate with the memory device 200 using the HBM communication protocol, or another protocol defined by an industry standardized specification (e.g., a JEDEC specification).

[0033] A multi-layer semiconductor device may include two or more memory dies stacked one above the other. Stacking memory dies may allow a memory system to increase the density of memory cells within the same footprint. The control circuitry of the two or more memory dies may be included in a substrate positioned below the stack of memory dies (e.g., under-array CMOS). For example, the substrate may include support circuitry, such as drivers, decoders, error control circuitry, and sense amplifiers (and other components). A second memory die 220 (e.g., an initial memory die) may be positioned to contact the substrate. Other memory dies (e.g., one or more first memory dies 210 as part of the core and top memory die) may be stacked on top of the second memory die 220.

[0034] Although features of the present disclosure are described in the context of memory dies (e.g., first memory die 210, second memory die 220, and top memory die 230), these features can be applied to any stacked semiconductor device. For example, memory device 200 can be an example of a multi-layer semiconductor device including one or more first memory dies (e.g., core die), second memory die 220 (e.g., initial die), and top memory die 230 (e.g., top die). Although Figure 2 2 , three first dies 210 - a, 210 - b, 210 - c are shown, but other examples may include more or fewer first dies 210 (e.g., 2, 4, 8, 16, etc.). Any features, techniques, or relationships described with reference to memory device 200 and / or memory dies may also be applicable to more general semiconductor devices including stacked dies.

[0035] Some of the dies included in the memory die stack may include a silicon layer, pillars, and pads. For example, each of the first memory dies 210 may include a first silicon layer 212, one or more pillars 214 formed on a first side 215 of the first silicon layer 212 (e.g., the first memory die 210), and one or more corresponding pads 216 formed on a second side 217 of the first silicon layer 212. In some examples, TSVs 218 may be formed in each first memory die 210 and coupled to each other in different first memory dies 210 (e.g., 210-a, 210-b, 210-c). TSVs 218 may be configured to couple pads 216 on the second side 217.

[0036] The second memory die 220 may include a second silicon layer 222, one or more pillars 224 formed on a first side 215 of the second silicon layer 222 (e.g., the second memory die 220), and one or more corresponding pads 226 formed on a second side 217 of the second silicon layer 222. One or more TSVs 228 may be formed in the second memory die 220. In some examples, the TSVs 228 in the second memory die 220 may be coupled with the TSVs 218 formed in the first memory die 210. In some examples, the pillars 224 formed on the first side 215 of the second silicon layer 222 may be coupled with electronic circuitry (not shown) included in a substrate associated with the memory device 200. For example, the electronic circuitry may be formed on the substrate for communicating with some or all of the memory dies (e.g., the first memory die 210, the second memory die 220, and the top memory die 230).

[0037] The top memory die 230 may also include a third silicon layer 232 and one or more pillars 234 formed on its first side 215. In contrast to the first memory die 210 and the second memory die 220, the top memory die 230 does not include pads or TSVs on its second side 217. In some examples, the top memory die 230 may include TSVs (not shown) that extend to a region below the top surface (e.g., the second side 217). In other words, such TSVs may not extend through the second side 217 of the top memory die 230 in order to prevent electrical shorts that may cause failures in the memory device 200. For example, the top of the stacked memory device may be coupled with other components that may cause electrical challenges if the TSVs are exposed in the top memory die 230. In some examples, the second side 217 of the top memory die 230 may not have any patterns or markings. Depending on the specific application of the memory device 200, a heat sink (not shown) may be coupled to the top memory die 230 after the manufacturing process is completed.

[0038] The memory device 200 may be formed by a manufacturing process that aligns and stacks different memory dies 210, 220, 230 together. In some examples, a manufacturing system (not shown) may align one of the first memory dies 210-a with the second memory die 220. For example, the manufacturing system may align the first memory die 210 with the second memory die 220 using information associated with the positions of the pillars 214 and TSVs 218 of the first memory die 210-a and the pads 226 and TSVs 228 of the second memory die 220. Additional first memory dies 210 may be aligned in a similar manner (e.g., first memory die 210-a and first memory die 210-b). The manufacturing system may also detect alignment marks (not shown) on the first side 215 (e.g., bottom) of the first silicon layer 212 and on the second side 217 (e.g., top) of the second silicon layer 222 during the alignment process. In some examples, a first temperature and pressure may be applied to cause an initial bond between the first memory die 210 and the second memory die 220. The first temperature and first pressure may be applied as part of a first type of bonding operation. In some examples, after all memory dies are in the stack, a second type of bonding operation may be performed on the memory device 200. The second type of bonding operation may apply a second temperature and a second pressure to the memory device 200 after aligning and stacking the top memory die 230. The second temperature and second pressure may be greater than the first temperature and first pressure applied to the first memory die 210 and the second memory die 220. In addition, the second temperature and second pressure may cause the electrical connector to melt to couple the first memory die 210, the second memory die 220, and the top memory die 230, thereby enabling the use of TSVs to communicate signals (e.g., commands, data, etc.) between different memory dies.

[0039] like Figure 2, the top memory die 230 does not include TSVs or detectable patterns on the second side 217. The lack of such features may cause difficulty in aligning the top memory die 230 with the first memory die 210-c. For example, during the manufacturing process, the pillars 234 of the top memory die 230 may not be properly aligned with the pads 216 of the final first memory die 210-c. Misalignment of the top memory die 230 may cause connection failures of the memory device 200. For example, misalignment (e.g., shifting) of the top memory die 230 may cause an offset between the pillars 234 of the top memory die 230 and the pads 216 of the final first memory die 210-c. The offset may cause some pillars 234 to contact multiple pads 216 of the final first memory die 210-c, or fail to contact any pads 216 from the final first memory die 210-c. Due to this misalignment, an electrical short or interconnect failure between the top memory die 230 and the final first memory die 210-c may be detected during a test or verification procedure of the memory device 200. As a result, the memory device 200 will be discarded.

[0040] Many factors may further contribute to misalignment of the top memory die 230. For example, a manufacturing system may be used to transport and position the top memory die 230 on the first memory die 210. In some examples, the position of the top memory die 230 may shift due to movement or calibration errors of the manufacturing system. In other examples, the position of the top memory die 230 may shift due to vibrations during transportation. The manufacturing system may also include a vacuum chuck that secures the top memory die 230. Changes in vacuum pressure may cause the top memory die 230 to shift during transportation.

[0041] Misalignment of the top memory die 230 can occur in different ways. For example, the top memory die 230 can be shifted along a first axis (eg, the X-axis), such as Figure 2 The top memory die 230 can also be arranged along a vertical axis. Figure 2 . The top memory die 230 may also undergo a rotational shift (e.g., θ) along a plane defined by the first and second axes (e.g., about the Z axis). In some examples, misalignment of the top memory die 230 may be detected by measuring displacement along the first axis, displacement along the second axis, rotational shift, or any combination thereof.

[0042] If not corrected, the amount of misalignment may continue to change and even increase as additional memory devices 200 are produced during the manufacturing process. For example, as the manufacturing process continues, the misalignment associated with a first memory device 200 due to a 2μ shift along a first axis may continue to increase to exceed 10μ for subsequent memory devices 200. Increasing levels of misalignment may result in test failures and adversely affect the yield of memory devices 200 produced in the manufacturing process.

[0043] According to examples described herein, one or more marks (e.g., alignment marks) may be formed on the second side 217 of the top memory die 230 to assist in aligning the top memory die 230 with the first memory die 210. In some examples, the one or more marks may be positioned in several locations on the second side 217 based on the alignment marks on the first side 215 of the memory die or the positions of the pillars 234 formed on the first side 215 of the memory die. The manufacturing system may use the one or more marks to determine the position and orientation of the top memory die 230. For example, the one or more marks may be used to determine the center and rotation angle of the top memory die 230. Thus, the manufacturing system may refer to the detectable pattern on the second side 217 of the first memory die 210, thereby improving the accuracy with which the manufacturing system may align the top memory die 230 with the first memory die 210.

[0044] In some examples, the memory device 200 may be subjected to a post-bonding inspection after performing the second type of bonding operation to apply the second temperature and the second pressure. The post-bonding inspection may utilize one or more inspection detectors (e.g., cameras) to identify an alignment shift between the top memory die 230 and the first memory die 210. The alignment shift may be based on a displacement along the X-axis, a displacement along the Y-axis, a rotation on the XY plane (e.g., about the Z-axis), or any combination thereof.

[0045] According to examples described herein, an alignment offset can be used to improve processes associated with aligning the top memory die 230 with the first memory die 210. In some examples, a threshold can be associated with the alignment offset. The threshold can incorporate one or more components (or parameters) based at least in part on information obtained from one or more inspection cameras. For example, the threshold can be in the form of: threshold (x, y, θ), where x = displacement along the X axis, y = displacement along the Y axis, and / or θ = rotation about the Z axis - alone or in any combination.

[0046] For example, a threshold value (3, 3, 5) may be satisfied when a displacement of less than 3μ along the X-axis, a displacement of less than 3μ along the Y-axis, and a rotation of less than 5° about the Z-axis are detected. As described herein, some or all of the parameters may be applied. Thus, the threshold parameter may have a zero value (e.g., a threshold value (3, 0, 0)) to indicate that a single parameter (e.g., a displacement along the X-axis) may be applicable to the alignment offset. In response to satisfying the threshold value, the manufacturing system may be controlled to adjust the alignment of the top memory die 230 during the manufacturing process of the subsequent memory device 200. For example, the manufacturing system may adjust the alignment of the top memory die 230 of the next memory device along the X-axis so as to reduce or eliminate any misalignment with the first memory die 210. In some examples, the manufacturing system may also be checked to detect any calibration errors or damage that may affect the alignment of the top memory die 230.

[0047] In some examples, a post-joining inspection may be performed on a group of memory devices 200. An example of a post-joining inspection may include a process of measuring aspects of a stacked memory device and may include cutting or otherwise exposing a portion of the stacked memory device for measurement. Alignment offset values ​​associated with different memory devices 200 may be analyzed to obtain an average value representing a group of memory devices 200. The alignment offset value may be used to determine when a threshold parameter is met. Therefore, the manufacturing system may be controlled to adjust the position of the top memory die 230 during the manufacturing process of subsequent memory devices 200. In some examples, the manufacturing system may be controlled to make incremental adjustments less than the threshold until a new post-joining inspection is performed and the results are analyzed. The manufacturing system may be controlled to make additional adjustments based on the results of the new post-joining inspection. In some examples, the manufacturing system may be controlled to make adjustments corresponding to the value of the alignment offset.

[0048] According to the disclosed examples, one or more alignment marks formed on the second side 217 of the top memory die 230 can improve alignment with the first memory die 210 to reduce connection failures when testing the memory device 200. A post-bonding inspection can also be performed to identify an alignment offset between the top memory die 230 and the first memory die 210. When the alignment offset meets a threshold, one or more alignment processes associated with the top memory die 230 can be adjusted to reduce connection failures in subsequent manufacturing processes of the memory device 200. Therefore, the number of discarded memory devices 200 can be reduced. In addition, the production yield of the memory device can be improved.

[0049] Figure 3An example of a system 300 supporting top die backside marking for a memory system according to examples as disclosed herein is shown. In some examples, the system 300 can be used in a process of trimming the top memory die 230 in order to achieve desired parameters of the memory device 200. The parameters can be set according to specific requirements or applications. For example, the memory device 200 can be used in an application that uses a specific height with a low tolerance for deviations from the specific height.

[0050] As part of manufacturing the top memory die 230, the memory die can be coupled to a carrier wafer 310. The carrier wafer can be an example of a substrate to which other semiconductor wafers can be bonded during manufacturing. By bonding the wafer to the carrier wafer, safe handling and processing can be allowed while preventing damage to the wafer being manufactured. Therefore, the processing of the top memory die 230 can include a process of trimming the height of the top memory die 230 while also compensating for the variation in the height of the first memory die 210 and the second memory die 220. Therefore, the resulting memory device 200 will meet the desired application height. In some examples, the top memory die 230 can be manufactured to have a thickness that is greater than the thickness of each first memory die 210 or the thickness of the second memory die 220. Additionally or alternatively, as part of the process of forming a mark on the second side 217 of the top memory die 230, the top memory die 230 can be bonded to the carrier wafer 310.

[0051] According to the described example, system 300 can include a carrier wafer 310 on which a device wafer 330 (e.g., top memory die 230) is mounted. Device wafer 330 can be an example of top memory die 230. An adhesive such as bonding glue 320 can be applied between device wafer 330 and carrier wafer 310. In some examples, bonding glue 320 and carrier wafer 310 can be selected to reduce warpage of device wafer 330. A bonding temperature can be applied to activate bonding glue 320 and secure device wafer 330. Device wafer 330 can be processed to a reduced height that meets the requirements of memory device height.

[0052] The system 300 may include a measuring device 340 for measuring and monitoring the height (or thickness) of the device wafer 330 during the trimming process. In some examples, the measuring device 340 may include an inner gauge for physically detecting the height of the device wafer 330 and an outer gauge for measuring the height of the carrier wafer 310. Once the device wafer 330 has reached a specified height, a debonding temperature may be applied to melt the bonding glue 320 and remove the device wafer 330 from the carrier wafer 310. Although the measuring device 340 is shown for illustrative purposes, other measuring techniques may be used to measure the device wafer 330 (e.g., a touch-type measuring device or an optical-type measuring device).

[0053] Figure 4 A side elevation view of a top memory die 401 and a top plan view of a top memory die 402 are shown supporting top die backside marking for a memory system according to examples as disclosed herein. The top plan view of the top memory die 402 illustrates selective transparency to show features on the top surface (e.g., alignment marks on the backside) and other features that would be buried below the top surface (e.g., bottom side marks or front side). In some cases, the first side 215 and / or the first side 410 may be referred to as the bottom side or front side. In some cases, the second side 217 and / or the second side 430 may be referred to as the top side or back side. Various processes may be performed to select the location of a mark 460 (e.g., an alignment mark) and form the mark 460 on the second side of the top memory die 230. According to the described example, the top memory die 230 may include a first side 410 including one or more pillars 234. The top memory die 230 may also include a silicon layer 232 (e.g., a third silicon layer) and a second side 430 (e.g., a top side). In some cases, second side 430 may be blank and may not include any structures that may be used in the alignment process.Techniques for forming mark 460 on second side 430 are described.

[0054] According to examples described herein, a through silicon alignment (TSA) process may be performed on the top memory die 230 in order to detect the location of the front side alignment mark 440 formed as part of the first side 410. The TSA process may be performed, for example, using one or more photolithography tools. According to an example, an infrared (IR) beam may be directed toward the first side 410 of the top memory die 230. The IR beam may pass through the third silicon layer 232 to detect patterns and features formed in the first side 410. For example, the IR beam may be used to detect the location of the front side alignment mark 440 formed as part of the first side 410. In some examples, the IR beam may be directed from an exposure tool (not shown) used in a photolithography process. Once the IR beam identifies the location of the front side alignment mark 440 from the first side 410, one or more locations of the mark 460 may be selected on the second side 430 of the top memory die 230.

[0055] According to the described example, the location identified based on detecting the front side alignment mark 440 can be used to form a mark 460 (eg, a back side alignment mark) on the second side 430 of the top memory die 230. Figure 4 As shown in FIG. 1 , the mark 460 formed on the second side 430 of the top memory die 230 is positioned at a different location relative to the front side alignment mark 440. Figure 42, one or more additional marks 460 can be formed on the second side 430 of the top memory die 230. The pattern of marks 460 on the second side 430 can include one mark or two or more marks in the pattern, and the position of the second mark can be based on the position of the front side alignment mark 440, the position of the mark 460, or both. According to the described example, all marks 460 formed on the second side 430 of the top memory die 230 are positioned at different positions relative to the front side alignment mark 440.

[0056] Figure 5 An example of steps in a manufacturing process 500 that supports top die backside marking for a memory system according to examples as disclosed herein is shown. According to the described example, the second surface of the top memory die 230 can be processed to form marks at one or more locations identified during the TSA process. In some examples, multiple locations can be identified, thereby resulting in multiple marks being formed on the second side of the top memory die 230. Figure 5 , an etching process is performed on the second side of the top memory die 230. Although not shown, a layer of photoresist material 510 is first applied to the second side of the top memory die 210. In some examples, the photoresist material 510 may be applied using a spin coating operation to achieve a uniform material layer. A pattern corresponding to the mark 460 on the second side may be created in the photoresist material 510 using a development process that may involve exposing the photoresist material 510 to radiation. In some examples, a photomask may be used to define the mark by delineating where the radiation exposes the photoresist material 510. In some examples, a photomask may be used to define a plurality of marks on the photoresist material 510. According to the described examples, one or more marks defined by the photomask may correspond to alignment marks (e.g., mark 460) on the second side of the top memory die 230.

[0057] Next, an etching process may be used, for example, to remove the exposed photoresist areas to leave a desired pattern 520 within the third silicon layer 232. In some examples, the etching process may be a dry etching process. The etching process may remove at least a portion of the photoresist material 510 and the third silicon layer 232. In some examples, the dry etching process may produce byproducts (e.g., polymers) that may be formed on the photoresist material 510 and / or the third silicon layer 232. The byproducts may be in the form of Figure 5. However, the polymer layer 530 may prevent or reduce the subsequent removal of the photoresist material 510. Therefore, it may be useful to remove the polymer layer 530 before removing the photoresist material 510 in order to prevent or reduce uniformity issues. In some examples, a plasma etching process may be performed to remove the polymer layer 530. In some instances, the plasma etching process may be a reactive ion etching (RIE) process using oxygen. Once the polymer layer 530 has been removed, the photoresist material 510 may be removed from the second side of the top memory die 230. In some examples, a wet stripping process may be performed to remove the photoresist material 510. Since at least a portion of the third silicon layer is etched, the mark 460 may remain in the third silicon layer 232.

[0058] Figure 6 An example of a manufacturing process 600 that supports top die backside marking for a memory system according to examples as disclosed herein is shown. Figure 6 , the process begins after processing of the top memory die is completed and the top memory die is formed. At 610, the process may include performing a trim operation to trim the top memory die 230.

[0059] At 615 , the process can include reversibly bonding the first side of the top memory die 230 to a carrier wafer to perform additional processing steps without subjecting the top memory die 230 to accidental damage. In some cases, the carrier wafer can correspond to carrier wafer 310 .

[0060] At 620 and 625, the process may include a planarization operation and / or a grinding operation to reduce the thickness of the top memory die 230. In some examples, the thickness of the top memory die 230 may be continuously monitored during the planarization operation and / or the grinding operation until a desired threshold is achieved. The planarization operation and / or the grinding operation may be performed in order to achieve a desired height of the memory device 200. In some examples, the planarization operation and / or the grinding operation performed at 620 and 625 may correspond to the reference Figure 3 In some cases, the planarization process and the grinding process can also flatten and smooth the second side of the top memory die 230. In some examples, the planarization process can include chemical mechanical polishing, which uses a polishing tool to apply a slurry fluid to the second side of the top memory die. At 625, the process can include a grinding operation to further control the thickness of the top memory die 230.

[0061] At 630, the process may include applying a photoresist material to the second side of the top memory die 230. In some examples, the photoresist material may be applied using a spin coating operation. The photoresist material may also correspond to Figure 5. The photoresist material 510 is shown in FIG. The photoresist material can be developed at least in part using a mask to define a pattern of one or more alignment marks on the second side of the top memory die 230.

[0062] At 635, the process may include a metrology process to locate reference points (e.g., front side marks) and select the locations of one or more marks to place on the back side of the top memory die 230. For example, a measurement technique may be used to identify the location of the front side marks or other reference points. The manufacturing system may then identify the location of the pattern of marks on the back side of the top memory die 230. In some examples, the metrology operations performed at 635 may correspond to the reference points. Figure 4 At 640, the process may include etching the photoresist material and the silicon layer at the second side of the top memory die 230 to define the alignment mark. In some examples, the etching process may be a dry etching process, such as reference Figure 5 At 645, the process may include performing a plasma etching process (e.g., RIE using oxygen) to remove polymer redeposition caused by etching the photoresist material. In some examples, the etching and RIE may correspond to reference Figure 5 Process described.

[0063] At 650, the process may include stripping the photoresist material from the second side of the top memory die 230. In some examples, a wet stripping operation may be used to remove the photoresist material, as described in reference to Figure 5 At 655, the process can include debonding the top memory die 230 from the carrier wafer. In some examples, the manufacturing system can utilize alignment marks formed on the second side of the top memory die 230 to align the top memory die 230 with the first memory die 210 to complete the memory device 200.

[0064] Figure 7An example of a memory device 700 supporting a top die backside mark for a memory system according to an example as disclosed herein is shown. In some examples, the memory device 700 may correspond to a second or subsequent memory device 700 manufactured after an alignment shift is detected. The memory device 700 may include one or more first memory dies 710 (e.g., core memory dies 710-a, 710-b, 710-c), a second memory die 720 (e.g., an initial memory die), and a top memory die 730 (e.g., a third memory die). In some examples, the memory device 700 may include more or fewer first memory dies 710 (e.g., 2, 4, 8, 16, etc.). The selected first memory die 710-a may be aligned with the second memory die 720. Two additional first memory dies 710-b, 710-c may also be stacked on the selected first memory die 710-a. In some examples, additional memory dies (not shown) may also be stacked on the selected first memory die 710-a. Each of the first memory dies 710 may include a first silicon layer 712 (e.g., 712-a, 712-b, 712-c), one or more first pillars 714 (e.g., 714-a, 714-b, 714-c) formed on a first side of the first silicon layer 712, and one or more corresponding first pads 716 (e.g., 716-a, 716-b, 716-c) formed on a second side of the first silicon layer 712. In some examples, one or more first TSVs 718 (e.g., 718-a, 718-b, 718-c) may be formed in each first silicon layer 712 and coupled to each other in different first memory dies 710 (e.g., 710-a, 710-b, 710-c).

[0065] The second memory die 720 may include a second silicon layer 722, one or more second pillars 724 formed on a first side of the second silicon layer 722, and one or more corresponding second pads 726 formed on a second side of the second silicon layer 722. One or more second TSVs 728 may be formed in the second silicon layer 722. In some examples, the second TSVs 728 in the second silicon layer 722 may be coupled with the first TSVs 718 formed in the first silicon layer 712. In some examples, the second pillars 724 formed on the first side of the second silicon layer 722 may be coupled with electronic circuitry (not shown) associated with the memory device 700. For example, the electronic circuitry may be formed on the substrate for communicating with some or all of the memory dies (e.g., the first memory die 710, the second memory die 720, and the top memory die 730).

[0066] The top memory die 730 may also include a third silicon layer 732, one or more third pillars 734 formed on a first side thereof. In contrast to the first memory die 710 and the second memory die 720, the top memory die 730 does not include a pad or TSV on a second side of the third silicon layer 732. In some examples, the top memory die 730 may include a TSV (not shown) extending into a portion of the third silicon layer 732. In other words, such TSVs do not extend through the second side of the third silicon layer 732, thereby preventing electrical shorts that may cause failures in the memory device 700. In some examples, a heat sink (not shown) may be coupled to the top memory die 730 after the manufacturing process is completed.

[0067] The memory device 700 may be formed by a manufacturing process that uses a manufacturing system (not shown) to align one of the first memory dies 710-a with the second memory die 720. For example, the manufacturing system may align the first memory die 710-a with the second memory die 720 so that the first pillar 714-a contacts the second pad 726. In some examples, the manufacturing system may align additional first memory dies (e.g., 710-b, 710-c, etc.) in a similar manner. The manufacturing system may also detect alignment marks (not shown) on the first silicon layer 712 and the second silicon layer 722 during the alignment process. In some examples, a first type of bonding operation may be performed using a first temperature and a first pressure to cause an initial bond between the first memory die 710 and the second memory die 720.

[0068] According to the disclosed examples, the top memory die 730 can include one or more alignment marks 736-a, 736-b formed on the second side of the third silicon layer 732. In some examples, the alignment marks 736-a and 736-b can correspond to Figure 4 One or more marks 460 shown in FIG. Figures 3 to 6 The manufacturing system may use the described techniques to form the alignment mark 736. In some examples, the manufacturing system may use the alignment mark 736 to align the top memory die 730 with the first memory die 710 so that the third pillar 734 contacts the first pad 716. A second type of bonding operation may be performed to couple the first memory die 710, the second memory die 720, and the third memory die 730 together. In some examples, the second type of bonding operation may apply a second temperature and a second pressure to melt the electrical connector in the memory device 700, thereby enabling signals (e.g., commands, data, power, etc.) to be communicated between the first memory die 710, the second memory die 720, and the top memory die 730.

[0069] according to Figure 7, information obtained from alignment offsets associated with a previous memory device (e.g., memory device 200) is used to reduce or eliminate alignment offsets in memory device 700. As previously discussed, one or more inspection cameras can be used to perform post-bonding inspection after the manufacturing process is completed. The post-bonding inspection can determine the alignment offset between the third memory die 230 and the first memory die 210, such as Figure 2 . The alignment offset may be based on a displacement along the X-axis, a displacement along the Y-axis, a rotation about the Z-axis, or any combination thereof. The alignment offset may be used to determine when a threshold is met. Therefore, one or more alignment procedures of the top memory die 730 are adjusted to reduce or eliminate the alignment offset. For example, the position of the top memory die 730 in the memory device 700 may be shifted and / or rotated to correct the alignment offset. According to the disclosed examples, the misalignment of the third memory die may be reduced, thereby reducing the failure rate of the memory device during testing. In addition, the production yield of the memory device may be improved.

[0070] Figure 8 A flow chart illustrating one or more methods 800 for supporting top die backside marking for a memory system according to examples as disclosed herein is shown. The operations of the method 800 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0071] At 810, the method may include aligning a first memory die with a second memory die. The first memory die may include a first silicon layer, a first pillar positioned on a first side of the first silicon layer, and a first pad positioned on a second side of the first silicon layer. The first memory die may also include a first via extending through the first silicon layer and coupled to the first pillar and the first pad. The second memory die may include a second silicon layer, a second pillar positioned on a first side of the second silicon layer, and a second pad positioned on a second side of the second silicon layer. In some instances, aligning the first memory die with the second memory die may include positioning the first pillar of the first memory die in contact with the second pad of the second memory die. In some instances, the second memory die may include a second via extending through the second silicon layer and coupled to the second pillar and the second pad. In some examples, the first memory die and the second memory die may correspond to Figure 7 8. The first memory die 710 and the second memory die 720 are shown in FIG.

[0072] At 820, the method may include bonding the first memory die to the second memory die. In some examples, the first memory die and the second memory die may be bonded together using a first type of bonding operation that applies a first pressure and a first temperature. At 825, the method may optionally include bonding an additional first memory die together. In some examples, the additional first memory die may correspond to Figure 7 . In some examples, additional first memory dies may be bonded together during the first type of bonding operation.

[0073] At 830, the method may include identifying a first position of a first alignment mark on a third memory die. In some examples, the third memory die may include a third silicon layer and a third pillar positioned on a first side of the third silicon layer. The first position of the first alignment mark may be identified on a second side of the third silicon layer. In some examples, a TSA process may be performed to detect the position of the alignment mark on the first side of the third silicon layer. Then, the detected position may be used to identify the first position of the first alignment mark on the second side of the third silicon layer.

[0074] At 840, the method may include forming one or more alignment marks at a first location on the second side of the third silicon layer. In some examples, the alignment marks may be formed using, for example, Figure 5 and 6 The first alignment mark may be formed by various semiconductor manufacturing techniques described in the semiconductor manufacturing techniques. For example, a layer of photoresist material may be applied on the second side of the third silicon layer. An etching process may be performed to remove the photoresist material and a portion of the third silicon layer, thereby forming a pattern defining the first alignment mark. Then, the remaining layer of photoresist material may be removed from the second side of the third silicon layer. In some examples, a dry etching process may be performed to remove the photoresist material and a portion of the third silicon layer. In some examples, a wet stripping process may be performed to remove the remaining layer of photoresist material from the second side of the third silicon layer.

[0075] At 845, the method may optionally include forming one or more second alignment marks at additional locations on the second side of the third silicon layer. In some examples, the first location of the first alignment mark may be used to identify a location for forming the second alignment mark. In other examples, an additional TSA process may be performed to detect the locations of different alignment marks on the first side of the third silicon layer. The detected additional locations may then be used to identify locations on the second side of the third silicon layer where the second alignment mark may be formed. In some cases, forming the alignment marks at 840 and 845 may be completed before 810, or before 820, or before 825, or before 830.

[0076] At 850, the method may include aligning a third memory die with the first memory die (e.g., one or more first memory die bonded to the second memory die). For example, a third pillar of the third memory die may be positioned to contact a first pad of the first memory die. In some examples, alignment marks (e.g., a first alignment mark and / or one or more second alignment marks) formed on a second side of the third silicon layer may be used to position the third memory die while aligned with the first memory die.

[0077] At 860, the method may include bonding a third memory die to the first memory die to form a multilayer semiconductor device. In some examples, a second type of bonding operation may be used to bond the third memory die to the first memory die. The second type of bonding operation may apply a second pressure and a second temperature that are different from the first temperature and pressure applied during the first type of bonding application. In some examples, the second pressure and the second temperature may be higher than the first temperature and pressure, and bonding the third memory die to the first memory die may establish a connection between the first memory die, the second memory die, and the third memory die.

[0078] At 870, the method may include determining an alignment offset between the third memory die and the first memory die. In some examples, a post-bonding inspection may be performed after bonding the third memory die to the first memory die to determine Figure 2 2 and 3. The alignment offset between the third memory die 230 and the first memory die 210 shown in FIG. The alignment offset can be based on, for example, a displacement along the X-axis, a displacement along the Y-axis, a rotation on the XY plane (e.g., about the Z-axis), or any combination thereof. In some examples, the displacement and rotation can be determined using one or more inspection cameras during post-bonding inspection.

[0079] At 880, the method may include adjusting one or more alignment procedures of a second (or next) multilayer semiconductor being manufactured. For example, when the alignment offset satisfies a threshold, the alignment procedure may be adjusted. In some instances, the threshold may include a parameter corresponding to a displacement along an X-axis, a displacement along a Y-axis, a rotation in an XY plane (e.g., about a Z-axis), or any combination thereof. The second multilayer semiconductor device may include one or more fourth memory dies aligned with a fifth memory die. In some instances, when the alignment offset satisfies the threshold, a value associated with the alignment offset may be used to adjust the placement of a sixth memory die on the fourth memory die. In some instances, the sixth memory die may correspond to Figure 7. Thus, the sixth memory die may include alignment marks (e.g., one or more alignment marks 736-a and 736-b) formed on the second side of the sixth silicon layer. Thus, the alignment marks may be used to adjust the positioning of the sixth memory die.

[0080] Fig. 9 A flowchart illustrating a method 900 for supporting top die backside marking for a memory system according to an example as disclosed herein is shown. The operations of the method 900 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. For example, the method 900 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. Figures 1 to 8 The described manufacturing system or one or more controllers perform the operations of method 900. In some examples, the one or more controllers may execute a set of instructions to control the functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the manufacturing system or one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0081] At 905, the method may include aligning a first memory die with a second memory die, the first memory die including: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die including a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die so that it contacts the second pad of the second memory die.

[0082] At 910, the method may include aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die including a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die is based at least in part on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die so that it contacts the first pad of the first memory die.

[0083] At 915, the method can include bonding a third memory die with the first memory die to form a multi-layered semiconductor device.

[0084] In some examples, an apparatus as described herein may perform one or several methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0085] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions for: aligning a first memory die with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die comprising a second pillar positioned on the first side of the second silicon layer and a second pad positioned on the second side of the second silicon layer, wherein the first memory die is aligned with the first memory die to position the first memory die. a first pillar to contact the second pad of the second memory die; aligning a third memory die with the first memory die based at least in part on the alignment of the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die is based at least in part on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die to contact the first pad of the first memory die; and bonding the third memory die to the first memory die to form a multi-layer semiconductor device.

[0086] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for joining the first memory die with the second memory die based at least in part on aligning the first memory die with the second memory die, wherein aligning the third memory die with the first memory die is based at least in part on joining the first memory die with the second memory die.

[0087] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein the first memory die and the second memory die are bonded together using a first type of bonding operation including a first pressure and a first temperature, and the third memory die and the first memory die are bonded together using a second type of bonding operation including a second pressure and a second temperature.

[0088] Aspect 4: A method, apparatus, or non-temporary computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining an alignment offset between the third memory die and the first memory die based at least in part on the one or more marks and adjusting one or more alignment procedures of the second multilayer semiconductor device based at least in part on the alignment offset.

[0089] Aspect 5: The method, apparatus, or non-temporary computer-readable medium of Aspect 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: aligning a fourth memory die with a fifth memory die of the second multilayer semiconductor device; and as part of the one or more alignment procedures, adjusting the placement of a sixth memory die on the fourth memory die based at least in part on the alignment offset satisfying a threshold.

[0090] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 5, wherein bonding the third memory die together with the first memory die establishes connections between the first memory die, the second memory die, and the third memory die.

[0091] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein joining the third memory die to the first memory die further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for applying a second pressure and a second temperature to the first memory die, the second memory die, and the third memory die based at least in part on aligning the third memory die to the first memory die.

[0092] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming the one or more marks in the second side of the third silicon layer prior to aligning the third memory die.

[0093] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to Aspect 8, wherein forming the one or more marks further includes operations, features, circuit systems, logic, components, or instructions for: identifying a first position of a first alignment mark on the first side of the third silicon layer; and forming a first alignment mark at the first position on the second side of the third silicon layer based at least in part on identifying the first position of the first alignment mark, wherein the one or more marks include the first alignment mark.

[0094] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of Aspect 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for forming one or more second alignment marks at additional locations on the second side of the third silicon layer based at least in part on identifying the first location of the first alignment mark, wherein the one or more marks include the first alignment mark and the one or more second alignment marks.

[0095] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 8 to 10, wherein forming the one or more marks further includes operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: joining the first side of the third memory die to a carrier die; patterning the one or more marks on the second side of the third memory die based at least in part on joining the first side of the third memory die; and de-joining the third memory die from the carrier die.

[0096] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 8 to 11, wherein forming the one or more marks further includes operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: applying a layer of photoresist material on the second side of the third silicon layer; etching the photoresist material and the third silicon layer to form one or more patterns on the second side of the third silicon layer, wherein the one or more marks include the one or more patterns; and removing a portion of the layer of photoresist material from the second side of the third silicon layer based at least in part on etching the one or more patterns.

[0097] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to Aspect 12, wherein removing the photoresist material layer includes operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: performing a wet stripping process to remove the photoresist material layer from the second side of the third silicon layer; and etching the photoresist material and the third silicon layer to form the one or more patterns further includes performing a dry etching process on the second side of the third silicon layer.

[0098] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 13, wherein etching the photoresist material and the third silicon layer to form the one or more patterns further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing a dry etching process on the second side of the third silicon layer.

[0099] Aspect 15: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 14, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for removing the polymer material formed by etching the photoresist material and the third silicon layer based at least in part on etching the one or more patterns.

[0100] Fig.10 A flowchart illustrating a method 1000 for supporting top die backside marking for a memory system according to an example as disclosed herein is shown. The operations of the method 1000 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. Figures 1 to 8 The described manufacturing system or one or more controllers perform the operations of method 1000. In some examples, the one or more controllers may execute a set of instructions to control the functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the manufacturing system or one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0101] At 1005 , a method may include bonding a memory die with a carrier die, the memory die including a silicon layer and one or more pillars positioned on a first side of the silicon layer.

[0102] At 1010 , the method may include identifying a first position of a first alignment mark on a first side of a silicon layer.

[0103] At 1015, the method may include forming one or more second alignment marks at multiple locations on a second side of the silicon layer based at least in part on identifying a first location of the first alignment mark, wherein the first alignment mark and the one or more second alignment marks can be used to align the memory die as a top die in a multi-layer semiconductor device.

[0104] At 1020, the method may include debonding the memory die from the carrier die.

[0105] In some examples, an apparatus as described herein may perform one or several methods, such as method 1000. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0106] Aspect 16: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: bonding a memory die to a carrier die, the memory die comprising a silicon layer and one or more pillars positioned on a first side of the silicon layer; identifying a first position of a first alignment mark on the first side of the silicon layer; forming one or more second alignment marks at multiple positions on a second side of the silicon layer based at least in part on identifying the first position of the first alignment mark, wherein the first alignment mark and the one or more second alignment marks can be used to align the memory die as a top die in a multi-layer semiconductor device; and debonding the memory die from the carrier die.

[0107] Aspect 17: A method, apparatus, or non-transitory computer-readable medium according to Aspect 16, wherein forming the first alignment mark further includes operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: applying a layer of photoresist material on the second side of the silicon layer; etching the photoresist material and the silicon layer to form the one or more second alignment marks on the second side of the silicon layer; and removing a portion of the layer of photoresist material from the second side of the silicon layer based at least in part on etching the one or more second alignment marks.

[0108] Aspect 18: The method, apparatus, or non-transitory computer-readable medium of Aspect 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for removing the polymer material formed by etching the photoresist material and the silicon layer based at least in part on etching the one or more second alignment marks.

[0109] Fig.11 A flowchart illustrating a method 1100 for supporting top die backside marking for a memory system according to an example as disclosed herein is shown. The operations of the method 1100 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. For example, the operations of the method 1100 may be implemented by a manufacturing system or one or more controllers or components thereof as described herein. Figures 1 to 8The described manufacturing system or one or more controllers perform the operations of method 1100. In some examples, the one or more controllers may execute a set of instructions to control the functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the manufacturing system or one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0110] At 1105, the method may include aligning a first memory die with a second memory die, the first memory die including: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die including a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die so that it contacts the second pad of the second memory die.

[0111] At 1110, the method may include aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die including a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die is based at least in part on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die so that it contacts the first pad of the first memory die.

[0112] At 1115, the method can include bonding a third memory die with the first memory die to form a multi-layered semiconductor device.

[0113] At 1120, the method can include determining an alignment offset between the third memory die and the first memory die based at least in part on the one or more markings.

[0114] At 1125 , the method may include adjusting one or more alignment procedures of the second multilayer semiconductor device based at least in part on the alignment offset.

[0115] In some examples, an apparatus as described herein may perform one or several methods, such as method 1100. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0116] Aspect 19: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions for each of the following, or any combination thereof: aligning a first memory die with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die comprising a second pillar positioned on the first side of the second silicon layer and a second pad positioned on the second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die so that it contacts the second pad of the second memory die; and aligning the first memory die based at least in part on positioning the first memory die. A memory die is aligned with the second memory die and a third memory die is aligned with the first memory die, the third memory die including a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die is based at least in part on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die so that it contacts the first pad of the first memory die; the third memory die is bonded together with the first memory die to form a multi-layer semiconductor device; an alignment offset between the third memory die and the first memory die is determined at least in part based on the one or more marks; and one or more alignment procedures of the second multi-layer semiconductor device are adjusted at least in part based on the alignment offset.

[0117] Aspect 20: The method, apparatus, or non-transitory computer-readable medium of Aspect 19, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: aligning a fourth memory die with a fifth memory die of the second multilayer semiconductor device; and as part of the one or more alignment procedures, adjusting the placement of a sixth memory die on the fourth memory die based at least in part on the alignment offset satisfying a threshold.

[0118] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0119] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0120] Aspect 21: A device comprising: a first memory die aligned with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die comprising a second pillar positioned on a first side of the second silicon layer and a second pad positioned on a second side of the second silicon layer, wherein the first memory die has the first pillar of the first memory die in contact with the second pad of the second memory die; a third memory die aligned with the first memory die at least partially based on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein the third memory die causes the third pillar of the third memory die to contact the first pad of the first memory die based at least partially on the one or more marks on the second side of the third silicon layer; and wherein the third memory die is bonded together with the first memory die to form a multilayer semiconductor device.

[0121] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0122] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (e.g., in conductive contact, connected, coupled to each other) if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication with each other (e.g., in conductive contact, connected, coupled to each other) may be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path including an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., a switch or transistor).

[0123] The term "coupled" (e.g., "electrically coupled") may refer to a state of moving from an open circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0124] The terms "layer" and "level" may refer to an organization (e.g., stratum, sheet) of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer or level may include different elements, components, or materials. In some examples, a layer or level may be composed of two or more sub-layers or sub-levels.

[0125] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic.

[0126] The switch components (e.g., transistors) discussed herein may be field effect transistors (FETs), and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may cause the channel to become conductive in some examples. The switch component may be an example of an n-type FET or a p-type FET.

[0127] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0128] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label to distinguish among the similar components. If only the first reference label is used in the specification, the description may apply to any of the similar components with the same first reference label without regard to the additional reference label.

[0129] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may be physically located at various locations, including portions that are distributed such that the functions are implemented at different physical locations.

[0130] The illustrative blocks and modules described herein may be implemented or executed using one or more processors designed to perform the functions described herein, such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0131] As used herein, including in the claims, "or" as used in a list of items (for example, a list of items preceded by a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0132] As used herein, including in the claims, the article "a" before a noun is open-ended and is understood to refer to "at least one" of the noun or "one or more" of the noun. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" may be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The term "the / said" is then used to refer to the component introduced using the article "a" may refer to any one or all of the one or more components. For example, a component introduced using the article "a" may be understood to mean "one or more components", and then referring to "component" in the claims may be understood to be equivalent to referring to "at least one of one or more components". Similarly, the term "the / said" subsequently used to refer to a component introduced as "one or more components" may refer to any or all of the one or more components. For example, subsequently referring to "one or more components" in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0133] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media or combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0134] The description and drawings are provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will appreciate various modifications to the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Aligning a first memory die with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled with the first pillar and the first pad, the second memory die comprising a second pillar positioned on the first side of the second silicon layer and a second pad positioned on the second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die to contact the second pad of the second memory die; aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die is based at least in part on the one or more marks on the second side of the third silicon layer to position the third pillar of the third memory die to contact the first pad of the first memory die; and The third memory die is bonded together with the first memory die to form a multi-layer semiconductor device.

2. The method according to claim 1, further comprising: The first memory die is bonded to the second memory die based at least in part on aligning the first memory die to the second memory die, wherein aligning the third memory die to the first memory die is based at least in part on bonding the first memory die to the second memory die.

3. The method according to claim 2, wherein: bonding the first memory die and the second memory die together using a first type of bonding operation including a first pressure and a first temperature; and Bonding the third memory die with the first memory die uses a second type of bonding operation including a second pressure and a second temperature.

4. The method according to claim 1, further comprising: determining an alignment offset between the third memory die and the first memory die based at least in part on the one or more markings; and One or more alignment procedures of the second multilayer semiconductor device are adjusted based at least in part on the alignment offset.

5. The method according to claim 4, further comprising: aligning a fourth memory die with a fifth memory die of the second multi-layered semiconductor device; and As part of the one or more alignment procedures, placement of a sixth memory die on the fourth memory die is adjusted based at least in part on the alignment offset satisfying a threshold.

6. The method of claim 1, wherein bonding the third memory die together with the first memory die establishes connections between the first memory die, the second memory die, and the third memory die.

7. The method of claim 1 , wherein bonding the third memory die to the first memory die further comprises: A second pressure and a second temperature are applied to the first memory die, the second memory die, and the third memory die based at least in part on aligning the third memory die with the first memory die.

8. The method according to claim 1, further comprising: The one or more marks are formed in the second side of the third silicon layer prior to aligning the third memory die.

9. The method of claim 8, wherein forming the one or more marks further comprises: identifying a first position of a first alignment mark on the second side of the third silicon layer; and A first alignment mark is formed at the first location on the second side of the third silicon layer based at least in part on identifying the first location of the first alignment mark, wherein the one or more marks include the first alignment mark.

10. The method according to claim 9, further comprising: One or more second alignment marks are formed at additional locations on the second side of the third silicon layer based at least in part on identifying the first location of the first alignment mark, wherein the one or more marks include the first alignment mark and the one or more second alignment marks.

11. The method of claim 8, wherein forming the one or more marks further comprises: bonding the first side of the third memory die to a carrier die; patterning the one or more marks on the second side of the third memory die based at least in part on bonding the first side of the third memory die; and The third memory die is debonded from the carrier die.

12. The method of claim 8, wherein forming the one or more marks further comprises: applying a layer of photoresist material on said second side of said third silicon layer; etching the photoresist material and the third silicon layer to form one or more patterns on the second side of the third silicon layer, wherein the one or more marks include the one or more patterns; and A portion of the photoresist material layer is removed from the second side of the third silicon layer based at least in part on etching the one or more patterns.

13. The method according to claim 12, wherein: Removing the photoresist material layer further includes performing a wet strip process to remove the photoresist material layer from the second side of the third silicon layer; and Etching the photoresist material and the third silicon layer to form the one or more patterns further includes performing a dry etching process on the second side of the third silicon layer.

14. The method of claim 12, wherein etching the photoresist material and the third silicon layer to form the one or more patterns further comprises: A dry etching process is performed on the second side of the third silicon layer.

15. The method according to claim 12, further comprising: A polymer material formed by etching the photoresist material and the third silicon layer is removed based at least in part on etching the one or more patterns.

16. A method comprising: bonding a memory die to a carrier die, the memory die comprising a silicon layer and one or more pillars positioned on a first side of the silicon layer; identifying a first position of a first alignment mark on the first side of the silicon layer; forming one or more second alignment marks at a plurality of locations on a second side of the silicon layer based at least in part on identifying the first location of the first alignment mark, wherein the first alignment mark and the one or more second alignment marks can be used to align the memory die as a top die in a multi-layer semiconductor device; as well as The memory die is debonded from the carrier die.

17. The method according to claim 16, wherein forming the first alignment mark further comprises: applying a layer of photoresist material on said second side of said silicon layer; etching the photoresist material and the silicon layer to form the one or more second alignment marks on the second side of the silicon layer; and A portion of the layer of photoresist material is removed from the second side of the silicon layer based at least in part on etching the one or more second alignment marks.

18. The method according to claim 17, further comprising: A polymer material formed by etching the photoresist material and the silicon layer is removed based at least in part on etching the one or more second alignment marks.

19. A method comprising: Aligning a first memory die with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled with the first pillar and the first pad, the second memory die comprising a second pillar positioned on the first side of the second silicon layer and a second pad positioned on the second side of the second silicon layer, wherein aligning the first memory die positions the first pillar of the first memory die to contact the second pad of the second memory die; aligning a third memory die with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein aligning the third memory die positions the third pillar of the third memory die to contact the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer; bonding the third memory die to the first memory die to form a multi-layer semiconductor device; determining an alignment offset between the third memory die and the first memory die based at least in part on the one or more markings; and One or more alignment procedures of the second multilayer semiconductor device are adjusted based at least in part on the alignment offset.

20. The method of claim 19, further comprising: aligning a fourth memory die with a fifth memory die of the second multi-layered semiconductor device; and As part of the one or more alignment procedures, placement of a sixth memory die on the fourth memory die is adjusted based at least in part on the alignment offset satisfying a threshold.

21. An apparatus comprising: a first memory die aligned with a second memory die, the first memory die comprising: a first pillar positioned on a first side of a first silicon layer; a first pad positioned on a second side of the first silicon layer; and a first via extending through the first silicon layer and coupled to the first pillar and the first pad, the second memory die comprising a second pillar positioned on the first side of the second silicon layer and a second pad positioned on the second side of the second silicon layer, wherein the first memory die has the first pillar of the first memory die in contact with the second pad of the second memory die; and a third memory die aligned with the first memory die based at least in part on aligning the first memory die with the second memory die, the third memory die comprising a third pillar positioned on a first side of a third silicon layer and one or more marks on a second side of the third silicon layer, wherein the third memory die contacts the third pillar of the third memory die with the first pad of the first memory die based at least in part on the one or more marks on the second side of the third silicon layer; The third memory die is bonded with the first memory die to form a multi-layer semiconductor device.

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