Semiconductor temporary bonding structure, bonding and de-bonding method and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and provides a temporary semiconductor bonding structure, a bonding and de-bonding method and a semiconductor device. The bonding structure layer is arranged on one side of the first substrate; the bonding structure layer comprises a bonding layer and a second substrate, and the bonding layer is configured to bond the first substrate and the second substrate; the bonding structure layer is configured to have a thermal stress relief dot matrix. According to the invention, the second substrate with an approximate thermal expansion coefficient and lower material cost is temporarily bonded on the back surface of the first substrate, and the thickness of the semiconductor temporary bonding structure is increased through the bonding of the second substrate, so that the wafer is prevented from being damaged in the transfer and high-temperature processing processes, the material cost caused by the consumption of the back reduction material is reduced, and the production efficiency is improved. Meanwhile, through the thermal stress relief dot matrix of the bonding structure layer, wafer damage caused by concentrated thermal stress generated by the semiconductor temporary bonding structure in a high-temperature processing environment can be avoided, and the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a semiconductor temporary bonding structure, a bonding and debonding method and a semiconductor device. Background Art

[0002] Lithium tantalate and lithium niobate crystals are typical multifunctional materials with good piezoelectric, ferroelectric, pyroelectric, acousto-optic, electro-optic, photorefractive and nonlinear physical properties. They are widely used in surface acoustic wave devices, optical communications, lasers and optoelectronics. Lithium tantalate and lithium niobate crystals have large piezoelectric coefficients, so they are suitable for manufacturing substrates for low insertion loss surface acoustic wave filters.

[0003] Surface acoustic wave filters use the special properties of piezoelectric materials to convert electrical signals into surface acoustic waves through interdigital transducers (IDTs) and propagate on the surface of the crystal. The energy of the surface acoustic wave is confined to the contact surface for propagation, and certain frequencies are selectively enhanced or suppressed through specific frequency characteristics, thereby achieving the purpose of filtering. Lithium tantalate and lithium niobate crystals are processed through crystal rod cutting-grinding-polishing-photoresist coating-pattern exposure-pattern development-electrode coating-electrode etching, and the back of the substrate is thinned during the packaging stage and then packaged into devices.

[0004] Currently, the cost of lithium tantalate and lithium niobate materials is high, and due to the limitation of the surface acoustic wave filter processing platform, the thickness of lithium tantalate 6-inch wafer usually needs to be >350um, and the thickness of lithium niobate 6-inch wafer usually needs to be >500um. The use of backside thinning technology will lead to higher semiconductor post-processing costs, and reducing the thickness of lithium tantalate and lithium niobate materials can effectively reduce the manufacturing costs of lithium tantalate and lithium niobate.

[0005] The 6-inch lithium tantalate or lithium niobate substrate required for the current surface acoustic wave filter needs to have a lithium tantalate thickness of >350um and a lithium niobate thickness of >500um. Then, electrodes are made on the surface through a coating process to realize the surface acoustic wave vibration. Considering that during the wafer processing, the entire substrate wafer needs to be transferred and the high temperature environment of the coating is likely to cause the wafer to break, so the incoming substrate is made relatively thick. After the electrode is made on one side of the substrate wafer, the entire back of the wafer needs to be thinned according to the device thickness requirements, and the final wafer thickness is controlled at 150~250um. The process flow is as follows: Figure 1 This process causes huge waste of substrate materials, and its material cost naturally becomes high.

[0006] On the other hand, in the process of preparing integrated circuits using silicon wafers made of single crystal silicon, there is also the problem of making the substrate too thick in order to provide a higher strength wafer substrate, resulting in high substrate material costs.

[0007] Therefore, how to reduce the high cost of substrate materials caused by the need to make the substrate thick enough to maintain substrate strength during the semiconductor device manufacturing process is an urgent problem to be solved. Summary of the invention

[0008] In order to solve at least one technical problem in the above-mentioned prior art, the present invention provides a semiconductor temporary bonding structure, a bonding and debonding method and a semiconductor device.

[0009] In a first aspect of the present invention, a semiconductor temporary bonding structure is provided, comprising: a first substrate; A bonding structure layer, disposed on one side of the first substrate; Wherein, the bonding structure layer comprises a bonding layer and a second substrate, and the bonding layer is configured to bond the first substrate and the second substrate; Wherein, the bonding structure layer is configured to have a thermal stress relief lattice.

[0010] Optionally, the material of the first substrate includes lithium tantalate, lithium niobate or single crystal silicon; the material of the second substrate includes glass, silicon wafer or ceramic.

[0011] Optionally, the bonding layer is configured as a dotted arrangement; The bonding layer arranged in a lattice between the first substrate and the second substrate forms a bonding lattice, and the bonding lattice and the second substrate form a bonding structure layer having a thermal stress relief lattice on one side of the first substrate.

[0012] Optionally, the second substrate is configured as a dot-shaped substrate structure; Wherein, each bonding unit in the bonding lattice is respectively bonded to the first substrate and each substrate unit in the dot-shaped substrate structure, and the dot-shaped substrate structure and the bonding lattice form a bonding structure layer having a thermal stress relief lattice on one side of the first substrate.

[0013] Optionally, a size of a vertical projection of each bonding unit in the bonding lattice on the first substrate is smaller than a size of a vertical projection of each substrate unit having a bonding relationship in the dot-shaped substrate structure on the first substrate.

[0014] Optionally, each thermal stress relief unit in the thermal stress relief lattice is connected to other thermal stress relief units around it to form a thermal stress relief grid.

[0015] Optionally, the bonding layer is an adhesive bonding layer formed by curing an adhesive or a sintered bonding layer formed by sintering a sintered material.

[0016] In a second aspect of the present invention, a bonding method for a semiconductor temporary bonding structure is provided, which is used for the semiconductor temporary bonding structure as described in any one of the above items, comprising: providing a first substrate and a second substrate; forming a bonding layer on one side of the first substrate; The first substrate and the second substrate are bonded via the bonding layer, so that the second substrate and the bonding layer form a bonding structure layer having a thermal stress relief lattice.

[0017] Optionally, forming a bonding layer on one side of the first substrate includes: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; Each bonding unit in the bonding lattice formed by the bonding layer arranged in a lattice manner bonds the first substrate and the second substrate respectively, so that the bonding lattice constitutes a thermal stress relief lattice of the bonding structure layer.

[0018] Optionally, providing a second substrate includes: providing a second substrate with a dot-shaped substrate structure; A bonding layer is formed on one side of the first substrate, comprising: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; The first substrate is bonded to each substrate unit in the dot-shaped substrate structure through each bonding unit in the bonding lattice, so that the dot-shaped substrate structure and the bonding lattice form a thermal stress relief lattice of the bonding structure layer.

[0019] A third aspect of the present invention provides a method for debonding a semiconductor temporary bonding structure, which is used for the semiconductor temporary bonding structure as described in any one of the above items, comprising: The bonding structure layer in the semiconductor temporary bonding structure is removed by grinding and thinning or acid etching. A fourth aspect of the present invention provides a semiconductor device, which is prepared by using the bonding method of a semiconductor temporary bonding structure as described in any one of the above and / or the debonding method of a semiconductor temporary bonding structure as described in the above.

[0020] The beneficial effects of the present invention are embodied in: Provided are a semiconductor temporary bonding structure, a bonding and debonding method, and a semiconductor device. By temporarily bonding a second substrate having a similar thermal expansion coefficient to a first substrate but with a lower material cost on the back side of the first substrate, the thickness of the semiconductor temporary bonding structure can be increased by bonding the second substrate, thereby avoiding damage to the wafer during transfer and high-temperature processing, and reducing the material cost caused by material consumption during the back reduction process. At the same time, by means of a thermal stress relief lattice of a bonding structure layer formed by the bonding layer and the second substrate, damage to the wafer caused by concentrated thermal stress generated by the semiconductor temporary bonding structure in a high-temperature processing environment can be avoided, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is the schematic diagram of the process of surface acoustic wave filter processing; Figure 2 It is a first cross-sectional structural principle diagram of the semiconductor temporary bonding structure of the present invention; Figure 3 It is a thermal stress analysis diagram of direct bonding of two different substrate materials in the first cross-sectional structure of the semiconductor temporary bonding structure of the present invention; Figure 4 It is a second cross-sectional structural principle diagram of the semiconductor temporary bonding structure of the present invention; Figure 5 It is a thermal stress analysis diagram of direct bonding of two different substrate materials in the second cross-sectional structure of the semiconductor temporary bonding structure of the present invention; Figure 6 It is a third cross-sectional structural principle diagram of the semiconductor temporary bonding structure of the present invention; Figure 7 is a third cross-sectional structural schematic diagram of the semiconductor temporary bonding structure of the present invention; Figure 8 It is a schematic structural diagram of a square-shaped bonding unit and a substrate unit; Fig. 9 It is a structural schematic diagram of a circular bonding unit and a substrate unit; Fig.10 It is a schematic structural diagram of a thermal stress relief grid formed by a thermal stress relief lattice of the present invention; Fig.11 It is a thermal stress analysis diagram of direct bonding of two different substrate materials in the third cross-sectional structure of the semiconductor temporary bonding structure of the present invention; Fig.12 is a fourth cross-sectional structural principle diagram of the semiconductor temporary bonding structure of the present invention; Fig.13 is a fourth cross-sectional structural schematic diagram of the semiconductor temporary bonding structure of the present invention; Fig.14It is a thermal stress analysis diagram of direct bonding of two different substrate materials in the fourth cross-sectional structure of the semiconductor temporary bonding structure of the present invention; Fig.15 is a flow chart of a bonding method of a semiconductor temporary bonding structure of the present invention; Fig.16 The present invention is a flowchart of a method for debonding a semiconductor temporary bonding structure.

[0022] Reference numerals: 1-first substrate; 2-bonding structure layer; 21-bonding layer; 22-second substrate. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Embodiment 1: Reference Figure 2 , Figure 2 A cross-sectional structural schematic diagram of a semiconductor temporary bonding structure is provided. Embodiment 1 of the present invention provides a semiconductor temporary bonding structure, which includes: a first substrate 21; a bonding structure layer, which is arranged on one side of the first substrate 21; wherein the bonding structure layer includes a bonding layer 21 and a second substrate 22, and the bonding layer 21 is configured to bond the first substrate 21 to the second substrate 22.

[0025] It should be noted that in the preparation process of the surface acoustic wave filter, the material of the first substrate 21 is preferably lithium tantalate or lithium niobate, and the thickness of the first substrate 21 is preferably 150-250 um. In the preparation process of the integrated circuit, the material of the first substrate 21 is further preferably single crystal silicon.

[0026] It should be noted that the material of the second substrate 22 is preferably glass, silicon wafer and ceramic, and the thickness of the second substrate 22 is preferably 20-500 um.

[0027] It should be noted that the bonding layer 21 is an adhesive bonding layer solidified by an adhesive or a sintered bonding layer sintered by a sintered material. When the bonding layer 21 is an adhesive bonding layer, the bonding layer 21 is preferably solidified by an adhesive that is not easily volatilized at high temperatures. When applying the adhesive, the adhesive coating thickness is controlled within the range of 1 to 20 um, and the coating uniformity is less than 0.2 um. When the bonding layer 21 is a sintered bonding layer, the bonding layer 21 is preferably sintered by glass powder.

[0028] It should be noted that, in the packaging stage after the subsequent processing of the semiconductor temporary bonding structure is completed, it is preferred to remove the bonding structure layer in the semiconductor temporary bonding structure by grinding and thinning or acid etching.

[0029] It should be noted that, since the first substrate 21 and the second substrate 22 are made of different substrate materials, considering that the thermal expansion coefficients of the two different materials are different during the later processing of the structural substrate, especially in the high-temperature coating environment, when the first substrate 21 is made of lithium tantalate material and the second substrate 22 is made of glass material, Figure 3 As shown, the thermal stress value of the bonding between the first substrate 21 and the second substrate 22 is 6.2e6Pa, which exceeds the maximum thermal stress value of lithium tantalate 1.2e6Pa, which easily leads to excessive thermal stress and wafer damage. In order to solve this problem, when selecting the second substrate 22 in this embodiment, it is preferred that the first substrate 21 and the second substrate 22 are substrate materials with similar thermal expansion coefficients to meet the thermal adaptation effect. When the substrate material is affected by high temperature, the wafer will not be damaged due to the different expansion of the two substrate materials.

[0030] In this embodiment, the semiconductor temporary bonding structure adopts a bonding structure layer set on one side of the first substrate 21, and the bonding layer 21 in the bonding structure layer is used to bond the structure of the first substrate 21 and the second substrate 22. The bonding of the second substrate 22 can increase the thickness of the semiconductor temporary bonding structure, and avoid the damage of the wafer during the transfer and high-temperature processing. At the same time, the first substrate 21 is configured as a wafer substrate with good material properties but more expensive, and the second substrate 22 is configured as a wafer substrate with a lower price but poor material properties. The second substrate 22 is preferably a substrate material with a thermal expansion coefficient close to that of the first substrate 21. Therefore, by temporarily bonding the second substrate 22 with a similar thermal expansion coefficient but lower material cost on the back of the first substrate 21, the material cost caused by the consumption of back-reduced materials is reduced.

[0031] In view of the situation that the bonding of the above two substrate materials with different expansion coefficients causes excessive deformation and breakage due to heat, this embodiment proposes a thermal stress relief lattice set in the bonding structure layer, which is used to release thermal stress to solve the problem of chip breakage.

[0032] Reference Figure 4 , Figure 4A second cross-sectional structural schematic diagram of a semiconductor temporary bonding structure is provided. In a preferred embodiment, the bonding structure layer is configured to have a thermal stress relief lattice, and the bonding layer 21 is configured to be arranged in a lattice; wherein the bonding layer 21 arranged in a lattice between the first substrate 21 and the second substrate 22 forms a bonding lattice, and the bonding lattice and the second substrate 22 form a bonding structure layer having a thermal stress relief lattice on one side of the first substrate 21.

[0033] It should be noted that, in the bonding lattice formed by the bonding layer 21 arranged in a lattice, the shape of each bonding unit is preferably square or circular.

[0034] In this embodiment, the bonding layer 21 used to bond the first substrate 21 and the second substrate 22 is arranged in a lattice, and the bonding lattice after the lattice arrangement and the second substrate 22 together constitute a bonding structure layer, and all the bonding units in the bonding lattice form a thermal stress relief lattice on the bonding structure layer. Such a bonding structure layer can release the thermal stress generated by the first substrate 21 in a high temperature environment, and avoid the chip damage caused by the different expansion coefficients of the first substrate 21 and the second substrate 22. Figure 5 As shown, a thermal stress analysis is performed on the semiconductor temporary bonding structure provided in this embodiment. The maximum stress at the edge of the bonding surface between the second substrate 22 material and the first substrate 21 material is 1.1e6Pa, and the stress value at the bonding surface between the middle lattice area and the first substrate 21 is only 0.8e6Pa, which can effectively prevent stress concentration from causing chip cracking.

[0035] Reference Figure 6 , Figure 6 A third cross-sectional structural schematic diagram of a semiconductor temporary bonding structure is provided. In a preferred embodiment, on the basis that the bonding layer 21 is configured as a dot matrix setting, the second substrate 22 is configured as a dot-shaped substrate structure; wherein each bonding unit in the bonding dot matrix is ​​respectively bonded to the first substrate 21 and each substrate unit in the dot-shaped substrate structure, and the dot-shaped substrate structure and the bonding dot matrix form a bonding structure layer having a thermal stress relief dot matrix on one side of the first substrate 21, such as Figure 7 shown.

[0036] It should be noted that the shape of each bonding unit in the bonding lattice formed by the bonding layer 21 arranged in a lattice and each substrate unit in the first substrate 21 configured as a dot-shaped substrate structure is preferably square or circular. Figure 8 and Fig. 9 shown.

[0037] It should be noted that each thermal stress relief unit in the thermal stress relief lattice is connected to other thermal stress relief units around it to form a thermal stress relief grid (the thermal stress relief grid can be formed by a single bonding unit in the bonding lattice, or by the bonding lattice and the bonding units in the second substrate and the substrate units together forming a thermal stress relief grid). Since the thermal stress relief grid has each thermal stress relief unit in the thermal stress relief lattice, it can also release the thermal stress generated by the first substrate 21 when processed in a high temperature environment, such as Fig.10 shown.

[0038] It should be noted that any other thermal stress relief structure formed based on the thermal stress relief lattice of the present invention, because it has the thermal stress relief unit in the thermal stress relief lattice of the present invention, also has the effect of releasing the thermal stress generated by the first substrate 21 during processing in a high temperature environment, and should be within the scope of the present invention.

[0039] In this embodiment, the bonding layer 21 used for bonding the first substrate 21 and the second substrate 22 is arranged in a dot matrix, and the second substrate 22 is configured as a dot-shaped substrate structure. Each bonding unit in the dot matrix after the dot matrix arrangement and each substrate unit in the dot-shaped substrate structure together constitute a bonding structure layer. Each bonding unit with a bonding relationship and the substrate unit together form a thermal stress relief dot matrix on the bonding structure layer. Such a bonding structure layer can further release the thermal stress generated by the first substrate 21 in a high temperature environment, and avoid chip damage caused by the different expansion coefficients of the first substrate 21 and the second substrate 22. Fig.11 As shown, a thermal stress analysis is performed on the semiconductor temporary bonding structure provided in this embodiment. The maximum stress at the edge of the bonding surface between the second substrate 22 material and the first substrate 21 material is 0.85e6Pa, and the stress value at the bonding surface between the middle lattice area and the first substrate 21 is only 0.75e6Pa, which can effectively prevent stress concentration from causing chip cracking.

[0040] Reference Fig.12 , Fig.12 A fourth cross-sectional structural schematic diagram of a semiconductor temporary bonding structure is provided. In a preferred embodiment, the bonding layer 21 is configured as a dot matrix arrangement, the second substrate 22 is configured as a dot-shaped substrate structure, and each bonding unit is respectively bonded to the first substrate 21 and each substrate unit. The size of the vertical projection of each bonding unit in the bonding dot matrix on the first substrate 21 is smaller than the size of the vertical projection of each substrate unit having a bonding relationship in the dot-shaped substrate structure on the first substrate 21. Fig.13 shown.

[0041] In this embodiment, the bonding layer 21 used to bond the first substrate 21 and the second substrate 22 is arranged in a dot matrix, and the second substrate 22 is configured as a dot substrate structure. On the basis of each bonding unit respectively bonding the first substrate 21 and each substrate unit, each substrate unit and each bonding unit with a smaller size together constitute a bonding structure layer, and each bonding unit with a bonding relationship and the substrate unit together form a thermal stress relief dot matrix on the bonding structure layer. Such a bonding structure layer can further release the thermal stress generated by the first substrate 21 in a high temperature environment, and avoid chip damage caused by the different expansion coefficients of the first substrate 21 and the second substrate 22. Fig.14 As shown, a thermal stress analysis is performed on the semiconductor temporary bonding structure provided in this embodiment. The maximum stress at the edge of the bonding surface between the second substrate 22 material and the first substrate 21 material is 0.75e6Pa, and the stress value at the bonding surface between the middle lattice area and the first substrate 21 is only 0.6e6Pa, which can effectively prevent stress concentration from causing chip cracking.

[0042] Embodiment 2: Reference Fig.15 , Fig.15 This is a flow chart of a bonding method for a semiconductor temporary bonding structure according to Embodiment 2 of the present invention. The bonding method for a semiconductor temporary bonding structure is used for a semiconductor temporary bonding structure as described in any one of the above items, comprising: S1: providing a first substrate and a second substrate; S2: forming a bonding layer on one side of the first substrate; S3: bonding the first substrate and the second substrate via the bonding layer, so that the second substrate and the bonding layer form a bonding structure layer having a thermal stress relief lattice.

[0043] In this embodiment, the bonding preparation of the semiconductor temporary bonding structure adopts a method of setting a bonding structure layer on one side of the first substrate, and bonding the first substrate and the second substrate using the bonding layer in the bonding structure layer. The bonding of the second substrate can increase the thickness of the semiconductor temporary bonding structure, and avoid the damage of the wafer during the transfer and high-temperature processing. Therefore, by temporarily bonding the second substrate with a similar thermal expansion coefficient but lower material cost on the back of the first substrate, the material cost caused by the consumption of back-reducing materials is reduced.

[0044] At the same time, the bonding layer used to bond the first substrate and the second substrate is arranged in a dot matrix. The bonding matrix after the dot matrix arrangement and the second substrate together constitute a bonding structure layer. All bonding units in the bonding matrix form a thermal stress relief matrix on the bonding structure layer. Such a bonding structure layer can release the thermal stress generated by the first substrate when processed in a high-temperature environment, thereby avoiding chip damage caused by the different expansion coefficients of the first substrate and the second substrate.

[0045] In a preferred embodiment, forming a bonding layer on one side of the first substrate includes: S211: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; S212: each bonding unit in the bonding lattice formed by the lattice-arranged bonding layer is bonded to the first substrate and the second substrate respectively, so that the bonding lattice constitutes a thermal stress relief lattice of the bonding structure layer.

[0046] In this embodiment, the bonding layer used to bond the first substrate and the second substrate is arranged in a dot matrix. The bonding matrix after the dot matrix arrangement and the second substrate together constitute a bonding structure layer. All bonding units in the bonding matrix form a thermal stress relief matrix on the bonding structure layer. Such a bonding structure layer can release the thermal stress generated by the first substrate when processed in a high-temperature environment, thereby avoiding chip damage caused by the different expansion coefficients of the first substrate and the second substrate.

[0047] In a preferred embodiment, providing a second substrate comprises: providing a second substrate with a dot-shaped substrate structure; forming a bonding layer on one side of the first substrate comprises: S221: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; S222: respectively bonding the first substrate to each substrate unit in the dot-shaped substrate structure through each bonding unit in the bonding lattice, so that the dot-shaped substrate structure and the bonding lattice constitute a thermal stress relief lattice of the bonding structure layer.

[0048] In this embodiment, the bonding layer used to bond the first substrate and the second substrate is arranged in a dot matrix, and the second substrate is configured as a dot-shaped substrate structure. On the basis of each bonding unit respectively bonding the first substrate and each substrate unit, each substrate unit and each bonding unit with a smaller size together constitute a bonding structure layer, and each bonding unit with a bonding relationship and the substrate unit together form a thermal stress relief dot matrix on the bonding structure layer. Such a bonding structure layer can further release the thermal stress generated by the first substrate in a high-temperature environment, thereby avoiding chip damage caused by the different expansion coefficients of the first substrate and the second substrate.

[0049] Embodiment 3: Reference Fig.16 , Fig.16 This is a flow chart of a method for debonding a semiconductor temporary bonding structure according to Embodiment 3 of the present invention. The method for debonding a semiconductor temporary bonding structure is used for a semiconductor temporary bonding structure as described in any one of the above items, comprising: S1: removing the bonding structure layer in the semiconductor temporary bonding structure by grinding and thinning or acid etching.

[0050] In this embodiment, in the packaging stage after the subsequent processing of the semiconductor temporary bonding structure is completed, it is preferred to remove the bonding structure layer in the semiconductor temporary bonding structure by grinding thinning or acid etching. Thus, by temporarily bonding a second substrate with a similar thermal expansion coefficient but lower material cost to the back side of the first substrate, compared with thinning the first substrate material in the traditional method, the material cost caused by the consumption of back thinning material is reduced.

[0051] Embodiment 4: Provided is a semiconductor device, which is manufactured using any of the bonding methods for a semiconductor temporary bonding structure as described above and / or the debonding method for a semiconductor temporary bonding structure as described above.

[0052] In the description of the embodiments of the present invention, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0053] In the description of the embodiments of the present invention, it should be understood that "-" and "~" represent a range between two values, and the range includes the endpoints. For example: "AB" represents a range greater than or equal to A and less than or equal to B. "A~B" represents a range greater than or equal to A and less than or equal to B.

[0054] In the description of the embodiments of the present invention, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein generally indicates that the associated objects before and after are in an "or" relationship.

[0055] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor temporary bonding structure, characterized in that: include: a first substrate; A bonding structure layer, disposed on one side of the first substrate; Wherein, the bonding structure layer comprises a bonding layer and a second substrate, and the bonding layer is configured to bond the first substrate and the second substrate; Wherein, the bonding structure layer is configured to have a thermal stress relief lattice.

2. The semiconductor temporary bonding structure according to claim 1, characterized in that: The material of the first substrate includes lithium tantalate, lithium niobate or single crystal silicon; the material of the second substrate includes glass, silicon wafer or ceramic.

3. The semiconductor temporary bonding structure according to claim 1, characterized in that: The bonding layer is configured as a dotted arrangement; The bonding layer arranged in a lattice between the first substrate and the second substrate forms a bonding lattice, and the bonding lattice and the second substrate form a bonding structure layer having a thermal stress relief lattice on one side of the first substrate.

4. The semiconductor temporary bonding structure according to claim 3, characterized in that: The second substrate is configured as a dot-shaped substrate structure; Wherein, each bonding unit in the bonding lattice is respectively bonded to the first substrate and each substrate unit in the dot-shaped substrate structure, and the dot-shaped substrate structure and the bonding lattice form a bonding structure layer having a thermal stress relief lattice on one side of the first substrate.

5. The semiconductor temporary bonding structure according to claim 4, characterized in that: The size of a vertical projection of each bonding unit in the bonding lattice on the first substrate is smaller than the size of a vertical projection of each substrate unit having a bonding relationship in the dot-shaped substrate structure on the first substrate.

6. The semiconductor temporary bonding structure according to claim 1, characterized in that: Each thermal stress relief unit in the thermal stress relief lattice is connected with other thermal stress relief units around it to form a thermal stress relief grid.

7. The semiconductor temporary bonding structure according to claim 1, characterized in that: The bonding layer is an adhesive bonding layer formed by curing an adhesive or a sintered bonding layer formed by sintering a sintered material.

8. A bonding method for a semiconductor temporary bonding structure, characterized in that: A semiconductor temporary bonding structure as claimed in any one of claims 1 to 7, comprising: providing a first substrate and a second substrate; forming a bonding layer on one side of the first substrate; The first substrate and the second substrate are bonded via the bonding layer, so that the second substrate and the bonding layer form a bonding structure layer having a thermal stress relief lattice.

9. The bonding method of a semiconductor temporary bonding structure according to claim 8, characterized in that: A bonding layer is formed on one side of the first substrate, comprising: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; Each bonding unit in the bonding lattice formed by the bonding layer arranged in a lattice manner bonds the first substrate and the second substrate respectively, so that the bonding lattice constitutes a thermal stress relief lattice of the bonding structure layer.

10. The bonding method of a semiconductor temporary bonding structure according to claim 9, characterized in that: Providing a second substrate includes: providing a second substrate with a dot-shaped substrate structure; A bonding layer is formed on one side of the first substrate, comprising: forming a bonding layer arranged in a dotted pattern on one side of the first substrate; The first substrate is bonded to each substrate unit in the dot-shaped substrate structure through each bonding unit in the bonding lattice, so that the dot-shaped substrate structure and the bonding lattice form a thermal stress relief lattice of the bonding structure layer.

11. A method for debonding a semiconductor temporary bonding structure, characterized in that: A semiconductor temporary bonding structure as claimed in any one of claims 1 to 7, comprising: The bonding structure layer in the semiconductor temporary bonding structure is removed by grinding and thinning or acid etching.

12. A semiconductor device, characterized in that: A semiconductor device manufactured using the bonding method of a semiconductor temporary bonding structure as described in any one of claims 8 to 10 and / or the debonding method of a semiconductor temporary bonding structure as described in claim 11.

Images