Array of memory cells individually including capacitors and transistors and methods of forming such arrays

Abstract

Embodiments of the invention relate to arrays of memory cells individually including capacitors and transistors and methods of forming such arrays. An array of memory cells individually including capacitors and transistors includes alternating columns of digital lines and conductive shield lines in a first level. In a second level above the first level, there is a row of transistor word lines. In a third level above the second level, rows and columns of capacitors are present. In a fourth level above the third level, there is a row of transistor word lines. In a fifth level above the fourth level, there are alternating columns of digital lines and conductive shielded lines. Other embodiments and aspects, including methods, are disclosed.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of an invention patent application with an application date of September 21, 2020, application number "201980020589.2", and invention name "Memory cell array individually including capacitors and transistors and method of forming such an array". Technical Field

[0003] Embodiments disclosed herein relate to arrays of memory cells that individually include capacitors and transistors. Background Art

[0004] Memory is a type of integrated circuit system and it is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, sense lines, or data / sense lines) and word lines (which may also be referred to as access lines). Digit lines can conductively interconnect memory cells along columns of the array, and word lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and word lines.

[0005] A continuing goal when manufacturing memory circuitry is to form smaller and denser components of memory cells. Unfortunately, as conductors are placed closer together, undesirable parasitic capacitances appear and grow, and can adversely affect the design and operation of the memory circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagrammatic cross-sectional view of a substrate configuration according to an embodiment of the present invention, and is a cross-sectional view through Figure 2 The line 1-1 is obtained.

[0007] Figure 2 yes Figure 1 A cross-sectional view of a portion of the structure, and which is through Figure 1 The line 2-2 is obtained.

[0008] Figure 3 yes Figure 1 and 2 A diagrammatic perspective view of a construction with certain material removed for clarity.

[0009] Figure 4 is a diagrammatic cross-sectional view of a substrate configuration according to an embodiment of the present invention.

[0010] Figure 5 is a diagrammatic cross-sectional view of a substrate configuration according to an embodiment of the present invention.

[0011] Figure 6 is a process in the process according to an embodiment of the present invention Figure 1 A diagrammatic cross-sectional view of a portion of a leading construction of a construction.

[0012] Figure 7 It is in the Figure 6 The processing steps after the steps shown are Figure 6 Constructed view.

[0013] Figure 8 It is in the Figure 7 The processing steps after the steps shown are Figure 7 Constructed view.

[0014] Fig. 9 is a process in the process according to an embodiment of the present invention Figure 1 A diagrammatic cross-sectional view of a portion of a leading construction of a construction.

[0015] Fig.10 It is in the Fig. 9 The processing steps after the steps shown are Fig. 9 Constructed view.

[0016] Fig.11 It is in the Fig.10 The processing steps after the steps shown are Fig.10 Constructed view. DETAILED DESCRIPTION

[0017] Embodiments of the present invention include memory cell arrays that individually include capacitors and transistors and methods of forming such arrays. Figures 1 to 3 Describing example embodiments, Figures 1 to 3 The display includes a base substrate 11 ( Figure 1 ) is an example fragment of a substrate construction 8 of an array or array region 10 manufactured by using a substrate 11. The substrate 11 may include any one or more of a conductive / conductor / conductive (i.e., conductive herein), a semiconductive / semiconductor / semiconductive, and an insulating / memory / insulating (i.e., electrically insulating herein) material. Various materials are above the base substrate 11. The materials may be Figures 1 to 3 The depicted material may be located next to, inwardly from, or outwardly from the depicted material. For example, other partially or fully manufactured components of the integrated circuit system may be provided somewhere above, around, or within the base substrate 11. Control and / or other peripheral circuitry for operating components within the memory array may also be manufactured and may or may not be completely or partially within the memory array or sub-array. In addition, multiple sub-arrays may also be manufactured or operated independently, in conjunction, or otherwise relative to each other. As used in the present invention, a "sub-array" may also be considered an array. To make certain operating components clearer, Figure 3 The base substrate 11 is not shown and the surrounding dielectric isolation material is not shown.

[0018] Array 10 includes memory cells 75 that individually include capacitors 85 and transistors 25. In one embodiment, transistors 25 are highly extended transistors and are vertical or within 10° of vertical in one such embodiment. In one embodiment, memory cells 75 individually have only one transistor in total and only one capacitor in total (e.g., a 1T-1C memory cell with only one transistor and only one capacitor and no other / additional operable electronic components [e.g., no other selection devices, etc.]). Array 10 includes a first level 12 having columns 14 of alternating digit lines 16 and columns 18 of conductive shield lines 20 (e.g., which shield in operation or at least reduce parasitic capacitance between adjacent digit lines 16 compared to parasitic capacitance that would otherwise occur in the absence of shield lines 20). "Columns" and "rows" are used in the present invention for convenience in distinguishing one series of lines from another series of lines. Columns may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may rows. In addition, columns and rows may intersect at 90° or one or more other angles relative to each other. Lines 16 and 20 may include, consist essentially of, or consist of any suitable conductive material(s) (eg, conductively doped semiconductor materials and / or metallic materials).For example, shield line 20 may be narrower (eg, 50%) than digit line 16, as shown.

[0019] Figures 1 to 3 An example ideal embodiment is shown in which the columns 14 of first-level digit lines 16 and the columns 18 of first-level conductive shield lines 20 alternate with each other every other, such that each immediately adjacent digit line 16 of the first-level digit lines 16 has one of the first-level conductive shield lines 20 laterally interposed therebetween, and such that each immediately adjacent shield line 20 of the first-level conductive shield lines 20 has one of the first-level digit lines 16 laterally interposed therebetween. However, in one embodiment, one of the first-level conductive shield lines is laterally interposed between each immediately adjacent digit line of the first-level digit lines, regardless of what may be laterally interposed between the immediately adjacent shield lines (e.g., two or more shield lines may be laterally interposed between each or some of the immediately adjacent first-level digit lines). Further alternatively, the columns of digit lines and the columns of conductive shield lines may alternate in other ways, such as, for example, pairs of two immediately adjacent digit lines alternate with pairs of two immediately adjacent conductive shield lines, or in other ways.

[0020] The array 10 has a second level 22 having highly extended transistors 25 therein, each of which includes an upper source / drain region 24, a lower source / drain region 26, and a channel region 28 extending in height therebetween. Rows 30 of second level word lines 32 (e.g., comprising, consisting essentially of, or consisting of conductively doped semiconductor material and / or metallic material) operably extend adjacent to and interconnect the second level transistors 25 in the second level rows 30 of respective second level transistors 25 of respective memory cells 75 within the array 10. A gate insulator 34 (e.g., comprising, consisting essentially of, or consisting of silicon dioxide, silicon nitride, and / or ferroelectric material) is interposed between the word lines 32 and the channel regions 28. Each of the source / drain regions 24, 26 includes at least a portion thereof having a conductivity-increasing dopant therein, which has a maximum concentration of such conductivity-increasing dopant within the respective source / drain region 24, 26 to, for example, render such portion conductive (e.g., having at least 10 19 atoms / cm 3 ). Thus, all or only a portion of each of source / drain regions 24, 26 may have this maximum concentration of conductivity increasing dopant. Source / drain regions 24 and / or 26 may include other doped regions (not shown), such as halo regions, LDD regions, etc. Channel region 28 may be suitably doped with a conductivity increasing dopant, which may be of the opposite conductivity type to the dopant in source / drain regions 24, 26, and, for example, at no greater than 1×10 16 atoms / cm 3 When a suitable voltage is applied to word line 32, a conductive channel may be formed within channel region 28 so that current may flow between source / drain regions 24 and 26. Individuals of first level digit lines 16 are electrically coupled (in one embodiment directly electrically coupled) to individual lower source / drain regions 26 of individual second level transistors 25, where such digit lines interconnect second level transistors 25 along second level columns.

[0021] The array 10 has a third level 36 above the second level 22, with rows and columns of capacitors 85 in the third level 36. In one embodiment, the capacitors 85 are arranged in a 2D Bravais lattice. In one such embodiment, the 2D Bravais lattice is not hexagonal or centered rectangular, and in one embodiment, it is one of square or non-centered rectangular, with a square 2D Bravais lattice being shown. However, other Bravais lattices (e.g., hexagonal or centered rectangular) and non-Bravais lattices may be used.

[0022] The capacitors 85 each include a first capacitor electrode 38 (38x or 38y) (conductive material), a second capacitor electrode 40 (conductive material), and a capacitor insulator 42 material (e.g., silicon dioxide, silicon nitride, and / or ferroelectric material) interposed (laterally interposed in one embodiment) between the first capacitor electrode and the second capacitor electrode. To make other components clear, Figure 3 38x / 38y) is a pillar having a substantially circular periphery 39. Regardless, in one such embodiment, each of the capacitors 85 has only one capacitor electrode (e.g., 38x / 38y) having a height greater than the width, wherein each of the capacitors 85 has its other capacitor electrode (e.g., 40) common to all capacitors 85 in the third level 36 of the array 10, wherein this common other electrode in the array 10 has a width greater than the height. In one embodiment and as shown, individual ones of the first capacitor electrodes (e.g., 38x) are electrically coupled to (in one embodiment directly electrically coupled to) individual upper source / drain regions 24 of individual second level transistors 25 and extend upward in height from the upper source / drain regions 24.

[0023] The fourth level 46 is above the third level 36 and has therein height extension transistors 25 similar to the transistors 25 described above with respect to the second level 22. However, respective other ones of the first capacitor electrodes (e.g., 38y) are electrically coupled to (in one embodiment directly electrically coupled to) respective ones of the lower source / drain regions 26 of the respective fourth level transistors 25.

[0024] The fifth level 50 is above the fourth level 46 and has therein columns 14 of digit lines 16 and columns 18 of conductive shield lines 20. Individuals of the fifth level digit lines 16 are electrically coupled (in one embodiment directly electrically coupled) to individual upper source / drain regions 24 of individual fourth level transistors 25 and interconnect the fourth level transistors 25 in the fourth level columns. The alternating relationship(s) of the columns 14 and 18 in the fifth level 50 may be the same or different than the described alternation of the columns 14 and 18 in the second level 22 and may have any of their attributes. In an ideal embodiment and as shown, the fifth level digit line 16 columns 14 and the fifth level conductive shield line 20 columns 18 alternate with each other every other, such that each immediately adjacent digit line 16 of the fifth level digit line 16 has one of the fifth level conductive shield lines 20 laterally interposed therebetween, and such that each immediately adjacent shield line 20 of the fifth level conductive shield line 20 has one of the fifth level digit lines 16 laterally interposed therebetween. Dielectric material 35 (e.g., silicon dioxide and / or silicon nitride; Figure 1) is shown as surrounding the above structure. In operation, the conductive shield line 20 will likely be controlled to one or more of a positive voltage, a negative voltage, or ground (rather than being allowed to "float") to reduce parasitic capacitance between adjacent digit lines 16.

[0025] Multiple example arrays as shown and / or described above may be stacked on top of each other, including stacks comprising more than two such arrays. Figure 4 An alternative example configuration 8a is shown. The same numerals from the previous embodiments have been used where appropriate, with some configuration differences indicated with a suffix "a" or with different numerals. The array 10 in configuration 8a may be considered a first array 10. Configuration 8a includes another first array (e.g., designated by the numeral 100) above the first array 10. In this example embodiment, the first level 12 of the other first array 100 is above the fifth level 50 of the first array 10 (e.g., separated by an insulator level 90 [e.g., silicon dioxide and / or silicon nitride], as shown). The arrays 10 and 100 need not have the same configuration relative to each other.

[0026] Figure 5 An alternative example embodiment configuration 8b is shown. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "b". In configuration 8b, the fifth level 50 of the first array 10 is the first level 12 of another first array 100, such that the alternating columns 14, 18 of digit lines 16 and conductive shield lines 20 therein are shared by the first array 10 and another first array 100, respectively. The arrays 10 and 100 need not have the same configuration relative to each other. Regardless, any (several) other attributes or aspects as shown and / or described herein may be used Figure 4 and 5 In the embodiment.

[0027] Embodiments of the present invention include an array of memory cells that individually include capacitors and transistors. This array includes alternating columns of digit lines and conductive shield lines in a first level. A second level is above the first level and has rows of transistor word lines therein. A third level is above the second level and has rows and columns of capacitors therein. A fourth level is above the third level and has rows of transistor word lines therein. A fifth level is above the fourth level and has alternating columns of digit lines and conductive shield lines therein. This array may have any of the properties described above with respect to features 14, 16, 18, 20, 85, 30, and 32, but is also independent of any of the properties described above for such features. Any (several) other properties or aspects as shown and / or described herein may be used.

[0028] Embodiments of the present invention encompass methods of forming an array of memory cells that individually include capacitors and transistors, wherein the array includes alternating columns of digit lines and conductive shield lines in a first level. A second level is above the first level and has rows of transistor word lines therein. A third level is above the second level and has rows and columns of capacitors therein. A fourth level is above the third level and has rows of transistor word lines therein. A fifth level is above the fourth level and has alternating columns of digit lines and conductive shield lines therein. This method includes forming, in at least one of the first level and the fifth level, one of the columns of conductive shield lines therein or the columns of digit lines therein in a self-aligned manner using one of the columns of conductive shield lines therein or the columns of digit lines therein as a template.

[0029] Next reference Figures 6 to 8 An example method of forming a conductive shield line in at least one of the first and fifth levels is described.The same numbers from the above embodiments have been used for leading materials and constructions, with some construction differences indicated with different numbers.

[0030] refer to Figure 6 , which shows Figure 1 Columns 14 of digit lines 16 are shown as having been formed in at least one of the first level 12 or the fifth level 50. Thus, Figures 6 to 8 The processing of may be viewed as occurring in only one of levels 12 and 50 or in both.

[0031] refer to Figure 7 , material 60 has been formed between immediately adjacent ones of digit lines 16 to fill the space laterally between such immediately adjacent digit lines in one of the first and fifth levels with an insufficient amount of this material, and to leave void space 62 laterally between such immediately adjacent digit lines in said one of the first and fifth levels. Material 60 may be a dielectric and at least mostly remain in the finished circuitry construction of the array. Alternatively, material 60 may be a dielectric and mostly not remain in the finished circuitry construction of the array. Still and alternatively, material 60 may be at least mostly sacrificial (e.g., any one or more of conductive, dielectric, and / or semiconductive) and mostly not remain in the finished circuitry construction of the array. Ideally, Figure 7The configuration is formed in a self-aligned manner, for example, by conformally depositing material 60 and to the depicted example depth whereby a lateral gap (e.g., a precursor to void space 62) is naturally formed therebetween, and using digit line 16 as a template. Thereafter, material 60 at the base of the lateral gap may be removed by an unmasked spacer-like anisotropic etch (i.e., unmasked at least within array 10) so that the bases of digit line 16 and conductive shield line 20 may ultimately be uniform in height. Alternatively, but less ideally, material 60 may be deposited and then patterned using a mask (e.g., using photolithography and etching).

[0032] refer to Figure 8 , the conductive material of the conductive shield line 20 has been formed in the void space 62 laterally between the immediately adjacent digit lines 16 in the depicted first and fifth levels.

[0033] Next reference Figures 9 to 11 An example method of forming digit lines in at least one of the first and fifth levels is described. The same digits from the above embodiments have been used for leading materials and constructions.

[0034] refer to Fig. 9 , which shows Figure 1 The example portion of the leading structure 8 of the structure. The column 18 of the conductive shield line 20 is shown as having been formed in at least one of the first level 12 or the fifth level 50. Therefore, Figures 9 to 10 The processing of may be viewed as occurring in only one of levels 12 and 50 or in both.

[0035] refer to Fig.10 , material 60 has been formed between adjacent shielding wires 20 of the conductive shielding wires 20 to fill the space laterally between such adjacent shielding wires with insufficient amount of this material in one of the first and fifth levels, and to leave void space 62 laterally between such adjacent shielding wires in said one of the first and fifth levels. Ideally, Fig.10 The configuration is formed in a self-aligned manner, for example, by conformally depositing material 60 and to the depicted example depth whereby a lateral gap (e.g., a precursor to void space 62) is naturally formed therebetween, and using conductive shield line 20 as a template. Thereafter, material 60 at the base of the lateral gap may be removed by an unmasked spacer-like anisotropic etch (i.e., unmasked at least within array 10), so that the bases of digit lines 16 and conductive shield lines 20 may ultimately be uniform in height. Alternatively, but less ideally, material 60 may be deposited and then patterned using a mask (e.g., using photolithography and etching).

[0036] refer to Fig.11, the conductive material of the digit lines 16 has been formed in the void spaces 62 laterally between the immediately adjacent shield lines 20 in the depicted first and fifth levels.

[0037] Any (several) attributes or aspects shown and / or described herein with respect to structural embodiments may be used in method embodiments, and vice versa. The pitch multiplication principle may be used in method aspects of the invention (e.g., a feature may be formed along the sidewall of another feature to have a lateral thickness that is less than the lateral thickness of the other feature, regardless of how the other feature is formed).

[0038] In the present invention, unless otherwise indicated, "height", "higher", "up", "down", "top", "above", "below", "down", "below", "upward", and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "completely horizontal" is a direction along the surface of the main substrate (i.e., not angled thereto) and can be relative to the direction in which the substrate is handled during manufacturing. Moreover, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "extending in height" and "extending in height" refer to a direction that deviates from completely horizontal by at least 45°. Moreover, "extending in height", "extending in height", extending horizontally, and extending horizontally relative to a field effect transistor are references to the orientation of the channel length of the transistor, in operation, current flows between the source / drain regions along the orientation. For a bipolar junction transistor, "extending in height", "extending in height", extending horizontally and extending horizontally are referenced to the orientation of the substrate length along which, in operation, current flows between the emitter and the collector.

[0039] In addition, "directly above" and "directly below" require that the two regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, the use of "above" without a preceding "directly" only requires that some portion of the region / material / component above another region / material / component is outward from the height of the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components). Similarly, the use of "below" without a preceding "directly" only requires that some portion of the region / material / component below another region / material / component is inward from the height of the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components).

[0040] Any materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be overlying any material, either continuously or discontinuously. Furthermore, unless otherwise stated, each material may be formed using any suitable or yet to be developed technique, examples being atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0041] In addition, "thickness" itself (without a directional adjective before) is defined as the average straight-line distance perpendicular to a given material or region from the closest surface of the adjacent material or adjacent region of different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness unless otherwise indicated, and this material or region will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that the parts of the two materials or regions that can directly abut against each other are chemically and / or physically different (for example, if such materials or regions are not homogeneous). If the two materials or regions are not directly against each other, "different compositions" only require that the parts of the two materials or regions that are closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In the present invention, when a material, region or structure is in at least some physical touching contact with respect to another material, region or structure, the materials, regions or structures are "directly against" each other. In contrast, the words “over,” “on,” “adjacent,” “along,” and “against” without the word “directly” in front of them encompass “directly against” as well as configurations in which (several) intervening materials, (several) regions, or (several) structures result in the materials, regions, or structures not being in physical contact with each other.

[0042] Herein, region-material-components are "electrically coupled" to one another if, in normal operation, electrical current is able to flow continuously from one of the region-material-components to the other and flows primarily due to the movement of subatomic positive and / or negative charges (when such charges are sufficiently generated). Another electronic component may be between the region-material-components and may be electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0043] In addition, a "metal material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

[0044] Furthermore, "self-aligned" (or "self-aligning") means a technique in which at least one pair of opposing edges of a structure is formed by a pair of previously defined edges, whereby no subsequent photolithographic processing is required with respect to the opposing edges.

[0045] Summarize

[0046] In some embodiments, an array of memory cells that individually include capacitors and transistors includes alternating columns of digit lines and conductive shield lines in a first level. In a second level above the first level, there are rows of transistor word lines. In a third level above the second level, there are rows and columns of capacitors. In a fourth level above the third level, there are rows of transistor word lines. In a fifth level above the fourth level, there are alternating columns of digit lines and conductive shield lines.

[0047] In some embodiments, an array of memory cells individually including capacitors and transistors includes highly extended transistors in a second level above a first level, each of which includes an upper source / drain region, a lower source / drain region, and a channel region extending in height therebetween. Rows of second level word lines are adjacent to individual second level channel regions of individual second level transistors of individual memory cells within the array and are operably extended and interconnect the second level transistors in the second level rows. In the first level, there are alternating columns of digit lines and columns of conductive shield lines. Individuals of the first level digit lines are electrically coupled to individual lower source / drain regions of the individual second level transistors and interconnect the second level transistors in the second level columns. One of the first level conductive shield lines is laterally interposed between each immediately adjacent digit line of the first level digit lines. A third level is above the second level and includes capacitors, each of which includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator interposed between the first capacitor electrode and the second capacitor electrode. Individual ones of the first capacitor electrodes are electrically coupled to individual ones of the upper source / drain regions of the individual second level transistors and extend upward in height from individual ones of the upper source / drain regions. In a fourth level above the third level, height-extended transistors individually include upper source / drain regions, lower source / drain regions, and channel regions extending in height therebetween. Rows of fourth level word lines are operably extended adjacent to the individual fourth level channel regions of individual fourth level transistors of individual memory cells within the array and interconnect the fourth level transistors in the fourth level rows. Individual other ones of the first capacitor electrodes are electrically coupled to individual ones of the lower source / drain regions of individual fourth level transistors. In a fifth level above the fourth level, there are columns of digit lines and columns of conductive shield lines. Individual ones of the fifth level digit lines are electrically coupled to individual upper source / drain regions of the individual fourth level transistors and interconnect the fourth level transistors in the fourth level columns. One of the fifth level conductive shield lines is laterally interposed between each immediately adjacent digit line of the fifth level digit lines.

[0048] Some embodiments are a method of forming an array of memory cells that individually include capacitors and transistors. The array includes alternating columns of digit lines and conductive shield lines in a first level. In a second level above the first level, there are rows of word lines. In a third level above the second level, there are rows and columns of capacitors. In a fourth level above the third level, there are rows of word lines. In a fifth level above the fourth level, there are alternating columns of digit lines and conductive shield lines. The method includes forming the other of the conductive shield lines or the columns of digit lines therein in a self-aligned manner in at least one of the first level and the fifth level using the columns of the conductive shield lines therein or the columns of the digit lines therein as a template.

[0049] Some embodiments are a method of forming an array of memory cells that individually include capacitors and transistors. The array includes alternating columns of digit lines and conductive shield lines in a first level. In a second level above the first level, there are rows of word lines. In a third level above the second level, there are rows and columns of capacitors. In a fourth level above the third level, there are rows of word lines. In a fifth level above the fourth level, there are alternating columns of digit lines and conductive shield lines. The method includes sequentially forming the conductive shield lines therein in at least one of the first level and the fifth level, including forming the columns of digit lines. Material is formed between immediately adjacent digit lines of the digit lines to fill the space laterally between the immediately adjacent digit lines with an insufficient amount of the material in one of the first level and the fifth level and leave a void space laterally between the immediately adjacent digit lines in the one of the first level and the fifth level. The conductive material of the conductive shield line is formed in the void space laterally between the immediately adjacent digit lines in the one of the first level and the fifth level.

[0050] Some embodiments are a method of forming an array of memory cells that individually include capacitors and transistors. The array includes alternating columns of digit lines and conductive shield lines in a first level. In a second level above the first level, there are rows of word lines. In a third level above the second level, there are rows and columns of capacitors. In a fourth level above the third level, there are rows of word lines. In a fifth level above the fourth level, there are alternating columns of digit lines and conductive shield lines. The method includes sequentially forming the digit lines therein in at least one of the first level and the fifth level, including forming the columns of conductive shield lines. Material is formed between immediately adjacent shield lines of the conductive shield lines to fill the space laterally between the immediately adjacent conductive shield lines in the one of the first level and the fifth level with an insufficient amount of the material and leave a void space laterally between the immediately adjacent conductive shield lines in the one of the first level and the fifth level. The conductive material of the digit lines is formed in the interstitial space laterally between the immediately adjacent conductive shield lines in the one of the first level and the fifth level.

Claims

1. A memory cell array each comprising a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in the first level; a row of transistor word lines in a second level above the first level; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; and alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and Another first array, which is directly above the first array. 2 . The array of claim 2 , wherein the digit lines of the another first array are directly above the shield lines of the first array.

3. The array of claim 1 wherein the memory cells individually have only one total transistor and only one total capacitor.

4. The array of claim 1 wherein one of the first level conductive shield lines is laterally interposed between each immediately adjacent digit line of the first level digit lines.

5. An array according to claim 1, wherein the first-level digital line columns and the first-level conductive shielding line columns alternate with each other every other one, so that each adjacent digital line of the first-level digital line has one of the first-level conductive shielding lines laterally interposed therebetween, and so that each adjacent shielding line of the first-level conductive shielding line has one of the first-level digital lines laterally interposed therebetween.

6. The array of claim 1 wherein one of the fifth level conductive shield lines is laterally interposed between each immediately adjacent digit line of the fifth level digit lines.

7. An array according to claim 1, wherein the fifth-level digital line columns and the fifth-level conductive shielding line columns alternate with each other every other one, so that each adjacent digital line of the fifth-level digital line has one of the fifth-level conductive shielding lines laterally interposed therebetween, and so that each adjacent shielding line of the fifth-level conductive shielding line has one of the fifth-level digital lines laterally interposed therebetween.

8. A memory cell array each comprising a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in the first level; a row of transistor word lines in a second level above the first level; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and The memory cells individually have only one transistor in total and only one capacitor in total; and Another first array is directly above the first array, and the first level of the another first array is directly above the fifth level of the first array.

9. A memory cell array each comprising a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in the first level; a row of transistor word lines in a second level above the first level; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and The memory cells individually have only one transistor in total and only one capacitor in total; and Another first array is directly above the first array, the fifth level of the first array is the first level of the another first array, so that the alternating columns of digit lines and conductive shield lines therein are shared by the first array and the another first array.

10. A memory cell array each including a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in a first level, the digit lines extending in a column direction; a row of transistor word lines in a second level above the first level, the row extending in a row direction; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and The memory cells individually have a total of only one transistor and a total of only one capacitor, the transistors individually including a channel region, the transistor word lines being laterally located on opposite sides of the individual ones of the channel regions in the row direction; and Another first array, which is directly above the first array.

11. A memory cell array each comprising a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in a first level, the digit lines extending in a column direction; a row of transistor word lines in a second level above the first level, the row extending in a row direction; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and The memory cells individually have a total of only one transistor and a total of only one capacitor, the transistors individually including a channel region, the transistor word lines being laterally located on opposite sides of the individual ones of the channel regions in the column direction; and Another first array, which is directly above the first array.

12. A memory cell array each comprising a capacitor and a transistor, comprising: A first array, the first array comprising: alternating columns of digit lines and conductive shield lines in a first level, the digit lines extending in a column direction; a row of transistor word lines in a second level above the first level, the row extending in a row direction; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and The memory cells individually have a total of only one transistor and a total of only one capacitor, the transistors individually including a channel region, the transistor word lines laterally surrounding all sides of the individual ones of the channel regions; and Another first array, which is directly above the first array.

13. A memory cell array each comprising a capacitor and a transistor, comprising: alternating columns of digit lines and conductive shield lines in the first level; a row of transistor word lines in a second level above the first level; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and At least one of: individual ones of the capacitors include a ferroelectric capacitor insulator, or individual ones of the transistors include a ferroelectric gate insulator.

14. The array of claim 13 wherein the individual capacitors comprise ferroelectric capacitor insulators.

15. The array of claim 13 wherein the individual transistors comprise a ferroelectric gate insulator.

16. The array of claim 13, wherein each of the capacitors has at least one capacitor electrode having a height greater than a width.

17. An array according to claim 16, wherein each of the capacitors has only one capacitor electrode whose height is greater than its width, each of the capacitors has its other capacitor electrode common to all of the capacitors in the third level of the array, the common other electrode in the array having a width greater than its height.

18. A memory cell array each comprising a capacitor and a transistor, comprising: alternating columns of digit lines and conductive shield lines in the first level; a row of transistor word lines in a second level above the first level; rows and columns of capacitors in a third level above the second level; a row of transistor word lines in a fourth level above the third level; alternating columns of digit lines and conductive shield lines in a fifth level above the fourth level; and Individuals of the conductive shield lines are narrower than individual ones of the digit lines.

19. A memory array comprising: a first digit line and a first conductive shield in a first level; a first vertical transistor in a second level above the first level, the first vertical transistor electrically coupled to the first digit line; a first capacitor and a second capacitor in a third level above the second level, the first capacitor being electrically coupled to the first vertical transistor; a second vertical transistor in a fourth level above the third level, the second vertical transistor electrically coupled to the second capacitor; and A second digit line and a second conductive shield in a fifth level above the fourth level, the second digit line being electrically coupled to the second vertical transistor.

20. The memory array of claim 19, further comprising: a third digit line and a third conductive shield in a sixth level above the fifth level; a third vertical transistor in a seventh level above the sixth level, the third vertical transistor being electrically coupled to the third digit line; a third capacitor and a fourth capacitor in an eighth level above the seventh level, the third capacitor being electrically coupled to the third vertical transistor; a fourth vertical transistor in a ninth level above the eighth level, the fourth vertical transistor being electrically coupled to the fourth capacitor; and A fourth digit line and a fourth conductive shield in a tenth level above the ninth level, the fourth digit line coupled to a fourth vertical transistor.

21. The memory array of claim 20, wherein the first digit line, the first vertical transistor, the first capacitor, the second conductive shield, the third digit line, the third vertical transistor, the third capacitor, and the fourth conductive shield are vertically aligned.

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