Fault synchronization circuit and energy storage inverter parallel operation system

Abstract

The invention discloses a fault synchronous circuit and an energy storage inverter parallel operation system, and belongs to the field of photovoltaic technology. The fault synchronization circuit comprises a signal processing module and a synchronization signal conversion module. When the signal processing module detects that the energy storage inverter has a fault, the signal output end outputs a fault synchronization signal, and judges whether other energy storage inverters in the parallel operation system have a fault according to a signal accessed from the feedback input end; the synchronizing signal conversion module comprises a signal conversion unit and a signal feedback unit; the signal conversion unit controls the common signal end to be connected with the fault synchronization signal bus when receiving the fault synchronization signal, and controls the common signal end to be disconnected from the fault synchronization signal bus when the energy storage inverter is powered down; and the signal feedback unit is conducted when the fault synchronization signal bus is communicated with the common signal end of the at least one fault synchronization circuit. According to the invention, the fault synchronization of the parallel operation system in a wide working frequency range can be ensured, and the reliability of the parallel operation system is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a fault synchronization circuit and an energy storage inverter parallel system. Background Art

[0002] As the demand for photovoltaic energy storage changes, the power requirements of photovoltaic energy storage power stations are getting higher and higher. It is difficult for one energy storage inverter to meet the high power demand of the market, so the parallel operation of energy storage inverters is gradually increasing. When multiple energy storage inverters are connected in parallel, it is necessary to perform fault synchronization between multiple machines when a fault occurs during the operation of the energy storage inverter. In the related technology, if communication chips such as CAN are used for fault synchronization, the synchronization scheme will be limited by the operating frequency. For example, when the signal frequency processed by the CAN chip is lower than 250Hz, a signal level error will occur, normal communication will not be possible, and fault synchronization under low-speed communication will be difficult to achieve. For the scheme that uses the bus level to characterize whether there is a machine fault, when one machine loses power, the bus level will be lowered, resulting in the inability to transmit the fault synchronization related signals in the parallel system normally, causing the fault synchronization to fail, and even causing other machines to shut down by mistake, affecting the reliability of the system. Summary of the invention

[0003] The present invention provides a fault synchronization circuit and an energy storage inverter parallel system to ensure fault synchronization of the energy storage inverter parallel system within a wide operating frequency range and improve the reliability of the parallel system.

[0004] In a first aspect, an embodiment of the present invention provides a fault synchronization circuit, which is applied to any energy storage inverter in an energy storage inverter parallel system; the energy storage inverter parallel system includes a fault synchronization signal bus;

[0005] The fault synchronization circuit comprises:

[0006] A signal processing module, comprising a signal output terminal and a feedback input terminal; the signal processing module is used to output a fault synchronization signal from the signal output terminal when a fault is detected in the energy storage inverter, and to determine whether other energy storage inverters in the energy storage inverter parallel system are faulty according to the signal received by the feedback input terminal;

[0007] A synchronous signal conversion module comprises a signal conversion unit and a signal feedback unit; the signal conversion unit is respectively connected to the signal output end, the common signal end of the fault synchronization circuit and the fault synchronization signal bus; the common signal end of the fault synchronization circuit of all the energy storage inverters in the energy storage inverter parallel system is connected to the same voltage; the signal conversion unit is used to control the common signal end to be connected to the fault synchronization signal bus when the signal processing module outputs the fault synchronization signal, and to control the common signal end to be disconnected from the fault synchronization signal bus when the energy storage inverter is powered off; the signal feedback unit is respectively connected to the fault synchronization signal bus and the feedback input end; the signal feedback unit is used to be turned on when the fault synchronization signal bus is connected to the common signal end of at least one of the fault synchronization circuits.

[0008] Optionally, the signal conversion unit includes:

[0009] A control subunit, wherein the control end of the control subunit is connected to the signal output end, the first connection end of the control subunit is connected to the common signal end, and the second connection end of the control subunit is connected to the first power supply end of the fault synchronization circuit; the control subunit is used to control the connection between the first connection end or the second connection end and the output end of the control subunit according to the signal connected to its control end; the common signal end and the first power supply end are connected to different voltages;

[0010] A switch subunit, wherein the control end of the switch subunit is connected to the output end of the control subunit, the input end of the switch subunit is connected to the common signal end, and the output end of the switch subunit is connected to the fault synchronization signal bus; the switch subunit is used to control whether the input end and the output end of the switch subunit are connected according to the signal connected to the control end;

[0011] The transmission control subunit is connected between the first connection end and the fault synchronization signal bus, and is used to control whether the signal on the fault synchronization signal bus is transmitted to the first connection end.

[0012] Optionally, the control subunit includes: a first transistor and a first resistor; the gate of the first transistor is connected to the signal output terminal, the first electrode of the first transistor is connected to the common signal terminal, the second electrode of the first transistor is respectively connected to the first end of the first resistor and the output end of the control subunit, and the second end of the first resistor is connected to the first power supply terminal;

[0013] The switch subunit comprises: a second transistor; a gate of the second transistor is connected to the output end of the control subunit, a first electrode of the second transistor is connected to the common signal end, and a second electrode of the second transistor is connected to the fault synchronization signal bus;

[0014] The transmission control subunit includes: a first diode and a second resistor connected in series between the first power supply terminal and the fault synchronization signal bus;

[0015] The signal feedback unit includes: a second diode and a third resistor; the first pole of the second diode is connected to the fault synchronization signal bus, the second pole of the second diode is respectively connected to the first end of the third resistor and the feedback input end, and the second end of the third resistor is connected to the second power supply end of the fault synchronization circuit; the voltage connected to the common signal end is different from that of the second power supply end.

[0016] Optionally, the control subunit further includes: a fourth resistor, a fifth resistor and a first capacitor; the fourth resistor is connected between the signal output terminal and the gate of the first transistor, and the fifth resistor and the first capacitor are both connected between the gate of the first transistor and the common signal terminal;

[0017] The switch subunit further includes: a sixth resistor and a seventh resistor; the sixth resistor is connected between the output terminal of the control subunit and the gate of the second transistor, and the seventh resistor is connected between the gate of the second transistor and the common signal terminal;

[0018] The signal feedback unit further includes: a second capacitor connected between the first end of the third resistor and the common signal end.

[0019] Optionally, the signal processing module includes: a digital signal processor and a complex programmable logic device;

[0020] The complex programmable logic device is respectively connected to the digital signal processor, the signal output end and the feedback input end; the digital signal processor is used to output a fault signal when a fault is detected in the energy storage inverter, and the complex programmable logic device is used to generate the fault synchronization signal according to the fault signal; and the complex programmable logic device is also used to generate a feedback signal according to the signal connected to the feedback input end, and the digital signal processor is also used to determine whether other energy storage inverters in the energy storage inverter parallel system are faulty according to the feedback signal.

[0021] Optionally, the synchronization signal conversion module further includes: a surge suppression unit connected between the common signal terminal and the fault synchronization signal bus;

[0022] And / or, the fault synchronization circuit further includes: a parallel communication module connected to the signal processing module; the parallel communication module of any energy storage inverter in the energy storage inverter parallel system is communicatively connected with the parallel communication module of other energy storage inverters;

[0023] And / or, the energy storage inverter parallel system further includes: a common signal bus connected to the common signal end of the fault synchronization circuit in each of the energy storage inverters;

[0024] And / or, the fault synchronization circuit further comprises: an interface module, the synchronization signal conversion module is connected to the fault synchronization signal bus through the interface module;

[0025] And / or, the fault synchronization circuit further includes: an isolation module, which is respectively connected to the signal output end, the feedback input end, the signal conversion unit and the signal feedback unit.

[0026] Optionally, the fault synchronization circuit further includes an isolation module; the isolation module includes: a pull-up unit, a first filtering unit, a second filtering unit and an isolation unit;

[0027] The first end of the pull-up unit is connected to the third power supply end of the fault synchronization circuit, and the second end of the pull-up unit is connected to the signal output end; the input end of the first filtering unit is connected to the signal output end, the output end of the first filtering unit is connected to the first input end of the isolation unit, the first output end of the isolation unit is connected to the signal conversion unit, the second input end of the isolation unit is connected to the signal feedback unit, the second output end of the isolation unit is connected to the input end of the second filtering unit, and the output end of the second filtering unit is connected to the feedback input end.

[0028] Optionally, the energy storage inverter parallel system further includes: a common signal bus connected to the common signal end of the fault synchronization circuit in each of the energy storage inverters; the fault synchronization circuit further includes: an interface module; the interface modules of each of the energy storage inverters in the energy storage inverter parallel system are connected in sequence;

[0029] Wherein, the interface module includes a first interface and a second interface; the first interface includes a first contact and a second contact, and the second interface includes a third contact and a fourth contact;

[0030] The first contact and the third contact in the same interface module are connected via a first connecting line, and the first contact in any interface module is connected to the third contact in the previous interface module via a second connecting line; each of the first connecting lines and each of the second connecting lines constitute the fault synchronization signal bus; the second contact and the fourth contact in the same interface module are connected via a third connecting line, and the second contact in any interface module is connected to the fourth contact in the previous interface module via a fourth connecting line; each of the third connecting lines and each of the fourth connecting lines constitute the common signal bus.

[0031] In a second aspect, an embodiment of the present invention further provides an energy storage inverter parallel system, comprising: a fault synchronization signal bus and multiple energy storage inverters, each of the energy storage inverters comprising a fault synchronization circuit as provided in any embodiment of the present invention.

[0032] Optionally, the energy storage inverter parallel system further includes: a host computer, connected to the signal processing modules in each of the fault synchronization circuits respectively;

[0033] Among them, the fault synchronization circuit includes: a parallel communication module; one energy storage inverter among the multiple energy storage inverters is the host, and the other energy storage inverters are slaves; when the host has a fault, the signal processing module in the host uploads the fault information of the host to the host computer; when the slave has a fault, the parallel communication module in the slave transmits the fault information of the slave to the parallel communication module of the host.

[0034] In the fault synchronization circuit provided by the embodiment of the present invention, a signal processing module and a synchronization signal conversion module are provided. Among them, when the signal processing module detects the fault of the energy storage inverter, the signal conversion unit pulls the voltage on the fault synchronization signal bus to the same voltage as the common signal terminal, so as to inform other fault synchronization circuits in the parallel system of the information that there is a faulty energy storage inverter in the parallel system; and the signal processing module can judge whether other energy storage inverters in the parallel system are faulty according to the signal feedback from the voltage on the fault synchronization signal bus through the signal feedback unit. In this way, by controlling the voltage change on the fault synchronization signal bus and analyzing the voltage on the fault synchronization signal bus, fault synchronization between energy storage inverters in the parallel system can be achieved. Compared with the scheme of using a communication chip for fault synchronization, the embodiment of the present invention is not limited by frequency, and can ensure that the energy storage inverter parallel system can achieve fault synchronization within a wide operating frequency range, which is particularly conducive to achieving low-speed fault synchronization. Furthermore, by setting the signal conversion unit to have the function of controlling the disconnection between the common signal terminal and the fault synchronization signal bus when the energy storage inverter loses power, power failure of any energy storage inverter in the parallel system will not affect the voltage on the fault synchronization signal bus, so that other energy storage inverters can still operate normally and synchronously, thereby improving the operating reliability and stability of the parallel system.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a structural schematic diagram of a fault synchronization circuit provided by an embodiment of the present invention;

[0038] Figure 2 It is a structural schematic diagram of an energy storage inverter parallel system provided by an embodiment of the present invention;

[0039] Figure 3 is a structural schematic diagram of another fault synchronization circuit provided by an embodiment of the present invention;

[0040] Figure 4 is a structural schematic diagram of another fault synchronization circuit provided by an embodiment of the present invention;

[0041] Figure 5is a structural schematic diagram of another fault synchronization circuit provided by an embodiment of the present invention;

[0042] Figure 6 is a structural schematic diagram of another energy storage inverter parallel system provided by an embodiment of the present invention;

[0043] Figure 7 is a schematic diagram of a fault synchronization simulation result provided by an embodiment of the present invention;

[0044] Figure 8 This is another schematic diagram of fault synchronization simulation results provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0047] The embodiment of the present invention provides a fault synchronization circuit, which is applied to any energy storage inverter in an energy storage inverter parallel system (also referred to as a parallel system), and can transmit relevant fault information to other energy storage inverters in the parallel system when any energy storage inverter has a fault, so as to achieve fault information synchronization between the energy storage inverters in the parallel system. Among them, each energy storage inverter in the parallel system includes a fault synchronization circuit, and the energy storage inverter parallel system includes a fault synchronization signal bus, and the fault synchronization circuits of each energy storage inverter in the parallel system are connected to the fault synchronization signal bus, and transmit their own fault synchronization signals or receive fault synchronization signals output by other energy storage inverters through the fault synchronization signal bus.

[0048] The structure of the fault synchronization circuit is described below. Figure 1 is a schematic diagram of a fault synchronization circuit provided by an embodiment of the present invention. Figure 1 The fault synchronization circuit 100 includes: a signal processing module 10 and a synchronization signal conversion module 20.

[0049] Among them, the signal processing module 10 includes a signal output terminal Sync and a feedback input terminal Fdb. The signal processing module 10 is used to output a fault synchronization signal from the signal output terminal Sync when a fault is detected in the energy storage inverter, and judge whether other energy storage inverters in the energy storage inverter parallel system have faults according to the signal connected to the feedback input terminal Fdb. It can be understood that the fault of the energy storage inverter mentioned here can be any type of operating fault, such as abnormal voltage, current or temperature of any key node of the energy storage inverter, or loss of synchronization with other energy storage inverters in the parallel system. The synchronization signal conversion module 20 includes a signal conversion unit 21 and a signal feedback unit 22. The signal conversion unit 21 is respectively connected to the signal output terminal Sync, the common signal terminal COM of the fault synchronization circuit 100 and the fault synchronization signal bus LSFdb. The common signal terminal COM in the fault synchronization circuit 100 of all energy storage inverters in the energy storage inverter parallel system is connected to the same voltage. The signal conversion unit 21 is used to control the common signal terminal COM to be connected to the fault synchronization signal bus Sync when the signal processing module 10 outputs a fault synchronization signal, and to control the common signal terminal COM to be disconnected from the fault synchronization signal bus Sync when the energy storage inverter is powered off. The signal feedback unit 22 is connected to the fault synchronization signal bus LSFdb and the feedback input terminal Fdb respectively; the signal feedback unit 22 is used to be turned on when the fault synchronization signal bus LSFdb is connected to the common signal terminal COM of at least one fault synchronization circuit 100.

[0050] Among them, see Figure 2 In the parallel system, the fault synchronization circuit 100 of each energy storage inverter is connected to the fault synchronization signal bus LSFdb to achieve fault synchronization. Exemplarily, the common signal terminal COM of each fault synchronization circuit 100 is connected to a common signal, which is a DC voltage signal, such as a common ground signal.

[0051] For any fault synchronization circuit 100, its working process is as follows:

[0052] The process of the fault synchronization circuit 100COM transmitting a signal representing the fault to the fault synchronization signal bus LSFdb when the energy storage inverter fails is as follows: when the signal processing module 10 detects that the energy storage inverter is faulty, the signal processing module 10 generates a fault synchronization signal and outputs it via the signal output terminal Sync; when the signal conversion unit 21 receives the fault synchronization signal, it controls the common signal terminal COM to be connected to the fault synchronization signal bus LSFdb, and transmits the common signal to the fault synchronization signal bus Sync. In this way, the fault synchronization circuit is equivalent to pulling the voltage on the fault synchronization signal bus Sync to the same voltage as the voltage connected to the common signal terminal COM when the energy storage inverter is detected to be faulty, that is, when the voltage on the fault synchronization signal bus Sync is equal to the voltage of the common signal, it represents that there is a fault in the energy storage inverter in the parallel system.

[0053] Exemplarily, when the signal processing module 10 detects that there is no fault in the energy storage inverter, the fault synchronization signal may not be output, and the fault synchronization signal may be stopped after a period of time (such period of time is sufficient for other fault synchronization circuits to capture and analyze the voltage transmitted on the fault synchronization signal bus LSFdb) after the signal processing module 10 outputs the fault synchronization signal; when the signal processing module 10 does not output the fault synchronization signal, the common signal terminal V1 may be disconnected from the fault synchronization signal bus LSFdb, thereby releasing the control of the voltage of the fault synchronization signal bus LSFdb, so that the fault synchronization signal bus LSFdb can change the voltage accordingly according to the output of other fault synchronization circuits. Exemplarily, when there is no faulty energy storage inverter in the parallel system, the fault synchronization signal bus LSFdb may maintain a voltage different from the common signal, which may be provided by the signal conversion unit 21, or by other separately provided pull-up or pull-down modules.

[0054] The process by which the fault synchronization circuit 100 determines whether there is a faulty energy storage inverter in the parallel system based on the voltage on the fault synchronization signal bus Sync is as follows: when the fault synchronization signal bus LSFdb is connected to the common signal terminal COM of at least one fault synchronization circuit 100, the voltage on the fault synchronization signal bus LSFdb is equal to the voltage connected to the common signal terminal COM, so that the signal feedback unit 22 in the fault synchronization circuit 100 is turned on, and the voltage on the fault synchronization signal bus LSFdb is transmitted to the feedback input terminal Fdb of the signal processing module 10; when the voltage received by the signal processing module 10 at the feedback input terminal Fdb is a voltage related to the voltage connected to the common signal terminal COM (for example, equal to the voltage of the common signal), it can be confirmed that there is a faulty energy storage inverter in other energy storage inverters other than itself in the parallel system. When the fault synchronization signal bus LSFdb is not connected to the common signal terminal of all fault synchronization circuits 100, the voltage on the fault synchronization signal bus LSFdb is not equal to the voltage connected to the common signal terminal COM, so that the signal feedback unit 22 in the fault synchronization circuit 100 is disconnected, and the feedback input terminal Fdb cannot receive the common signal. Therefore, the signal processing module 10 can confirm that there is no faulty energy storage inverter in the parallel system.

[0055] The above describes the process of the fault synchronization circuit 100 transmitting a signal to the fault synchronization signal bus LSFdb, and judging whether there is a faulty energy storage inverter in the parallel system according to the signal on the fault synchronization signal bus LSFdb. It can be understood that the above two processes can be performed simultaneously or in time-sharing according to actual needs, and the execution frequency can be set according to actual needs. It should be noted that the above two processes are normal fault synchronization processes that can be implemented by the fault synchronization circuit 100 on the basis that the energy storage inverter is normally powered and can support the normal operation of the fault synchronization circuit 100.

[0056] For any fault synchronization circuit 100, when the energy storage inverter in which it is located loses power, the signal processing module 10 and the synchronization signal conversion module 20 also lose power. In this case, the signal processing module 10 cannot realize the functions of detecting whether the energy storage inverter in which it is located is faulty, transmitting fault synchronization signals, and analyzing the signal connected to the feedback input terminal Fdb, and cannot correctly control whether the common signal terminal COM and the fault synchronization signal bus LSFdb are connected according to the fault condition of the energy storage inverter. Then, in this case, by controlling the disconnection between the common signal terminal COM and the fault synchronization signal bus LSFdb, it can effectively avoid the voltage connected to the common signal terminal COM from being mistakenly transmitted to the fault synchronization signal bus LSFdb, thereby avoiding affecting the judgment of the fault condition in the parallel system by other fault synchronization circuits in the parallel system, and ensuring that other energy storage inverters in the parallel system can operate normally and synchronously.

[0057] In the fault synchronization circuit 100 provided in the embodiment of the present invention, a signal processing module 10 and a synchronization signal conversion module 20 are provided. Among them, when the signal processing module 10 detects a fault in the energy storage inverter, the signal conversion unit 21 pulls the voltage on the fault synchronization signal bus LSFdb to the same voltage as the common signal terminal COM, so as to inform other fault synchronization circuits 100 in the parallel system of the information that there is a faulty energy storage inverter in the parallel system; and the signal processing module 10 can judge whether other energy storage inverters in the parallel system are faulty according to the signal feedback from the voltage on the fault synchronization signal bus LSFdb through the signal feedback unit 22. In this way, by controlling the voltage change on the fault synchronization signal bus LSFdb and analyzing the voltage on the fault synchronization signal bus LSFdb, fault synchronization between energy storage inverters in the parallel system can be achieved. Compared with the scheme of using a communication chip for fault synchronization, the embodiment of the present invention is not limited by frequency, and can ensure that the energy storage inverter parallel system can achieve fault synchronization within a wide operating frequency range, which is particularly conducive to achieving low-speed fault synchronization. Furthermore, by setting the signal conversion unit 21 to have the function of controlling the disconnection between the common signal terminal COM and the fault synchronization signal bus LSFdb when the energy storage inverter is powered off, power failure of any energy storage inverter in the parallel system will not affect the voltage on the fault synchronization signal bus LSFdb, so that other energy storage inverters can still operate normally and synchronously, thereby improving the operating reliability and stability of the parallel system.

[0058] Figure 3 FIG. 1 is a schematic diagram of another fault synchronization circuit provided by an embodiment of the present invention. Figure 3On the basis of the above embodiments, optionally, the signal processing module 10 includes: a digital signal processor (DSP) 11 and a complex programmable logic device (CPLD) 12. The complex programmable logic device 12 is respectively connected to the digital signal processor 11, the signal output terminal Sync and the feedback input terminal Fdb. The digital signal processor 11 is used to output a fault signal when a fault is detected in the energy storage inverter, and the complex programmable logic device 12 is used to generate a fault synchronization signal according to the fault signal; and the complex programmable logic device 12 is also used to generate a feedback signal according to the signal connected to the feedback input terminal Fdb, and the digital signal processor 11 is also used to determine whether other energy storage inverters in the energy storage inverter parallel system are faulty according to the feedback signal. In this embodiment, the digital signal processor 11 serves as the core digital processing component in the signal processing module 10, and the complex programmable logic device 12 can perform logic processing such as filtering and delaying on the connected signal. Exemplarily, any one of the digital signal processor 11 and the complex programmable logic device 12 can also be replaced by a different type of digital processing chip, such as a single-chip microcomputer and an FPGA (Field-Programmable Gate Array).

[0059] Continue to see Figure 3 On the basis of the above embodiments, the signal conversion unit 21 may optionally include: a control subunit 211, a switch subunit 212 and a transmission control subunit 213. The control end of the control subunit 211 is connected to the signal output end Sync, the first connection end of the control subunit 211 is connected to the common signal end COM, and the second connection end of the control subunit 211 is connected to the first power supply end V1 of the fault synchronization circuit 100. The control end of the switch subunit 212 is connected to the output end of the control subunit 211, the input end of the switch subunit 212 is connected to the common signal end COM, and the output end of the switch subunit 212 is connected to the fault synchronization signal bus LSFdb. The transmission control subunit 213 is connected between the first connection end of the control subunit 211 and the fault synchronization signal bus LSFdb.

[0060] The control subunit 211 is used to control the connection between the first connection terminal or the second connection terminal and the output terminal of the control subunit 211 according to the signal connected to its control terminal (i.e., the signal output by the signal output terminal Sync), so as to transmit the voltage connected to the first connection terminal or the second connection terminal of the control subunit 211 to the control terminal of the switch subunit 212. The voltage connected to the first connection terminal of the control subunit 211 may be the voltage connected to the common signal terminal COM, and the voltage connected to the second connection terminal may be the voltage connected to the first power terminal V1. The common signal terminal COM is different from the voltage connected to the first power terminal V1. For example, the first power terminal V1 is connected to a first power signal with a positive voltage, which may be 12V. The common signal terminal COM may be connected to a common ground signal. Exemplarily, the control subunit 211 can control the connection between different connection terminals and output terminals when its control terminal receives or does not receive the fault synchronization signal. For example, the control subunit 211 can transmit the voltage connected to the first power terminal V1 to the control terminal of the switch subunit 212 when its control terminal receives the fault synchronization signal, and transmit the voltage connected to the common signal terminal COM to the control terminal of the switch subunit 212 when it does not receive the fault synchronization signal. Exemplarily, the control subunit 211 can include a controllable switch device and a corresponding pull-up or pull-down structure.

[0061] The switch subunit 212 is used to control whether the input and output ends of the switch subunit 212 are connected according to the signal received by its control end, thereby controlling whether the common signal end COM is connected to the fault synchronization signal bus LSFdb. Exemplarily, the switch subunit 212 may include a controllable switch device.

[0062] The transmission control subunit 213 is used to control whether the signal on the fault synchronization signal bus LSFdb is transmitted to the first connection end of the control subunit 211. Exemplarily, the transmission control subunit 213 can be turned on or off according to the voltage difference between its two ends. The transmission control subunit 213 can have a unidirectional conduction structure. When the switch subunit 212 is not turned on, the transmission control subunit 213 can be turned on to provide the voltage connected to the first power supply terminal V1 to the fault synchronization signal bus LSFdb. When the energy storage inverter is powered off, the first power supply terminal V1 loses its power supply, and the transmission control subunit 213 can be turned off to prevent the voltage on the fault synchronization signal bus LSFdb from being transmitted to the second connection end of the control subunit 211, thereby preventing the voltage from being further transmitted to the control end of the switch subunit 212, so that the switch subunit 212 can remain turned off, avoiding the situation where the switch subunit 212 is mis-conducted due to the power failure of the energy storage inverter, and forcing the fault synchronization signal bus LSFdb to be pulled to the voltage connected to the common signal terminal COM.

[0063] The signal feedback unit 22 can be connected to the second power supply terminal V2 of the fault synchronization circuit 100. The voltage connected to the second power supply terminal V2 is different from the voltage connected to the common signal terminal COM. For example, the second power supply terminal V2 is connected to a second power supply signal with a positive voltage, which can be 3.3V. The signal feedback unit 22 can be turned on when the voltage on the fault synchronization signal bus LSFdb is equal to the voltage connected to the common signal terminal COM (i.e., the common signal), and transmit the common signal to the feedback input terminal Fdb, and when the voltage on the fault synchronization signal bus LSFdb is not equal to the voltage connected to the common signal terminal COM, it is turned off and the voltage connected to the second power supply terminal V2 is transmitted to the feedback input terminal Fdb. In this way, the signal processing module 10 can determine the voltage condition on the fault synchronization signal bus LSFdb according to the signal connected to the feedback input terminal Fdb, and then determine whether there is a faulty energy storage inverter in the parallel system.

[0064] Further, see Figure 4 On the basis of the above embodiments, the synchronization signal conversion module 20 may optionally further include: a surge suppression unit 23. The surge suppression unit 23 is connected between the common signal terminal COM and the fault synchronization signal bus LSFdb, and is used to protect the fault synchronization circuit 100 from internal device breakdown due to plugging or static electricity, etc., which can effectively improve the circuit reliability and safety.

[0065] Continue to see Figure 4 , based on the above embodiments, optionally, the fault synchronization circuit also includes: an isolation module 30. The isolation module 30 is respectively connected to the signal output terminal Sync, the feedback input terminal Fdb, the signal conversion unit 21 and the signal feedback unit 22. The isolation module 30 is specifically used to realize the isolation between the signal processing module 10 and the synchronous signal conversion module 20 to improve the circuit safety. Specifically, isolation chips with different widths and different withstand voltages can be selected according to the voltage level of the system to form the isolation module 30, so as to meet the requirements of safety spacing, creepage distance and withstand voltage test of different voltage level systems. It should be noted that at least one isolation structure can be set in the isolation module 30 according to safety requirements, and the isolation structure may include an isolation chip.

[0066] Specifically, the isolation module 30 may include: a pull-up unit 33, a first filter unit 31, a second filter unit 32 and an isolation unit 34. The first end of the pull-up unit 33 is connected to the third power supply terminal V3 of the fault synchronization circuit, and the second end of the pull-up unit 33 is connected to the signal output terminal Sync; the input end of the first filter unit 31 is connected to the signal output terminal Sync, the output end of the first filter unit 31 is connected to the first input end IN1 of the isolation unit 34, the first output end OUT1 of the isolation unit 34 is connected to the signal conversion unit 21, and can be specifically connected to the control end of the control subunit 211, the second input end IN2 of the isolation unit 34 is connected to the signal feedback unit 22, the second output end OUT2 of the isolation unit 34 is connected to the input end of the second filter unit 32, and the output end of the second filter unit 32 is connected to the feedback input end Fdb. Among them, the first input end IN1 of the isolation unit 34 corresponds to the signal transmitted by the first output end OUT1, the second input end IN2 of the isolation unit 34 corresponds to the signal transmitted by the second output end OUT2, and the isolation unit 34 may include an isolation chip. The pull-up unit 33 is used to pull the signal of the first input terminal IN1 of the isolation unit 34 to the voltage connected to the third power terminal V3 when the signal output terminal Sync does not output the fault synchronization signal. The third power terminal V3 is connected to a third power signal with a positive voltage, which can be 3.3V.

[0067] Continue to see Figure 4 On the basis of the above-mentioned embodiments, the energy storage inverter parallel system may optionally further include: a common signal bus LCOM. The common signal bus LCOM is connected to the common signal terminal COM of the fault synchronization circuit 100 in each energy storage inverter, and is used to provide a common signal so that the common signal terminals COM of all fault synchronization circuits 100 are connected to the same voltage.

[0068] Continue to see Figure 4 On the basis of the above embodiments, optionally, the fault synchronization circuit 100 further includes: an interface module 40. The interface module 40 can be used as an external interface of the fault synchronization circuit 100. The synchronization signal conversion module 20 can be connected to the fault synchronization signal bus LSFdb and the common signal bus LCOM through the interface module 40.

[0069] Continue to see Figure 4On the basis of the above embodiments, the fault synchronization circuit 100 may optionally further include: a parallel communication module 50. The parallel communication module 50 is connected to the signal processing module 10, and may be specifically connected to the digital signal processor 11. The parallel communication module 50 of any energy storage inverter in the energy storage inverter parallel system is connected to the parallel communication module 50 of other energy storage inverters in communication, so as to realize information interaction between the energy storage inverters and ensure the parallel operation of the energy storage inverters. Among them, each energy storage inverter in the parallel system may include a host and multiple slaves, and each slave may upload fault information to the host through the parallel communication module 50, so that the host can determine the specific fault information in the system. Among them, the fault information may include relevant data such as the fault type and the identity information (such as the number) of the energy storage inverter where the fault occurs. Exemplarily, the parallel communication module 50 may include a CAN chip, and may also be replaced by a processing chip with the same or similar functions, such as a single-chip microcomputer with transceiver functions, a digital processor, and an analog processing device.

[0070] The above embodiments illustrate the functional modules and functions of the fault synchronization circuit 100. Among the multiple energy storage inverters in the parallel system, one is the master and the others are slaves. The fault synchronization process in the parallel system is as follows:

[0071] When the digital signal processor 11 in the fault synchronization circuit 100 of the host detects a host fault, it sends a fault signal to the complex programmable logic device 12. The complex programmable logic device 12 forms a fault synchronization signal after filtering and delay logic processing and sends it to the isolation module 30 to achieve isolation required by safety regulations; after isolation by the isolation module 30, the isolation module 30 sends a control signal corresponding to the fault synchronization signal to the signal conversion unit 21, and the signal conversion unit 21 is controlled to process so that the common signal terminal COM is connected to the fault synchronization signal bus LSFdb, and the common signal connected to the common signal terminal COM is transmitted to the fault synchronization signal bus LSFdb, thereby completing the sending of the host's fault synchronization related signals. When the voltage on the fault synchronization signal bus LSFdb of the slave is equal to the voltage of the common signal terminal COM, the synchronization signal conversion module in the slave receives and processes the voltage. Specifically, the signal feedback unit 22 in the slave is turned on, and the voltage on the fault synchronization signal bus LSFdb is transmitted to the isolation module 30 to achieve isolation required by safety regulations. The isolation module 30 transmits the voltage related to the voltage fed back by the signal feedback unit 22 to the complex programmable logic device 12 for filtering delay logic processing. After processing, a feedback signal is formed and sent to the digital signal processor 11 in the slave for overall processing.

[0072] The above briefly describes the process in which the host sends fault synchronization related signals and the slave receives and analyzes the fault synchronization related signals when the host fails. When the slave fails, the process in which the slave sends fault synchronization related signals can refer to the process in which the host sends fault synchronization related signals, and the process in which the host and other slaves receive and analyze fault synchronization related signals can refer to the process in which the slave receives and analyzes fault synchronization related signals, which will not be described in detail. In short, no matter whether the host or the slave fails, the fault synchronization circuit 100 provided therein can pull the voltage on the fault synchronization signal bus LSFdb to the same voltage as the common signal terminal COM, thereby completing the sending of the fault synchronization related signals; and both the host and the slave can receive and analyze the fault synchronization related signals on the fault synchronization signal bus LSFdb.

[0073] When a fault occurs, the host not only sends a fault synchronization related signal to the fault synchronization signal bus LSFdb, but also receives a fault synchronization related signal sent by itself to confirm whether it has correctly completed the signal sending.

[0074] Exemplarily, when a slave fails, after completing the sending of the fault synchronization related signal, no matter what the current operating state of the slave is, it can be shut down immediately. When the host fails and needs to exit the parallel system, the host can control all slaves to shut down through the parallel communication module 50 while completing the sending of the fault synchronization related signal. Alternatively, when the host fails and needs to exit the parallel system, and the slaves have no faults at this time, the host can inform the slaves to compete for the position of a host through the parallel communication module 50 while completing the sending of the fault synchronization related signal. The slaves do not need to shut down. After the host exits the parallel system, the remaining energy storage inverters can continue to run in parallel.

[0075] The following is an illustrative description of the specific structures that each functional module of the fault synchronization circuit 100 may have, but it is not intended to limit the present invention.

[0076] Figure 5 FIG. 1 is a schematic diagram of another fault synchronization circuit provided by an embodiment of the present invention. Figure 5 In one embodiment, the control subunit 211 optionally includes: a first transistor Q1 and a first resistor R1; the gate of the first transistor Q1 is connected to the signal output terminal Sync, the first electrode of the first transistor Q1 is connected to the common signal terminal COM, the second electrode of the first transistor Q1 is respectively connected to the first end of the first resistor R1 and the output end of the control subunit 211, and the second end of the first resistor R1 is connected to the first power supply terminal V1. The first transistor Q1 is turned on or off according to the voltage of its gate, and the first resistor R1 can be used as a pull-up resistor.

[0077] Furthermore, the control subunit 211 may also include: a fourth resistor R4, a fifth resistor R5 and a first capacitor C1. The fourth resistor R4 is used as a current limiting resistor, connected between the signal output terminal Sync and the gate of the first transistor Q1; the fifth resistor R5 is used as a protection resistor, connected between the gate of the first transistor Q1 and the common signal terminal COM; the first capacitor C1 is used as a filter capacitor, connected between the gate of the first transistor Q1 and the common signal terminal COM.

[0078] The switch subunit 212 includes: a second transistor Q2; the gate of the second transistor Q2 is connected to the output end of the control subunit 211, the first electrode of the second transistor Q2 is connected to the common signal end COM, and the second electrode of the second transistor Q2 is connected to the fault synchronization signal bus LSFdb. The second transistor Q2 is turned on or off according to the voltage of its gate.

[0079] Furthermore, the switch subunit 212 may also include: a sixth resistor R6 and a seventh resistor R7; the sixth resistor R6 serves as a current limiting resistor, connected between the output end of the control subunit 211 and the gate of the second transistor Q2; the seventh resistor R7 serves as a protection resistor, connected between the gate of the second transistor Q2 and the common signal terminal COM.

[0080] The transmission control subunit 213 includes: a first diode D1 and a second resistor R2 connected in series between the first power supply terminal V1 and the fault synchronization signal bus LSFdb. The anode of the first diode D1 is used to connect to the first power supply terminal V1, and the cathode is used to connect to the fault synchronization signal bus LSFdb. Based on the first diode D1, unidirectional transmission of the transmission control subunit 213 can be achieved, and the second resistor R2 can be used as a protection resistor with functions such as current limiting.

[0081] The surge suppression unit 23 may include a bidirectional voltage regulator (TVS) D3, whose protection voltage is greater than the voltage of the first power signal connected to the first power terminal V1, for example, at least 1.1 times the first power signal. Exemplarily, the first power signal V1 is 12V, and the protection voltage of the bidirectional voltage regulator D3 can be set to 15V. In this way, it can effectively prevent the internal components of the fault protection circuit 100 from being broken down by surge voltages caused by static electricity caused by hand contact and plugging and unplugging.

[0082] The signal feedback unit 22 includes: a second diode D2 and a third resistor R3; the first electrode (e.g., cathode) of the second diode D2 is connected to the fault synchronization signal bus LSFdb, the second electrode (e.g., anode) of the second diode D2 is respectively connected to the first end of the third resistor R3 and the feedback input terminal Fdb, and the second end of the third resistor R3 is connected to the second power supply terminal V2 of the fault synchronization circuit. Based on the second diode D2, the unidirectional conduction of the signal feedback unit 22 can be realized, and the third resistor R3 can be used as a pull-up resistor; when the second diode D2 is turned on, the voltage on the fault synchronization signal bus LSFdb can be transmitted to the feedback input terminal Fdb; when the second diode D2 is turned off, the voltage connected to the second power supply terminal V2 is transmitted to the feedback input terminal Fdb through the third resistor R3.

[0083] Furthermore, the signal feedback unit 22 may further include: a second capacitor C2 , which serves as a filter capacitor and is connected between the first end of the third resistor R3 and the common signal end COM.

[0084] The first transistor Q1 and the second transistor Q2 can both be any type of controllable switch device, for example, both are MOS tubes, specifically both can be NMOS tubes, or can also be replaced by other controllable switch tubes such as triodes. The synchronization signal conversion module 20 as a whole can be an analog circuit composed of transistors, resistors, capacitors and diodes, etc., and can also be replaced by a chip with the same function, etc., without specific limitation.

[0085] Continue to see Figure 5 In the isolation module 30, the pull-up unit 33 may include an eighth resistor R8, which is connected between the third power supply terminal V3 and the signal output terminal Sync. The first filtering unit 31 may include a third capacitor C3 and a ninth resistor R9, which is connected between the signal output terminal Sync and the first input terminal of the isolation unit 34, and the third capacitor C3 is connected between the first input terminal of the isolation unit 34 and the ground terminal GND of the fault synchronization circuit. The second filtering unit 32 may include a fourth capacitor C4 and a tenth resistor R10, the tenth resistor R10 is connected between the feedback input terminal Fdb and the second output terminal of the isolation unit 34, and the fourth capacitor C4 is connected between the feedback input terminal Fdb and the ground terminal GND. The isolation unit 34 may include an isolation chip, and the isolation chip may select different isolation modes as needed, such as capacitive isolation, optical isolation or magnetic isolation. Figure 5 It is exemplified that each filtering unit has a first-order filtering circuit, but this is not intended to limit the present invention. In other implementations, each filtering unit may also be a multi-order filtering circuit or a digital filtering circuit.

[0086] On the basis of the above embodiments, the interface modules 40 of the energy storage inverters in the energy storage inverter parallel system are optionally connected in sequence, so that the fault synchronization circuits in the parallel system are connected hand in hand through the interface modules 40. For details, see Figure 6 .

[0087] Specifically, see Figure 5 In any fault synchronization circuit, the interface module 40 may include a first interface P1 and a second interface P2; the first interface P1 includes a first contact J1 and a second contact J2, and the second interface P2 includes a third contact J3 and a fourth contact J4. The first contact J1 and the third contact J3 in the same interface module 40 are connected via a first connection line L1, and the first contact J1 in any interface module 40 is connected to the third contact J3 in the previous interface module 40 via a second connection line L2; each first connection line L1 and each second connection line L2 constitute a fault synchronization signal bus LSFdb. The second contact J2 and the fourth contact J4 in the same interface module 40 are connected via a third connection line L3, and the second contact J2 in any interface module 40 is connected to the fourth contact J4 in the previous interface module 40 via a fourth connection line L4; each third connection line L3 and each fourth connection line L4 constitute a common signal bus LCOM.

[0088] In summary, Figure 5 Taking the fault synchronization circuit in as an example, its working process is as follows:

[0089] When the digital signal processor 11 detects a fault in the energy storage inverter, it sends a fault signal to the complex programmable logic device 12. The fault signal may be a low-speed synchronous fault signal, and its frequency may be less than 1kHz. The complex programmable logic device 12 performs filtering and delay logic processing on the fault signal to form a low level. The low level passes through the pull-up unit 33 and then enters the first filter unit 31 with an RC low-pass filter structure. After exiting the first filter unit 31, it enters the first input end of the isolation unit 34 for signal isolation. Then, the low level is output from the first output end of the isolation unit 34 and enters the control subunit 211. Specifically, it enters the gate of the first transistor Q1 after the fourth resistor R4 limits the current and the first capacitor C1 filters, and controls the first transistor Q1 to turn off. The voltage of the first power supply terminal V1 is transmitted to the gate of the second transistor Q2 through the first resistor R1 and the sixth resistor R6, and controls the second transistor Q2 to turn on, so that the common signal terminal COM is connected to the fault synchronization signal bus LSFdb. Then, when there is a faulty energy storage inverter in the parallel system, the level on the fault synchronization signal bus LSFdb becomes the same low level as the common signal, for example, 0V. When the level on the fault synchronization signal bus LSFdb is low, the 12V power supply voltage drop of the first power supply terminal V1 is all added to the first diode D1 and the second resistor R2, and the -3.3V voltage drop of the second power supply terminal V2 is all added to the third resistor R3 and the second diode D2.

[0090] When any energy storage inverter in the parallel system fails, the fault synchronization circuit therein will pull the fault synchronization signal bus LSFdb to a low level. At this time, both the host and the slave can detect the fault synchronization related signal on the bus and receive and process it. Specifically, the second diode D2 is turned on, and the low level is fed back to the second input end of the isolation unit 34. After the isolation process, the second output end of the isolation unit 34 outputs a low level and enters the second filter unit 32 with an RC low-pass filter structure for filtering. After the filtering is completed, it enters the complex programmable logic 12. The complex programmable logic 12 performs delay, filtering, and logic processing to form a feedback signal and send it to the digital signal processor 11 for fault reception processing. After the digital signal processor 11 of the slave detects the fault of the slave, it immediately shuts down the slave, and at the same time sends the fault information to the parallel communication module 50 of the host through the parallel communication module 50, and then transmits it to the digital signal processor 11 of the host for fault processing. The digital signal processor 11 of the host can send the fault information to the host computer and receive the new deployment command formed after the host computer processes the fault information. If only a slave fails, the failed slave is separated from the parallel system, and the remaining machines continue to operate in the network. After the digital signal processor 11 of the host detects the host failure, it can shut down the host and disconnect it from the grid system, and command each slave to shut down or command each slave to compete for a new master through the parallel communication module 50; and the digital signal processor 11 of the host can report the fault information to the host computer for maintenance or control of the new host.

[0091] When the digital signal processor 11 does not detect a fault in the energy storage inverter where it is located, it does not send a fault signal, and the complex programmable logic device 12, for example, does not output. At this time, the 3.3V high level of the third power supply terminal V3 enters the first input terminal of the isolation unit 34 via the eighth resistor R8 and the first filtering unit 31 for signal isolation, and then outputs a high level from the first output terminal of the isolation unit 34 to enter the control subunit 211. The high level controls the first transistor Q1 to turn on, so that the low level of the common signal terminal COM is transmitted to the gate of the second transistor Q2 via the first transistor Q1 and the sixth resistor R6, and controls the second transistor Q2 to turn off; the 12V power supply of the first power supply terminal V1 is transmitted to the fault synchronization signal bus LSFdb via the first diode D1 and the second resistor R2. At this time, if the 12V power supply of the first power supply terminal V1 has abnormally high voltage, the bidirectional voltage regulator D3 will break down and conduct, clamping the voltage to no more than 15V, protecting other circuits connected to the bidirectional voltage regulator D3; when a person is plugging and unplugging the fault synchronization signal bus LSFdb, if there is static electricity, the bidirectional voltage regulator D3 will also be broken down, discharging static electricity energy, protecting the components connected to the bidirectional voltage regulator D3 from being damaged by static electricity. Then, when all energy storage inverters have no faults, the fault synchronization signal bus LSFdb maintains a high level of 12V. At this time, the second diode D2 in each fault synchronization circuit is reverse biased and non-conductive. The high level of the second power supply terminal V2 is filtered by the third resistor R3 and the second capacitor C2 and then fed back to the second input terminal of the isolation unit 34. The level is high, and the level transmitted to the feedback input terminal Fdb via the isolation module 30 is also high, which is consistent with the level logic on the fault synchronization signal bus LSFdb.

[0092] When any energy storage inverter loses power, the other energy storage inverters run normally in parallel and have no faults. The fault synchronization signal bus LSFdb can be set high normally. Due to the existence of the first diode D1, the high level will not be added back to the inside of the power-off machine, and will not be transmitted to the gate of the second transistor Q2 of the power-off energy storage inverter. Therefore, the second transistor Q2 will not be turned on, and the fault synchronization signal bus LSFdb will not be clamped to 0V connected to the common signal terminal COM, so it will not affect the normal synchronous operation of other machines.

[0093] It should be noted that the voltages of the power supply terminals mentioned above are examples, and the actual power supply voltage can be replaced with different voltage levels according to different circuits and devices.

[0094] The embodiment of the present invention also provides an energy storage inverter parallel system, which includes a fault synchronization signal bus and multiple energy storage inverters, each of which includes a fault synchronization circuit as provided in any embodiment of the present invention, and has corresponding beneficial effects. The energy storage inverter parallel system can be specifically applied to 5-20KW three-phase household energy storage parallel projects.

[0095] Figure 6 FIG. 1 is a schematic diagram of another energy storage inverter parallel system provided by an embodiment of the present invention. Figure 6 On the basis of the above embodiments, optionally, the energy storage inverter parallel system further includes: a host computer, which is respectively connected to the signal processing modules in each fault synchronization circuit 100, and specifically can be connected to the digital signal processor 11. The host computer can include at least one of a cloud platform 200 and an energy management system (EMS) 300.

[0096] Among them, the fault synchronization circuit 100 may also include: a parallel communication module, and the parallel communication modules of each energy storage inverter can be connected in a chain or other connection mode, and each parallel communication module can communicate with any other parallel communication module. One of the multiple energy storage inverters is the host, and the other energy storage inverters are slaves. When the host has a fault, the signal processing module in the host (specifically, the digital signal processor 11) uploads the fault information of the host to the host. When the slave has a fault, the parallel communication module in the slave transmits the fault information of the slave to the parallel communication module of the host. Specifically, the fault information of the slave can be generated by the signal processing module in the slave (specifically, the digital signal processor 11), and the fault information of the slave is finally transmitted to the host for processing via the signal transmission path of the slave signal processing module-the slave parallel communication module-the host parallel communication module-the host signal processing module-the host.

[0097] In summary, when a slave fails, the slave needs to report to the slave control unit for fault protection shutdown, and at the same time report to the host to let the host know that the slave has failed and cannot operate, and the slave needs to be disconnected from the parallel system; when a master fails, the master needs to shut down and inform the slave of the fault, and the master needs to shut down all machines or disconnect from the parallel system, and inform the remaining slaves that a new master needs to be automatically generated through competitive employment to keep the parallel system running.

[0098] In order to verify the fault synchronization effect in the parallel system equipped with the fault synchronization circuit, the inventor simulated the circuit. The simulation results can be found in Figure 7 and Figure 8 ,in, Figure 7 A comparison diagram of the fault synchronization related MOUT output from the host signal output terminal and the signal SIN connected to the slave feedback input terminal is shown, wherein the lower half is an enlarged schematic diagram of the rectangular frame in the upper half;

[0099] Figure 8The waveform diagram of the fault synchronization signal bus is shown, where the lower part is an enlarged diagram of the rectangular frame in the upper part. Figure 7 and Figure 8 It can be seen that the signal sent by the host is basically the same as the signal received by the slave, with almost no delay time. Among them, the amplitude of the signal sent by the main board is 3.36V, and the amplitude of the signal received by the slave is 4.06V, and the frequency is 500Hz.

[0100] During actual testing, the test interface may include a debugging setting section, a register setting section, and a data display section to facilitate the adjustment of the test process and the intuitive display of the test results. Among them, when the fault synchronization related signal is normal, no fault will be reported; when the fault synchronization related signal is abnormal, the machine will automatically report a synchronization fault. The fault results can be displayed in a list, and the abnormal results and abnormal time can be displayed in the list. When the fault synchronization related signal is abnormal, "Appear" can be displayed at the abnormal result, and when the fault synchronization related signal is normal, "Disappear" can be displayed at the abnormal result.

[0101] In summary, the embodiment of the present invention provides a fault synchronization solution for a parallel energy storage inverter system, which can support a minimum operating frequency of 0 Hz and a maximum operating frequency of more than 2 MHz. Moreover, if any machine in the parallel system loses power, it will not affect other machines and will not lower the bus voltage to cause other machines to shut down.

[0102] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0103] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A fault synchronization circuit, characterized in that: Applicable to any energy storage inverter in the energy storage inverter parallel system; The energy storage inverter parallel system includes a fault synchronization signal bus; The fault synchronization circuit comprises: A signal processing module, comprising a signal output terminal and a feedback input terminal; the signal processing module is used to output a fault synchronization signal from the signal output terminal when a fault is detected in the energy storage inverter, and to determine whether other energy storage inverters in the energy storage inverter parallel system are faulty according to the signal received by the feedback input terminal; A synchronous signal conversion module comprises a signal conversion unit and a signal feedback unit; the signal conversion unit is respectively connected to the signal output end, the common signal end of the fault synchronization circuit and the fault synchronization signal bus; the common signal end of the fault synchronization circuit of all the energy storage inverters in the energy storage inverter parallel system is connected to the same voltage; the signal conversion unit is used to control the common signal end to be connected to the fault synchronization signal bus when the signal processing module outputs the fault synchronization signal, and to control the common signal end to be disconnected from the fault synchronization signal bus when the energy storage inverter is powered off; the signal feedback unit is respectively connected to the fault synchronization signal bus and the feedback input end; the signal feedback unit is used to be turned on when the fault synchronization signal bus is connected to the common signal end of at least one of the fault synchronization circuits.

2. The fault synchronization circuit according to claim 1, characterized in that: The signal conversion unit comprises: A control subunit, wherein the control end of the control subunit is connected to the signal output end, the first connection end of the control subunit is connected to the common signal end, and the second connection end of the control subunit is connected to the first power supply end of the fault synchronization circuit; the control subunit is used to control the connection between the first connection end or the second connection end and the output end of the control subunit according to the signal connected to its control end; the common signal end and the first power supply end are connected to different voltages; A switch subunit, wherein the control end of the switch subunit is connected to the output end of the control subunit, the input end of the switch subunit is connected to the common signal end, and the output end of the switch subunit is connected to the fault synchronization signal bus; the switch subunit is used to control whether the input end and the output end of the switch subunit are connected according to the signal connected to the control end; The transmission control subunit is connected between the first connection end and the fault synchronization signal bus, and is used to control whether the signal on the fault synchronization signal bus is transmitted to the first connection end.

3. The fault synchronization circuit according to claim 2, characterized in that: The control subunit includes: a first transistor and a first resistor; the gate of the first transistor is connected to the signal output terminal, the first electrode of the first transistor is connected to the common signal terminal, the second electrode of the first transistor is respectively connected to the first end of the first resistor and the output end of the control subunit, and the second end of the first resistor is connected to the first power supply terminal; The switch subunit comprises: a second transistor; a gate of the second transistor is connected to the output end of the control subunit, a first electrode of the second transistor is connected to the common signal end, and a second electrode of the second transistor is connected to the fault synchronization signal bus; The transmission control subunit includes: a first diode and a second resistor connected in series between the first power supply terminal and the fault synchronization signal bus; The signal feedback unit includes: a second diode and a third resistor; the first pole of the second diode is connected to the fault synchronization signal bus, the second pole of the second diode is respectively connected to the first end of the third resistor and the feedback input end, and the second end of the third resistor is connected to the second power supply end of the fault synchronization circuit; the voltage connected to the common signal end is different from that of the second power supply end.

4. The fault synchronization circuit according to claim 3, characterized in that: The control subunit further includes: a fourth resistor, a fifth resistor and a first capacitor; the fourth resistor is connected between the signal output terminal and the gate of the first transistor, and the fifth resistor and the first capacitor are both connected between the gate of the first transistor and the common signal terminal; The switch subunit further includes: a sixth resistor and a seventh resistor; the sixth resistor is connected between the output terminal of the control subunit and the gate of the second transistor, and the seventh resistor is connected between the gate of the second transistor and the common signal terminal; The signal feedback unit further includes: a second capacitor connected between the first end of the third resistor and the common signal end.

5. The fault synchronization circuit according to any one of claims 1 to 4, characterized in that: The signal processing module includes: a digital signal processor and a complex programmable logic device; The complex programmable logic device is respectively connected to the digital signal processor, the signal output end and the feedback input end; the digital signal processor is used to output a fault signal when a fault is detected in the energy storage inverter, and the complex programmable logic device is used to generate the fault synchronization signal according to the fault signal; and the complex programmable logic device is also used to generate a feedback signal according to the signal connected to the feedback input end, and the digital signal processor is also used to determine whether other energy storage inverters in the energy storage inverter parallel system are faulty according to the feedback signal.

6. The fault synchronization circuit according to any one of claims 1 to 4, characterized in that: The synchronization signal conversion module further includes: a surge suppression unit connected between the common signal terminal and the fault synchronization signal bus; And / or, the fault synchronization circuit further includes: a parallel communication module connected to the signal processing module; the parallel communication module of any energy storage inverter in the energy storage inverter parallel system is communicatively connected with the parallel communication module of other energy storage inverters; And / or, the energy storage inverter parallel system further includes: a common signal bus connected to the common signal end of the fault synchronization circuit in each of the energy storage inverters; And / or, the fault synchronization circuit further comprises: an interface module, the synchronization signal conversion module is connected to the fault synchronization signal bus through the interface module; And / or, the fault synchronization circuit further includes: an isolation module, which is respectively connected to the signal output end, the feedback input end, the signal conversion unit and the signal feedback unit.

7. The fault synchronization circuit according to claim 1, characterized in that: It also includes an isolation module; the isolation module includes: a pull-up unit, a first filtering unit, a second filtering unit and an isolation unit; The first end of the pull-up unit is connected to the third power supply end of the fault synchronization circuit, and the second end of the pull-up unit is connected to the signal output end; the input end of the first filtering unit is connected to the signal output end, the output end of the first filtering unit is connected to the first input end of the isolation unit, the first output end of the isolation unit is connected to the signal conversion unit, the second input end of the isolation unit is connected to the signal feedback unit, the second output end of the isolation unit is connected to the input end of the second filtering unit, and the output end of the second filtering unit is connected to the feedback input end.

8. The fault synchronization circuit according to claim 1, characterized in that: The energy storage inverter parallel system also includes: a common signal bus connected to the common signal end of the fault synchronization circuit in each of the energy storage inverters; the fault synchronization circuit also includes: an interface module; the interface modules of each of the energy storage inverters in the energy storage inverter parallel system are connected in sequence; Wherein, the interface module includes a first interface and a second interface; the first interface includes a first contact and a second contact, and the second interface includes a third contact and a fourth contact; The first contact and the third contact in the same interface module are connected via a first connecting line, and the first contact in any interface module is connected to the third contact in the previous interface module via a second connecting line; each of the first connecting lines and each of the second connecting lines constitute the fault synchronization signal bus; the second contact and the fourth contact in the same interface module are connected via a third connecting line, and the second contact in any interface module is connected to the fourth contact in the previous interface module via a fourth connecting line; each of the third connecting lines and each of the fourth connecting lines constitute the common signal bus.

9. An energy storage inverter parallel system, characterized in that: include: A fault synchronization signal bus and multiple energy storage inverters, each of the energy storage inverters includes a fault synchronization circuit as described in any one of claims 1-8.

10. The energy storage inverter parallel system according to claim 9, characterized in that: Also includes: A host computer, connected to the signal processing modules in each of the fault synchronization circuits respectively; Among them, the fault synchronization circuit includes: a parallel communication module; one energy storage inverter among the multiple energy storage inverters is the host, and the other energy storage inverters are slaves; when the host has a fault, the signal processing module in the host uploads the fault information of the host to the host computer; when the slave has a fault, the parallel communication module in the slave transmits the fault information of the slave to the parallel communication module of the host.

Images