System for mutual inductance cancellation of t-type multilevel converter

Abstract

A system for mutual inductance cancellation for a T-type multilevel converter is provided. A multi-phase power inverter for an electric propulsion system includes a plurality of T-type multi-level power converters arranged between a high voltage direct current (DC) power source and an electric machine. Each of the plurality of T-type multilevel power converters is a solid state integrated circuit including a positive DC power bus, a negative DC power bus, a neutral bus, and a plurality of semiconductor switches disposed in a stacked arrangement. The plurality of semiconductor switches are interconnected by a positive DC power bus, a negative DC power bus, and a neutral bus.

Description

Technical Field

[0001] Concepts described herein generally relate to vehicles employing an electrified powertrain or propulsion system consisting of a direct current (DC) power source providing electrical power to a multi-phase power inverter to control the operation of one or more electric machines. Background Art

[0002] As the trend of transportation electrification rapidly expands toward high-capacity public transportation systems (such as electric airplanes, trains, and ships), high-voltage and high-power multilevel inverters (MLIs) have received attention. MLIs such as neutral point clamped (NPC) and bidirectional three-phase / three-level (T-type) inverters provide high voltage and high power operating capabilities, but may require stacked DC link capacitors with neutral point connections to achieve zero voltage vectors. Such neutral point connections to stacked DC link capacitors may generate neutral point currents that oscillate at three times the fundamental frequency, which may cause capacitor voltage imbalance and overvoltage stress on capacitors and switching devices.

[0003] The multi-phase inverter circuit may generate an inherent power loop in which high current flows from the DC link capacitor to the high side of the multi-level power inverter, then to the low side of the multi-level power inverter and back. The power loop may generate a magnetic field that forms a parasitic inductance.

[0004] Since multi-phase power inverters operate at higher switching frequencies, even small parasitic inductances may cause problems such as, but not limited to, ringing and / or electromagnetic interference (EMI).

[0005] The current flow path determines the size of the power loop, which determines the size of the generated magnetic field and, thereby, the size of the parasitic inductance, and is defined by the topology of the circuit, which may affect the size of the parasitic inductance. Summary of the invention

[0006] In view of the above discussion, it would be useful to develop a system and method for mutual inductance cancellation of a multiphase power inverter including a plurality of T-type multilevel power converters having a topology that reduces parasitic inductance within the multiphase power inverter.

[0007] The concepts disclosed herein relate to a system of a multiphase power inverter for an electric drive system, comprising a plurality of T-type multilevel power converters arranged between a high voltage direct current (DC) power source and an electric machine, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC) comprising: a positive DC power bus; a negative DC power bus; a neutral bus; and a plurality of semiconductor switching switches arranged in a stacked arrangement. A plurality of semiconductor switching switches are interconnected via a positive DC power bus, a negative DC power bus and a neutral bus, and the plurality of semiconductor switching switches include: a first semiconductor switch connected to a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch and the second semiconductor switch are arranged in series between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch via a neutral bus; and an alternating current (AC) bus connected to the first node, wherein the AC bus is connected to an electric machine; a first heat sink adjacent to at least one of the positive DC power bus and / or the negative DC power bus of a solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink adjacent to the neutral bus of the solid-state IC via a second DBC substrate.

[0008] Another aspect of the present disclosure may include a stacked arrangement including a first layer consisting of a first semiconductor switch arranged coplanar with a second semiconductor switch; and a second layer consisting of a third semiconductor switch arranged coplanar with a fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0009] Another aspect of the present disclosure may include the positive DC power bus and the negative DC power bus being disposed at a first end of a T-type multilevel power converter, and wherein the AC bus is disposed at a second end of the T-type multilevel power converter.

[0010] Another aspect of the present disclosure may include an AC bus being arranged in parallel with at least one of a positive DC power bus, a negative DC power bus, and / or a neutral bus.

[0011] Another aspect of the present disclosure may include each of the first semiconductor switch and the second semiconductor switch being a gallium nitride (GaN) device.

[0012] Another aspect of the present disclosure may include each of the third semiconductor switch and the fourth semiconductor switch being an insulated gate bipolar transistor (IGBT).

[0013] Another aspect of the present disclosure may include a stack having: a first layer consisting of a first semiconductor switch; a second layer consisting of a third semiconductor switch arranged coplanar with a fourth semiconductor switch, wherein the second layer is arranged parallel to the first layer; and a third layer consisting of a second semiconductor switch, wherein the third layer is arranged parallel to the second layer.

[0014] Another aspect of the present disclosure may include the positive DC power bus and the negative DC power bus being disposed at a first end of a T-type multilevel power converter, and wherein the AC bus is disposed at a second end of the T-type multilevel power converter.

[0015] Another aspect of the present disclosure may include an AC bus being arranged in parallel with at least one of a positive DC power bus, a negative DC power bus, and / or a neutral bus.

[0016] Another aspect of the present disclosure may include a T-type multi-level power converter for a multi-phase power inverter of an electric propulsion system, comprising a solid-state integrated circuit (IC) having: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected at the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and an AC bus connected to the first node; a first heat sink adjacent to at least one of the positive DC power bus and / or the negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink adjacent to the neutral bus of the solid-state IC via a second DBC substrate.

[0017] Another aspect of the present disclosure may include an electrified vehicle including an electric propulsion system, comprising: an electric motor configured to provide power to a vehicle driveline; a multiphase power inverter including a plurality of T-type multilevel power converters arranged between a high voltage direct current (DC) power source and the electric motor, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC), the solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus. A plurality of semiconductor switches include: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch and the second semiconductor switch are arranged in series between a positive DC power bus and a negative DC power bus; a third semiconductor switch connected at the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch via a neutral bus; and an AC bus connected to the first node; a first heat sink adjacent to at least one of a positive DC power bus and / or a negative DC power bus of a solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink adjacent to a neutral bus of the solid-state IC via a second DBC substrate.

[0018] Another aspect of the present disclosure may include a method for eliminating inductance in a multi-phase power inverter, comprising: arranging a plurality of semiconductor switches into a T-type multi-level stack; assembling the plurality of semiconductor switches arranged into a T-type multi-level stack into a solid-state integrated circuit (IC), the solid-state integrated circuit (IC) having: a positive DC power bus; a negative DC power bus; and a neutral bus; and interconnecting the plurality of semiconductor switches via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0019] Another aspect of the present disclosure may include arranging a plurality of semiconductor switches into a first layer and a second layer; wherein the first layer is composed of a first semiconductor switch arranged coplanar with a second semiconductor switch, and the second layer is composed of a third semiconductor switch arranged coplanar with a fourth semiconductor switch; and wherein the first layer is arranged parallel to the second layer.

[0020] The following options are provided:

[0021] 1. A multiphase power inverter for an electric drive system, the multiphase power inverter comprising:

[0022] A plurality of T-type multilevel power converters are arranged between a high voltage DC power source and an electric machine, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC) comprising:

[0023] Positive DC power bus;

[0024] Negative DC power bus;

[0025] Neutral bus;

[0026] A plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via a positive DC power bus, a negative DC power bus, and a neutral bus, the plurality of semiconductor switches comprising:

[0027] a first semiconductor switch connected to the first node;

[0028] a second semiconductor switch connected to the first semiconductor switch at a first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus;

[0029] a third semiconductor switch connected to the first node;

[0030] a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and

[0031] an AC bus connected to the first node, wherein the AC bus is connected to the electric machine;

[0032] a first heat sink abutting at least one of a positive DC power bus and / or a negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and

[0033] The second heat sink is adjacent to the neutral bus of the solid-state IC via the second DBC substrate.

[0034] 2. The multiphase power inverter of claim 1, wherein the stack arrangement comprises a stack having:

[0035] a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch; and

[0036] A second layer is composed of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0037] 3. The multiphase power inverter according to claim 2, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of a T-type multilevel power converter, and wherein the AC bus is arranged at a second end of the T-type multilevel power converter.

[0038] 4. The multiphase power inverter according to claim 3, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus.

[0039] 5. The multiphase power inverter according to claim 2, wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device.

[0040] 6. The multiphase power inverter according to claim 2, wherein each of the third semiconductor switch and the fourth semiconductor switch comprises an insulated gate bipolar transistor (IGBT).

[0041] 7. The multiphase power inverter of claim 1, wherein the stack arrangement comprises a stack having:

[0042] a first layer consisting of a first semiconductor switch;

[0043] a second layer consisting of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the second layer is arranged parallel to the first layer; and

[0044] A third layer is composed of second semiconductor switches, wherein the third layer is arranged in parallel with the second layer.

[0045] 8. The multiphase power inverter according to claim 7, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of a T-type multilevel power converter, and wherein the AC bus is arranged at a second end of the T-type multilevel power converter.

[0046] 9. The multiphase power inverter of claim 8, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus.

[0047] 10. The multiphase power inverter of claim 7, wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device.

[0048] 11. The multiphase power inverter of claim 7, wherein each of the third semiconductor switch and the fourth semiconductor switch comprises an insulated gate bipolar transistor (IGBT).

[0049] 12. A T-type multi-level power converter for a multi-phase power inverter of an electric propulsion system, the T-type multi-level power converter comprising:

[0050] A solid-state integrated circuit (IC) having:

[0051] Positive DC power bus;

[0052] Negative DC power bus;

[0053] Neutral bus;

[0054] A plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via a positive DC power bus, a negative DC power bus, and a neutral bus, the plurality of semiconductor switches comprising:

[0055] A first semiconductor switch connected to a first node;

[0056] a second semiconductor switch connected to the first semiconductor switch at a first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus;

[0057] a third semiconductor switch connected to the first node;

[0058] a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and

[0059] An AC bus connected to the first node;

[0060] a first heat sink abutting at least one of a positive DC power bus and / or a negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and

[0061] The second heat sink is adjacent to the neutral bus of the solid-state IC via the second DBC substrate.

[0062] 13. The T-type multilevel power converter according to claim 12, wherein the stack arrangement comprises a stack having:

[0063] a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch; and

[0064] A second layer is composed of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0065] 14. The T-type multilevel power converter according to claim 12, wherein the stack arrangement comprises a stack having:

[0066] a first layer consisting of a first semiconductor switch;

[0067] a second layer consisting of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the second layer is arranged parallel to the first layer; and

[0068] A third layer is composed of second semiconductor switches, wherein the third layer is arranged in parallel with the second layer.

[0069] 15. The T-type multi-level power converter according to aspect 12, wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device.

[0070] 16. The T-type multilevel power converter according to aspect 12, wherein each of the third semiconductor switch and the fourth semiconductor switch comprises an insulated gate bipolar transistor (IGBT).

[0071] 17. An electrified vehicle comprising:

[0072] Electric propulsion system, including:

[0073] an electric motor configured to provide power to a vehicle driveline;

[0074] A multiphase power inverter, comprising a plurality of T-type multilevel power converters arranged between a high voltage direct current (DC) power source and a motor, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC), the solid-state integrated circuit (IC) comprising:

[0075] Positive DC power bus;

[0076] Negative DC power bus;

[0077] Neutral bus;

[0078] A plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via a positive DC power bus, a negative DC power bus, and a neutral bus, the plurality of semiconductor switches comprising:

[0079] A first semiconductor switch connected to a first node;

[0080] a second semiconductor switch connected to the first semiconductor switch at a first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus;

[0081] a third semiconductor switch connected to the first node;

[0082] a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and

[0083] An AC bus connected to the first node;

[0084] a first heat sink abutting at least one of a positive DC power bus and / or a negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and

[0085] The second heat sink is adjacent to the neutral bus of the solid-state IC via the second DBC substrate.

[0086] 18. The electrified vehicle of claim 17, wherein the stack arrangement comprises a stack having:

[0087] a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch; and

[0088] A second layer is composed of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0089] 19. The electrified vehicle of claim 17, wherein the stack arrangement comprises a stack having:

[0090] a first layer consisting of a first semiconductor switch;

[0091] a second layer consisting of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the second layer is arranged parallel to the first layer; and

[0092] A third layer is composed of second semiconductor switches, wherein the third layer is arranged in parallel with the second layer.

[0093] 20. The electrified vehicle of claim 17, wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device; and

[0094] Each of the third semiconductor switch and the fourth semiconductor switch includes an insulated gate bipolar transistor (IGBT).

[0095] The above-mentioned features and advantages of the present disclosure and other features and attendant advantages will be readily apparent from the following detailed description of illustrative examples and modes of implementing the present disclosure when combined with the accompanying drawings and the appended claims. In addition, the present disclosure explicitly includes combinations and sub-combinations of the elements and features presented above and below. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate implementations of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0097] Figure 1 An electric powertrain system according to the present disclosure is schematically illustrated and includes a multi-phase power inverter disposed between a high voltage direct current (DC) power source and an electric machine.

[0098] Figure 2 An electric drivetrain including a multi-phase power inverter including a plurality of T-type multi-level power converters arranged between a high voltage DC power source and an electric machine according to the present disclosure is schematically illustrated.

[0099] Figure 3 A T-type multi-level power converter according to one aspect of the present disclosure is schematically illustrated.

[0100] Figure 4A cross-sectional side view of a T-type multi-level power converter according to one aspect of the present disclosure is schematically shown.

[0101] Figure 5 Schematically illustrates a cross-sectional side view of a T-type multi-level power converter according to another aspect of the present disclosure.

[0102] Figure 6 Schematically illustrates an isometric view of the arrangement of components of a T-type multilevel power converter according to one aspect of the present disclosure.

[0103] Figure 7 Schematically illustrates an isometric view of an arrangement of components of a T-type multilevel power converter according to another aspect of the present disclosure.

[0104] The accompanying drawings are not necessarily drawn to scale and may present somewhat simplified representations of various preferred features of the present disclosure disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes. The details surrounding these features will be determined in part by the specific intended application and use environment. DETAILED DESCRIPTION

[0105] The components of the disclosed embodiments described and shown herein may be arranged and designed in various configurations. Therefore, the following detailed description is not intended to limit the scope of the disclosure claimed for protection, but is merely a representative of its possible embodiments. In addition, although many specific details are set forth in the following description to provide a comprehensive understanding of the embodiments disclosed herein, some embodiments may be practiced without some of these details. In addition, for the sake of clarity, some technical materials understood in the relevant art are not described in detail to avoid unnecessarily obscuring the disclosure. In addition, as shown and described herein, the disclosure may be practiced in the absence of elements not specifically disclosed herein.

[0106] The present disclosure allows for many different forms of embodiments. Representative examples of the present disclosure are shown in the accompanying drawings and are described in detail herein as non-limiting examples of the disclosed principles. For this reason, elements and limitations described herein but not explicitly set forth in the claims should not be incorporated into the claims individually or collectively by implication, inference or otherwise.

[0107] For the purposes of this description, unless otherwise stated, the use of the singular includes the plural and vice versa, the terms "and" and "or" shall be conjunctions and disjunctions, and the words "including," "comprising," "containing," "having," and the like shall mean "including but not limited to." In addition, approximate words, such as "approximately," "almost," "substantially," "generally," "approximately," and the like, may be used herein in the following senses: "at, close to, or approximately at," or "within 0-5% of ...," or "within an acceptable manufacturing tolerance," or their logical combinations.

[0108] As used herein, the term "system" refers to mechanical and electrical hardware, software, firmware, electronic control components, processing logic and / or processor devices, alone or in combination, including but not limited to: application-specific integrated circuits (ASICs), electronic circuits, processors (shared, dedicated or grouped) that execute one or more software or firmware programs, memory devices that electrically store software or firmware instructions, combinational logic circuits and / or other components that provide the described functionality.

[0109] As used herein, terms such as "vertical," "horizontal," "left," "right," "upper," "lower," "top," "bottom" and similar expressions are non-limiting terms that merely describe the various elements shown in the figures and are not intended to limit the scope of the present disclosure.

[0110] As used herein, the term "electric machine" refers to an electric motor / generator device including a rotor and a stator that is capable of converting electrical power to mechanical power and / or converting mechanical power to electrical power through electromagnetic action.

[0111] Referring to the drawings, wherein like reference numerals refer to the same or similar components throughout the several views, Figure 1 and Figure 2 Schematically illustrated are elements of an electric drive system 100, which includes a high voltage direct current (DC) power source 101, a multiphase power inverter 104, a multiphase rotary motor / generator (electric machine) 10, and a torque actuator 120, the operation of which is monitored and controlled by a controller 30. According to one aspect of the present disclosure, the electric drive system 100 is arranged to generate torque and transmit it to an actuator 120 in the form of one or more drive wheels to perform work. The controller 30 executes a control routine to control and manage the operation of the multiphase power inverter 104. According to another aspect of the present disclosure, the electric drive system 100 is disposed on an electrified vehicle (schematically shown at 20) and is capable of generating traction torque for vehicle propulsion. When disposed on the electrified vehicle 20, the electrified vehicle 20 may include, but is not limited to, a mobile platform in the form of a commercial vehicle, an industrial vehicle, an agricultural vehicle, a bus, an airplane, a ship, a train, an all-terrain vehicle, a personal mobility device, a robot, etc., to achieve the purposes of the present disclosure. Alternatively, the electric drive system 100 may be an element of a fixed system.

[0112] The controller 30 may be embodied as one or more digital computing devices and may include one or more processors 34 and memory 32. A control routine 36 may be stored as a set of executable instructions in the memory 32 and executed by one of the processors 34 of the controller 30. The controller 30 communicates with the multi-phase power inverter 104 to control its operation in response to the execution of the control routine 36, thereby operating the electric machine 10.

[0113] The term "controller" and related terms such as microcontroller, control module, module, control, control unit, processor and similar terms refer to one or various combinations of application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), electronic circuits, central processing units (e.g., microprocessors) and associated memory components in the form of temporary and / or non-transitory memory components and storage devices (read-only, programmable read-only, random access, hard drives, etc.). The non-transitory memory components are capable of storing machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuits, input / output circuits and devices, signal conditioning and buffering circuits, and other components that can be accessed by one or more processors to provide the described functions. The input / output circuits and devices include analog / digital inverters and related devices that monitor inputs from sensors, monitoring these inputs at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms and similar terms mean the set of instructions executable by the controller, including calibration and lookup tables.

[0114] The electric machine 10 includes a cylindrical rotor assembly arranged on a rotor shaft and disposed within an annular stator, wherein the rotor assembly is coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10, such as end caps, bearings, electrical connections, etc., are included but not shown. The electrical windings of the stator are arranged with a certain number of electrical phases and a certain number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can be between 3 and 6, and the number of conductor layers can be between 4 and 12.

[0115] The multi-phase power inverter 104 includes a plurality of semiconductor switches (see Figure 3, etc.), the plurality of semiconductor switching switches are arranged and controllable by the controller 130 to convert DC electric power into alternating current (AC) electric power and convert AC electric power into DC electric power using a pulse width modulation signal 108 or another control technique. The multiphase power inverter 104 is arranged and controllable to convert DC electric power from the high-voltage DC power supply 101 into AC electric power to actuate the electric machine 10 via electromagnetic action. When operating in the torque generation mode, the electric machine 10 can be controlled to rotate and generate mechanical torque, which is transmitted to the actuator 120 via the rotatable member 12 and the gear system 114. The electric machine 10 is controllable by the controller 130 to generate AC electric power from the mechanical torque from the actuator 120 via electromagnetic action, and when operating in the electric power generation mode, the AC electric power is converted into DC electric power by the multiphase power inverter 104 to be stored in the high-voltage DC power supply 101. According to one aspect of the present disclosure, as part of a traction propulsion system, actuators 120 include wheels that transfer torque to the ground to achieve forward motion. High voltage DC power source 101 may be in the form of a rechargeable electrochemical battery device, a fuel cell, a supercapacitor, and / or another electrical energy storage / generation technology.

[0116] The high voltage DC power source 101 may be a rechargeable electrochemical battery device, a fuel cell, a supercapacitor and / or another electrical energy storage / generation technology. The high voltage DC power source 101 is connected to a multi-phase power inverter 104 via a high voltage DC bus having a positive link 102 and a negative link 103, and the multi-phase power inverter 104 is connected to the electric machine 10 via a plurality of first AC buses 121 and a second AC bus 122 to transmit a pulse width modulation signal 108.

[0117] As reference Figure 2 As shown, the multiphase power inverter 104 of the electric drive system 100 is composed of a plurality of T-type multilevel power converters 150 arranged between the high-voltage DC power source 101 and the electric machine 10, with a single DC link capacitor 105 between the high-voltage DC power source 101 and the multiphase power inverter 104 of the electric drive system 100. As shown and in one non-limiting aspect of the present disclosure, the multiphase power inverter 104 of the electric drive system 100 is composed of three T-type multilevel power converters 150.

[0118] Each T-type multilevel power converter 150 is arranged as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or layered arrangement.

[0119] Other constituent elements of the T-type multilevel power converter 150 include a positive DC power bus 110 , a neutral bus 111 , a negative DC power bus 112 , and an AC bus 121 , as well as other elements described herein.

[0120] Reference Figure 3 , the topology of each T-type multilevel power converter 150 is arranged as a multilevel inverter (MLI). According to one aspect of the present disclosure and as described herein, each T-type multilevel power converter 150 adopts a non-neutral point (NPL) MLI topology. Topology refers to the physical arrangement of constituent elements, including network busbar interconnections, dielectrics, semiconductor switches, and other elements.

[0121] In one aspect of the present disclosure and as shown, the plurality of semiconductor switches include a first semiconductor switch S1151, a second semiconductor switch S2152, a third semiconductor switch S3153, and a fourth semiconductor switch S4154. According to one aspect of the present disclosure, at least a portion of the semiconductor switches are field effect transistors (FETs). According to another aspect of the present disclosure, the FETs are gallium nitride (GaN) transistors. According to another aspect of the present disclosure, at least a portion of the semiconductor switches are insulated gate bipolar transistors (IGBTs).

[0122] The first semiconductor switch S1151 and the fourth semiconductor switch S4154 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112, and the first semiconductor switch S1151 is connected to the fourth semiconductor switch S4154 at the first node 161. The third semiconductor switch S3153 is also connected to the first node 161. The first node 161 is connected to the AC bus 121 to transfer power to the electric machine 10 (refer to Figure 2 ). The third semiconductor switch S3153 is arranged in series with the second semiconductor switch S2152, and the second semiconductor switch S2152 is connected to the neutral bus 111.

[0123] A positive DC power bus 110 , a neutral power bus 111 , and a negative DC power bus 112 are schematically shown.

[0124] By configuring the topology within each T-type multilevel converter 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111 , mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop current within each T-type multilevel converter 150 .

[0125] According to one aspect of the present disclosure, as shown in (I), the buses are configured from top 33 to bottom 34 such that positive DC power bus 110 is parallel to neutral bus 111 , which is then parallel to negative DC power bus 112 .

[0126] According to another aspect of the present disclosure, as shown in (II), the buses are configured from top 33 to bottom 34 such that positive DC power bus 110 is parallel to negative DC power bus 112 , which is then parallel to neutral bus 111 .

[0127] According to another aspect of the present disclosure, as shown in (III), the buses are configured from top 33 to bottom 34 such that neutral bus 111 is parallel to positive DC power bus 110 , which is then parallel to negative DC power bus 112 .

[0128] According to another aspect of the present disclosure, as shown in (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112 , while both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111 .

[0129] Although several topologies are discussed above, they are merely exemplary and non-limiting aspects of the present disclosure. Therefore, it should be understood that within each T-type multilevel converter 150, mutual inductance cancellation minimizes parasitic inductance by coupling positive mutual inductance and negative mutual inductance for the commutation loop current within each T-type multilevel converter 150, i.e., configuring the topology of the T-type multilevel inverter 150 so that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111.

[0130] Reference again Figure 3 The controller 130 controls activation and deactivation of the first semiconductor switch S1151, the second semiconductor switch S2152, the third semiconductor switch S3153 and the fourth semiconductor switch S4154 to convert DC electric power into AC electric power and convert AC electric power into DC electric power using the pulse width modulation signal 108.

[0131] Reference now Figure 4 , aspects of the present disclosure of a T-type multilevel power converter 150 include a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a positive DC power bus 110, a negative DC power bus 112, a neutral bus 111, a first node 161, a first direct bonded copper (DBC) plate 143, a second DBC plate 144, a third DBC plate 145, a plurality of conductive spacers 146, a first heat sink 141, and a second heat sink 142. The positive DC power bus 110 and the negative DC power bus are located at a first end 131 of the T-type multilevel power converter 150, and the AC bus 121 is located at a second end 132 opposite to the first end 131 of the T-type multilevel power converter 150. The first node 161 is connected to the AC bus 121 to transfer power to the reference Figure 1 and Figure 2One phase of the electric machine 10 is shown.

[0132] Reference again Figure 4 , the first semiconductor switch S1151, the second semiconductor switch S2152, the third semiconductor switch S3153, and the fourth semiconductor switch S4154 are arranged in a stacked or multi-layer configuration, including a first (lower) layer 135, a second (middle) layer 136, and a third (upper) layer 137. The first layer 135 includes the fourth semiconductor switch S4154 and the negative DC power bus 112 arranged on the first DBC board 143. The second layer 136 includes the second semiconductor switch S2152 and the third semiconductor switch S3153 (which are coplanar), the second DBC board 144, the neutral bus 111, and the AC bus 121. The third layer 137 includes the first semiconductor switch S1151 and the positive DC power bus 110 arranged on the third DBC board 145.

[0133] In ascending order from bottom 134 to top 133, the complete stack arrangement includes: a first heat sink 141; a first DBC board 143; a negative DC power bus 112; a first layer 135, including a second semiconductor switch S2152 and a fourth semiconductor switch S4154; a neutral bus 111; a second layer 136, including a fifth semiconductor switch S5155 and a sixth semiconductor switch S6156, an AC bus 121, a second AC bus 122, a second DBC board 144 and a plurality of conductive spacers 146; a third layer 137, including a first semiconductor switch S1151, a third semiconductor switch S3153 and a positive DC power bus 110; a third DBC board 145; and a second heat sink 142.

[0134] The first semiconductor switch S1151, the third semiconductor switch S3153 and the fourth semiconductor switch S4154 are coupled at a first node 161 connected to the AC bus 121. The first heat sink 141 is adjoined via a first DBC plate 143 and the second heat sink is adjoined via a third DBC plate 145.

[0135] Reference now Figure 5Another aspect of the present disclosure of a T-type multilevel power converter 250 includes a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a positive DC power bus 210, a negative DC power bus 212, a neutral bus 211, a first node 261, a first DBC board 243, a third DBC board 245, a plurality of conductive spacers 246, a first heat sink 241, and a second heat sink 242. The positive DC power bus 210 and the negative DC power bus 212 are located at a first end 231 of the T-type multilevel power converter 250, and the AC bus 221 is located at a second end 232 opposite to the first end 231 of the T-type multilevel power converter 250. The first node 261 is connected to the AC bus 221 to transfer power to the reference Figure 1 and Figure 2 One phase of the electric machine 10 is shown.

[0136] Reference again Figure 5 , the first semiconductor switch S1251, the second semiconductor switch S2252, the third semiconductor switch S3253 and the fourth semiconductor switch S4254 are arranged in a stacked or multi-layer configuration, including a first (lower) layer 235, a second (middle) layer 236 and a third (upper) layer 237. The first layer 235 includes the second semiconductor switch S2252 and the third semiconductor switch S3253 (which are coplanar), and a neutral bus 211 arranged on the first DBC board 243.

[0137] The second layer 236 includes a first node 261 connected to the AC bus 221 .

[0138] The third layer 237 includes a first semiconductor switch S1 251 and a fourth semiconductor switch S4 254 arranged on the third DBC board 245 , a positive DC power bus 210 , and a negative DC power bus 212 .

[0139] In ascending order from bottom 234 to top 233, the complete stack arrangement includes: a first heat sink 241, a first DBC plate 243; a first layer 235, including a neutral bus 211, a third semiconductor switch S3253 and a fourth semiconductor switch S4254; a second layer 236, including a first node 261 connected to the AC bus 121; a conductive spacer 246; a third layer 237, including a first semiconductor switch S1251 and a fourth semiconductor switch S4254 arranged coplanar with each other, a positive DC power bus 210 and a negative DC power bus 212 arranged coplanar with each other; a third DBC plate 245; and a second heat sink 242.

[0140] The first semiconductor switch S1 251, the third semiconductor switch S3 253 and the fourth semiconductor switch S4 254 are coupled at a first node 261 connected to the AC bus 221. The first heat sink 241 is adjoined via a first DBC plate 243 and the second heat sink is adjoined via a third DBC plate 245.

[0141] Figure 6 Aspects of the present disclosure of a T-type multilevel power converter 350 are schematically shown and include a first semiconductor switch S1 351, a second semiconductor switch S2 352, a third semiconductor switch S3 353, a fourth semiconductor switch S4 354, a positive DC power bus 310, and a negative DC power bus 312, which are connected to an AC bus 321. It should be understood that other elements that have been previously described have been omitted, but when put into practice, they are included in aspects of the present disclosure of the T-type multilevel power converter 350.

[0142] The first semiconductor switch S1351, the second semiconductor switch S2352, the third semiconductor switch S3353, and the fourth semiconductor switch S4354 are arranged in a stacked or multi-layer configuration, including a first (lower) layer 335, a second (middle) layer 336, and a third (upper) layer 337. The first layer 335 includes the coplanar second semiconductor switch S2352 and the third semiconductor switch S3353. The second layer 336 includes a first node 361 connected to the AC bus 321. The third layer 337 includes the coplanar first semiconductor switch S1351 and the fourth semiconductor switch S4354. The AC bus 321, the positive DC power bus 310, and the negative DC power bus 312 are connected as shown, with reference to FIG. Figure 3 The circuit arrangement shown is consistent.

[0143] Figure 7 Aspects of the present disclosure of a T-type multilevel power converter 450 are schematically shown and include a first semiconductor switch S1 451, a second semiconductor switch S2 452, a third semiconductor switch S3 453, a fourth semiconductor switch S4 454, a positive DC power bus 410, and a negative DC power bus 412, which are connected to an AC bus 421. It should be understood that other elements that have been previously described have been omitted, but when put into practice, they are included in aspects of the present disclosure of the T-type multilevel power converter 450.

[0144] The first semiconductor switch S1451, the second semiconductor switch S2452, the third semiconductor switch S3453, and the fourth semiconductor switch S4454 are arranged in a stacked or multi-layer configuration, including a first (lower) layer 435, a second (middle) layer 436, and a third (upper) layer 437. The first layer 435 includes the fourth semiconductor switch S4454 and the negative DC power bus 412. The second layer includes the coplanar second semiconductor S2452 and the third semiconductor switch S3453, and the AC bus 421 connected to the first node. The third layer 437 includes the first semiconductor switch S1451 and the positive DC power bus 410. The AC bus 421, the positive DC power bus 410, and the negative DC power bus 412 are connected as shown, with reference to FIG. Figure 3 The circuit arrangement shown is consistent.

[0145] The illustrated aspects of the present disclosure of a T-type multilevel power converter provide an overlap of a positive DC power bus, a neutral bus, and a negative DC power bus to reduce mutual inductance. This arrangement includes overlaying an AC bus on a second AC bus to cancel dV / dt and reduce or remove electromagnetic interference, and achieve field cancellation via P, 0, and N currents to minimize parasitic loops and stray inductance.

[0146] The concepts and aspects of the present disclosure described herein facilitate optimal design of the positive DC power bus, the negative DC power bus, the neutral bus, and the DC link capacitors to achieve mutual inductance cancellation.

[0147] The concepts and aspects of the present disclosure described herein facilitate various heat transfer and cooling systems, including direct cooling, indirect cooling, immersion cooling, single-sided or double-sided cooling.

[0148] The concepts and aspects of the present disclosure described herein facilitate reducing voltage / current overshoots that stress devices including die / power modules, bus bars, DC link capacitors.

[0149] The concepts and aspects of the present disclosure described herein facilitate reduced size and increased power density compared to current systems.

[0150] The concepts and aspects of the present disclosure described herein facilitate the use of lower voltage rated semiconductor switch dies to achieve lower conduction losses and increased EV range compared to current systems.

[0151] The concepts and aspects of the present disclosure described herein facilitate reducing ringing and radiated / conducted electromagnetic interference to other subsystems.

[0152] The concepts and aspects of the present disclosure described herein facilitate higher switching speeds, which reduces losses and thereby improves vehicle range and current capability.

[0153] In view of the foregoing disclosure, those skilled in the art will appreciate these and other attendant benefits of the present disclosure.

[0154] The detailed description and the accompanying drawings or figures are support and description of the present teaching, but the scope of the present teaching is limited only by the claims. Although some best modes and other examples for implementing the present teaching have been described in detail, there are various alternative designs and aspects of the present disclosure to practice the present teaching defined in the appended claims.

Claims

1. A multiphase power inverter for an electric drive system, the multiphase power inverter comprising: A plurality of T-type multilevel power converters are arranged between a high voltage DC power source and an electric machine, wherein each of the plurality of T-type multilevel power converters is a solid-state integrated circuit (IC) comprising: Positive DC power bus; Negative DC power bus; Neutral bus; A plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via a positive DC power bus, a negative DC power bus, and a neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected to the first node; a second semiconductor switch connected to the first semiconductor switch at a first node, wherein the first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected to the first node; a fourth semiconductor switch arranged in series with the third semiconductor switch via the neutral bus; and an AC bus connected to the first node, wherein the AC bus is connected to the electric machine; a first heat sink abutting at least one of a positive DC power bus and / or a negative DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and The second heat sink is adjacent to the neutral bus of the solid-state IC via the second DBC substrate.

2. The multiphase power inverter of claim 1 , wherein the stack arrangement comprises a stack having: a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch; and A second layer is composed of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

3. The multiphase power inverter of claim 2, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the T-type multilevel power converter, and wherein the AC bus is arranged at a second end of the T-type multilevel power converter.

4. The multiphase power inverter of claim 3, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus. 5 . The multiphase power inverter of claim 2 , wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device. 6 . The multiphase power inverter of claim 2 , wherein each of the third semiconductor switch and the fourth semiconductor switch comprises an insulated gate bipolar transistor (IGBT).

7. The multiphase power inverter of claim 1 , wherein the stack arrangement comprises a stack having: a first layer consisting of a first semiconductor switch; a second layer consisting of a third semiconductor switch arranged coplanarly with a fourth semiconductor switch, wherein the second layer is arranged parallel to the first layer; as well as A third layer is composed of second semiconductor switches, wherein the third layer is arranged in parallel with the second layer.

8. The multiphase power inverter of claim 7, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the T-type multilevel power converter, and wherein the AC bus is arranged at a second end of the T-type multilevel power converter.

9. The multiphase power inverter of claim 8, wherein the AC bus is arranged in parallel with at least one of the positive DC power bus, the negative DC power bus and / or the neutral bus.

10. The multiphase power inverter of claim 7, wherein each of the first semiconductor switch and the second semiconductor switch comprises a gallium nitride (GaN) device.

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