System for mutual inductance cancellation for H-type multilevel converter

Abstract

A multi-phase power inverter for an electric propulsion system includes a plurality of H-type multi-level power converters disposed between a high voltage DC power source and an electric machine. Each of the plurality of H-type multilevel power converters is a solid state integrated circuit (IC) including a positive DC power bus, a negative DC power bus, a neutral bus, and a plurality of semiconductor switches disposed in a stacked arrangement. The plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

Description

Technical Field

[0001] Concepts described herein generally relate to vehicles employing an electrified powertrain or propulsion system comprised of a direct current (DC) power source that provides electrical power to a multi-phase power converter to control the operation of one or more electric machines. Background Art

[0002] As the trend of transportation electrification is rapidly expanding toward high-capacity mass transportation systems (such as electric aircraft, trains, and ships), high-voltage and high-power multi-level inverters (MLIs) have gained attention. MLIs such as neutral point clamped (NPC) and T-type inverters provide high voltage and high power operating capabilities, but require stacked DC link capacitors with a neutral point connection for zero voltage vectors. This neutral point connection to the stacked DC link capacitors can generate a neutral current oscillating at three times the fundamental frequency, which can cause capacitor voltage imbalance and / or overvoltage stress on the capacitors and switchgear.

[0003] The multi-phase inverter circuit may generate an inherent power loop in which a high current flows from the DC link capacitor to the high side of the multi-level power inverter, then to the low side of the multi-level power inverter and back. The power loop may generate a magnetic field, which forms a parasitic inductance.

[0004] Since multi-phase power inverters operate at higher switching frequencies, even small levels of parasitic inductance may cause problems such as, but not limited to, ringing and / or electromagnetic interference (EMI).

[0005] The current flow path determines the size of the power loop, which determines the size of the generated magnetic field and thus the size of the parasitic inductance, and is defined by the topology of the circuit, which may affect the size of the parasitic inductance. Summary of the invention

[0006] In view of the above discussion, it would be useful to develop a system and method for mutual inductance cancellation of a multiphase power inverter including a plurality of H-type multilevel power converters having a topology that reduces parasitic inductance within the multiphase power inverter.

[0007] The concepts disclosed herein relate to a system for a multiphase power inverter including a plurality of H-type multilevel power converters that achieve mutual inductance cancellation. Such a system can be used in a vehicle with an electrified propulsion system, such as, but not limited to, an automobile with an electrified powertrain or propulsion system (e.g., an electric vehicle (EV) or a plug-in hybrid vehicle (PHEV)) or another mobile platform that can be powered by an electric propulsion system to reduce parasitic inductance within a multiphase power inverter.

[0008] Each multi-phase power inverter may include: a plurality of H-type multi-level power converters arranged between a high voltage direct current (DC) power source and the motor. The number of H-type multi-level power converters required is application specific.

[0009] Each H-type multilevel power converter is a solid-state integrated circuit (IC) comprising a plurality of circuit components, such as but not limited to semiconductor switches, buses, and bus bars, connected to form an interconnected network through which current can flow. The form of this network of interconnected circuits is called a circuit topology.

[0010] The concept described herein provides a multiphase power inverter that is advantageously arranged to minimize stray inductance and loop inductance using magnetic field cancellation. This includes using a cancellation field by arranging positive, neutral and negative buses and multiple H-type multilevel power converters in a solid-state integrated circuit using stacked or layered elements. The arrangement of each H-type multilevel power converter using stacked or layered elements enables single-sided or double-sided cooling to reduce thermal impedance. The results of reduced stray inductance can include lower switching losses, less ringing, less electromagnetic interference (EMI), and lower device thermal stress.

[0011] One aspect of the present disclosure may include a multiphase power inverter for an electric powertrain, wherein the multiphase power inverter transforms high voltage DC electric power into multiphase AC power that is delivered to the electric powertrain. The multiphase power inverter includes: a plurality of H-type multilevel power converters arranged between a high voltage DC power source and an electric machine.

[0012] Each of the plurality of H-type multilevel power converters is: a solid-state integrated circuit (IC) having a plurality of semiconductor switches, a positive DC power bus, a negative DC power bus, and a neutral bus, which are arranged in a stacked arrangement or a layered configuration between a first direct bonded copper (DBC) plate and a second DBC plate. The solid state also includes a first AC bus, a second AC bus, a first heat sink, and a second heat sink. The plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus. The plurality of semiconductor switches include a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, and a sixth semiconductor switch.

[0013] The first semiconductor switch is arranged in series with the second semiconductor switch between the positive DC power bus and the negative DC power bus, wherein the first semiconductor switch is connected to the second semiconductor switch at a first node. The third semiconductor switch is arranged in series with the fourth semiconductor switch between the positive bus and the negative bus, wherein the third semiconductor switch is connected to the fourth semiconductor switch at a second node. The fifth semiconductor switch is arranged in series with the sixth semiconductor switch via the neutral bus, wherein the fifth semiconductor switch is connected to the first node and the sixth semiconductor switch is connected to the second node. The first node is connected to the first AC bus, and the second node is connected to the second AC bus.

[0014] The first heat sink is adjacent to the solid-state IC via the first DBC substrate; and the second heat sink is adjacent to the solid-state IC via the second DBC substrate.

[0015] Another aspect of the present disclosure may include: the stacking arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged in parallel with the second layer; and a third layer, consisting of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the second layer is arranged in parallel with the third layer.

[0016] Another aspect of the present disclosure may include: the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

[0017] Another aspect of the present disclosure may include the second AC bus projecting outwardly from a bottom portion of the solid-state IC.

[0018] Another aspect of the present disclosure may include: the stack arrangement has a stack, the stack having: a first layer, consisting of the first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch arranged to be coplanar with each other; and a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0019] Another aspect of the present disclosure may include: the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

[0020] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the second semiconductor switch arranged to be coplanar with the fourth semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; and a third layer, consisting of the first semiconductor switch arranged to be coplanar with the third semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0021] Another aspect of the present disclosure may include: the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

[0022] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; and a third layer, consisting of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0023] Another aspect of the present disclosure may include that the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are all gallium nitride (GaN) devices.

[0024] Another aspect of the present disclosure may include that the fifth semiconductor switch and the sixth semiconductor switch are both insulated gate bipolar transistors (IGBTs).

[0025] Another aspect of the present disclosure may include a method for inductance cancellation in a multi-phase power inverter, comprising: arranging a plurality of semiconductor switches in an H-type multi-level stack; assembling the plurality of semiconductor switches arranged in the H-type multi-level stack into a solid-state integrated circuit (IC) having the following items: a positive DC power bus; a negative DC power bus; and a neutral bus; and interconnecting the plurality of semiconductor switches via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0026] Another aspect of the present disclosure may include a vehicle including an electric propulsion system, wherein the vehicle includes the electric propulsion system, the electric propulsion system comprising: an electric motor configured to provide power to the electric propulsion system; a multi-phase power inverter including a plurality of H-type multi-level power converters arranged between a high voltage direct current (DC) power source and the electric motor, wherein each of the plurality of H-type multi-level power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a neutral bus; and a plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0027] Another aspect of the present disclosure may include an H-type multilevel power converter for a multiphase power inverter for an electric propulsion system, the H-type multilevel power converter comprising: a solid-state integrated circuit (IC) having: a plurality of semiconductor switches arranged in a stacked arrangement; a positive DC power bus; a negative DC power bus; a neutral bus, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch and the second semiconductor switch are arranged in series between the positive DC power bus and the neutral bus. a first semiconductor switch connected to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0028] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; and a third layer, consisting of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0029] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch arranged to be coplanar with each other; and a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0030] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the third semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; and a third layer, consisting of the first semiconductor switch arranged to be coplanar with the third semiconductor switch, wherein the first layer is arranged parallel to the second layer.

[0031] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; and a third layer, consisting of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer.

[0032] Another aspect of the present disclosure may include that the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch each include a gallium nitride (GaN) device.

[0033] Another aspect of the present disclosure may include that the fifth semiconductor switch and the sixth semiconductor switch each include an insulated gate bipolar transistor (IGBT).

[0034] Another aspect of the present disclosure may include a vehicle including an electric propulsion system, the vehicle including: an electric propulsion system installed in the vehicle, the electric propulsion system including: an electric motor configured to provide power to the electric propulsion system; a multiphase power inverter including a plurality of H-type multilevel power converters arranged between a high voltage direct current (DC) power source and the electric motor, wherein each of the plurality of H-type multilevel power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches including: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor a body switch and the second semiconductor switch arranged in series between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected at a second node; a fourth semiconductor switch connected to the third semiconductor switch at the second node, wherein the third semiconductor switch and the fourth semiconductor switch are arranged in series between the positive DC power bus and the negative DC power bus; a fifth semiconductor switch connected at the first node; a sixth semiconductor switch connected at the second node, wherein the fifth semiconductor switch is arranged in series with the sixth semiconductor switch via the neutral bus; and a first AC bus connected to the first node; a second AC bus connected to the second node; a first heat sink adjacent to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0035] Another aspect of the present disclosure may include: the stack arrangement includes a stack having the following items: a first layer, consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer, consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged in parallel with the second layer; and a third layer, consisting of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the second layer is arranged in parallel with the third layer.

[0036] The above features and advantages of the present disclosure and other features and attendant advantages will be apparent from the following detailed description of illustrative examples and modes for implementing the present disclosure when taken in conjunction with the accompanying drawings and the appended claims. In addition, the present disclosure expressly includes combinations and sub-combinations of the elements and features presented above and below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate implementations of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0038] Figure 1 An electric powertrain system according to the present disclosure including a multi-phase power inverter arranged between a high voltage DC power source and an electric machine is schematically illustrated.

[0039] Figure 2 An electric powertrain system including a multi-phase power inverter including a plurality of H-type multi-level power converters arranged between a high voltage DC power source and an electric machine according to the present disclosure is schematically illustrated.

[0040] Figure 3 An H-type multi-level power converter according to one aspect of the present disclosure is schematically illustrated.

[0041] Figure 4 Schematically illustrated is a cross-sectional side view of an H-type multi-level power converter according to one aspect of the present disclosure.

[0042] Figure 5 Schematically illustrated is a cross-sectional side view of an H-type multi-level power converter according to another aspect of the present disclosure.

[0043] Figure 6 An isometric view schematically illustrates an arrangement of elements of an H-type multilevel power converter according to one aspect of the present disclosure.

[0044] Figure 7 Schematically illustrates an isometric view of one arrangement of elements of an H-type multilevel power converter according to another aspect of the present disclosure.

[0045] Figure 8 Schematically illustrates an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the present disclosure.

[0046] Fig. 9 Schematically illustrates an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the present disclosure.

[0047] Fig.10 Schematically illustrates an isometric view of another arrangement of elements of an H-type multilevel power converter according to another aspect of the present disclosure.

[0048] The accompanying drawings are not necessarily drawn to scale and may present somewhat simplified representations of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, locations and shapes. The details adjacent to such features will be determined in part by the specific intended application and use environment. DETAILED DESCRIPTION

[0049] The parts of the disclosed embodiments as described and illustrated herein can be arranged and designed in a variety of different configurations. Therefore, the following detailed description is not intended to limit the scope of the present disclosure as claimed, but merely represents its possible embodiments. In addition, although many specific details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed herein, some embodiments can be practiced without some of these details. In addition, for the purpose of clarity, a certain technical material understood in the relevant art is not described in detail in order to avoid making the present disclosure unnecessarily obscure. In addition, the present disclosure as illustrated and described herein can be practiced in the absence of elements not specifically disclosed herein.

[0050] The present disclosure allows for embodiments that exist in many different forms. Representative examples of the present disclosure are shown in the accompanying drawings and are described in detail herein as non-limiting examples of the disclosed principles. For this reason, elements and limitations described herein but not explicitly set forth in the claims should not be incorporated into the claims individually or collectively, by implication, inference or otherwise.

[0051] For the purposes of this description, unless specifically disclaimed, the use of the singular includes the plural, and vice versa, the terms "and" and "or" shall be both conjunctive and disjunctive, and the words "including," "comprising," "containing," "having," and the like shall mean "including but not limited to." Furthermore, approximate words such as "about," "almost," "substantially," "generally," "approximately," and the like may be used herein in the sense of "at, around, or nearly at," or "within 0-5% of," or "within acceptable manufacturing tolerances," or their logical combinations.

[0052] As used herein, the term "system" refers individually or in combination to mechanical and electrical hardware, software, firmware, electronic control components, processing logic, and / or processor devices, including, but not limited to: application specific integrated circuits (ASICs), electronic circuits, processors (shared, dedicated, or groups) that execute one or more software or firmware programs, (one or more) memory devices that electrically store software or firmware instructions, combinational logic circuits, and / or other components that provide the described functionality.

[0053] As used herein, terms such as "vertical," "horizontal," "left," "right," "upper," "lower," "top," "bottom" and similar expressions are non-limiting terms that merely describe the various elements as illustrated in the various figures and are not intended to limit the scope of the present disclosure.

[0054] As used herein, the term "electrical machine" refers to an electric motor, generator, or motor-generator device including a rotor and a stator that is capable of converting electrical power to mechanical power and / or converting mechanical power to electrical power through electromagnetic efforts.

[0055] Referring to the drawings, wherein like reference numerals designate the same or similar parts throughout the several views, Figure 1 and 2 An electric powertrain 100 is schematically illustrated and consists of a high voltage DC power source 101 , a multi-phase power inverter 104 , a multi-phase rotary electric motor, generator or motor-generator (motor) 10 , and a torque actuator 120 , the operation of which is monitored and controlled by a controller 130 .

[0056] According to one aspect of the present disclosure, the electric powertrain 100 is arranged to generate and transmit torque in the form of one or more drive wheels 120 to actuators 120 to achieve work. A controller 130 executes a control routine 36 to control and manage the operation of the multi-phase power inverter 104 .

[0057] The electric powertrain 100 is disposed on an electrified vehicle schematically illustrated at 20 and is capable of generating traction torque for vehicle propulsion. When disposed on the electrified vehicle 20, the electrified vehicle 20 may include, but is not limited to, a mobile platform in the form of a commercial vehicle, an industrial vehicle, an agricultural vehicle, a passenger vehicle, an aircraft, a watercraft, a train, an all-terrain vehicle, a personal mobility device, a robot, etc., to accomplish the purposes of the present disclosure. Alternatively, the electric powertrain 100 may be an element of a stationary system.

[0058] The controller 130 may be embodied as one or more digital computing devices and may include one or more processors 134 and a memory 132. The control routine 36 may be stored as a set of executable instructions in the memory 132 and executed by one of the processors 134 of the controller 130. The controller 130 communicates with the multi-phase power inverter 104 to control its operation in response to execution of the control routine 36 to operate the electric machine 10.

[0059] The term "controller" and related terms (such as microcontroller, control module, module, control, control unit, processor and similar terms) refer to one or various combinations of application specific integrated circuit(s) (ASICs), field programmable gate arrays (FPGAs), electronic circuit(s), central processing unit(s) (e.g., microprocessor(s)), and associated memory components(s) (read-only, programmable read-only, random access, hard drive, etc.) in the form of transient and / or non-transient memory components and storage devices. Non-transient memory components can store machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuit(s), input / output circuit(s) and devices, signal conditioning and buffering circuits, and other components accessible by one or more processors to provide the described functionality. Input / output circuit(s) and devices include analog / digital inverters and related devices that monitor inputs from sensors, where such inputs are monitored at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms and similar terms mean controller executable instruction sets including calibration and lookup tables.

[0060] The electric machine 10 includes a cylindrical rotor assembly arranged on a rotor shaft and disposed within an annular stator, wherein the rotor assembly is coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10 (e.g., end caps, shafting bearings, electrical connections, etc.) are included but not shown. The electrical windings of the stator are arranged with a certain number of electrical phases and a certain number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can be between 3 and 6, and the number of layers of conductors can be between 4 and 12.

[0061] The multi-phase power inverter 104 includes: a plurality of semiconductor switches (refer to Figure 2 The multiphase power inverter 104 is arranged and controllable to transform DC electric power into AC electric power and transform AC electric power into DC electric power using a pulse width modulation signal 108 or another control technique. The multiphase power inverter 104 is arranged and controllable to transform DC electric power emitted from the high voltage DC power source 101 into AC electric power to actuate the motor 10 via electromagnetic effort. The motor 10 can be controlled to rotate and generate mechanical torque transmitted to the actuator 120 via the rotatable member 12 and the gear train 114 when operating in the torque generation mode. The motor 10 can be controlled to generate AC electric power from the mechanical torque emitted at the actuator 120 via electromagnetic effort, and when operating in the electric power generation mode, the AC electric power is transformed by the multiphase power inverter 104 into DC electric power for storage in the high voltage DC power source 101.

[0062] According to one aspect of the present disclosure, the actuator 120 includes wheels that transmit torque to the ground surface as part of a traction propulsion system to achieve forward motion. The high voltage DC power source 101 may be in the form of a rechargeable electrochemical battery device, a fuel cell, a supercapacitor, and / or another electrical energy storage / generation technology.

[0063] The high voltage DC power source 101 may be a rechargeable electrochemical battery device, a fuel cell, a supercapacitor, and / or another electrical energy storage / generation technology. The high voltage DC power source 101 is connected to a multi-phase power inverter 104 via a high voltage DC bus having a positive link 102 and a negative link 103, and the multi-phase power inverter 104 is connected to the motor 10 via a plurality of first AC buses 121 and a second AC bus 122 to deliver a pulse width modulated signal 108.

[0064] As reference Figure 2 As shown, the multiphase power inverter 104 of the electric powertrain 100 is composed of a plurality of H-type multilevel power converters 150 arranged between the high voltage DC power source 101 and the motor 10, wherein a single DC link capacitor 105 is between the high voltage DC power source 101 of the electric powertrain 100 and the multiphase power inverter 104. As shown and in one non-limiting aspect of the present disclosure, the multiphase power inverter 104 of the electric powertrain 100 is composed of three H-type multilevel power converters 150.

[0065] Reference now Figure 3 , the topology of each of the H-type multilevel power converters 150 is arranged as a multilevel inverter (MLI).

[0066] According to one aspect of the present disclosure and as described herein, each of the H-type multilevel power converters 150 employs a no-neutral-point (NPL) MLI topology. Topology refers to the physical arrangement of constituent elements, including network busbar interconnects, dielectrics, semiconductor switches, and other elements.

[0067] Each of the H-type multilevel power converters 150 is arranged as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or layered arrangement. In one aspect of the present disclosure and as shown, the plurality of semiconductor switches include a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, and a sixth semiconductor switch S6 156.

[0068] According to one aspect of the present disclosure, at least some of the semiconductor switches are field effect transistors (FETs). According to another aspect of the present disclosure, the FETs are gallium nitride (GaN) transistors. According to another aspect of the present disclosure, at least some of the semiconductor switches are insulated gate bipolar transistors (IGBTs).

[0069] Other components of the H-type multilevel power converter 150 include a positive DC power bus 110, a neutral bus 111, a negative DC power bus, a first AC bus 121, and a second AC bus 122. A first semiconductor switch S1 151 and a second semiconductor switch S2 152 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112, wherein the first semiconductor switch S1 151 is connected to the second semiconductor switch S2 at a first node 161. A fifth semiconductor switch S5 155 is also connected to the first node 161. The first node 161 is connected to the first AC bus 121 to transfer power to the motor 10 (refer to FIG. 1 ). Figure 2 shown).

[0070] The third semiconductor switch S3 153 and the fourth semiconductor switch S4 154 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112, wherein the third semiconductor switch S3 153 is connected to the fourth semiconductor switch S4 154 at a second node 162. The sixth semiconductor switch 156 is also connected to the second node 162. The second node 162 is connected to the second AC bus 122 to transfer power to the motor 10 (refer to Figure 2 The fifth semiconductor switch S5 155 is arranged in series with the sixth semiconductor switch S6 156 via the neutral bus 111 between the first node 161 and the second node 162 .

[0071] A positive DC power bus 110 , a neutral power bus 111 , and a negative DC power bus 112 are schematically illustrated.

[0072] By configuring the topology within each of the H-type multilevel converters 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111 , mutual inductance cancellation minimizes parasitic inductance by coupling positive mutual inductance and negative mutual inductance for commutation loop current within each of the H-type multilevel converters 150 .

[0073] According to one aspect of the present disclosure, as illustrated at (I), the buses are configured from top 33 to bottom 34 such that positive DC power bus 110 is parallel to neutral bus 111 , which is then parallel to negative DC power bus 112 .

[0074] According to another aspect of the present disclosure, as illustrated at (II), the buses are configured from top 33 to bottom 34 such that positive DC power bus 110 is parallel to negative DC power bus 112 , which is then parallel to neutral bus 111 .

[0075] According to another aspect of the present disclosure, as illustrated at (III), the buses are configured from top 33 to bottom 34 such that neutral bus 111 is parallel to positive DC power bus 110 , which is then parallel to negative DC power bus 112 .

[0076] According to another aspect of the present disclosure, as illustrated at (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112 , while both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111 .

[0077] Although several topologies are discussed above, they are merely exemplary and non-limiting aspects of the present disclosure. Accordingly, it should be appreciated that within each of the H-type multilevel converters 150, mutual inductance cancellation minimizes parasitic inductance by coupling positive mutual inductance and negative mutual inductance for commutation loop currents within each of the H-type multilevel converters 150 (i.e., by configuring the topology of the H-type multilevel inverter 150 so that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111).

[0078] Reference now Figure 4 According to one aspect of the present disclosure, an H-type multilevel power converter 150 is illustrated, and the H-type multilevel power converter 150 includes a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a positive DC power bus 110, a negative DC power bus 112, a neutral bus 111, a first AC bus 121, a second AC bus 122, a first direct bonded copper (DBC) plate 143, a second DBC plate 144, a third DBC plate 145, a plurality of conductive spacers 146, a first heat sink 141, and a second heat sink 142.

[0079] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, the fourth semiconductor switch S4 154, the fifth semiconductor switch S5 155, and the sixth semiconductor switch S6 156 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 135, a second (middle) layer 136, and a third (upper) layer 137. The first layer 135 includes coplanar second semiconductor switches S2 152 and fourth semiconductor switches S4 154. The second layer 136 includes coplanar fifth semiconductor switches S5 155 and sixth semiconductor switches S6 156. The third layer 137 includes coplanar first semiconductor switches S1 151 and third semiconductor switches S3 153.

[0080] The fully stacked arrangement includes, in ascending order from bottom 134 to top 133: a first heat sink 141; a first DBC plate 143; a negative DC power bus 112; a first layer 135, including a second semiconductor switch S2 152 and a fourth semiconductor switch S4 154; a neutral bus 111; a second layer 136, including a fifth semiconductor switch S5 155 and a sixth semiconductor switch S6 156, a second AC bus 122, a first AC bus 121, a second DBC plate 144 and various conductive spacers 146; a third layer 137, including a first semiconductor switch S1 151, a third semiconductor switch S3 153 and a positive DC power bus 110; a third DBC plate 145; and a second heat sink 142.

[0081] The first semiconductor switch S1 151, the second semiconductor switch S2 152, and the fifth semiconductor switch S5 155 are coupled at a first node 161 connected to the second AC bus 122. The third semiconductor switch S3 153, the fourth semiconductor switch S4 154, and the sixth semiconductor switch S6 156 are coupled at a second node 162 connected to the first AC bus 121. The first heat sink 141 is adjacent via the first DBC plate 143, and the second heat sink is adjacent via the third DBC plate 145.

[0082] Reference now Figure 5According to another aspect of the present disclosure, an H-type multilevel power converter 250 is illustrated, and the H-type multilevel power converter 250 includes a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256, a positive DC power bus 210, a negative DC power bus 212, a neutral bus 211, a first AC bus 221, a second AC bus 222, a first direct bonded copper (DBC) plate 243, a second DBC plate 244, a plurality of conductive spacers 246, a first heat sink 241, and a second heat sink 242.

[0083] The first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, the fourth semiconductor switch S4 254, the fifth semiconductor switch S5 255, and the sixth semiconductor switch S6 256 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 235, a second (middle) layer 236, and a third (upper) layer 237. The first layer 235 includes a coplanar second semiconductor switch S2 252, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256, and a fourth semiconductor switch S4 254. The second semiconductor switch S2 252 and the fourth semiconductor switch S4 254 are arranged on the negative DC power bus 212, which is arranged on the first DBC board 243. The fifth semiconductor switch S5 255 and the sixth semiconductor switch S6 256 are arranged on the neutral bus 211, which is arranged on the first DBC board 243. The second layer 236 includes the second AC bus 222 and the first AC bus 221 and various conductive spacers 246. The third layer 237 includes the first semiconductor switch S1 251 and the third semiconductor switch S3 253 that are coplanar and arranged on the positive DC power bus 210.

[0084] The fully stacked arrangement includes, in ascending order from bottom 234 to top 233: a first heat sink 241; a first DBC board 243; a negative DC power bus 212 and a neutral bus 211; a first layer 235, including a second semiconductor switch S2 252, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256 and a fourth semiconductor switch S4 254; a second layer 236, including a second AC bus 222, a first AC bus 221 and various conductive spacers 246; a third layer 237, including a first semiconductor switch S1 251 and a third semiconductor switch S3 253; a positive DC power bus 210; a second DBC board 244; and a second heat sink 242.

[0085] The first semiconductor switch S1 251, the second semiconductor switch S2 252, and the fifth semiconductor switch S5 255 are coupled at a first node 261 connected to the first AC bus 221. The third semiconductor switch S3 253, the fourth semiconductor switch S4 254, and the sixth semiconductor switch S6 256 are coupled at a second node 262 connected to the second AC bus 222. The first heat sink 241 is adjacent via the first DBC plate 243, and the second heat sink is adjacent via the second DBC plate 244.

[0086] Reference now Figure 6 According to another aspect of the present disclosure, an H-type multilevel converter 350 is illustrated, and the H-type multilevel converter 350 includes a first semiconductor switch S1 351, a second semiconductor switch S2 352, a third semiconductor switch S3 353, a fourth semiconductor switch S4 354, a fifth semiconductor switch S5 355, a sixth semiconductor switch S6 356, a positive DC power bus 310, a negative DC power bus 312, a neutral bus 311, a first AC bus 321, and a second AC bus 322. It should be understood that other elements that have been previously described have been omitted, but are included in aspects of the H-type multilevel power converter 350 when simplified to practice.

[0087] The first semiconductor switch S1 351, the second semiconductor switch S2 352, the third semiconductor switch S3 353, the fourth semiconductor switch S4 354, the fifth semiconductor switch S5 355, and the sixth semiconductor switch S6 356 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 335, a second (middle) layer 336, and a third (upper) layer 337. The first layer 335 includes a coplanar first semiconductor switch S1 251 and a fifth semiconductor switch S2 352. The second layer 336 includes a coplanar fifth semiconductor switch S5 355 and a sixth semiconductor switch S6 356. The third layer 337 includes a coplanar fourth semiconductor switch S4 354 and a third semiconductor switch S3 353.

[0088] The positive DC power bus 310 and the negative DC power bus 312 are located at the first end 358 of the H-type multilevel converter 350, and the first AC bus 321 and the second AC bus 322 are located at the second end 360 of the H-type multilevel converter. The first AC bus 321, the second AC bus 322, the positive DC power bus 310, the negative DC power bus 312 and the neutral bus 311 are connected as shown, which is consistent with the reference Figure 3 The circuit is the same as shown in the figure.

[0089] According to this aspect of the disclosure, both the first AC bus 321 and the second AC bus 322 are on the same end (ie, the second end 360) of the H-type multilevel converter 350. This configuration promotes improved electromagnetic coupling, thereby reducing parasitic inductance.

[0090] Reference now Figure 7 According to another aspect of the present disclosure, an H-type multilevel converter 450 is illustrated, and includes a first semiconductor switch S1 451, a second semiconductor switch S2 452, a third semiconductor switch S3 453, a fourth semiconductor switch S4 454, a fifth semiconductor switch S5 455, a sixth semiconductor switch S6 456, a positive DC power bus 410, a negative DC power bus 412, a neutral bus 411, a first AC bus 421, and a second AC bus 422. It should be understood that other elements that have been previously described have been omitted, but are included in aspects of the H-type multilevel power converter 450 when simplified to practice.

[0091] The first semiconductor switch S1 451, the second semiconductor switch S2 452, the third semiconductor switch S3 453, the fourth semiconductor switch S4 454, the fifth semiconductor switch S5 455, and the sixth semiconductor switch S6 456 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 435, a second (middle) layer 436, and a third (upper) layer 437. The first layer 435 includes the coplanar sixth semiconductor switch S6 456 and the fifth semiconductor switch S5 455. The second layer 436 includes the first AC bus 421 and the second AC bus 422. The third layer 437 includes the coplanar fourth semiconductor switch S4 454, the third semiconductor switch S3 453, the second semiconductor switch S2 452, and the first semiconductor switch S1 451.

[0092] The positive DC power bus 410 and the negative DC power bus 412 are located at the first end 458 of the H-type multilevel converter 350, and the first AC bus 421 and the second AC bus 422 are located at the second end 460 of the H-type multilevel converter. The first AC bus 421, the second AC bus 422, the positive DC power bus 410, the negative DC power bus 412, and the neutral bus 411 are connected as shown, which is consistent with the reference Figure 3 The circuit is the same as shown in the figure.

[0093] Reference now Figure 8According to another aspect of the present disclosure, an H-type multilevel power converter 550 is illustrated, and the H-type multilevel power converter 550 includes a first semiconductor switch S1 551, a second semiconductor switch S2 552, a third semiconductor switch S3 553, a fourth semiconductor switch S4 554, a fifth semiconductor switch S5 555, a sixth semiconductor switch S6 556, a positive DC power bus 510, a negative DC power bus 512, a first AC bus 521, and a second AC bus 522. It should be understood that other elements that have been previously described have been omitted, but are included in aspects of the disclosure of the H-type multilevel power converter 550 when simplified to practice.

[0094] The first semiconductor switch S1 551, the second semiconductor switch S2 552, the third semiconductor switch S3 553, the fourth semiconductor switch S4 554, the fifth semiconductor switch S5 555, and the sixth semiconductor switch S6 556 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 535, a second (middle) layer 536, and a third (upper) layer 537. The first layer 535 includes the second semiconductor switch S2 552 and the fourth semiconductor switch S4 554 that are coplanar. The second layer 536 includes the fifth semiconductor switch S5 555 and the sixth semiconductor switch S6 556. The third layer 537 includes the first semiconductor switch S1 551 and the third semiconductor switch S3 553 that are coplanar. The first AC bus 521, the second AC bus 522, the positive DC power bus 510, and the negative DC power bus 512 are connected as shown, which is consistent with the reference Figure 3 The layout of the circuit shown in the figure is consistent.

[0095] According to this aspect of the disclosure, the first AC bus 521 is located on the first end 558 of the H-type multilevel converter 550, while the second AC bus 522 is located on the second end 560 of the H-type multilevel converter 550. Each of the first AC bus 520 and the second AC bus 522 extends the width W of two semiconductor switches S2 552, S4 554 and S1 551, S3 553, respectively, of the H-type multilevel converter 550. This configuration provides a wider parallelization of the first AC bus 521 and the second AC bus 522, facilitating current flow, thereby reducing both resistance and parasitic inductance.

[0096] Reference now Fig. 9According to another aspect of the present disclosure, an H-type multilevel power converter 650 is illustrated, and the H-type multilevel power converter 650 includes a first semiconductor switch S1 651, a second semiconductor switch S2 652, a third semiconductor switch S3 653, a fourth semiconductor switch S4 654, a fifth semiconductor switch S5 655, a sixth semiconductor switch S6 656, a positive DC power bus 610, a negative DC power bus 612, a first AC bus 621, and a second AC bus 622. It should be understood that other elements that have been previously described have been omitted, but are included in the embodiment of the H-type multilevel power converter 650 when simplified to practice.

[0097] The first semiconductor switch S1 651, the second semiconductor switch S2 652, the third semiconductor switch S3 653, the fourth semiconductor switch S4 654, the fifth semiconductor switch S5 655, and the sixth semiconductor switch S6 656 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 635, a second (middle) layer 636, and a third (upper) layer 637. The first layer 635 includes a coplanar first semiconductor switch S1 651 and a second semiconductor switch S2 652. The second layer 636 includes a fifth semiconductor switch S5 655 and a sixth semiconductor switch S6 656. The third layer 637 includes a coplanar third semiconductor switch S3 653 and a fourth semiconductor switch S4 654. The first AC bus 621, the second AC bus 622, the positive DC power bus 610, and the negative DC power bus 612 are connected as shown, which is consistent with the reference Figure 3 The layout of the circuit shown in the figure is consistent.

[0098] According to this aspect of the disclosure, both the first AC bus 621 and the second AC bus 622 extend vertically downward from the H-type multilevel converter 650. This configuration allows for direct mounting of the H-type multilevel converter to the motor 10, thereby reducing the length of the AC buses 621, 622 between the H-type multilevel converter 650 and the motor 10, reducing voltage overshoot.

[0099] Reference now Fig.10 According to another aspect of the present disclosure, an H-type multilevel power converter 750 is illustrated, and the H-type multilevel power converter 750 includes a first semiconductor switch S1 751, a second semiconductor switch S2 752, a third semiconductor switch S3 753, a fourth semiconductor switch S4 754, a fifth semiconductor switch S5 755, a sixth semiconductor switch S6 756, a positive DC power bus 710, a negative DC power bus 712, a first AC bus 721, and a second AC bus 722. It should be understood that other elements that have been previously described have been omitted, but are included in aspects of the disclosure of the H-type multilevel power converter 750 when simplified to practice.

[0100] The first semiconductor switch S1 751, the second semiconductor switch S2 752, the third semiconductor switch S3 753, the fourth semiconductor switch S4 754, the fifth semiconductor switch S5 755, and the sixth semiconductor switch S6 756 are arranged in a stacked or multi-layer configuration, which includes a first (lower) layer 735, a second (middle) layer 736, and a third (upper) layer 737. The first layer 735 includes the first semiconductor switch S1 751 and the second semiconductor switch S2 752 that are coplanar. The second layer 736 includes the fifth semiconductor switch S5 755 and the sixth semiconductor switch S6 756. The third layer 737 includes the third semiconductor switch S3 753 and the fourth semiconductor switch S4 754 that are coplanar. The first AC bus 721, the second AC bus 722, the positive DC power bus 710, the negative DC power bus 712, and the neutral bus 711 are connected as shown, which is consistent with the reference Figure 3 The layout of the circuit shown in the figure is consistent.

[0101] According to this aspect of the disclosure, both the negative DC power bus 712 and the positive DC power bus 710 are located on the first end 758 of the H-type multilevel converter 750, while the first AC bus 721 and the second AC bus 722 are located on the second end 760 of the H-type multilevel converter 750. Each of the first AC bus 720 and the second AC bus 722 extends the width W of two semiconductor switches S1 751, S2 752 and S3 753, S4 754, respectively, of the H-type multilevel converter 750. This configuration facilitates current flow, thereby reducing both resistance and parasitic inductance.

[0102] The illustrated aspects of the disclosure of an H-type multi-level power converter provide an overlap of a positive DC power bus, a neutral bus, and a negative DC power bus to reduce mutual inductance. The arrangement includes: overlaying a first AC bus on a second AC bus to cancel dV / dt and reduce or eliminate electromagnetic interference and achieve field cancellation via P, 0, and N currents to minimize parasitic loops and stray inductance.

[0103] This arrangement facilitates optimal design of the positive DC power bus, the negative DC power bus, the neutral bus, and the DC link capacitors to achieve mutual inductance cancellation.

[0104] This arrangement facilitates a variety of heat transfer and cooling systems including direct cooling, indirect cooling, immersion cooling, single-sided or double-sided cooling.

[0105] This arrangement facilitates reduction in voltage / current overshoots for equipment stress, including die / power modules, bus bars, DC link capacitors.

[0106] This arrangement facilitates size reduction and increased power density compared to current systems.

[0107] This arrangement facilitates the use of lower voltage rated semiconductor switch dies for lower conduction losses and increased EV range compared to current systems.

[0108] This arrangement promotes reduced ringing and radiated / conducted electromagnetic interference to other subsystems and enables higher switching speeds, which reduces losses and thus increases vehicle range and improves current capability.

[0109] These and other attendant advantages of the present disclosure will be appreciated by those skilled in the art upon consideration of the above disclosure.

[0110] The detailed description and the accompanying drawings or figures support and describe the present teaching, but the scope of the present teaching is limited only by the claims. Although some of the best modes and other examples for implementing the present teaching have been described in detail, various alternative designs and aspects of the present disclosure exist for practicing the present teaching defined in the appended claims.

Claims

1. A multiphase power inverter for an electric propulsion system, the multiphase power inverter comprising: a plurality of H-type multilevel power converters disposed between the electric machine and the high voltage DC power source of the electric propulsion system, wherein each of the plurality of H-type multilevel power converters is a solid-state integrated circuit (IC) comprising: Positive DC power bus; Negative DC power bus; Neutral bus; a plurality of semiconductor switches arranged in a stacked arrangement, wherein the plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at the first node, wherein the first semiconductor switch and the second semiconductor switch are arranged in series between the positive DC power bus and the negative DC power bus; a third semiconductor switch connected at the second node; a fourth semiconductor switch connected to the third semiconductor switch at the second node, wherein the third semiconductor switch is arranged in series with the fourth semiconductor switch between the positive DC power bus and the negative DC power bus; a fifth semiconductor switch connected at the first node; and a sixth semiconductor switch connected at the second node, wherein the fifth semiconductor switch is arranged in series with the sixth semiconductor switch via the neutral bus; and a first AC bus connected to the first node; a second AC bus connected to the second node; a first heat sink adjacent to a positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and A second heat sink is adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

2. The multiphase power inverter of claim 1, wherein the stack arrangement comprises a stack having: a first layer consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged in parallel with the second layer; as well as A third layer is composed of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the second layer is arranged in parallel with the third layer.

3. The multiphase power inverter of claim 2, wherein the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

4. The multiphase power inverter of claim 3, wherein the second AC bus projects outwardly from a bottom portion of the solid-state IC.

5. The multiphase power inverter of claim 1 , wherein the stack arrangement comprises a stack having: a first layer consisting of the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch arranged to be coplanar with each other; and A second layer is composed of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch, wherein the first layer is arranged in parallel with the second layer.

6. The multiphase power inverter of claim 5, wherein the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

7. The multiphase power inverter of claim 1, wherein the stack arrangement comprises a stack having: a first layer consisting of the second semiconductor switch arranged to be coplanar with the fourth semiconductor switch; a second layer consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; as well as A third layer is composed of the first semiconductor switch arranged to be coplanar with the third semiconductor switch, wherein the first layer is arranged in parallel with the second layer.

8. The multiphase power inverter of claim 7, wherein the positive DC power bus and the negative DC power bus are arranged on a first end of the H-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged on a second end of the H-type multilevel power converter.

9. The multiphase power inverter of claim 1, wherein the stack arrangement comprises a stack having: a first layer consisting of the first semiconductor switch arranged to be coplanar with the second semiconductor switch; a second layer consisting of the fifth semiconductor switch arranged to be coplanar with the sixth semiconductor switch; as well as A third layer is composed of the third semiconductor switch arranged to be coplanar with the fourth semiconductor switch, wherein the first layer is arranged in parallel with the second layer.

10. The multiphase power inverter of claim 1, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch each comprise a gallium nitride (GaN) device.

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