Broadband reconfigurable low-noise amplifier

Abstract

The broadband reconfigurable low noise amplifier sequentially comprises an input matching network, a first transistor, an inter-stage matching network, a second transistor and an output matching network in the direction from input to output, and in addition, the first transistor is further connected with a negative feedback network. The interstage network comprises a first inductor, a first capacitor, a second capacitor and a third capacitor, wherein the first capacitor and the third capacitor are switch frequency-selecting capacitors. The negative feedback network is composed of a feedback resistor and a feedback capacitor. According to the reconfigurable low-noise amplifier, the dual-band signal can be amplified under the condition that noise is not excessively deteriorated, and then the reconfigurable low-noise amplifier is achieved. The invention can be widely applied to the field of radio frequency integrated circuits.

Description

Technical Field

[0001] The invention relates to the field of radio frequency integrated circuits, and in particular to a broadband reconfigurable low noise amplifier. Background Art

[0002] With the development and evolution of mobile communications, 5G has begun to be deployed for commercial use, and at the same time, it has also posed new challenges to the RF front-end circuit. On the one hand, the number of RF channels integrated in 5G communication equipment has increased significantly. For example, in the application of communication base stations, 4G base stations use a system solution that integrates 8 RF channels, while 5G base stations use massive multiple-input multiple-output (MassiveMIMO) technology, and the number of integrated RF channels can reach 64 or even more; in the application of smartphones in mobile terminals, 4G mobile phones use a 1-transmit 2-receive architecture, while 5G independent networking mobile phones use a 2-transmit 4-receive circuit architecture. On the other hand, while 5G is compatible with 4G / 3G / 2G communication standards, the number of signal frequency bands supported has also increased. For example, 5G has added n77 (3.3-4.2GHz) and n79 (4.4-5.0GHz) in Sub 6GHz applications, and n257 (26.5-29.5GHz) and n258 (24.25-27.5GHz) in millimeter wave applications. Therefore, with the increase in the number of 5G RF channels and supported signal frequency bands, the number of RF components required in the communication system has increased significantly, and the circuit complexity has increased accordingly. In order to integrate a large number of circuits in a limited space, RF front-end circuits with high integration and miniaturization have become a design requirement.

[0003] As a key component of the RF front-end circuit, the low-noise amplifier is mainly used to amplify the weak signal received by the antenna from the air to achieve signal transmission at the receiving front end. Designing a broadband multi-band low-noise amplifier is the key to achieving high signal sensitivity, high dynamic range and high reliability in 5G communications. Existing solutions cannot amplify dual-band signals without excessively deteriorating noise. Summary of the invention

[0004] In view of this, in order to solve the technical problem that the existing integrated antenna cannot simultaneously meet the requirements of low noise and high gain required by the scene, the present invention proposes a broadband reconfigurable low noise amplifier, which includes an input matching network, a first transistor, an inter-stage matching network, a second transistor and an output matching network in sequence from input to output. In addition, the first transistor is also connected to a negative feedback network, wherein:

[0005] The inter-stage network includes a first inductor, a first capacitor, a second capacitor and a third capacitor, wherein the first capacitor and the third capacitor are both switch frequency selection capacitors.

[0006] The negative feedback network consists of a feedback resistor and a feedback capacitor.

[0007] The switch frequency selection capacitor is realized by switch logic, reverse logic and MOS tube, and the capacitance of the first capacitor and the third capacitor is adjusted by the switch to realize the selection of the frequency band.

[0008] An inductor that only introduces broadband is used as the input matching network to reduce parasitic resistance and achieve a low noise figure.

[0009] Based on the above scheme, the present invention provides a broadband reconfigurable low-noise amplifier, which directly integrates the switch frequency selection circuit into the inter-stage matching module, and can amplify the dual-band signal without excessively deteriorating the noise, thereby realizing a reconfigurable low-noise amplifier. In addition, the inter-stage matching circuit also plays a role in current reuse, minimizing the chip area, and can effectively reduce costs; further, the proposed new structure abandons the LC resonance to form the input matching network, and only selects a broadband inductor as the input matching network. By utilizing the parasitic capacitance of the transistor itself and the influence of the inter-stage matching network on the input impedance and the effect of the feedback network on the optimal noise impedance, this structure meets the requirements of low noise and high gain of the low-noise amplifier circuit under broadband. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural schematic diagram of a broadband reconfigurable low noise amplifier provided by the present invention;

[0011] Figure 2 It is a circuit schematic diagram of a broadband reconfigurable low noise amplifier provided by the present invention;

[0012] Figure 3 It is a schematic diagram of the inter-stage switch frequency selection capacitor provided by the present invention;

[0013] Figure 4 It is a small signal and noise model diagram of the input stage of the broadband low noise amplifier provided by the present invention;

[0014] Figure 5 is a schematic diagram of a small signal model of a first transistor provided by the present invention;

[0015] Figure 6 This is a diagram showing the effect of implementing the broadband reconfigurable low noise amplifier provided by the present invention;

[0016] Figure 7 This is a simulation result diagram of "S parameters" of the broadband reconfigurable low noise amplifier provided by the present invention;

[0017] Figure 8 It is a diagram of the simulation results of the “noise coefficient” of the broadband reconfigurable inter-stage circuit according to a specific embodiment of the present invention.

[0018] Reference numerals: C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; L1, first inductor; L2, second inductor; L3, third inductor; L4, fourth inductor; L5, fifth inductor; L out , output inductor; R f , feedback resistance; C f , feedback capacitor; M1, first transistor; M2, second transistor; C block1 , the first isolation capacitor; C block2 , second isolation capacitor; S0, first switch logic; S1, second switch logic; First reverse logic; Second reverse logic; SW n1 , the first MOS tube; SW n2 , the second MOS tube; C n1 , a first preset capacitor; C n2 , the second preset capacitor; C n3 , the third preset capacitor; C n4 , a fourth preset capacitor. DETAILED DESCRIPTION

[0019] The existing solution is to apply a switch frequency selection circuit to the input matching circuit, but this will introduce a switch device with resistance noise at the input end, thereby deteriorating the noise of the circuit.

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] It should be noted that, for the convenience of description, only the parts related to the relevant invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0022] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. The elements defined by the sentence "includes a..." do not exclude the existence of other identical elements in the process, method, commodity or device that includes the elements.

[0023] In the description of the embodiments of the present application, "plurality" means two or more than two. The following terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0024] In addition, flow charts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, the various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes, or a certain step or several steps of operations may be removed from these processes.

[0025] Reference Figure 1 , is a schematic diagram of an optional example of a broadband reconfigurable low-noise amplifier proposed by the present invention, comprising an input matching network, a first transistor, a negative feedback network, an inter-stage matching network, a second transistor and an output matching network, wherein the input matching network, the first transistor, the inter-stage matching network, the second transistor and the output matching network are connected in sequence based on the current direction, and the first transistor is also connected to a negative feedback network, wherein:

[0026] The overall circuit structure principle of the broadband reconfigurable low noise amplifier is referenced Figure 2 .

[0027] The low noise amplifier (LNA) consists of two common source amplifiers (first transistor M1, second transistor M2). VG1 is powered by the gate terminal of the first transistor M1 through voltage division, and VG2 is powered by the gate terminal of the first transistor M2. The first front end uses a large capacitor first isolation capacitor C block Isolate RF signals and do not participate in circuit matching. Only broadband inductors are introduced as input matching networks to reduce parasitic resistance and achieve low noise figures. In order to achieve a good balance between input return loss and noise figure, this circuit introduces a key inter-stage matching circuit (composed of the third capacitor C3, the first inductor L1, the first capacitor C1, and the second capacitor C2) and a negative feedback network (composed of the feedback resistor R f , feedback capacitor C f By selecting appropriate values ​​of the interstage matching network and the negative feedback network, the LNA can achieve both low noise figure and high input return loss. In order to reduce power consumption, the interstage matching circuit adopts a current multiplexing structure. The first inductor L1 isolates the AC signal and conducts the DC signal. The third capacitor C3 isolates the DC signal and conducts the AC signal. The second capacitor C2 acts as an RF ground to isolate the DC signal, which is crucial in the current multiplexing structure. The interstage switch frequency selection circuit uses the first switch logic S0, the second switch logic S1 and the first reverse logic Second reverse logic and the first MOS tube SW n1 And the second MOS tube SW n2 Implementation, such as Figure 3 As shown. Where n represents two logic paths, n is 0 or 1, x represents two capacitors in the inter-stage matching network, x is 1 or 3. The first capacitor C1 and the third capacitor C3 are adjusted by switches to select the frequency band. The first inductor L1, the output inductor L out The fourth capacitor C4 forms a T-type matching network to expand the bandwidth. By changing the value of the choke inductor (the third inductor L1), a good output matching can be achieved, and the gain of the circuit can be adjusted to achieve better gain flatness.

[0028] From the circuit schematic diagram, it can be seen that the DC current passes through the inductor (the third inductor L3, the output inductor L out , the second inductor L2, the first inductor L1) flows from the drain of the second stage to the source of the first stage, because the source capacitor (the second capacitor C2) isolates the DC. For low-frequency signals, the circuit is equivalent to a common source and common gate structure; for high-frequency signals, the circuit is equivalent to a two-stage common source structure. Compared with the common source and common gate circuit, the inter-stage current reuse structure can provide a high-frequency pole together with the second stage to improve the gain in the high-frequency region; compared with the cascaded common source circuit, the current reuse structure can significantly save current and effectively reduce the power consumption of the amplifier.

[0029] In order to further explain the effect of the inter-stage current multiplexing structure and negative feedback structure on the simultaneous matching of input impedance and noise impedance under broadband, the circuit is analyzed for small signals and noise. It can be obtained that its input impedance Z in , noise impedance Z opt It can be expressed as:

[0030]

[0031] Among them, Z L is the first stage equivalent output load, C gd1 ,C gs1 ,R ds1 are the parasitic capacitance and parasitic resistance of the transistor, respectively, m1 is the transconductance of the transistor, s represents the complex frequency variable, used for Laplace transform or s-domain analysis, s = jω, where j is the imaginary unit and ω is the angular frequency; γ is related to the transistor characteristics, for long channel MOS tubes, γ = 2 / 3;. According to qualitative analysis, Z L is pure reactance, is input impedance Z in Provides the imaginary part. By adjusting Z L , that is, the inter-stage matching circuit part in the total circuit, can make the inter-stage matching circuit, the gate-drain parasitic capacitance C of the first transistor M1gd1 It forms a resonant network with the source degeneration inductor (fifth inductor L5), making the imaginary part of the input impedance zero (Im(Z in )=0). In order to meet the input impedance matching, it is also necessary to select a reasonable bias and transistor size to ensure that the real part of the input impedance at frequency f1 is equal to the characteristic impedance (assuming it is 50Ω, that is, Re(Z in )=50). In addition, the gate-source parasitic capacitance C of the first transistor M1 is gs1 It can achieve impedance matching with the fifth inductor L5 at another frequency f2, thereby achieving high input return loss at two different frequency points. Similarly, the optimal noise impedance can also achieve noise impedance matching at two different frequency points f3 and f4 (i.e., Im(Z opt )=0,Re(Z opt )=50), so that the output noise is as close to the lowest noise as possible. L and R f , so that the resonant frequency satisfies f1=f3,f2=f4 (i.e. Im(Z in )=Im(Z opt )=0,Re(Z in )=Re(Z opt )=50), thus achieving dual frequency points to meet the optimal return loss and low noise. It is worth noting that since the impedance changes continuously, a point y can always be found near the resonant frequency so that f 1y =f 3y ,f 2y =f 4y (At this time Im(Z iny )≈Im(Z opty )≈0,Re(Z iny )≈Re(Z opty )≈50)), so that the impedance point is around the characteristic impedance, such as Figure 4 As shown. Figure 4 As can be seen in the figure, compared with the traditional circuit, the circuit with feedback network and inter-stage matching network solves the problem that input impedance and optimal noise impedance are difficult to match at the same time. The input impedance and noise impedance curves can be around the characteristic impedance, which improves the overall noise and gain level of the circuit. Figure 5 Schematic diagram of a small signal model of the first transistor.

[0032] The reconfigurable function of LNA is realized by switching SW Cn1 , SW Cn2 The state switching of the first switch S0 and the second switch S1 changes the capacitance of the inter-stage capacitor (the third capacitor C3 and the first capacitor C1), so that the resonant frequency of the LNA inter-stage matching network changes, thereby changing the input impedance (Zin ) to achieve the switching of the working frequency band. Figure 6 The broadband reconfigurable LNA implementation effect shown in the figure, when S0 and S1 are both in the high level state, C3, C1, R f and L3 reach their maximum values, the resonance point of the inter-stage matching circuit moves to low frequency, the feedback effect is weakened, the leakage of the output matching inductor is weakened, the bandwidth of the LNA is narrow, and the gain is high; when S0 is at a high level and S1 is at a low level, C3, C1, R f The value of L3 decreases, the resonance point of the inter-stage matching circuit moves to high frequency, the feedback effect increases, the leakage of the output matching inductor increases, the bandwidth of the LNA becomes wider, and the gain decreases. It is worth mentioning that the 2-bit switch can form 4 modes of reconfigurable states, so the working states of the above two modes can be expanded to four. It should be noted that the size of the switch determines the equivalent resistance of the switch in the on state and the equivalent capacitance of the switch in the off state, and its influence needs to be considered in the reconfiguration circuit design.

[0033] like Figure 7 and Figure 8 As shown in the figure, the LNA realizes mode switching of two frequency bands through a reconfigurable switch. In working mode 1, the frequency range of the 3dB bandwidth of the LNA is 0.6-3.5GHz, the relative bandwidth is about 70.7%, the noise figure is lower than 0.96dB, and the maximum gain reaches 24.2dB; in working mode 2, the frequency range of the 3dB bandwidth of the LNA is 0.6-5.5GHz, the relative bandwidth is about 80.3%, the noise figure is lower than 1.12dB, and the maximum gain reaches 21.7dB. It can be clearly seen that the proposed structure has obvious advantages in bandwidth expansion. At the same time, within the bandwidth range, the structure can simultaneously achieve low noise figure and high input / output return loss.

[0034] In summary, the new structure proposed in this embodiment integrates the existing switch frequency selection circuit topology, is based on the "reconfigurable topology", innovatively abandons the input matching circuit that easily deteriorates the circuit noise performance, and introduces a tunable inter-stage matching circuit. Through this circuit, we have achieved reconfiguration while the design can achieve bandwidth expansion without deteriorating the amplifier noise and gain performance, and complete the broadband multi-band design of the low-noise amplifier to meet the communication requirements of 5G technology.

[0035] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A broadband reconfigurable low noise amplifier, characterized in that: It includes an input matching network, a negative feedback network, a first transistor, an inter-stage matching network, a second transistor and an output matching network, wherein: The input matching network, the first transistor, the inter-stage matching network, the second transistor and the output matching network are connected in sequence; The first transistor is also connected to the negative feedback network; The inter-stage matching network is provided with a switch frequency selection capacitor.

2. A broadband reconfigurable low noise amplifier according to claim 1, characterized in that: The inter-stage matching network includes a first inductor, a first capacitor, a second capacitor and a third capacitor, wherein The first end of the first inductor, the first end of the first capacitor, the first end of the third capacitor and the drain of the first transistor are connected; The second end of the third capacitor is connected to the gate of the second transistor; The second end of the first inductor, the source of the second transistor and the first end of the second capacitor are connected; The first capacitor and the third capacitor are both switch frequency selection capacitors.

3. A broadband reconfigurable low noise amplifier according to claim 2, characterized in that: The circuit implementation of the switch frequency selection capacitor includes a first switch logic, a second switch logic, a first reverse logic, a second reverse logic, a first MOS transistor, a second MOS transistor, a first preset capacitor, a second preset capacitor, a third preset capacitor and a fourth preset capacitor, wherein: The first end of the first preset capacitor, the drain of the first MOS tube and the second end of the first reverse logic are connected; The first switch logic is connected to the gate of the first MOS tube; The source of the first MOS tube is connected to the first end of the second preset capacitor; The first end of the third preset capacitor, the drain of the second MOS tube and the second end of the second reverse logic are connected; The second switch logic is connected to the gate of the second MOS tube; The source of the second MOS tube is connected to the first end of the fourth preset capacitor.

4. A broadband reconfigurable low noise amplifier according to claim 3, characterized in that: The output matching network includes a second inductor, a third inductor, an output inductor and a fourth capacitor, wherein: The first end of the second inductor is connected to the drain of the second transistor; The second end of the second transistor, the first end of the fourth capacitor and the first end of the output short rod are connected; The second end of the output inductor is connected to the first end of the third inductor.

5. A broadband reconfigurable low noise amplifier according to claim 3, characterized in that: The working process of the switch frequency selection capacitor is as follows: When the first switch logic and the second switch logic are both in a high level state, the first capacitor, the third capacitor, the feedback resistor and the third inductor obtain maximum values, the resonance point of the inter-stage matching circuit moves toward the low frequency, the feedback effect is weakened, the leakage of the output matching inductor is weakened, and the broadband reconfigurable low noise amplifier has a narrow bandwidth and a high gain; When the first switch logic is at a high level and the second switch logic is at a low level, the values ​​of the first capacitor, the third capacitor, the feedback resistor and the third inductor decrease, the resonance point of the inter-stage matching circuit moves toward the high frequency, the feedback effect increases, the leakage of the output matching inductor increases, the bandwidth of the broadband reconfigurable low noise amplifier becomes wider, and the gain decreases.

6. A broadband reconfigurable low noise amplifier according to claim 4, characterized in that: The negative feedback network includes a feedback resistor and a feedback capacitor, wherein: The first end of the feedback resistor, the gate of the first transistor and the input matching network are connected; The second end of the feedback resistor is connected to the first end of the feedback capacitor; The second end of the feedback capacitor is connected to the second end of the first inductor.

7. A broadband reconfigurable low noise amplifier according to claim 6, characterized in that: The input matching network is a fourth inductor, and a first end of the fourth inductor is connected to the gate of the first transistor.

8. A broadband reconfigurable low noise amplifier according to claim 7, characterized in that: Also included is a first isolation capacitor, a second isolation capacitor and a fifth inductor, wherein: The first end of the first isolation capacitor is connected to the second end of the fourth inductor; A first end of the fifth inductor is connected to a source of the first transistor; A first end of the second DC blocking capacitor is connected to a second end of the output inductor.

9. A broadband reconfigurable low noise amplifier according to claim 8, characterized in that: The input impedance is expressed as follows: Among them, Z L is the first stage equivalent output load, C gd1 represents the gate-drain parasitic capacitance of the first transistor, C gs1 represents the gate-source parasitic capacitance of the first transistor, R ds1 represents the parasitic resistance of the transistor, g m1 is the transconductance of the transistor, L5 represents the fifth inductor, and s represents the complex frequency variable.

10. The broadband reconfigurable low noise amplifier according to claim 8, characterized in that: The noise impedance is expressed as follows: Where ω represents the angular frequency, R f Represents the feedback resistor, R g represents the gate parasitic resistance, g m1 is the transconductance of the transistor, g d0 Yes V ds1 = 0, the equivalent transconductance across the drain and source, C gs1 represents the gate-source parasitic capacitance of the first transistor, γ represents a preset parameter, j represents an imaginary unit, L4 represents a fourth inductor, and L5 represents a fifth inductor.

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