Anti-deviation clock duty ratio control circuit based on copy path

Abstract

The invention discloses an anti-deviation clock duty ratio control circuit based on a copy path, which is used for relieving clock duty ratio distortion caused by an aging effect, and belongs to the technical field of control or regulation. According to the clock duty ratio control circuit, the clock duty ratio is monitored and corrected through the same clock duty ratio stretching circuit, the duty ratio of a clock signal can be dynamically adjusted according to a monitoring result, it is ensured that the clock signal keeps the stable 50% duty ratio in long-time operation, and a system time sequence error caused by duty ratio distortion is avoided. The clock duty ratio control circuit does not need additional calibration steps, has high PVTA deviation adaptability, and can accurately adjust the clock duty ratio within the working frequency range of the circuit. In addition, a clock path copy circuit and a critical path copy circuit are adopted to carry out non-intrusive monitoring on a target circuit, and a duty ratio control circuit is started.

Description

Technical Field

[0001] The invention relates to integrated circuit technology, and in particular discloses an anti-deviation clock duty cycle control circuit based on a replica path, belonging to the technical field of control or regulation. Background Art

[0002] In modern integrated circuit design, the clock duty cycle plays a vital role in the timing stability of the system. In many low-power designs, clock gating technology is widely used to reduce unnecessary power consumption. However, the use of clock gating introduces asymmetric aging caused by the bias temperature instability (BTI) effect, which causes asymmetric delays between the rising and falling edges of the clock signal, thereby causing clock duty cycle distortion (DCD). This clock duty cycle distortion can significantly affect the operating performance of sequential logic circuits, including latch-based designs and full-cycle designs based on flip-flops that are sensitive to clock duty cycles, which may cause timing violations, functional errors, and increase minimum supply voltage requirements.

[0003] The prior art proposes a method and device for symmetrical aging of clock trees, which achieves a relatively balanced symmetrical aging effect by controlling the clock gating to maintain a high or low level, and avoids duty cycle deviation caused by long-term gating in the same logic state. However, this type of solution requires more complex control logic, requires statistics on the high and low level gating dwell time, and it is difficult to ensure that the clock duty cycle calibration reaches 50%.

[0004] In addition, some adaptive voltage regulation systems can also solve the timing violation problem caused by PVTA deviation by indirectly monitoring and replicating the timing of critical paths. However, they only ensure the correct function of the circuit through passive adjustment methods such as increasing the operating voltage. They cannot solve the problem of the increase in the minimum operating voltage caused by DCD due to aging, and thus cannot guarantee better power consumption benefits.

[0005] At present, a variety of monitoring and correction technologies for critical path clock duty cycle have been proposed. The existing clock duty cycle controller (DCC) generally relies on adjusting the clock duty cycle at the clock root node, aiming to compensate for the duty cycle distortion caused by the clock leaf node by adjusting the duty cycle of the clock root node. These technologies are usually activated at system boot or voltage frequency conversion (Dynamic Voltage Frequency Scaling, DVFS) to adjust the duty cycle of the system clock. However, these solutions have certain limitations, which are mainly manifested in the following aspects:

[0006] Clock duty cycle distortion caused by PVTA (process angle, temperature, voltage, aging) changes: Since integrated circuits are affected by PVTA changes during actual operation, the measurement and adjustment accuracy of the clock duty cycle is often interfered by these factors, resulting in inaccurate duty cycle adjustment. Existing solutions usually rely on additional calibration steps, which not only increases system complexity but also increases costs;

[0007] The monitoring circuit needs to use clock sampling, which introduces additional oscillator circuit overhead and has certain requirements for the period of the oscillator used for monitoring sampling. In addition, the monitoring takes a large number of clock cycles, which increases the system power-on startup and DVFS adjustment time that requires duty cycle monitoring and adjustment to a certain extent.

[0008] Difficulty in monitoring leaf nodes of clocks: In order to accurately measure the clock duty cycle, traditional solutions need to monitor the leaf nodes of the clock tree, which will introduce a series of problems such as selecting monitoring nodes, interference with the original circuit, monitoring errors caused by wiring, and parasitic effects, thus affecting the reliability and accuracy of monitoring;

[0009] Response time and real-time issues: Existing clock duty cycle controllers usually only adjust the clock duty cycle at startup or voltage-frequency conversion, but cannot make timely dynamic adjustments during real-time operation. This may cause clock duty cycle distortion during operation, resulting in system timing errors and affecting system stability and reliability.

[0010] Therefore, in response to the above problems, the existing technology still has many challenges in clock duty cycle control, and it is necessary to develop a clock duty cycle control circuit that is more efficient, accurate, robust and does not require complex calibration. Summary of the invention

[0011] The purpose of the present invention is to provide an anti-deviation clock duty cycle control circuit based on a replica path in view of the deficiencies of the above-mentioned background technology, so as to solve the technical problems that the existing clock duty cycle control circuit requires a calibration step to improve the influence of PVTA deviation on the clock duty cycle and the existing clock duty cycle control circuit cannot reasonably set the start timing, so as to achieve the purpose of the invention of avoiding the clock duty cycle deviation caused by PVTA aging and causing the minimum operating voltage to degrade through simple and low-cost control logic.

[0012] The present invention adopts the following technical solutions to achieve the above-mentioned invention object:

[0013] A clock duty cycle control circuit with anti-deviation based on a replication path, comprising: an adaptive control circuit, a duty cycle monitoring circuit, a duty cycle correction circuit, a clock tree replication circuit and a critical path replication circuit;

[0014] The adaptive control circuit generates a monitoring process control signal after receiving a start signal, and generates a correction process control signal after receiving a monitoring mode signal. The start signal includes but is not limited to: a system power-on signal, a dynamic voltage and frequency adjustment signal, and a timing warning signal; the duty cycle monitoring circuit monitors the high phase duty cycle and the low phase duty cycle of the mirror clock signal under the action of the monitoring process control signal, and feeds back the monitoring mode signal to the adaptive control circuit after completing the monitoring;

[0015] The duty cycle correction circuit dynamically adjusts the duty cycle of the external clock signal it receives under the action of the correction process control signal, and outputs the correction clock signal to the target circuit;

[0016] A clock tree replication circuit is used to simulate the influence of the aging effect of the correction clock signal on the correction clock duty cycle and output a mirror clock signal;

[0017] The critical path replica circuit is used to simulate the timing influence of the mirror clock signal on the critical path in the target circuit and output a timing warning signal.

[0018] As a further optimization scheme of the anti-deviation clock duty cycle control circuit based on the replica path, the duty cycle correction circuit is the first duty cycle stretching circuit which stretches the high phase or low phase of the external clock signal by a maximum of N delay lengths according to the input correction process control signal. The correction process control signal includes: a correction direction control signal and a correction size control signal, and N is a positive integer.

[0019] As a further optimization scheme of an anti-deviation clock duty cycle control circuit based on a replica path, the duty cycle monitoring circuit includes: a second duty cycle stretching circuit having a tentative stretching function for a maximum of N delay lengths on a mirror clock signal, and a monitoring feedback circuit; the second duty cycle stretching circuit tentatively stretches the mirror clock signal according to an input monitoring process control signal, the monitoring feedback circuit generates a monitoring mode signal according to the tentative monitoring clock signal output by the second duty cycle stretching circuit and the mirror clock signal, and the monitoring process control signal includes: a monitoring direction control signal and a monitoring size control signal.

[0020] As a further optimization scheme of a deviation-resistant clock duty cycle control circuit based on a replica path, the first duty cycle stretching circuit and the second duty cycle stretching circuit time-share the same circuit structure.

[0021] As a further optimization scheme of an anti-deviation clock duty cycle control circuit based on a replica path, the monitoring feedback circuit includes: a positive trigger, a negative trigger, an inverter and an OR gate. The clock input terminals of the positive trigger and the negative trigger are both connected to the mirror clock signal, the data input terminals of the positive trigger and the negative trigger are both connected to the tentative monitoring clock signal, the input terminal of the NOT gate is connected to the output terminal of a trigger, the output terminal of another trigger and the output terminal of the NOT gate are respectively connected to the input terminal of the OR gate, and the OR gate outputs a monitoring mode signal.

[0022] As a further optimization scheme of a clock duty cycle control circuit with anti-deviation based on a replica path, the adaptive control circuit includes: a monitoring control circuit and a correction control circuit;

[0023] A monitoring control circuit generates a monitoring process control signal after receiving a start signal, and records the monitoring size control signal as a high-phase monitoring result signal or a low-phase monitoring result signal after receiving a monitoring mode signal;

[0024] The correction control circuit calculates and outputs a correction direction control signal and a correction magnitude control signal after receiving the high phase monitoring result signal and the low phase monitoring result signal.

[0025] As a further optimization scheme of the anti-skew clock duty cycle control circuit based on the replica path, the correction control circuit,

[0026] When the high phase monitoring result signal is greater than or equal to the low phase monitoring result signal, the output correction direction control signal is a high level representing the low phase of the stretched external clock signal, and the output correction magnitude control signal is half of the difference between the high phase monitoring result signal and the low phase monitoring result signal;

[0027] When the high phase monitoring result signal is smaller than the low phase monitoring result signal, the output correction direction control signal is a low level representing the high phase of the stretched external clock signal, and the output correction size control signal is half of the difference between the low phase monitoring result signal and the high phase monitoring result signal.

[0028] As a further optimization scheme of a clock duty cycle control circuit with anti-skewness based on a replication path, a clock tree replication circuit includes: a clock gating circuit and a replication clock path;

[0029] A clock gating circuit processes the correction clock signal under the action of the clock enable control signal of the longest clock path in the target circuit and outputs a gated clock signal;

[0030] The replica clock path is a replica circuit of the longest clock path in the target circuit, an input end of which is connected to a gated clock signal, and an output mirror clock signal.

[0031] The longest clock path in the target circuit refers to the path with the most intermediate inverter stages starting from a certain clock gating unit as the starting point to the clock end of a trigger or latch of a monitored circuit in the clock tree of the monitored circuit system.

[0032] As a further optimization scheme of a clock duty cycle control circuit with anti-skewness based on a replication path, a critical path replication circuit includes: a D flip-flop, a replication critical path, M groups of timing monitoring units and a multi-input OR gate;

[0033] A D flip-flop, used for performing a frequency division-by-two process on the mirror clock signal received by it;

[0034] The copied critical path is a copied circuit of the first M critical paths at each timing sign-off point in the target circuit, and the input end of each critical path is connected to the divided-by-two clock output by the D flip-flop, where M is a positive integer;

[0035] The M groups of timing monitoring units are used to monitor whether the timing margins at the ends of the triggers and latches are insufficient to affect the normal operation of the target circuit, and to send out an alarm signal in advance; the M groups of timing monitoring units receive the mirror clock signal and the output signals of the M critical path replication circuits, and monitor the timing violations of the M critical path replication circuits under the effect of the preset timing monitoring window width;

[0036] The input end of the multi-input OR gate is connected to the output end of the M groups of timing monitoring units, and a timing warning signal is generated when the timing of at least one critical path replica circuit is violated. The timing warning signal can also be used to dynamically adjust the voltage and frequency of the target circuit.

[0037] As a further optimization scheme for an anti-skew clock duty cycle control circuit based on a replication path, when the terminal timing element of the critical path replication circuit is a D flip-flop, the timing monitoring unit is configured as a D flip-flop type timing monitoring unit; when the terminal timing element of the critical path replication circuit is a latch, the timing monitoring unit is configured as a latch type timing monitoring unit.

[0038] The present invention adopts the above technical solution and has the following beneficial effects:

[0039] (1) No calibration operation: The DCC system of the present invention configures a duty cycle stretching circuit with the same circuit structure in the monitoring module and the correction module. The monitoring module is also configured with a monitoring feedback circuit for the high phase and the low phase of the quantized clock signal. The correction module performs correction according to the quantization result of the monitoring module to ensure the consistency of the monitoring and correction accuracy under PVTA deviation. Therefore, no additional calibration steps are required. The DCC system can adaptively respond to PVTA changes, achieve a wide voltage operating range, effectively respond to duty cycle distortion caused by clock tree aging, enhance the stability and reliability of the system during long-term operation, simplify the design process, reduce the complexity and cost of the system, and realize the monitoring and correction functions by time-division multiplexing the same hardware, thereby reducing hardware overhead.

[0040] (2) Avoiding the limitations of direct monitoring of clock leaf nodes: The present invention uses clock tree replication circuits and critical path replication circuits to perform indirect non-invasive monitoring of timing violations of the critical paths of the target circuits, avoiding the selection difficulties, wiring interference and inaccuracy caused by direct monitoring of clock leaf nodes, ensuring the accuracy of the monitoring results and the reliability of the system, and is particularly suitable for complex systems such as CPUs.

[0041] (3) Optimizing the DCC startup timing: The present invention simulates the impact of the aging effect of the target circuit clock tree on the critical path off-chip, combines the feedback system composed of the monitoring module, the control module, and the correction module, and dynamically generates a startup signal for starting the DCC, thereby reducing unnecessary DCC startup. However, when a system timing error occurs during operation, the DCC is started in time, thereby reducing power consumption and improving system efficiency, thereby optimizing power consumption and performance.

[0042] (4) Improving system accuracy and response speed: The present invention can complete clock duty cycle correction in only 51 clock cycles at a frequency of 1 GHz, with a clock duty cycle error of 1.1% and a monitoring error of 0.1%, ensuring real-time response and high-precision correction of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A configuration of a clock duty cycle control circuit with skew resistance according to an embodiment of the invention is illustrated.

[0044] Figure 2Picture shows Figure 1 Configuration of the duty cycle correction circuit.

[0045] Figure 3 Picture shows Figure 2 The configuration of the delay unit.

[0046] Figure 4 Picture shows Figure 1 Configuration of the duty cycle monitoring circuit.

[0047] Figure 5 Picture shows Figure 4 Configuration of the monitoring feedback circuit.

[0048] Figure 6 Picture shows Figure 1 Configuration of the adaptive control circuit.

[0049] Figure 7 Picture shows Figure 6 Flowchart of circuit control method.

[0050] Figure 8 Picture shows Figure 1 Configuration of the replicated clock tree.

[0051] Fig. 9 Picture shows Figure 1 Configuration of the replication critical path.

[0052] Fig.10 A configuration of a trigger type timing monitoring unit is shown.

[0053] Fig.11 A configuration of a latch type timing monitoring unit is shown.

[0054] Fig.12 Picture shows Figure 1 Circuit working waveform diagram.

[0055] Explanation of the numbers in the figure: XOR101_1, first XOR gate, XOR101_2, second XOR gate, XORF, third XOR gate, XORL, fourth XOR gate, BUFFER, input buffer, DU100_1~DU100_N, first to Nth delay units, OR100_1, OR gate, DFF500, D flip-flop, OR500, multi-input OR gate, D3, main flip-flop, D4, shadow flip-flop, D5, fifth flip-flop, L1, main latch, L2, shadow latch, TDE1, first adjustable delay unit, TDE2, second adjustable delay unit, ND2_1, first NAND gate, ND2_2, second NAND gate. DETAILED DESCRIPTION

[0056] The specific embodiments described below in conjunction with the accompanying drawings are intended to provide a specific description of the technical solution of the present application, rather than the only way to practice the technical solution of the present application. In order to provide a comprehensive understanding of the technical solution of the present application, the specific embodiments include specific details. However, it is obvious to those skilled in the art that the technical solution of the present application can be practiced without these specific details.

[0057] Hereinafter, a duty cycle control circuit according to the present application will be described below by way of embodiments with reference to the accompanying drawings.

[0058] See also Figure 1 According to the embodiment, the duty cycle control circuit may include a duty cycle correction circuit, an adaptive control circuit, a duty cycle monitoring circuit, a clock tree replication circuit, and a critical path replication circuit.

[0059] The duty cycle correction circuit can correct the duty cycle of the external clock signal CLK_IN according to the correction direction control signal DCA_D and the correction size control signal DCA_CFG[N:1] to generate a corrected clock signal CLK_OUT, wherein the external clock signal CLK_IN is a signal from the root node of the clock circuit in the target circuit system, and the correction size control signal DCA_CFG[N:1] is a thermometer code.

[0060] The adaptive control circuit can control the correction process of the duty cycle correction circuit and the monitoring process of the duty cycle monitoring circuit according to the timing warning signal ERROR and the monitoring mode signal STATE, and generate a monitoring direction control signal DCM_D and a monitoring size control signal DCM_CFG[N:1] for monitoring the duty cycle monitoring circuit, as well as a correction direction control signal DCA_D and a correction size control signal DCA_CFG[N:1] for the duty cycle correction circuit, wherein the monitoring size control signal DCM_CFG[N:1] is a thermometer code.

[0061] The duty cycle monitoring circuit can monitor the high and low phase duty cycles of the clock signal CLK_MIRR passing through the clock tree replication circuit according to the monitoring direction control signal DCM_D and the monitoring size control signal DCM_CFG[N:1], and feedback the duty cycle monitoring status of the correction clock signal CLK_MIRR to the adaptive control circuit, and generate a state switching signal STATE after completing the high phase duty cycle size monitoring or the low phase duty cycle size monitoring.

[0062] The clock tree replica circuit makes the received correction clock signal CLK_OUT simulate the duty cycle degradation process caused by the aging of the clock tree in the target circuit, and generates a mirror clock signal CLK_MIRR with a changed duty cycle after aging.

[0063] The critical path replication circuit will generate a timing warning signal ERROR based on the mirror clock signal CLK_MIRR to control the working state of the adaptive control circuit, prevent the change of the clock duty cycle from affecting the timing correctness of the target circuit, and avoid the occurrence of setup time violations, thereby avoiding circuit function errors caused by timing violations and the increase of the minimum operating voltage of the target circuit, which will cause additional power consumption overhead.

[0064] Figure 2 Picture shows Figure 1 Configuration of the duty cycle correction circuit.

[0065] See also Figure 2 A possible duty cycle correction circuit is implemented by a duty cycle stretching circuit, including: a first XOR gate XOR101_1, an output buffer BUFFER, first to Nth delay units DU100_1~DU100_N, an OR gate OR100_1, and a second XOR gate XOR101_2.

[0066] The first XOR gate XOR100_1 is used to receive the correction direction control signal DCA_D and the external clock signal CLK_IN, pre-process the external clock signal, determine the stretching direction of the subsequent clock duty cycle correction, and generate a pre-corrected clock signal.

[0067] The input buffer unit BUFFER is used to enhance the driving capability of the pre-correction clock signal and generate a phase-stretched input signal pe_in to drive a plurality of long series-connected delay units in the correction circuit. If the number of delay units is small, it is not required.

[0068] Each delay unit can stretch the phase-stretched input signal pe_in by a delay length. The delay length of a delay unit will be introduced later. The correction size control signal DCA_CFG[N:1] generated by the adaptive control circuit determines whether each delay unit is turned on. For example, the opening of the i-th delay unit DU100_i is controlled by the i-th thermometer code DCA_CDG[i] of the correction size control signal. N delay units connected in series can make the high / low phase stretching length of the phase-stretched input signal pe_in as small as 1 times the delay unit length and as large as N times the delay unit length, thereby achieving flexible timing adjustment and precise correction, where i can take values ​​of 1, 2, ..., N. Specifically, the larger N is, the wider the monitoring range of the clock duty cycle. The embodiment uses 256-level delay units to achieve clock duty cycle monitoring and correction from 125MHz to 1GHz under a 22nm process.

[0069] The first OR gate OR100_1 can combine the phase-stretched output signal pe_out whose high / low phase width is adjusted by the series delay unit and the phase-stretched input signal pe_in to generate a stretched clock signal pe_clk.

[0070] The second XOR gate XOR100_2 receives the correction direction control signal DCA_D, adjusts the phase of the stretched clock signal pe_clk under the control of the correction direction control signal DCA_D, and generates an output clock correction signal CLK_OUT synchronized with the external clock signal CLK_IN.

[0071] Figure 3 Shown Figure 2 The configuration of the delay unit.

[0072] See also Figure 3 A possible delay unit may include two NOR gates, one NOT gate, or a custom delay unit circuit with the same logic function and other standard units in the standard unit library. Specifically, the smaller the delay of the delay unit, the higher the duty cycle accuracy of the monitoring, and the higher the clock frequency that can be monitored and adjusted.

[0073] The delay unit can receive the phase stretch input signal pe_in via its first input port IN_1; the second input port IN_2 receives the output signal of the previous delay unit. In particular, for Figure 2 The Nth delay unit DU100_N in the duty cycle correction circuit has a second input port connected to a constant low level signal; the third input port IN_3 receives a duty cycle correction control signal DCA_CFG[i] for controlling the on and off state of the delay unit.

[0074] Figure 4 Picture shows Figure 1 Configuration of the duty cycle monitoring circuit.

[0075] See also Figure 4 The duty cycle monitoring circuit includes a duty cycle stretching circuit and a monitoring feedback circuit.

[0076] The duty cycle stretching circuit uses Figure 2 The circuit structure is the same as the duty cycle correction circuit, and the layout and routing are kept consistent during the back-end circuit implementation process. The circuit can perform a tentative stretching of the mirror clock signal CLK_MIRR of the simulated target circuit clock tree aging through the monitoring direction control signal DCM_D and the monitoring size control signal DCM_CFG[N:1] from the adaptive control circuit. In each stretching trial process, the pulse width change of the mirror clock signal CLK_MIRR is the same as the delay length of a delay unit in the clock correction circuit, generating a tentative monitoring clock pe_dcm.

[0077] The monitoring feedback circuit is a pair of sampling triggers, which can generate a monitoring mode signal STATE to control the adaptive control circuit's control process of the tentative monitoring of the duty cycle monitoring circuit based on the tentative monitoring clock pe_dcm from the duty cycle stretching circuit and the input mirror clock signal CLK_MIRR, and control the start of the clock correction process of the duty cycle correction circuit after the monitoring is completed.

[0078] Figure 5 Picture shows Figure 4 The structure of the monitoring feedback circuit.

[0079] See also Figure 5 The monitoring feedback circuit is implemented by a sampling trigger pair including a positive trigger and a negative trigger. The mirror clock signal CLK_MIRR of the input duty cycle stretching circuit is used as the sampling clock signal of the trigger pair clock input end, and the probe monitoring clock pe_dcm output by the clock duty cycle stretching circuit is used as the sampled signal of the trigger pair data input end. The monitoring mode signal STATE is obtained through the Q1 and Q2 signals output by the pair of sampling triggers, and the monitoring mode signal STATE is provided to the adaptive control circuit to complete the state switching of the monitoring process.

[0080] Figure 6 Picture shows Figure 1 Configuration of the adaptive control circuit. Figure 7 Picture shows Figure 6 A method for adaptively controlling a duty cycle circuit.

[0081] See also Figure 6 ,The adaptive control circuit includes a monitoring control circuit and a correction control circuit.

[0082] The monitoring control circuit is a finite state machine, which receives the timing warning signal ERROR from the critical path replication circuit. When ERROR is at a high level, the monitoring control process is started to generate the monitoring direction control signal DCM_D and the monitoring size control signal DCM_CFG[N:1]. After the duty cycle monitoring circuit completes the monitoring of the duty cycle of the mirror clock signal CLK_MIRR and the monitoring control circuit receives the monitoring mode signal STATE generated by the duty cycle monitoring circuit, the monitoring control circuit sends the recorded high phase monitoring code value clk_h[N:1] and low phase monitoring code value clk_l[N:1] to the correction control circuit. Other ways to start the monitoring circuit may also include the input of the system power-on boot signal and the dynamic voltage frequency adjustment DVFS signal.

[0083] The correction control circuit generates a correction direction control signal DCA_D and a correction magnitude control signal DCA_CFG[N:1] according to the magnitude relationship between the received high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1]. When the high phase monitoring code value clk_h[N:1] is greater than or equal to the low phase monitoring code value clk_l[N:1], the generated correction direction control signal DCA_D is at a high level, and the duty cycle correction circuit is controlled to perform phase stretching on the low phase of the external clock signal CLK_IN. When the high phase monitoring code value clk_h[N:1] is less than the low phase monitoring code value clk_l[N:1], the generated correction direction control signal DCA_D is at a low level, and the duty cycle correction circuit is controlled to perform phase stretching on the high phase of the external clock signal CLK_IN. The magnitude of the phase stretching is controlled by the correction magnitude control signal DCA_CFG[N:1], and the correction magnitude control signal DCA_CFG[N:1] is calculated by the relative relationship between the high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1].

[0084] The calculation formula of the correction size control signal DCA_CFG[N:1] is:

[0085] Figure 8 Picture shows Figure 1 Configuration of the clock tree replication circuit.

[0086] See also Figure 8 ,The clock tree replication circuit includes a clock gating circuit and a replicated clock path.

[0087] The clock gating circuit is composed of the clock gating unit provided by the foundry. It shares the same clock enable control signal EN with the longest clock path of the target circuit. The clock enable control signal EN determines whether the clock gating circuit gates the output gated clock CLK_CGC. The output clock can be gated to a high level or a low level according to the target circuit situation to perform subsequent clock aging simulation and clock duty cycle correction operations.

[0088] The replica clock path is a replica circuit of the longest clock path of the target circuit. Since the clock gating circuit and the target circuit share the same clock enable control signal EN, the replica clock path and the clock path in the target circuit will produce approximately the same aging clock duty cycle degradation, generating a mirror clock signal CLK_MIRR.

[0089] Fig. 9 Picture shows Figure 1 Configuration of the critical path replication circuit.

[0090] See also Fig. 9,The critical path replication circuit includes a D flip-flop DFF500, a replication critical path, a timing monitoring unit, and a multi-input OR gate OR500.

[0091] The D flip-flop DFF500 is used to receive the mirror clock signal CLK_MIRR output by the replica clock tree circuit, and divide the mirror clock signal CLK_MIRR by two to generate a data input activation signal.

[0092] The copy critical path is the M longest critical paths in the target circuit selected by the timing analysis tools such as PrimeTime according to the process, voltage and temperature conditions of the timing sign-off. The M copy critical paths receive the divided mirror clock signal and generate M copy path output signals CLK_RC[M:1]. Specifically, the first 8 critical paths under each timing sign-off condition can be selected for copying, where M refers to the number of the longest critical paths selected.

[0093] The timing monitoring unit configures the timing monitoring window width according to the monitoring control signal TW[5:0], monitors the setup time violation of the M replica path output signals CLK_RC[M:1] of the replica critical path output, and the reserved window is used to realize the early warning function to avoid starting the duty cycle adjustment after the timing is completely wrong. The timing monitoring unit has two structures, one is a D-type trigger-type timing monitoring unit, which is used to monitor the setup time violation of the D-type trigger caused by the excessive high-level duty cycle of the clock, and the other is a latch-type timing monitoring unit, which is used to monitor the setup time violation of the high-level transparent latch caused by the excessively small high-level duty cycle of the clock. Each group of timing monitoring units will process the output signal of a critical path replica circuit and monitor the timing violation. When a timing violation occurs, at least one group of timing monitoring units will generate a high-level monitoring violation signal ERROR_T[j:1], j=1,2,……,M.

[0094] The multi-input OR gate OR500 is used to merge the monitoring violation signal ERROR_T[j:1] into a violation signal ERROR to control the start of the adaptive control unit. That is, as long as there is a timing violation of a copy critical path, the duty cycle control circuit needs to be turned on for monitoring and adjustment.

[0095] Fig.10 The diagram shows a D-flip-flop type timing monitoring unit. For a critical path replica circuit whose terminal timing element is a D-flip-flop, a D-flip-flop type timing monitoring unit is configured in the timing monitoring unit corresponding to the critical path replica circuit.

[0096] See also Fig.10 , a possible D-flip-flop type timing monitoring unit is composed of a main flip-flop D3, a shadow flip-flop D4, a fifth flip-flop D5, a first adjustable delay unit TDE1, and a third XOR gate XORF.

[0097] The first adjustable delay unit TDE1 may be composed of a multi-stage inverter with a data selector, configure the delay length according to the monitoring control signal TW[5:0] configured by the user, set the timing protection band length in the timing monitoring, and generate a delayed input data signal CLK_RD.

[0098] The main trigger D3 receives the output signal CLK_RC of the critical path replica circuit and generates a reference monitoring signal Qref, and the shadow trigger D4 receives the delayed path clock CLK_RD and generates a configuration monitoring signal Qcfg. Both the main trigger and the shadow trigger have the same circuit structure as the end trigger of the critical path replica circuit.

[0099] The third XOR gate XORF determines whether the reference monitoring signal Qref is consistent with the configuration monitoring signal Qcfg, generates a determination signal error_DFF, and generates a monitoring violation signal ERROR_T after being sampled by the fifth D flip-flop D5.

[0100] Fig.11 The figure shows a latch-type timing monitoring unit. For a critical path replica circuit whose terminal timing element is a latch, a latch-type timing monitoring unit is configured in the timing monitoring unit corresponding to the critical path replica circuit.

[0101] See also Fig.11 A possible latch-type timing monitoring unit is composed of a main latch L1, a shadow latch L2, a second adjustable delay unit TDE2, a fourth XOR gate XORL, a first NAND gate ND2_1, and a second NAND gate ND2_2.

[0102] The second adjustable delay unit TDE2 has the same circuit structure as the first adjustable delay unit TDE1 in the D-flip-flop type timing monitoring unit.

[0103] The main latch L1 receives the output signal CLK_RC of the critical path replication circuit, and generates a reference monitoring signal Qref through the first NAND gate ND2_1L, and the shadow latch L2 receives the delayed path clock signal CLK_RD, and generates a configuration monitoring signal Qcfg through the second NAND gate ND2_2. Both the main latch and the shadow latch have the same circuit structure as the end latch of the critical path replication circuit.

[0104] The fourth XOR gate XORL determines whether the reference monitoring signal Qref is consistent with the configuration monitoring signal Qcfg, generates a judgment signal error_LAT, and generates a monitoring violation signal ERROR_T after being sampled by the D flip-flop L3.

[0105] In the following, the operation of the duty cycle correction circuit according to the present embodiment will be described as follows. Among them, the target circuit can select a more complex digital system, such as an open source RISC-V processor, a field-specific neural network accelerator, and a low-power, long-life, high-reliability processor and other integrated circuit systems.

[0106] When the clock duty cycle control circuit enable signal is at a low level, the duty cycle control circuit of the embodiment is in a dormant state, the target circuit operates normally, and no dynamic voltage frequency adjustment or timing violation occurs. In this stage, the adaptive control circuit does not work, and does not monitor the input external clock CLK_IN and perform duty cycle correction operations, thereby saving circuit power consumption.

[0107] When the system is powered on boot, DVFS adjustment or timing monitoring violation ERROR occurs, the clock duty cycle control circuit enable signal is high, the duty cycle control circuit of the embodiment is in working state, the clock tree replication circuit and the target circuit are turned on at the same time, and synchronous working aging occurs.

[0108] The duty cycle control circuit of this embodiment is on the same chip as the target circuit, so the process, voltage and temperature conditions are similar, and the working and sleep states are synchronized through the clock enable signal EN. Therefore, the aging state of the clock tree replica circuit can reflect the aging degradation of the clock path in the target circuit without invading the target circuit.

[0109] Aging degradation on the clock path manifests itself as an increase or decrease in the duty cycle of the output clock signal, and in the clock tree replica circuit manifests itself as a change in the duty cycle of the output mirror clock signal CLK_MIRR.

[0110] In the early stage of circuit aging, the duty cycle of the mirror clock signal CLK_MIRR does not change significantly, the mirror clock signal CLK_MIRR established by the timing monitoring unit in the critical path replication circuit has normal establishment time, no timing violation occurs, the generated violation signal ERROR is low, the adaptive control circuit does not work, the duty cycle correction circuit and the duty cycle monitoring circuit do not correct and monitor the input clock signal CLK_IN, and the duty cycle control circuit in this embodiment has the same CLK_OUT and CLK_IN.

[0111] In the later stage of circuit aging, the duty cycle of the mirror clock signal CLK_MIRR changes significantly. The mirror clock signal CLK_MIRR setup time detected by the timing monitoring unit in the critical path replication circuit is abnormal, a timing violation occurs, and the generated violation signal ERROR is high, and the adaptive control circuit starts working.

[0112] If the CLK_MIRR duty cycle change is manifested as a high-level duty cycle less than 50%, when the voltage is reduced or the frequency is increased, the latch-type timing monitoring unit in the timing monitoring unit in the critical path replication circuit will detect the insufficient setup time earlier, resulting in a timing violation, and the critical path replication circuit will generate a high-level violation signal ERROR.

[0113] If the CLK_MIRR duty cycle change is manifested as a high-level duty cycle far greater than 50%, when the voltage is reduced or the frequency is increased, the D-flip-flop type timing monitoring unit in the timing monitoring unit in the critical path replication circuit will detect the insufficient setup time earlier, resulting in a timing violation, and the critical path replication circuit will generate a high-level violation signal ERROR.

[0114] The high-level violation signal ERROR enables the adaptive control circuit and starts the duty cycle monitoring circuit. Fig.12 As shown in the figure, taking the clock duty cycle variation as 20% as an example, the Figure 1 The working waveform of the entire system.

[0115] The adaptive control circuit sends a monitoring direction control signal DCM_D to the duty cycle monitoring circuit to start clock monitoring of the mirror clock signal CLK_MIRR. The monitoring size control signal DCM_CDG[N:1] starts from 0 and gradually increases with an interval of 1.

[0116] When the monitoring size control signal DCM_CFG[N:1] increases for the first time to a level large enough to make the probe monitoring clock pe_dcm generated by the duty cycle stretching circuit in the duty cycle monitoring circuit a DC high level signal, the monitoring feedback circuit generates a high level monitoring mode signal STATE, that is, the positive trigger output Q1 switches from a low level to a high level.

[0117] The adaptive control circuit receives the high-level monitoring mode signal STATE, records the monitoring magnitude control signal DCM_CFG[N:1] at this time, and saves it as the low-phase monitoring code value clk_l[N:1].

[0118] After completing the recording of the low phase monitoring code value clk_l[N:1], the adaptive circuit resets the monitoring size control signal DCM_CFG[N:1] to 0, adjusts the monitoring direction control signal DCM_D to a DC high level signal, and starts high phase monitoring. The monitoring size control signal DCM_CDG[N:1] starts from 0 and gradually increases with an interval of 1.

[0119] When the monitoring size control signal DCM_CFG[N:1] increases for the first time to a level large enough to make the probe monitoring clock pe_dcm generated by the duty cycle stretching circuit in the duty cycle monitoring circuit a DC low level signal, the monitoring feedback circuit generates a high level monitoring mode signal STATE, that is, the negative trigger output Q2 switches from a high level to a low level.

[0120] The adaptive control circuit receives the high-level monitoring mode signal STATE, records the monitoring magnitude control signal DCM_CFG[N:1] at this time, and saves it as the high-phase monitoring code value clk_h[N:1].

[0121] The adaptive control circuit completes the high phase and low phase monitoring of the mirror clock signal CLK_MIRR, and after recording the high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1], the monitoring control circuit transmits the high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1] to the correction control circuit.

[0122] If the duty cycle of the mirror clock signal CLK_MIRR is less than 50%, the high phase monitoring code value clk_h[N:1] of the monitoring result is less than the low phase monitoring code value clk_l[N:1]. The correction control circuit sets the correction direction control signal DCA_D to a low level according to the magnitude relationship between the high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1], increases the input clock duty cycle of the clock root node, and calculates The correction magnitude control signal DCA_CFG[N:1] is determined.

[0123] If the duty cycle of the mirror clock signal CLK_MIRR is greater than 50%, the high phase monitoring code value clk_h[N:1] of the monitoring result is greater than or equal to the low phase monitoring code value clk_l[N:1]. The correction control circuit sets the correction direction control signal DCA_D to a high level according to the magnitude relationship between the high phase monitoring code value clk_h[N:1] and the low phase monitoring code value clk_l[N:1], reduces the input clock duty cycle of the clock root node, and calculates The correction magnitude control signal DCA_CFG[N:1] is determined.

[0124] The duty cycle correction circuit performs phase stretching on the input external clock CLK_IN according to the correction direction control signal DCA_D and the correction magnitude control signal DCA_CFG[N:1] to generate a correction clock CLK_OUT.

[0125] The output clock CLK_OUT may have a duty cycle shift due to aging degradation when passing through the replica clock tree circuit, and ultimately generate a mirror clock signal CLK_MIRR with a duty cycle of 50%.

[0126] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Accordingly, the DCC described herein should not be limited based on the described embodiments.

Claims

1. A clock duty cycle control circuit with anti-skewness based on a replica path, characterized in that: include: The adaptive control circuit generates a monitoring process control signal after receiving a start signal, and generates a correction process control signal after receiving a monitoring mode signal, wherein the start signal includes but is not limited to: a system power-on signal, a dynamic voltage and frequency adjustment signal, and a timing warning signal; A duty cycle monitoring circuit, under the action of the monitoring process control signal, monitors the high phase duty cycle and the low phase duty cycle of the mirror clock signal, and feeds back the monitoring mode signal to the adaptive control circuit after completing the monitoring; A duty cycle correction circuit, under the action of the correction process control signal, corrects the external clock signal it receives and outputs the corrected clock signal to the target circuit; A clock tree replica circuit, used to simulate the aging effect of the correction clock signal and output a mirror clock signal; and, The critical path replication circuit is used to simulate the timing influence of the mirror clock signal on the critical path in the target circuit and output a timing warning signal.

2. The anti-skew clock duty cycle control circuit based on the replica path according to claim 1, characterized in that: The duty cycle correction circuit is a first duty cycle stretching circuit that stretches the high phase or low phase of the external clock signal by a maximum of N delay lengths according to an input correction process control signal. The correction process control signal includes: a correction direction control signal and a correction size control signal, and N is a positive integer.

3. The anti-skew clock duty cycle control circuit based on the replica path according to claim 2, characterized in that: The duty cycle monitoring circuit includes: a second duty cycle stretching circuit that performs a tentative stretching function on the mirror clock signal by a maximum of N delay lengths, and a monitoring feedback circuit; the second duty cycle stretching circuit performs a tentative stretching on the mirror clock signal according to an input monitoring process control signal, and the monitoring feedback circuit generates a monitoring mode signal based on the tentative monitoring clock signal output by the second duty cycle stretching circuit and the mirror clock signal, and the monitoring process control signal includes: a monitoring direction control signal and a monitoring size control signal.

4. The anti-skew clock duty cycle control circuit based on the replica path according to claim 3, characterized in that: The first duty cycle stretching circuit and the second duty cycle stretching circuit use the same circuit structure in time-sharing multiplexing.

5. The anti-skew clock duty cycle control circuit based on a replica path according to claim 3 or 4, characterized in that: The monitoring feedback circuit includes: a positive trigger, a negative trigger, an inverter and an OR gate, the clock input ends of the positive trigger and the negative trigger are both connected to the mirror clock signal, the data input ends of the positive trigger and the negative trigger are both connected to the tentative monitoring clock signal, the input end of the NOT gate is connected to the output end of a trigger, the output end of another trigger and the output end of the NOT gate are respectively connected to the input end of the OR gate, and the OR gate outputs a monitoring mode signal.

6. The anti-skew clock duty cycle control circuit based on a replica path according to claim 5, characterized in that: The adaptive control circuit comprises: A monitoring control circuit generates a monitoring process control signal after receiving a start signal, and records the monitoring size control signal as a high phase monitoring result signal or a low phase monitoring result signal after receiving a monitoring mode signal; and, The correction control circuit calculates and outputs a correction direction control signal and a correction magnitude control signal after receiving the high phase monitoring result signal and the low phase monitoring result signal.

7. The anti-skew clock duty cycle control circuit based on a replica path according to claim 6, characterized in that: The correction control circuit, When the high phase monitoring result signal is greater than or equal to the low phase monitoring result signal, the output correction direction control signal is a high level representing the low phase of the stretched external clock signal, and the output correction magnitude control signal is half of the difference between the high phase monitoring result signal and the low phase monitoring result signal; When the high phase monitoring result signal is less than the low phase monitoring result signal, the output correction direction control signal is a low level representing the high phase of the stretched external clock signal, and the output correction size control signal is half of the difference between the low phase monitoring result signal and the high phase monitoring result signal.

8. The anti-skew clock duty cycle control circuit based on a replica path according to claim 5, characterized in that: The clock tree replication circuit comprises: a clock gating circuit, which processes the corrected clock signal under the action of the clock enable control signal of the longest clock path in the target circuit and outputs a gated clock signal; and, The replica clock path is a replica circuit of the longest clock path in the target circuit, an input end of which is connected to a gated clock signal, and an output mirror clock signal.

9. The anti-skew clock duty cycle control circuit based on a replica path according to claim 5, characterized in that: The critical path replication circuit comprises: A D flip-flop, used for performing a frequency division-by-two process on the mirror clock signal received by it; A copy critical path is a copy circuit of M critical paths in the target circuit, the input end of each critical path is connected to the output end of the D flip-flop, and M is a positive integer; M groups of timing monitoring units receive the mirror clock signal and the output signals of the M critical path replica circuits, and monitor the timing violations of the M critical path replica circuits under the effect of a preset timing monitoring window width; and, The multi-input OR gate has an input terminal connected to the output terminals of the M groups of timing monitoring units, and generates a timing warning signal when the timing of at least one critical path replica circuit is violated.

10. The anti-skew clock duty cycle control circuit based on a replica path according to claim 9, characterized in that: When the terminal timing element of the critical path replication circuit is a trigger, the timing monitoring unit is configured as a trigger-type timing monitoring unit; when the terminal timing element of the critical path replication circuit is a latch, the timing monitoring unit is configured as a latch-type timing monitoring unit.

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