Signal synchronization device and digital signal output device

Abstract

The present invention provides a signal synchronization device and a digital signal output device. A digital circuit counts a first frequency signal to generate a count value, generates an output voltage according to the count value, and an analog circuit generates a feedback signal according to the output voltage. A synchronization circuit samples the feedback signal according to a second frequency signal to generate a synchronization signal. A control circuit generates a voltage control signal according to the second frequency signal and the synchronization signal to control the digital circuit to stop counting the first frequency signal, wherein the frequency of the first frequency signal is lower than the frequency of the second frequency signal.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a signal synchronization device and a digital signal output device. Background Technology

[0002] Integrated circuits have become increasingly complex. A single chip not only integrates analog and digital circuit designs, but also contains several operating regions with different frequencies. To prevent digital signals from transmitting between different frequency domains and causing metastability, synchronization circuits are used to prevent metastability when digital signals cross frequency domains.

[0003] In existing technologies, a common synchronous circuit design uses two-stage flip-flops (D flip-flops) connected in series to avoid metastability. When metastability occurs in the first stage flip-flop, the second stage flip-flop can correct the metastable signal, preventing errors in the digital circuit due to metastability. However, because the digital signal experiences a two-cycle delay after passing through the two stages of flip-flops, this synchronous circuit is not suitable for applications requiring real-time control. Summary of the Invention

[0004] This invention provides a signal synchronization device and a digital signal output device, which can meet the real-time control requirements when synchronizing analog signals to the frequency domain of digital signals while avoiding metastability.

[0005] The signal synchronization device of the present invention includes a synchronization circuit and a control circuit. The signal synchronization device is coupled to a digital circuit that generates an output voltage based on a first frequency signal, and to an analog circuit that generates a feedback signal based on the output voltage. The synchronization circuit is coupled to the analog circuit and generates a synchronization signal by sampling the feedback signal based on a second frequency signal. The control circuit is coupled to the digital circuit and the synchronization circuit, and generates a voltage control signal based on the second frequency signal and the synchronization signal to control the digital circuit to generate the output voltage. The control circuit includes a first AND gate and multiple flip-flops. The output of the first AND gate is coupled to the digital circuit. The multiple flip-flops are connected in series between the output of the synchronization circuit and the input of the first AND gate, sequentially transmitting the synchronization signal in response to the second frequency signal. The input of the first AND gate is coupled to the output of each flip-flop and the output of the synchronization circuit, and generates a voltage control signal based on the output signals of each flip-flop and the synchronization signal, wherein the frequency of the first frequency signal is lower than the frequency of the second frequency signal, and the voltage control signal is synchronized with the feedback signal.

[0006] In one embodiment of the present invention, the signal synchronization device further includes a frequency adjustment circuit coupled to a digital circuit to adjust the frequency of the second frequency signal to generate the first frequency signal.

[0007] In one embodiment of the present invention, the number of the above-mentioned triggers satisfies the following formula:

[0008]

[0009] Where N is the number of triggers, FC1 is the frequency of the first frequency signal, and FC2 is the frequency of the second frequency signal.

[0010] The present invention also provides a digital signal output device, including a digital circuit, an analog circuit, and the above-mentioned signal synchronization device, wherein the digital circuit generates an output voltage according to a first frequency signal, and the analog circuit is coupled to the digital circuit and generates a feedback signal according to the output voltage.

[0011] In one embodiment of the present invention, the digital circuit includes a counter coupled to the output of a first AND gate, which counts a first frequency signal to generate a count value, and stops counting the first frequency signal under the control of a voltage control signal. A voltage regulator is coupled to the counter and an analog circuit, and generates the output voltage based on the count value.

[0012] In one embodiment of the present invention, the digital signal output device further includes an inverter and a second AND gate. The input and output terminals of the inverter are respectively coupled to the output terminal of the first AND gate and the input terminal of the counter. The counter stops counting the first frequency signal based on the output signal of the inverter. The input terminal of the second AND gate is coupled to the output terminal of the inverter and receives an enable signal. The output terminal of the second AND gate is coupled to the input terminal of the counter. The second AND gate controls the counter to stop counting the first frequency signal based on the enable signal and the output signal of the inverter.

[0013] In one embodiment of the present invention, the synchronization circuit includes a first synchronous flip-flop and a second synchronous flip-flop. The second synchronous flip-flop and the first synchronous flip-flop are connected in series between the analog circuit and the control circuit. The first synchronous flip-flop and the second synchronous flip-flop sequentially transmit feedback signals in response to a second frequency signal, so as to output a synchronization signal at the output terminal of the second synchronous flip-flop.

[0014] In one embodiment of the present invention, the analog circuit described above is a comparator. The input terminal of the comparator is coupled to the output terminal of the digital circuit and a reference voltage. The output terminal of the comparator is coupled to a synchronization circuit. The comparator compares the output voltage with the reference voltage to generate a feedback signal.

[0015] In one embodiment of the present invention, the above-mentioned digital signal output device further includes a first switching circuit, which is coupled to the output terminal of the digital circuit, the input terminal of the comparator and the output terminal of the signal generation circuit, and is controlled by a first switching signal to connect the input terminal of the comparator to the output terminal of the digital circuit or the output terminal of the signal generation circuit.

[0016] In one embodiment of the present invention, the digital signal output device further includes a latching circuit and a second switching circuit. The latching circuit latches the output signal of the comparator. The second switching circuit is coupled to the output terminal of the analog circuit, the synchronization circuit, and the latching circuit, and is controlled by a second switching signal to connect the output terminal of the comparator to the input terminal of the synchronization circuit or the input terminal of the latching circuit.

[0017] Based on the above, embodiments of the present invention ensure that the frequency of the frequency signal upon which the digital circuit generates the output voltage is lower than the frequency of the frequency signals input to the synchronization circuit and the control circuit. This allows the control circuit to respond in real-time to changes in the feedback signal output from the analog circuit and control the output voltage of the digital circuit. While using a synchronization circuit design to avoid metastability, the control circuit corrects for potential signal delays caused by the synchronization circuit, meeting the real-time control requirements when synchronizing the analog signal to the frequency domain of the digital signal. Furthermore, by coupling the outputs of multiple cascaded flip-flops in the control circuit to the input of an AND gate, and controlling the output voltage of the digital circuit based on the voltage control signal output by the AND gate, jitter in the feedback signal provided by the analog circuit can be avoided, preventing malfunctions in the digital signal output device. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a digital signal output device according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of a digital signal output device according to another embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the signal waveform of a digital signal output device according to an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of a digital signal output device according to another embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of a digital signal output device according to another embodiment of the present invention. Detailed Implementation

[0023] The term "coupled" as used in this specification (including the claims) may refer to any direct or indirect connection. For example, "the first device is coupled to the second device" may be interpreted as "the first device is directly connected to the second device" or "the first device is indirectly connected to the second device through other devices or connections." Furthermore, in any appropriate place in the drawings and embodiments, elements / devices / steps with the same reference numerals denote the same or similar parts. Elements / devices / steps with the same reference numerals or names in different embodiments may be cross-referenced.

[0024] The present application is described in detail below with reference to several embodiments, but the application is not limited to the embodiments provided, and the embodiments provided may be combined appropriately. In the following embodiments, the same or similar element symbols represent the same or similar components or signals.

[0025] Figure 1 This is a schematic diagram of a digital signal output device according to an embodiment of the present invention. Please refer to... Figure 1 The digital signal output device may include a digital circuit 102, an analog circuit 104, and a signal synchronization device including a synchronization circuit 106 and a control circuit 108. The digital circuit 102 is coupled to the analog circuit 104 and the control circuit 108, and the synchronization circuit 106 is coupled to the analog circuit 104 and the control circuit 108. The digital circuit 102 counts the frequency signal clk_L to generate a count value and generates an output voltage Vo corresponding to the count value. The analog circuit 104 generates a feedback signal d_in based on the output voltage and sends it to the synchronization circuit 106. The synchronization circuit 106 samples the feedback signal d_in based on the frequency signal clk_H to generate a synchronization signal sync2, wherein the frequency of the frequency signal clk_L is lower than the frequency of the frequency signal clk_H. For example, the control circuit 108 can generate a voltage control signal En_cnt based on the synchronization signal sync2 and the frequency signal clk_H and send it to the digital circuit 102 (the voltage control signal En_cnt is synchronized with the feedback signal d_in) to control the digital circuit 102 to stop counting the frequency signal clk_L, thereby correcting the output voltage Vo.

[0026] Furthermore, the control circuit 108 can be as follows: Figure 1 As shown, the circuit includes an AND gate AND1 and multiple flip-flops F1 to FN connected in series. The data input of flip-flop F1 is coupled to the synchronization circuit 106, and the data output of flip-flop F1 is coupled to the next stage flip-flop F2, and so on, with the data output of the (N-1)th stage flip-flop FN-1 coupled to the data input of the Nth stage flip-flop FN. The outputs of each flip-flop F1 to FN are coupled to the input of the AND gate AND1, and the frequency input of each flip-flop F1 to FN receives the frequency signal clk_H. The flip-flops F1 to FN sequentially transmit the synchronization signal sync2 in response to the frequency signal clk_H. The input of the AND gate AND1 is coupled to the outputs of each flip-flop F1 to FN and the output of the synchronization circuit 106, and the output of the AND gate AND1 is coupled to the digital circuit 102.

[0027] By coupling the output of the synchronization circuit 106 and the outputs of the flip-flops F1 to FN to the input of the AND gate AND1, the control circuit 108 ensures that the digital circuit 102 stops counting the frequency signal clk_L only when the feedback signal d_in provided by the analog circuit 104 is jitter-free, that is, when the sampling signals db1 to dbN output by the flip-flops F1 to FN and the synchronization signal sync2 are all at the same logic level, thus avoiding malfunctions. Furthermore, since the frequency of the frequency signal clk_L is set lower than the frequency of the frequency signal clk_H, the control circuit 108 can react in real time to changes in the feedback signal d_in output by the analog circuit 104 to control the output voltage of the digital circuit 102. This allows the control circuit to correct for signal delays that may be caused by the synchronization circuit while avoiding metastability, thus meeting the real-time control requirements when synchronizing the analog signal to the frequency domain of the digital signal.

[0028] Furthermore, the number N of flip-flops in the control circuit 108 can satisfy the following formula to ensure that the control circuit 108 can avoid malfunctions and meet the real-time control requirements when the analog signal is synchronized to the frequency domain of the digital signal.

[0029]

[0030] Where FC1 is the frequency of frequency signal clk_L and FC2 is the frequency of frequency signal clk_H.

[0031] Figure 2 This is a schematic diagram of a digital signal output device according to another embodiment of the present invention. In this embodiment, the digital signal output device may further include a frequency adjustment circuit 202, an AND gate AND2, and an inverter INV1. The digital circuit 102 may include a counter 204 and a voltage regulator 206. The synchronization circuit 106 may include cascaded synchronous flip-flops FS1 and FS2. The frequency adjustment circuit 202 is coupled to the counter 204 and the system SYS1, which may be, for example, a central processing unit, but is not limited thereto. The input of the AND gate AND2 is coupled to the system SYS1 and the output of the inverter INV1, the output of the AND gate AND2 is coupled to the counter 204, and the input of the inverter INV1 is coupled to the output of the AND gate AND1. Furthermore, in this embodiment, the analog circuit 104 is implemented using a comparator 208.

[0032] In this embodiment, the frequency signal clk is used as the frequency signal clk_H. The frequency signal clk can be frequency-adjusted by the frequency adjustment circuit 202. The frequency adjustment circuit 202 can be implemented, for example, as a frequency divider circuit, to divide the frequency signal clk by a frequency, and the resulting frequency signal clk / div is used as the frequency signal clk_L. In some embodiments, the frequency adjustment circuit 202 can also be implemented as a frequency multiplier circuit, and is not limited to this embodiment. The counter can count the frequency signal clk and output the adjustment signal TRIM to the voltage regulator 206 based on the count value obtained from counting the frequency signal clk, so as to control the voltage regulator to adjust the output voltage Vo. The comparator 208 can compare the output voltage Vo with the reference voltage V_Bias and generate a feedback signal d_in to the data input terminal of the synchronous flip-flop FS1. The synchronous flip-flops FS1 and FS2 can respond to the frequency signal clk by transmitting the feedback signal d_in, and generate synchronization signals sync1 and sync2 at the output terminals of the synchronous flip-flops FS1 and FS2, respectively.

[0033] like Figure 3 As shown in the signal waveform diagram, the feedback signal d_in is sampled by the synchronous flip-flops FS1 and FS2 of the synchronous circuit 106. The metastability of the synchronous signal sync1 output by the synchronous flip-flop FS1 (as shown by the dashed circle) can be eliminated after being sampled again by the synchronous flip-flop FS2. In addition, the signal delay caused by the transmission of the synchronous signal sync2 by the flip-flops F1 to FN makes the sampled signal dbN output by the flip-flop FN later than the sampled signal db1 by three signal cycles (assuming that in Figure 3 In this embodiment, N equals 3. When the feedback signal d_in is not jittered, the output signal dbout of AND gate AND1 can be converted to a high logic level based on the sampled signals db1 to dbN and the synchronization signal sync2. However, if the feedback signal d_in jitters, the time when the output signal dbout of AND gate AND1 is converted to a high logic level will be further delayed until the sampled signals db1 to dbN and the synchronization signal sync2 are simultaneously at a high logic level. This avoids malfunctions of the digital signal output device caused by the output signal dbout of AND gate AND1.

[0034] The output signal dbout of AND gate AND1 can be converted into a voltage control signal En_cnt via inverter INV1 and AND gate AND2 to control the counting operation of counter 204. For example, in the case where the digital signal output device is used in a voltage generator, when the feedback signal d_in output by comparator 208 changes (e.g., from high logic level to low logic level or from low logic level to high logic level), the voltage control signal En_cnt is generated through synchronization circuit 106, control circuit 108, inverter INV1 and AND gate AND2 to control counter 204 to stop counting, thereby correcting the output voltage Vo of regulator 206.

[0035] In some embodiments, the aforementioned reference voltage V_Bias can be the internal reference voltage of the chip using the digital signal output device. That is, system SYS1 only needs to provide the frequency signal clk to the digital signal output device to correct the output voltage Vo, so that the output voltage Vo meets the requirements of the load, without needing to provide a reference voltage from an external device, and reducing the additional circuit area reserved for correcting voltage deviations. Furthermore, in other embodiments, the frequency signal clk and the reference voltage V_Bias can also be provided externally. For example, when performing mass production testing of digital signal output devices, the externally provided frequency signal clk and reference voltage V_Bias can be provided simultaneously to multiple digital signal output devices to correct the output voltage Vo, significantly improving detection efficiency, unlike conventional techniques where the output voltage must be detected simultaneously during output voltage correction, and only one chip can be detected at a time.

[0036] exist Figure 3 In this embodiment, the voltage control signal En_cnt can also be generated based on the enable signal En provided by system SYS1. That is, the enable signal En provided by system SYS1 determines whether the AND gate AND2 is allowed to output the voltage control signal En_cnt. For example, when the enable signal En provided by system SYS1 is at a low logic level, regardless of whether the output signal dbout of the AND gate AND1 is at a high logic level, the voltage control signal En_cnt cannot be switched to a high logic level to control the counting action of counter 204 (e.g., to stop or start counting).

[0037] It is worth noting that in some embodiments, the digital signal output device may selectively exclude AND gate AND2 and inverter INV1, or exclude either AND gate AND2 or inverter INV1. When the digital signal output device excludes AND gate AND2, the output of inverter INV1 is coupled to counter 204, and the voltage control signal En_cnt is provided by inverter INV1. When inverter INV1 is excluded, the input of AND gate AND2 is coupled to the output of AND gate AND1 and system SYS1, and AND gate AND2 instead generates the voltage control signal En_cnt based on the enable signal En and the output signal dbout of AND gate AND1.

[0038] Figure 4 This is a schematic diagram of a digital signal output device according to another embodiment of the present invention. In this embodiment, the digital signal output device further includes switching circuits 402 and 404 and a latching circuit 406, wherein the switching circuit 402 is coupled to the output terminal of the voltage regulator 206, the output terminal of the signal generation circuit SG1 and the input terminal of the comparator 208, and the switching circuit 404 is coupled to the output terminal of the comparator 208, the latching circuit 406 and the data input terminal of the synchronous trigger FS1.

[0039] Switching circuit 402 can be controlled by switching signal SW1 to connect the input terminal of comparator 208 to the output terminal of voltage regulator 206 or the output terminal of signal generation circuit SG1. Signal generation circuit SG1 can be, for example, another application circuit within the chip of the digital signal output device. Switching operation of switching circuit 402 allows signal generation circuit SG1 to share comparator 208 of the digital signal output device, thereby reducing chip manufacturing costs. Furthermore, switching circuit 404 can be controlled by switching signal SW2 to connect the output terminal of comparator 208 to the data input terminal of synchronous trigger FS1 or the input terminal of latching circuit 406. For example, when the digital signal output device needs to correct the output voltage Vo, switching circuit 402 can be controlled by switching signal SW1 to connect the input terminal of comparator 208 to the output terminal of voltage regulator 206, while switching circuit 404 can be controlled by switching signal SW2 to connect the output terminal of comparator 208 to the data input terminal of synchronous trigger FS1. Since the latching circuit 406 can latch the output result of the comparator 208 when it is connected to the signal generation circuit SG1, even if the input terminal of the comparator 208 is switched to the output terminal of the voltage regulator 206 and the output terminal of the comparator 208 is connected to the data input terminal of the synchronous trigger FS1, it will not affect the operation of other circuits that use the output signal of the comparator 208 when it is connected to the signal generation circuit SG1.

[0040] Although various embodiments have been described with reference to the above figures, other embodiments are still possible. For example, see Figure 5The digital circuit 102 of the digital signal output device of the present invention can also be a digital proportional-integral-differential (PID) calculation unit 502. The digital PID calculation unit 502 is coupled to a digital-to-analog converter 504 and a control circuit 108. The digital-to-analog converter 504 is coupled to an analog circuit 104. A synchronization circuit 106 is coupled to an analog circuit 104 and a control circuit 108. The analog circuit 104 is implemented using a comparator 208. The digital PID calculation unit 502, the digital-to-analog converter 504, the comparator 208, the synchronization circuit 106, and the control circuit 108 form a closed-loop circuit. The digital PID calculation unit 502 can receive an external frequency signal clk_L and generate a control signal through P control (proportional control), PI control (proportional-integral control), PD control (proportional-derivative control), or PID control (proportional-integral-derivative control). The control signal is converted into an analog signal of the output voltage Vo by the digital-to-analog converter 504. Comparator 208 compares the output voltage Vo with the reference voltage V_Bias, generating a feedback signal d_in to the data input terminal of synchronization circuit 106. Synchronization circuit 106 samples the feedback signal d_in based on the frequency signal clk_H to generate a synchronization signal sync2. Control circuit 108 then generates a voltage control signal En_cnt based on the synchronization signal sync2 and the frequency signal clk_H, which is sent to digital PID calculation unit 502. Digital PID calculation unit 502 corrects the counting frequency signal clk_L based on the voltage control signal En_cnt, thereby correcting the output voltage Vo. In this example, digital PID calculation unit 502 is used to adjust the power supply output voltage, but it can also receive digital voltage or current values ​​for use in other digital feedback control systems, which will not be elaborated here.

[0041] In summary, embodiments of the present invention ensure that the frequency of the frequency signal upon which the digital circuit generates the output voltage is lower than the frequency of the frequency signals input to the synchronization circuit and the control circuit. This allows the control circuit to respond in real-time to changes in the feedback signal output from the analog circuit, controlling the output voltage of the digital circuit. This avoids metastability while meeting the real-time control requirements when synchronizing the analog signal to the frequency domain of the digital signal. Furthermore, by coupling the outputs of multiple cascaded flip-flops in the control circuit to the input of an AND gate, and controlling the output voltage of the digital circuit based on the voltage control signal output by the AND gate, jitter in the feedback signal provided by the analog circuit can be avoided, preventing malfunctions in the digital signal output device caused by jitter. In some embodiments, a latching circuit and two switching circuits can be used to allow the analog circuit to be shared with other circuits, reducing chip manufacturing costs without affecting normal chip operation.

[0042] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the scope of protection of the claims. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A signal synchronization apparatus coupled to a digital circuit that generates an output voltage in response to a first frequency signal and coupled to an analog circuit that generates a feedback signal in response to said output voltage, characterized by, comprising: a synchronization circuit coupled to the analog circuit, for sampling the feedback signal according to a second frequency signal to generate a synchronization signal; and a control circuit coupled to the digital circuit and the synchronization circuit, for generating a voltage control signal according to the second frequency signal and the synchronization signal to control the digital circuit to generate the output voltage, the control circuit comprising: a first AND gate having an output coupled to the digital circuit to output the voltage control signal, the digital circuit generating the output voltage according to the first frequency signal and the voltage control signal outputted by the output of the first AND gate; and a plurality of flip-flops connected in series between an output of the synchronization circuit and an input of the first AND gate to sequentially pass the synchronization signal in response to the second frequency signal, the input of the first AND gate coupled to an output of each of the flip-flops and the output of the synchronization circuit, and the first AND gate generating the voltage control signal according to an output signal of each of the flip-flops and the synchronization signal, wherein a frequency of the first frequency signal is lower than a frequency of the second frequency signal, and the voltage control signal is synchronized with the feedback signal. further comprising:

2. The signal synchronization apparatus according to claim 1, characterized by a frequency adjustment circuit coupled to the digital circuit, for adjusting the frequency of the second frequency signal to generate the first frequency signal. a number of the plurality of flip-flops satisfies the following equation:

3. The signal synchronization apparatus according to claim 1, characterized by where N is the number of the plurality of flip-flops, FC1 is the frequency of the first frequency signal, and FC2 is the frequency of the second frequency signal. the synchronization circuit comprising:

4. The signal synchronization apparatus according to claim 1, characterized by a first synchronization flip-flop; and a second synchronization flip-flop connected in series with the first synchronization flip-flop between the analog circuit and the control circuit, the first and second synchronization flip-flops sequentially passing the feedback signal in response to the second frequency signal to output the synchronization signal at an output of the second synchronization flip-flop. comprising:

5. A digital signal output device, characterized by comprising: a digital circuit, an analog circuit, and the signal synchronization device as claimed in any one of claims 1 to 4, wherein the digital circuit generates the output voltage according to the first frequency signal, and the analog circuit coupled to the digital circuit generates the feedback signal according to the output voltage. the digital circuit comprising:

6. The digital signal output apparatus according to claim 5, wherein a counter coupled to an output of the first AND gate to count the first frequency signal to generate a count value, and to stop counting the first frequency signal in response to the voltage control signal; and a voltage stabilizer coupled to the counter and the analog circuit to generate the output voltage according to the count value. further comprising:

7. The digital signal output apparatus according to claim 6, wherein an inverter having an input and an output coupled to the output of the first AND gate and an input of the counter, respectively, the counter stopping counting the first frequency signal in response to an output signal of the inverter; and a second AND gate having an input coupled to the output of the inverter to receive an enable signal, and an output coupled to the input of the counter, the second AND gate controlling the counter to stop counting the first frequency signal according to the enable signal and the output signal of the inverter. ​ ​ 8. The digital signal output apparatus according to claim 5, wherein The analog circuit is a comparator, input terminals of the comparator are coupled to output terminals of the digital circuit and a reference voltage, an output terminal of the comparator is coupled to the synchronization circuit, the comparator compares the output voltage with the reference voltage to generate the feedback signal.

9. The digital signal output apparatus according to claim 8, wherein Further comprising: a first switch circuit, coupled to the output terminals of the digital circuit, the input terminals of the comparator and an output terminal of a signal generating circuit, controlled by a first switching signal to connect the input terminals of the comparator to the output terminals of the digital circuit or the output terminal of the signal generating circuit.

10. The digital signal output apparatus according to claim 8, wherein Further comprising: a latch circuit, latching the output signal of the comparator; and a second switch circuit, coupled to the output terminal of the analog circuit, the synchronization circuit and the latch circuit, controlled by a second switching signal to connect the output terminal of the comparator to the input terminal of the synchronization circuit or the input terminal of the latch circuit. ​

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