Metastable state elimination comparator

Abstract

The invention relates to a metastable state elimination comparator, which is characterized in that a dynamic comparison circuit and a metastable state elimination circuit which also work in a clock control signal CLK are designed, the dynamic comparison circuit has the advantages of short transmission time, high comparison speed and low power consumption, and the metastable state elimination circuit detects whether the dynamic comparison circuit is in a metastable state or not according to the change of the clock control signal CLK; the metastable state of the dynamic comparison circuit is efficiently eliminated by changing potential through charging and discharging of a capacitor, the problem that the dynamic comparison circuit cannot work normally due to loss of an asynchronous clock is solved, a current source with adjustable current is applied to the metastable state elimination circuit, and the charging speed of the capacitor is controlled to eliminate the metastable state of the dynamic comparison circuit. The recovery speed of the dynamic comparison circuit exiting the metastable state is controlled, and the accuracy and efficiency of the dynamic comparison circuit in actual work are improved.

Description

Technical Field

[0001] The invention relates to a metastable state elimination comparator, belonging to the technical field of semiconductor integration. Background Art

[0002] Benefiting from the continuous development of technology, the performance of SAR ADC has been greatly improved, and it has received more and more attention. It has been widely used in wireless communication, wired communication (SERDES) and other fields. Compared with the traditional PIPELINE structure, since SAR ADC does not need to use traditional op amps and other modules, on the one hand, it has lower power consumption, and on the other hand, it can make full use of the advantages of shrinking process nodes to improve the sampling rate. Among them, the dynamic comparator is the basis of digital-to-analog conversion in SAR ADC, but the metastable problem of the dynamic comparator will cause some SARs to have functional abnormalities.

[0003] The paper “J. Zhang, X. Ren, S. Liu, C. -H. Chan and Z. Zhu, An 11-bit 100-MS / s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 7, pp. 1174-1178” proposes a dynamic comparator that uses partial multiplexing for PVT stabilization. The comparator uses an operational amplifier with a gain-boost structure to achieve high gain and track PVT. Although the structure has good sampling characteristics when the PVT changes dynamically, it does not eliminate the metastable state caused by the comparator itself, which causes the comparator to fail and fail to compare the results. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a metastable elimination comparator, which can timely detect the metastable state of the comparator and eliminate it, thereby solving the problem that the comparator cannot work normally due to the loss of asynchronous clock.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a metastable elimination comparator, including a dynamic comparison circuit and a metastable elimination circuit, wherein the dynamic comparison circuit and the metastable elimination circuit are connected to work under the clock control signal CLK, the dynamic comparison circuit switches between the reset stage and the comparison stage based on the clock control signal CLK, and compares the input signal VIP with the input signal VIN through positive feedback in the comparison stage to obtain the output signal VOP and the output signal VON;

[0006] The metastable elimination circuit calculates a clock control signal CLK according to the output signal VOP and the output signal VON, and determines whether the dynamic comparison circuit is in a metastable state according to the clock control signal CLK. If the dynamic comparison circuit is in a metastable state, the metastable elimination circuit controls the dynamic comparison circuit to exit the metastable state.

[0007] As a preferred technical solution of the present invention: the dynamic comparison circuit includes NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, and PMOS tube M10; wherein the gate of NMOS tube M0 is used to access the clock control signal CLK, the source of NMOS tube M0 is grounded GND, and the drain of NMOS tube M0, the source of NMOS tube M1, and the source of NMOS tube M2 are connected The gate of the NMOS tube M1 constitutes one of the input terminals of the dynamic comparison circuit, which is used to receive the input signal VIP. The gate of the NMOS tube M2 constitutes the other input terminal of the dynamic comparison circuit, which is used to receive the input signal VIN. The gate of the NMOS tube M2 is used to receive the input signal VIN. The source of the NMOS tube M3, the drain of the NMOS tube M1, and the drain of the PMOS tube M9 are connected, and the connection position constitutes the X node of the dynamic comparison circuit. The source of the NMOS tube M4, the drain of the NMOS tube M2, and the drain of the PMOS tube M10 are connected, and the connection position constitutes the X node of the dynamic comparison circuit. The connection position constitutes the Y node of the dynamic comparison circuit, the gate of the NMOS tube M3, the gate of the PMOS tube M5, the drain of the PMOS tube M6, the drain of the NMOS tube M4, and the drain of the PMOS tube M8 are connected, and the connection position constitutes one of the output ends of the dynamic comparison circuit, which is used to output the output signal VOP, the gate of the NMOS tube M4, the gate of the PMOS tube M6, the drain of the NMOS tube M3, the drain of the PMOS tube M5, and the drain of the PMOS tube M7 are connected, and the connection position constitutes another output end of the dynamic comparison circuit, which is used to output the output signal VOP. The output signal VON is output; the gate of the PMOS tube M8 is connected to the gate of the PMOS tube M10, and the connection position is used to access the clock control signal CLK; the gate of the PMOS tube M7 is connected to the gate of the PMOS tube M9, and the connection position is used to access the clock control signal CLK; the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M8, the source of the PMOS tube M9, and the source of the PMOS tube M10 are connected, and the connection position is used to access the power supply voltage VDD.

[0008] As a preferred technical solution of the present invention: the metastable elimination circuit includes a current source I1, a capacitor C1, a switch Sc, a first inverter INV0, a ​​second inverter INV1, an AND gate A0, an NMOS tube M11, and an NMOS tube M12, wherein one end of the current source I1 is connected to the power supply voltage VDD, the other end of the current source I1, one end of the capacitor C1, the input end of the first inverter INV0, and one end of the switch Sc are connected, the output end of the first inverter INV0 is connected to the input end of the second inverter INV1, the output end of the second inverter INV1 is connected to the gate of the NMOS tube M11, the drain of the NMOS tube M11 is connected to the X node of the dynamic comparison circuit, and the NMOS tube The drain of M12 is connected to the Y node of the dynamic comparison circuit, and the other end of the capacitor C1, the other end of the switch Sc, the source of the NMOS tube M11, the source of the NMOS tube M12, and the gate of the NMOS tube M12 are connected, and the connection position is grounded GND; the switch Sc is controlled by the clock control signal CLK to realize on-off, and then controls the start and stop of the current source I1 charging the capacitor C1; the NMOS tube M12 constitutes the DUMMY tube of the NMOS tube M11; the two input ends of the AND gate A0 are used to access the output signal VOP and the output signal VON output by the dynamic comparison circuit, and the AND gate A0 performs logic processing to output the clock control signal CLK to provide it to the dynamic comparison circuit and the metastable elimination circuit.

[0009] As a preferred technical solution of the present invention: the current source I1 is a current source with adjustable current size.

[0010] The metastable elimination comparator of the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0011] The present invention designs a metastable elimination comparator, and designs a dynamic comparison circuit and a metastable elimination circuit that also work on a clock control signal CLK. The dynamic comparison circuit has the advantages of short transmission time, fast comparison speed, and low power consumption. The metastable elimination circuit detects whether the dynamic comparison circuit is in a metastable state by the change of the clock control signal CLK, and efficiently eliminates the metastable state of the dynamic comparison circuit by changing the potential by charging and discharging a capacitor, thereby solving the problem that the dynamic comparison circuit cannot work normally due to the loss of an asynchronous clock. In addition, a current source with adjustable current size is applied in the metastable elimination circuit, and the recovery speed of the dynamic comparison circuit exiting the metastable state is controlled by controlling the charging speed of the capacitor, thereby improving the accuracy and efficiency of the dynamic comparison circuit in actual operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a metastable elimination comparator designed for the present invention;

[0013] Figure 2 The working timing diagram of the metastable elimination comparator designed for the present invention is shown. DETAILED DESCRIPTION

[0014] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0015] A metastable elimination comparator designed by the present invention comprises a dynamic comparison circuit and a metastable elimination circuit in practical application, wherein the dynamic comparison circuit and the metastable elimination circuit are connected to work under a clock control signal CLK, the dynamic comparison circuit switches between a reset phase and a comparison phase based on the clock control signal CLK, and compares an input signal VIP with an input signal VIN through positive feedback in the comparison phase to obtain an output signal VOP and an output signal VON.

[0016] The metastable elimination circuit calculates a clock control signal CLK according to the output signal VOP and the output signal VON, and determines whether the dynamic comparison circuit is in a metastable state according to the clock control signal CLK. If the dynamic comparison circuit is in a metastable state, the metastable elimination circuit controls the dynamic comparison circuit to exit the metastable state.

[0017] In practical applications, specific structural designs are carried out for dynamic comparison circuits and metastable elimination circuits, such as Figure 1As shown, the dynamic comparison circuit specifically includes NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, and PMOS tube M10; wherein, the gate of NMOS tube M0 is used to access the clock control signal CLK, the source of NMOS tube M0 is grounded GND, the drain of NMOS tube M0, the source of NMOS tube M1, and the source of NMOS tube M2 are connected, and NMOS tube M1 is connected to the ground. The gate of the NMOS tube M2 constitutes one of the input terminals of the dynamic comparison circuit, which is used to receive the input signal VIP. The gate of the NMOS tube M2 constitutes the other input terminal of the dynamic comparison circuit, which is used to receive the input signal VIN. The gate of the NMOS tube M2 is used to receive the input signal VIN. The source of the NMOS tube M3, the drain of the NMOS tube M1, and the drain of the PMOS tube M9 are connected, and the connection position constitutes the X node of the dynamic comparison circuit. The source of the NMOS tube M4, the drain of the NMOS tube M2, and the drain of the PMOS tube M10 are connected, and the connection position constitutes The gate of the NMOS tube M3, the gate of the PMOS tube M5, the drain of the PMOS tube M6, the drain of the NMOS tube M4, and the drain of the PMOS tube M8 are connected, and the connection position constitutes one of the output ends of the dynamic comparison circuit for outputting the output signal VOP. The gate of the NMOS tube M4, the gate of the PMOS tube M6, the drain of the NMOS tube M3, the drain of the PMOS tube M5, and the drain of the PMOS tube M7 are connected, and the connection position constitutes another output end of the dynamic comparison circuit for outputting the output signal VOP. The output signal VON is output; the gate of the PMOS tube M8 is connected to the gate of the PMOS tube M10, and the connection position is used to access the clock control signal CLK; the gate of the PMOS tube M7 is connected to the gate of the PMOS tube M9, and the connection position is used to access the clock control signal CLK; the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M8, the source of the PMOS tube M9, and the source of the PMOS tube M10 are connected, and the connection position is used to access the power supply voltage VDD.

[0018] like Figure 1As shown, the designed metastable elimination circuit specifically includes a current source I1, a capacitor C1, a switch Sc, a first inverter INV0, a ​​second inverter INV1, an AND gate A0, an NMOS tube M11, and an NMOS tube M12, wherein one end of the current source I1 is connected to the power supply voltage VDD, the other end of the current source I1, one end of the capacitor C1, the input end of the first inverter INV0, and one end of the switch Sc are connected, the output end of the first inverter INV0 is connected to the input end of the second inverter INV1, the output end of the second inverter INV1 is connected to the gate of the NMOS tube M11, the drain of the NMOS tube M11 is connected to the X node of the dynamic comparison circuit, the drain of the NMOS tube M12 is connected to the Y node of the dynamic comparison circuit, and the other end of the capacitor C1 is connected to the gate of the NMOS tube M11. The switch Sc is connected to the source of the NMOS tube M11, the source of the NMOS tube M12, and the gate of the NMOS tube M12, and the connection position is grounded GND; the switch Sc is controlled by the clock control signal CLK to realize on-off, thereby controlling the start and stop of the current source I1 charging the capacitor C1, and the NMOS tube M12 constitutes the DUMMY tube of the NMOS tube M11. In the application, the NMOS tube M12 is matched with the NMOS tube M11 to ensure that the capacitance at the Y node and the X node is the same; the two input ends of the AND gate A0 are used to access the output signal VOP and the output signal VON output by the dynamic comparison circuit, and the AND gate A0 performs logic processing to output the clock control signal CLK to provide it to the dynamic comparison circuit and the metastable elimination circuit.

[0019] In practical applications of the above design structure, the current source I1 is a current source with adjustable current size, such as Figure 1 and Figure 2As shown, when the dynamic comparison circuit works in a normal state, along with the flipping of the high and low levels of the clock control signal CLK, when the clock control signal CLK is at a low level, the dynamic comparison circuit works in a reset stage, and when the clock control signal CLK is at a high level, the dynamic comparison circuit works in a comparison stage. In the comparison stage, that is, when the difference between the input signal VIP connected to the dynamic comparison circuit and the input signal VIN is greater than a preset threshold value, such as when the input signal VIP is greater than the input signal VIN, the current on the NMOS tube M1 is greater than the current on the NMOS tube M2. When the parasitic capacitances of the X node and the Y node in the dynamic comparison circuit are the same, the discharge speed of the parasitic capacitance on the X node is faster than that of the parasitic capacitance on the Y node, that is, the voltage drop speed of the X node is faster than that of the Y node. The falling speed is faster, so the NMOS tube M3 is turned on before the NMOS tube M4, causing the parasitic capacitance at the output position of the output signal VON in the dynamic comparison circuit to start discharging before the parasitic capacitance at the output position of the output signal VOP. Therefore, the output signal VON falls faster than the output signal VOP, and the output signal VON will reach VDD-Vthp first, indicating the threshold voltage of the PMOS tube. The PMOS tube M6 is turned on before the PMOS tube M5. At this time, the PMOS tube M6 quickly pulls up the output signal VOP, thereby making the current of the NMOS tube M3 larger. The output signal VON falls faster through the positive feedback effect, and is finally pulled to the zero level, and the final latch is completed, then the output signal VOP=VDD, and the output signal VON=GND.

[0020] When the dynamic comparison circuit normally switches between the reset stage and the comparison stage, that is, the clock control signal CLK works periodically, the switch Sc is turned on when the clock control signal CLK works periodically, that is, when the clock control signal CLK is periodically flipped, the switch Sc is turned on, and too much charge will not accumulate on the capacitor C1. The input voltage of the first inverter INV0 is 0, the output voltage of the second inverter INV1 is 0, the gate of the NMOS tube M11 is 0, and the NMOS tube M11 is not turned on.

[0021] like Figure 2As shown, when the difference between the input signal VIP connected to the dynamic comparison circuit and the input signal VIN is less than or equal to the preset threshold, that is, when the input signal VIP is almost equal to the input signal VIN, the dynamic comparator will enter a metastable state. At this time, if the metastable elimination circuit is not applied in the circuit structure, the dynamic comparator will always be in a metastable state, affecting subsequent work; if the metastable elimination circuit is added according to the design scheme of this patent, the output signal VOP and the output signal VON of the dynamic comparator in the metastable state are maintained at an intermediate value, resulting in the clock control signal CLK being unable to flip between a high level and a low level within half a cycle, that is, the clock control signal CLK continuously outputs a high level within half a cycle, and the metastable elimination circuit determines that the dynamic comparator has entered a metastable state at this time. Since the switch Sc in the metastable elimination circuit is controlled by the clock control signal CLK to realize on and off, specifically, the high level control switch Sc that the clock control signal CLK continuously outputs within half a cycle is disconnected, then the current source I1 supplies current to the capacitor C1. The dynamic comparison circuit enters a recovery state. In practical applications, since the current source I1 selects a current source with an adjustable current size, the current size of the current source I1 can be adjusted during the charging process of the capacitor C1, thereby increasing the charging speed of the capacitor C1 and accelerating the recovery process of the dynamic comparator. When the potential of the upper plate of the capacitor C1 reaches VDD, the first inverter INV0 and the second inverter INV1 perform two reverse operations to output the voltage VDD, and the voltage of the gate of the NMOS tube M11 becomes higher and thus turned on. The current in the NMOS tube M11 becomes larger, and the voltage of the X node in the dynamic comparison circuit is quickly pulled down. The output signal VON is forced to be pulled low, and the output signal VOP is forced to be pulled high. The clock control signal CLK is flipped again, disrupting the metastable state of the dynamic comparator, that is, the dynamic comparator exits the metastable state, eliminating the influence of the metastable state on the dynamic comparator, thereby solving the problem that the SAR ADC cannot work properly due to the asynchronous clock loss caused by the dynamic comparator being unable to make a judgment after entering the metastable state.

[0022] The advantage of the design of the present invention is that the voltage characteristics of the output signal VON and the output signal VOP after the dynamic comparator enters the metastable state are used to perform calculation operations to control the charging and discharging of the capacitor C1, and further control the potential of the dynamic comparator X node. At the same time, the charging speed of the capacitor C1 can be controlled by changing the size of the current source I1, thereby controlling the time T1 for metastable state recovery.

[0023] The metastable elimination comparator designed by the present invention is a dynamic comparison circuit and a metastable elimination circuit that also work on a clock control signal CLK. The dynamic comparison circuit has the advantages of short transmission time, fast comparison speed and low power consumption. The metastable elimination circuit detects whether the dynamic comparison circuit is in a metastable state by the change of the clock control signal CLK, and efficiently eliminates the metastable state of the dynamic comparison circuit by changing the potential by charging and discharging the capacitor, thereby solving the problem that the dynamic comparison circuit cannot work normally due to the loss of the asynchronous clock. In addition, a current source with adjustable current size is applied in the metastable elimination circuit. By controlling the charging speed of the capacitor, the recovery speed of the dynamic comparison circuit exiting the metastable state is controlled, thereby improving the accuracy and efficiency of the dynamic comparison circuit in actual operation.

[0024] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A metastable elimination comparator, characterized in that: It includes a dynamic comparison circuit and a metastable elimination circuit, wherein the dynamic comparison circuit and the metastable elimination circuit are connected to work under the clock control signal CLK, the dynamic comparison circuit switches between the reset stage and the comparison stage based on the clock control signal CLK, and compares the input signal VIP with the input signal VIN through positive feedback in the comparison stage to obtain the output signal VOP and the output signal VON; The metastable elimination circuit calculates a clock control signal CLK according to the output signal VOP and the output signal VON, and determines whether the dynamic comparison circuit is in a metastable state according to the clock control signal CLK. If the dynamic comparison circuit is in a metastable state, the metastable elimination circuit controls the dynamic comparison circuit to exit the metastable state.

2. A metastable elimination comparator according to claim 1, characterized in that: The dynamic comparison circuit includes NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, and PMOS tube M10; wherein the gate of NMOS tube M0 is used to access the clock control signal CLK, the source of NMOS tube M0 is grounded GND, the drain of NMOS tube M0, the source of NMOS tube M1, and the source of NMOS tube M2 are connected, and the gate of NMOS tube M1 is configured to The gate of the NMOS tube M2 constitutes one of the input terminals of the dynamic comparison circuit, which is used to receive the input signal VIP. The gate of the NMOS tube M2 constitutes the other input terminal of the dynamic comparison circuit, which is used to receive the input signal VIN. The gate of the NMOS tube M2 is used to receive the input signal VIN. The source of the NMOS tube M3, the drain of the NMOS tube M1, and the drain of the PMOS tube M9 are connected, and the connection position constitutes the X node of the dynamic comparison circuit. The source of the NMOS tube M4, the drain of the NMOS tube M2, and the drain of the PMOS tube M10 are connected, and the connection position constitutes the dynamic comparison circuit. The Y node of the comparison circuit, the gate of the NMOS tube M3, the gate of the PMOS tube M5, the drain of the PMOS tube M6, the drain of the NMOS tube M4, and the drain of the PMOS tube M8 are connected, and the connection position constitutes one of the output ends of the dynamic comparison circuit, which is used to output the output signal VOP. The gate of the NMOS tube M4, the gate of the PMOS tube M6, the drain of the NMOS tube M3, the drain of the PMOS tube M5, and the drain of the PMOS tube M7 are connected, and the connection position constitutes another output end of the dynamic comparison circuit, which is used to output the output signal VOP. The gate of the PMOS tube M8 is connected to the gate of the PMOS tube M10, and the connection position is used to access the clock control signal CLK. The gate of the PMOS tube M7 is connected to the gate of the PMOS tube M9, and the connection position is used to access the clock control signal CLK. The source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M8, the source of the PMOS tube M9, and the source of the PMOS tube M10 are connected, and the connection position is used to access the power supply voltage VDD.

3. A metastable elimination comparator according to claim 2, characterized in that: The metastable elimination circuit includes a current source I1, a capacitor C1, a switch Sc, a first inverter INV0, a ​​second inverter INV1, an AND gate A0, an NMOS tube M11, and an NMOS tube M12, wherein one end of the current source I1 is connected to a power supply voltage VDD, the other end of the current source I1, one end of the capacitor C1, an input end of the first inverter INV0, and one end of the switch Sc are connected, the output end of the first inverter INV0 is connected to the input end of the second inverter INV1, the output end of the second inverter INV1 is connected to the gate of the NMOS tube M11, the drain of the NMOS tube M11 is connected to the X node of the dynamic comparison circuit, and the drain of the NMOS tube M12 is connected to the The Y node of the dynamic comparison circuit, the other end of the capacitor C1, the other end of the switch Sc, the source of the NMOS tube M11, the source of the NMOS tube M12, and the gate of the NMOS tube M12 are connected, and the connection position is grounded GND; the switch Sc is controlled by the clock control signal CLK to realize on-off, and then controls the start and stop of the current source I1 charging the capacitor C1; the NMOS tube M12 constitutes the DUMMY tube of the NMOS tube M11; the two input ends of the AND gate A0 are used to access the output signal VOP and the output signal VON output by the dynamic comparison circuit, and the AND gate A0 performs logic processing to output the clock control signal CLK to provide it to the dynamic comparison circuit and the metastable elimination circuit.

4. A metastable elimination comparator according to claim 3, characterized in that: The current source I1 is a current source with adjustable current magnitude.

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