Modulation circuit and pulse width modulation method

Abstract

According to the modulation circuit and the pulse width modulation method disclosed by the embodiment of the invention, the number of delay units in a clock period can be dynamically detected in real time, and the design precision is improved; the DLL module is not needed for implementation, the chip area occupied by DLL design is saved, it is avoided that the DLL module needs to conduct routing on the clock cluster, and errors caused by routing are avoided.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and more specifically, to a modulation circuit and a pulse width modulation method. Background Art

[0002] In digital chips, the resolution of PWM is usually determined by the clock. Therefore, in order to improve the resolution of PWM, the frequency of the clock needs to be increased. In chip design, high-frequency clocks have very stringent requirements on manufacturing processes and layout and wiring, which will undoubtedly increase the difficulty and cost of chip design. In addition to increasing the clock frequency, using a delay-locked loop (DLL) is also a common method. Although DLL can achieve high resolution of PWM, it also has certain disadvantages: although DLL can output a clock with a fixed delay, its design area will also increase in chip design, increasing the cost of chip design; at the same time, when the clock cluster output by DLL is input to the PWM module, there may be errors in the high resolution of PWM due to inconsistent routing, so the routing requirements for the clock cluster are relatively high. Summary of the invention

[0003] In view of this, the present invention proposes a modulation circuit and a pulse width modulation method to solve the technical problems in the prior art that the DLL has high requirements on wiring and high cost.

[0004] In the first aspect, an embodiment of the present invention provides a modulation circuit, comprising: a delay module, comprising a plurality of delay units connected in series in sequence, configured to receive a first pulse width modulation signal at an input end and generate a second pulse width modulation signal at an output end; a delay unit detection module, configured to detect the number of delay units included in a clock cycle; a calibration module, generating a selection signal based on a signal representing desired resolution information and the number of detected delay units; and the delay module selecting the output of the corresponding delay unit as an output based on the selection signal, thereby delaying the rising edge or falling edge of the first pulse width modulation signal to output the second pulse width modulation signal.

[0005] Preferably, the modulation circuit further comprises a pulse width modulation signal generating circuit configured to receive the clock signal and generate the first pulse width modulation signal, wherein a resolution of the first pulse width modulation signal is a period of the clock signal.

[0006] Preferably, the number of delay units included in the delay module is determined according to the number of theoretical delay times of the delay units included in one clock cycle.

[0007] Preferably, the calibration module generates the selection signal according to the ratio of the first numerical value to the second numerical value and according to the product of the ratio and a third numerical value, wherein the first numerical value represents the number of delay units detected within a clock cycle, the second numerical value represents the number of time units included in a clock cycle, the third numerical value is the signal representing the expected resolution information, and the time unit is the theoretical delay time of the delay unit.

[0008] Preferably, the delay unit detection module is configured to receive a delay detection signal and delay signals generated by each delay unit, and generate a first value representing the number of delay units detected within a clock cycle according to each delay signal during the effective level of the delay detection signal.

[0009] Preferably, the delay unit detection module includes holding units with the same number as the delay units, each of which receives the output of a corresponding delay unit, and when a transition edge of the delay unit output signal is detected during the effective level period of the delay detection signal, the step level after the transition edge is maintained.

[0010] Preferably, the delay unit detection module further includes a counting unit for counting the number of the step levels included in the effective level period of the delay detection signal to obtain the first value, wherein the effective level of the delay detection signal is one clock cycle.

[0011] Preferably, each holding unit is a D flip-flop, the data port of each holding unit receives the output of a corresponding delay unit, the clock input port of each holding unit receives the delay detection signal, and each holding unit outputs to the counting unit.

[0012] Preferably, the modulation circuit further includes a first synchronization module for synchronizing the first pulse width modulation signal with the clock signal.

[0013] Preferably, the modulation circuit also includes a second synchronization module for synchronizing the delay detection signal and the clock signal, wherein the synchronized delay detection signal includes a valid level of one clock cycle, and the synchronized delay detection signal lags behind the synchronized first pulse width modulation signal by one clock cycle.

[0014] Preferably, the delay unit detection module calibrates the number of the delay units included in one clock cycle once at every preset time interval.

[0015] In a second aspect, an embodiment of the present invention further provides a pulse width modulation method, comprising the following steps: inputting a first pulse width modulation signal into a delay module, wherein the delay module comprises a plurality of delay units connected in series in sequence; detecting the number of delay units included in a clock cycle; generating a selection signal based on an input signal representing desired resolution information and the first numerical value; and selecting an output of a corresponding delay unit for output based on the selection signal, thereby delaying a rising edge or a falling edge of the first pulse width modulation signal to output a second pulse width modulation signal.

[0016] Preferably, a clock signal is received to generate the first pulse width modulation signal, wherein a resolution of the first pulse width modulation signal is a period of the clock signal.

[0017] Preferably, the selection signal is generated according to the ratio of the first numerical value to the second numerical value and according to the product of the ratio and the third numerical value, wherein the first numerical value represents the number of delay units detected within one clock cycle, the second numerical value represents the number of theoretical delay times of the delay units included in one clock cycle, and the third numerical value is an input signal representing the desired resolution information.

[0018] Preferably, a delay detection signal and delay signals generated by delay units connected in series are received, and the first value is generated according to each delay signal during the effective level period of the delay detection signal.

[0019] Preferably, the first pulse width modulation signal and the delay detection signal are synchronized with a clock signal respectively, wherein after synchronization, the delay detection signal includes a valid level of one clock cycle.

[0020] Preferably, the synchronized delayed detection signal lags behind the synchronized first pulse width modulation signal by one clock cycle.

[0021] Preferably, the number of delay units included in one clock cycle is calibrated once at every preset time interval.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages: the present invention can dynamically detect the number of delay modules included in a clock cycle in real time, thereby improving the design accuracy; and does not require a DLL module for implementation, thereby saving the chip area occupied by the DLL design, and does not require routing of the clock cluster, thereby avoiding errors caused by inconsistent routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1is a structural block diagram of a modulation circuit according to an embodiment of the present invention;

[0025] Figure 2 is a circuit diagram of a modulation circuit according to an embodiment of the present invention;

[0026] Figure 3 is a timing diagram of a delay unit detection module according to an embodiment of the present invention;

[0027] Figure 4 It is a high-resolution waveform diagram of PWM according to an embodiment of the present invention;

[0028] Figure 5 A first waveform diagram of a PWM cycle with high resolution according to an embodiment of the present invention;

[0029] Figure 6 This is a second waveform diagram of the PWM period high resolution according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0031] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0032] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0033] like Figure 1As shown, it is a structural block diagram of the modulation circuit of an embodiment of the present invention, and the modulation circuit includes: a delay module 11, including a plurality of delay units connected in series in sequence, configured to receive a first pulse width modulation signal S_IN at an input end and generate a second pulse width modulation signal S_OUT at an output end; a delay unit detection module 12, configured to detect the number of delay units included in a clock cycle; a calibration module 13, generating a selection signal K2 according to an input signal representing the desired resolution information and the number of detected delay units; the delay module 11 selects the output of the corresponding delay unit for output according to the selection signal K2, thereby delaying the rising edge or falling edge of the first pulse width modulation signal to output the second pulse width modulation signal.

[0034] like Figure 1 As shown, the modulation circuit further includes a pulse width modulation signal generating circuit 14, which is configured to receive the clock signal Clock and generate the first pulse width modulation signal S_IN, wherein the resolution of the first pulse width modulation signal S_IN is the clock period T of the clock signal Clock.

[0035] The number of delay units included in the delay module 11 is determined according to the theoretical delay time of the delay unit. Specifically, the number of delay units included in the delay module 11 is determined according to the theoretical delay time of a clock cycle delay unit. For example, when the clock cycle is T, the theoretical delay time of a delay unit is t delay_1 , then a clock cycle is T including T / t delay_1 The theoretical delay time of a delay unit. However, due to temperature and air pressure, the actual delay time of the delay unit may differ from the theoretical delay time, and the resolution accuracy of the second pulse width modulation signal will be affected. Therefore, in the embodiment of the present invention, a certain margin needs to be reserved for the number of delay units, which should be greater than T / t delay_1 In one embodiment, the number of delay units included in the delay module is 2 k Each delay unit outputs a delay signal, which is also used as an input signal of the delay unit detection module 12. The present invention calibrates the number of delay units through the calibration module, thereby obtaining the number of delay units corresponding to the resolution of the second pulse width modulation signal.

[0036] Specifically, as an example, the delay unit detection module detects the number of delay units included in a clock cycle to generate a first value N representing the number of delay units. The calibration module generates a selection signal K2 according to the ratio of the first value N to the second value M and the product of the ratio and the third value K1. The delay module selects the output of the corresponding delay unit according to the selection signal K2, thereby obtaining a second pulse width modulation signal with a desired resolution. The second value M represents the number of time units included in a clock cycle, the third value K1 is a signal representing the desired resolution information, and the time unit is the theoretical delay time of the delay unit. Therefore, the modulation circuit of the embodiment of the present invention can dynamically adjust the number of delay modules included in a clock cycle T in real time by calibrating the number of delay units in a clock cycle, thereby improving the design accuracy.

[0037] like Figure 2 As shown, it is a circuit diagram of the modulation circuit 1 of an embodiment of the present invention. Among them, the delay module 11 includes n delay units 111 connected in series, which correspond to the output delay signals delay_1~delay_n respectively, and the rising edges of adjacent delay signals are offset by a delay time. The delay unit detection module 12 is configured to receive the delay signals delay_1~delay_n and the delay detection signal LINE_SAM generated by each delay unit, and generate a first value N representing the number of delay units detected in one clock cycle according to each delay signal during the effective level period of the delay detection signal LINE_SAM. The delay unit detection module 12 includes a holding module 121, and the holding module 121 includes the same number of holding units 1211 as the delay unit 111, and each holding unit 1211 receives the output of a corresponding delay unit 111 respectively. When the holding unit 1211 detects the transition edge of the received delay signal, the step level after the transition edge is maintained. The delay unit detection module 12 determines the number of delay units included in one clock cycle according to the number of step levels.

[0038] like Figure 2As shown, the delay unit detection module 12 also includes a counting unit 122, which is used to detect and count the number of the step levels included in a clock cycle, so as to obtain a first value N. Specifically, the counting unit 122 receives the output signals Q1-Qn of the holding unit to generate the first value N. Additional delays may be introduced in the wiring of the chip, and the signal delay caused by the wiring is eliminated by adding a clock synchronization module. When the delay unit detection module calibrates the number of delay units included in a clock cycle according to the actual delay time of the delay unit, the clock synchronization module is required to synchronize the delay detection signal LINE_SAM and the first pulse width modulation signal S_IN with the clock signal Clock, that is, the rising edge of the delay detection signal LINE_SAM and the first pulse width modulation signal S_IN needs to be aligned with the rising edge or falling edge of the clock signal Clock. This embodiment is described by aligning the rising edge with the rising edge and the step level is a high level as an example, but is not limited to this.

[0039] Specifically, Figure 2 As shown, the modulation circuit also includes a clock synchronization module, which is used to synchronize the first pulse width modulation signal S_IN and the delay detection signal LINE_SAM with the clock signal Clock respectively, wherein the synchronized delay detection signal includes a high level of one clock cycle, and the synchronized delay detection signal lags the synchronized first pulse width modulation signal by one clock cycle. The clock synchronization module includes a first synchronization module 14 and a second synchronization module 15, and the first synchronization module 14 and the second synchronization module 15 are both D triggers, the first input end of the D trigger is a data input end, and the second input end of the D trigger is a clock signal input end. The first input ends of the first synchronization module 14 and the second synchronization module 15 are connected to the first pulse width modulation signal S_IN and the delay detection signal LINE_SAM respectively, and the second input ends of the first synchronization module 14 and the second synchronization module 15 are connected to the clock signal Clock, so as to synchronize the first pulse width modulation signal S_IN and the delay detection signal LINE_SAM with the clock signal Clock, wherein, after detecting the rising edge of the first pulse width modulation signal S_IN, the delay detection signal LINE_SAM sends a high level of one clock cycle, so that the synchronized delay detection signal LINE_SAM_SYN output by the second synchronization module 15 lags behind the synchronized first pulse width modulation signal S_IN_SYN output by the first synchronization module 14 by one clock cycle. After detecting the rising edge of the LINE_SAM_SYN signal, each holding unit will latch the levels of the delay signals delay_1 to delay_n at the rising edge of the LINE_SAM_SYN signal, wherein delay_1 is the output after one delay unit 111, and delay_n is the output after n delay units 111.

[0040] like Figure 2 As shown, as an example, the holding unit 1211 is a D flip-flop, the first input end of each holding unit 1211 receives the output of the corresponding delay unit 111, the second input end of each holding unit 1211 is connected to the output of the second synchronization module 15, and the output signal of each holding unit 1211 is input to the counting unit 122.

[0041] As an example, the delay module 11 further includes a multiplexer 112, wherein the delayed signals delay_1 to delay_n and the undelayed signal delay_0 are used as input signals of the multiplexer 112, the undelayed signal delay_0 is the first pulse width modulation signal S_IN, and one of delay_0 to delay_n is selected by the selection signal K2 as the second pulse width modulation signal output. Figure 3 As shown, it is a timing diagram of the delay unit detection module of this embodiment. At time t1, the rising edge of the clock signal Clock is detected, the first pulse width modulation signal S_IN received by the first synchronization module 14 at the first input end is high, and the first pulse width modulation signal S_IN_SYN output by the first synchronization module 14 after synchronization is high; the delay detection signal LINE_SAM received by the second synchronization module 15 at the first input end is low, and the delay detection signal LINE_SAM_SYN output by the second synchronization module 15 after synchronization is low. At time t2, when another rising edge of the clock signal Clock is detected, the first pulse width modulation signal S_IN is high, and the first pulse width modulation signal S_IN_SYN after synchronization remains high; the delay detection signal LINE_SAM is high, and the delay detection signal LINE_SAM_SYN output by the second synchronization module 15 after synchronization jumps to high. Between time t1 and time t2 is a clock cycle T, and each delay unit outputs a corresponding delay signal delay_1~delay_n. After time t2, after the synchronized delay detection signal LINE_SAM_SYN is pulled high, each holding unit 1211 will latch the levels of delay_1~delay_n of the first input terminal at time t2. Therefore, after time t2, the counting unit 122 can obtain the number of delay units required for one clock cycle by judging the number of high levels in Q1~Qn output by all holding units 1211. As shown in Figure 3 as an example, the high levels in Q1~Qn are Q1~QN, that is, the number of high levels is N, that is, the number of delay units required for one clock cycle T after calibration is N, that is, the first value is N.

[0042] As an example, the counting unit 122 includes a first counter for counting the high level output by the holding unit 1211 after time t2, that is, counting the number of step levels included in one clock cycle, so as to obtain the number of delay units actually included in one clock cycle, that is, realizing the detection and calibration of the number of delay units included in one clock cycle according to the actual delay time of the delay unit.

[0043] Specifically, Figure 2 As shown, the modulation circuit 1 also includes a calibration module 13, which generates a selection signal K2 according to the ratio of the first value to the second value and according to the product of the ratio and the third value, wherein the second value is a number of theoretical delay times of the delay unit included in one clock cycle, and the third value is a signal representing the expected resolution information.

[0044] As an example, the output of the K2th delay unit is selected as the signal output by selecting the signal K2, wherein K2=K1*N / M, K1 is a signal representing the resolution information of the second pulse modulation signal to be outputted, and as an example, K1 is the delay time t required for delaying the rising or falling edge of the first pulse width signal and the theoretical delay time t of a delay unit. delay_1 , calculate the number of delay units required K1 = t / t delay_1 , M is a second value, representing the number of time units included in a clock cycle, where the time unit is the theoretical delay time of the delay unit, M = T / t delay_1 , N is a first value, thereby selecting signal K2 as an input signal to be input to the multiplexer 112, and the multiplexer 112 selects the output of the K2th delay unit as the signal output, that is, the output of the K2th delay unit is output as the second pulse width modulation signal S_OUT.

[0045] Specifically, the delay unit detection module 12 can calibrate the first value N once according to the actual delay time of the delay unit at a predetermined preset time interval, so as to dynamically adjust the number of delay modules required for a clock cycle T in real time, thereby improving the design accuracy.

[0046] Based on the above modulation circuit, a pulse width modulation method can be implemented, including the following steps:

[0047] Input a first pulse width modulation signal into a delay module, wherein the delay module includes a plurality of delay units connected in series; detect the number of delay units included in a clock cycle; generate a selection signal according to an input signal representing information of a desired resolution and the number of delay units detected; and select an output of a corresponding delay unit for output according to the selection signal, thereby delaying a rising edge or a falling edge of the first pulse width modulation signal to output a second pulse width modulation signal.

[0048] Specifically, a clock signal is received to generate the first pulse width modulation signal, wherein the resolution of the first pulse width modulation signal is the period of the clock signal. The selection signal is generated according to the ratio of the first value N and the second value M, and according to the product of the ratio and the third value K1, wherein the first value N represents the number of delay units detected in one clock cycle, the second value M represents the number of theoretical delay times of the delay units included in one clock cycle, and the third value K1 is a signal representing the expected resolution information.

[0049] As an example, a delay detection signal and delay signals generated by each delay unit are received, and a first value representing the number of delay units detected in one clock cycle is generated according to each delay signal during the effective level of the delay detection signal. The first pulse width modulation signal and the delay detection signal are synchronized with the clock signal respectively, wherein the delay detection signal after synchronization contains an effective level of one clock cycle. As an example, the synchronized delay detection signal lags behind the synchronized first pulse width modulation signal by one clock cycle.

[0050] Specifically, Figure 4 As shown, as a first example, as shown in PWM1 in the figure, it is selected to delay the rising edge of the first pulse width modulation signal S_IN, and not to delay the falling edge to achieve high resolution of the duty cycle of the PWM signal; as a second example, as shown in PWM2 in the figure, it is selected to delay the falling edge of the first pulse width modulation signal S_IN, but not to delay the rising edge to achieve high resolution of the duty cycle of the PWM signal or to achieve high resolution of the dead zone; as a third example, as shown in PWM3 in the figure, it is selected to delay both the rising edge and the falling edge of the first pulse width modulation signal S_IN to achieve high resolution of the phase.

[0051] Based on the above modulation circuit, a method for improving the period resolution of a PWM signal can be implemented, comprising the following steps: generating a first pulse width modulation signal according to a clock signal;

[0052] Dividing the period of the second pulse width modulation signal into a first integer multiple of a first resolution and a second integer multiple of a second resolution;

[0053] Generate a delay time according to the second integer and the number of delay units included in a clock cycle;

[0054] The rising edge and the falling edge of the first pulse width modulation signal are offset by an offset corresponding to the delay time to generate a second pulse width modulation signal.

[0055] Specifically, the following steps are also included:

[0056] Detecting the number of delay units included in one clock cycle;

[0057] Generate a selection signal according to the delay time and the number of delay units included in one clock cycle;

[0058] The output of the corresponding delay unit is selected according to the selection signal, thereby outputting the transition edge of the second pulse width modulation signal.

[0059] Specifically, the selection signal is generated according to the ratio of the first numerical value to the second numerical value, and according to the product of the ratio and a third numerical value; wherein the first numerical value is used to characterize the number of delay units detected within a clock cycle, the second numerical value characterizes the number of time units included in a clock cycle, and the third numerical value is a signal used to characterize the delay time, and the time unit is the theoretical delay time of a delay unit.

[0060] Specifically, the period value of the second pulse width modulation signal includes a first resolution of a first integer PRD times and a first resolution of a decimal times, and the first resolution of the decimal times is converted into a second resolution of a second integer PRDHR times; that is, the period value of the converted PWM signal includes a first resolution of a first integer PRD times and a second resolution of a second integer PRDHR times; wherein the first resolution corresponds to a clock cycle, the second resolution corresponds to a time unit, and the time unit is the theoretical delay time of a delay unit.

[0061] The first method for improving the period resolution of the PWM signal is described below, including the following steps:

[0062] The accumulated value PRDSUM is accumulated and counted in a loop according to the second integer PRDHR. When the accumulated value PRDSUM is less than the second value M, the count value counter corresponding to the moment when the counter is cleared is controlled to be the first integer PRD; when the accumulated value PRDSUM is greater than or equal to the second value M, the count value counter corresponding to the moment when the counter is cleared is controlled to be the first integer PRD plus 1; wherein the second value M is the number of time units contained in a clock cycle, and the time unit is the theoretical delay time of a delay unit.

[0063] The number of time units included in the delay of the transition edge of the second pulse width modulation signal relative to the modulation signal is obtained according to the modulation signal, the accumulated value PRDSUM and the count value counter of the counter, and then the number of theoretical delay units is converted into the number of delay units actually required, so as to output the transition edge of the second pulse width modulation signal with high resolution, thereby achieving high resolution of the PWM signal period.

[0064] In each PWM cycle, when the count value reaches the value corresponding to the modulation signal, the modulation signal is delayed relative to the modulation signal according to the accumulated value, so as to output the transition edge of the second pulse width modulation signal; wherein the modulation signal is used to control the rising edge or falling edge of the first pulse width modulation signal. Specifically, when the count value counter of the counter reaches the value corresponding to the modulation signal, the number of time units (i.e., the theoretical delay time of the delay unit) included in the delay relative to the modulation signal is obtained according to the accumulated value PRDSUM. When the accumulated value PRDSUM is greater than or equal to the second value M, the accumulated value PRDSUM is configured to be the current accumulated value minus the second value M. In the current PWM cycle, when the count value of the carrier counting module reaches the value corresponding to the modulation signal plus 1, the number of time units included in the delay relative to the modulation signal is obtained according to the accumulated value PRDSUM.

[0065] It should be noted that the numerical values ​​in the above steps are calculated based on the theoretical delay time of the delay unit. After the number of theoretical delay times of the delay unit included in the delay time of the relative modulation signal is calculated, it is also necessary to calibrate according to the actual number of delay units included in a clock cycle to obtain the actual number of delay times of the delay unit included in the delay time of the relative modulation signal, so as to achieve the delay of the transition edge of the first pulse width modulation signal through the above-mentioned modulation circuit.

[0066] Specifically, from the above analysis, it can be known that: K2=K1*N / M, corresponding to in this example, K1 is the number of time units included in the delay time of the relative modulation signal; K2 is the selection signal; the output of the corresponding delay unit is selected according to the selection signal, thereby outputting the transition edge of the second pulse width modulation signal; the second value M is the number of time units included in a clock cycle T, N is the first value, and the time unit is the theoretical delay time of the delay unit.

[0067] Assume that a clock period T contains M time units. The moment when the counter is cleared is related not only to the first integer PRD but also to the second integer PRDHR. In the k-th period of the PWM signal, when PRDHR + PRDSUM(k) < M, the moment when the count value counter of the counter is cleared is PRD, that is, the current period includes PRD clock cycles, and then the accumulated value PRDSUM(k) = PRDSUM(k - 1) + PRDHR is recorded; when PRDHR + PRDSUM(k) >= M, the moment when the count value counter of the counter is cleared is PRD + 1, that is, the current period includes PRD + 1 clock cycles, and then the accumulated value PRDSUM(k) = PRDSUM(k - 1) + PRDHR - M is recorded; where k refers to the k-th period of the PWM signal.

[0068] The modulation signal also has an integer part (CMP) and a fractional part (CMPHR). In the k-th period of the PWM signal, when CMPHR + PRDSUM(k) < M, the PWM transition edge corresponding to the modulation signal is at the position where the count value counter of the counter = CMP, and the number of delay units required for the delay time of the PWM transition edge relative to the modulation signal is CMPHR + PRDSUM(k); when CMPHR + PRDSUM(k) >= M, the PWM transition edge corresponding to the modulation signal is at the position where the carrier counter = CMP + 1, and the number of delay units required for the delay time of the PWM transition edge corresponding to the modulation signal is CMPHR + PRDSUM(k) - M. At this time, it can also be regarded as the PWM transition edge at the position where the carrier counter = CMP, and the delay time of the transition edge relative to the modulation signal is CMPHR + PRDSUM(k).

[0069] Such as Figure 5As shown, it is a waveform diagram of PWM cycle high resolution. In this example, assuming that M=16, the cycle value of the second pulse width modulation signal is 9.375 clock cycles, that is, 9 clock cycles and 0.375 / (1 / 16)=0.375*16=6 delay units of theoretical delay time, that is, the first integer PRD=9, the second integer PRDHR=6; the low level of the second pulse width modulation signal is 6 clock cycles, the low level of the second pulse width modulation signal includes the number of second resolutions CMPAHR=0, the high level of the second pulse width modulation signal is 3.375 clock cycles, the high level of the second pulse width modulation signal includes the number of second resolutions CMPBHR=PRDHR=6; in this example, the modulation signal includes the first modulation signal and the second modulation signal, which respectively control the rising edge and the falling edge of the first pulse width modulation signal S_IN, and the corresponding count values ​​of the counter are 4 and 7, that is, the number of the first modulation signal corresponding to the first resolution is CMPA=4, and the number of the second modulation signal corresponding to the first resolution is CMPB=7.

[0070] The first PWM cycle: PRDSUM(1)=0, PRDHR+PRDSUM(1)=0+6=6<16, the time when the counter value counter is cleared is PRD, so the current PWM cycle is 9 clock cycles, the delay value CMPAHR(1)=PRDSUM(1)=0 of the rising edge relative to the counter value counter=CMPA=4, and the delay value CMPBHR(1)=PRDSUM(1)+CMPBHR=0+6=6 of the falling edge relative to the counter value counter=CMPB=7 of the second modulation signal;

[0071] The second PWM cycle: PRDSUM(2)=PRDHR+PRDSUM(1)=6+0=6, PRDHR+PRDSUM(2)=6+6=12<16, the counter value counter is reset at PRD, so the current PWM cycle is 9 clock cycles; the delay value CMPAHR(2)=CMPAHR+PRDSUM(2)=0+6=6 of the rising edge relative to the counter value counter=CMPA=4, and the delay value CMPBHR(2)=PRDSUM(2)+CMPBHR=6+6=12 of the falling edge relative to the second modulation signal counter value counter=CMPB=7;

[0072] The third PWM cycle: PRDSUM(3)=PRDHR+PRDSUM(2)=6+6=12, PRDHR+PRDSUM(3)=6+12=18>16, the counter count value counter is reset at PRD+1, so the current PWM cycle is 10 clock cycles, the rising edge relative to the counter count value counter=CMPA=4 delay value CMPAHR(3)=CMPAHR+PRDSUM(3)=0+12=12, the falling edge relative to the counter count value counter=CMPB+1=8 delay value is 18-16=2;

[0073] The fourth PWM cycle: PRDSUM(4)=PRDHR+PRDSUM(3)=12+6=18>16, so PRDSUM(4)=PRDHR+PRDSUM(3)-M=12+6-16=2, PRDSUM(4)+PRDHR=8<16, so the current PWM cycle is 9 clock cycles; the delay value CMPAHR(4)=PRDSUM(4)+CMPAHR=2 of the rising edge relative to the count value of the counter counter=CMPA=4, and the delay value CMPBHR(4)=PRDSUM(4)+CMPBHR=2 of the falling edge relative to the count value of the counter counter=CMPB=7.

[0074] Afterwards, according to K2=K1*N / M, where K1 in this example corresponds to CMPAHR(k) and CMPBHR(k), k corresponds to the kth period of the second pulse width modulation signal, M is the number of time units included in a clock period T, and N is the first value; CMPAHR(k) is the number of theoretical delay times of the delay unit that needs to be delayed for the rising edge of the kth period of the PWM signal relative to the first modulation signal, and CMPBHR(k) is the number of theoretical delay times of the delay unit that needs to be delayed for the falling edge of the kth period of the second pulse width modulation signal relative to the second modulation signal. Specifically, CMPAHR(k) is converted by CMPAHR(k)*N / M to obtain the actual delay amount of the rising edge of the second pulse width modulation signal relative to the first modulation signal in the kth cycle, that is, in the kth cycle, the modulation circuit selects the output of the CMPAHR(k)*N / Mth delay unit relative to the first modulation signal as the rising edge of the PWM signal to output; CMPBHR(k) is converted by CMPBHR(k)*N / M to obtain the actual delay amount of the falling edge of the PWM wave relative to the second modulation signal in the kth cycle, that is, in the kth cycle, the modulation circuit selects the output of the CMPBHR(k)*N / Mth delay unit relative to the second modulation signal as the falling edge of the second pulse width modulation signal to output, thereby achieving high resolution of the PWM signal cycle by delaying the rising edge (or the first modulation signal corresponding to the rising edge) or the falling edge (or the second modulation signal corresponding to the falling rising edge) of the first pulse width modulation signal S_IN.

[0075] The second method for improving the period resolution of the PWM signal is described below, including the following steps:

[0076] The decrement value EXPRDHR is cumulatively decremented in a loop according to the second integer PRDHR. When the decrement value EXPRDHR is greater than the second integer PRDHR, the count value counter of the control counter is cleared to the first integer PRD; when the decrement value EXPRDHR is less than or equal to the second integer PRDHR, the count value counter of the control counter is cleared to the first integer PRD plus 1; wherein the second value M represents the number of time units included in a clock cycle, and the time unit is the theoretical delay time of a delay unit.

[0077] When the count value reaches the value corresponding to the modulation signal, the modulation signal is delayed relative to the decrement value, thereby outputting the transition edge of the second pulse width modulation signal; wherein the modulation signal is used to control the rising edge or falling edge of the first pulse width modulation signal. Specifically, the number of theoretical delay times of the delay unit included in the delay of the transition edge of the second pulse width modulation signal relative to the modulation signal is obtained according to the modulation signal, the decrement value and the count value counter of the counter, thereby achieving high resolution of the PWM signal cycle. When the decrement value EXPRDHR(k) is less than or equal to the second integer PRDHR, the decrement value EXPRDHR(k) is configured to be the current decrement value plus the second value M. In the current PWM cycle, when the count value of the carrier counting module reaches the value corresponding to the modulation signal, the number of time units included in the delay relative to the modulation signal is obtained according to the decrement value EXPRDHR(k); when the decrement value EXPRDHR(k) is greater than the second integer PRDHR, in the current PWM cycle, when the count value of the carrier counting module reaches the modulation signal minus 1, the number of time units included in the delay relative to the modulation signal is obtained according to the decrement value EXPRDHR(k).

[0078] It should be noted that the numerical values ​​in the above steps are calculated based on the theoretical delay time of the delay unit. After the number of time units included in the delay time of the relative modulation signal is calculated, it is also necessary to calibrate according to the actual number of delay units included in a clock cycle to obtain the actual number of delay times of the delay units included in the delay time of the relative modulation signal, so as to delay the jumping edge of the PWM signal through the above-mentioned modulation circuit.

[0079] Specifically, from the above analysis, it can be seen that: K2=K1*N / M, corresponding to in this example, K1 is the number of theoretical delay times of the delay unit included in the delay time of the relative modulation signal; K2 is the number of actual delay times of the delay unit included in the delay time of the relative modulation signal; M is the number of time units included in a clock cycle T, and N is the first value.

[0080] The following is an explanation with reference to a specific example. Assume that according to the theoretical delay time of the delay unit, a clock cycle includes M time units. The time when the counting module is reset is not only related to the first integer PRD, but also to the second integer PRDHR.

[0081] In the k-th period of the second pulse width modulation signal, when PRDHR >= EXPRDHR(k), the counter value counter is cleared at PRD + 1, that is, the current period includes PRD + 1 clock cycles, and then the value EXPRDHR(k) = M + EXPRDHR(k - 1) - PRDHR is recorded; when PRDHR < EXPRDHR(k), the counter value counter is cleared at PRD, that is, the current period includes PRD + 1 clock cycles, and then the decreasing value EXPRDHR(k) = EXPRDHR(k - 1) - PRDHR is recorded; where k refers to the k-th period of the PWM signal.

[0082] The modulation signal also has an integer part (CMP) and a fractional part (CMPHR). When CMPHR >= EXPRDHR(k), the PWM transition edge corresponding to the modulation signal is at the position where the counter value counter = CMP, and the number of delay units corresponding to the delay is CMPHR - EXPRDHR(k); when CMPHR < EXPRDHR(k), the PWM transition edge corresponding to the modulation signal is at the position where the counter value counter = CMP - 1, and the number of delay units corresponding to the delay time is M + CMPHR - EXPRDHR(k).

[0083] As Figure 6 shown, it is the waveform diagram of the high resolution of the PWM period. Assume M = 16, the period value of the second pulse width modulation signal is 9.375 clock cycles, that is, 9 clock cycles and 0.375 / (1 / 16) = 0.375 * 16 = 6 delay units, that is, the first integer PRD = 9, the second integer PRDHR = 6; the low level of the second pulse width modulation signal is 6 clock cycles, and the number of the second resolution included in the low level of the second pulse width modulation signal CMPCHR = 0; the high level of the second pulse width modulation signal is 3.375 clock cycles, and the number of the second resolution included in the high level of the second pulse width modulation signal CMPDHR = PRDHR = 6; in this example, the modulation signal includes a third modulation signal and a fourth modulation signal, which respectively control the rising edge and the falling edge of the first pulse width modulation signal S_IN, and respectively correspond to the counter values counter of 4 and 7, that is, the third modulation signal corresponds to the number of the first resolution of 4, and the fourth modulation signal corresponds to the number of the first resolution of CMPD = 7.

[0084] The first PWM period: EXPRDHR(1) = 0, PRDHR > EXPRDHR(1), the counter value counter is cleared at PRD + 1 = 10, so the current PWM period value is 10 clock cycles; CMPCHR >= EXPRDHR(1), the rising edge is at the counter value counter = CMPC, and the number of delay units required for the delay CMPCHR(1) = CMPCHR – EXPRDHR(1) = 0; CMPDHR >= EXPRDHR(1), the falling edge is at the counter value counter = CMPD, and the number of delay units required for the delay CMPDHR(1) = CMPDHR – EXPRDHR(1) = 6;

[0085] The second PWM period: Since EXPRDHR(1) < PRDHR, so EXPRDHR(2) = M + EXPRDHR(1) - PRDHR = 16 + 0 - 6 = 10; PRDHR < EXPRDHR(2), the counter value counter is cleared at PRD = 9, so the current PWM period value is 9 clock cycles; CMPCHR < EXPRDHR(2), the rising edge is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(2) = M + CMPCHR – EXPRDHR(2) = 16 + 0 - 10 = 6; CMPDHR < EXPRDHR(2), the falling edge is at the counter value counter = CMPD - 1, and the number of delay units required for the delay CMPDHR(2) = M + CMPDHR – EXPRDHR(2) = 16 + 6 - 10 = 12;

[0086] The third PWM period: EXPRDHR(3) = EXPRDHR(2) - PRDHR = 10 - 6 = 4; PRDHR > EXPRDHR(3), the counter value counter is cleared at PRD + 1 = 10, so the current PWM period value is 10 clock cycles; CMPCHR < EXPRDHR(3), the rising edge is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(3) = M + CMPCHR – EXPRDHR(3) = 16 + 0 - 4 = 12; CMPDHR >= EXPRDHR(3), the falling edge is at the counter value counter = CMPD, and the number of delay units required for the delay is CMPDHR(3) = CMPDHR – EXPRDHR(3) = 6 - 4 = 2;

[0087] Fourth PWM period: Since EXPRDHR(3) < PRDHR, then EXPRDHR(4) = M + EXPRDHR(3) - PRDHR = 16 + 4 - 6 = 14; PRDHR < EXPRDHR(4), the counter value counter is cleared at PRD, so the current PWM period value is 9 clock cycles; CMPCHR < EXPRDHR(4), the rising edge of the PWM is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(4) = M + CMPCHR – EXPRDHR(4) = 16 + 0 - 14 = 2; CMPDHR < EXPRDHR(4), the falling edge of the PWM is at the counter value counter = CMPD - 1, and the number of delay units required for the delay CMPDHR(4) = M + CMPDHR – EXPRDHR(4) = 16 + 6 - 14 = 8; then EXPRDHR(5) = EXPRDHR(4) - PRDHR = 14 - 6 = 8.

[0088] Similarly, in this embodiment, according to K2 = K1 * N / M, K1 corresponds to CMPCHR(k) and CMPDHR(k) in this instance, where k is the k-th period of the second pulse width modulation signal; the second value M is the number of time units included in one clock cycle T, and N is the first value. Specifically, CMPCHR(k) is converted by CMPCHR(k) * N / M to obtain the actual number of delay units of the rising edge of the PWM signal relative to the third modulation signal in the k-th period, that is, in the k-th period, the modulation circuit selects the output of the CMPCHR(k) * N / M-th delay unit relative to the counter value equal to CMPC - 1 or CMPC as the rising edge of the PWM signal to output; CMPDHR(k) is converted by CMPDHR(k) * N / M to obtain the actual number of delay units of the falling edge of the PWM signal relative to the fourth modulation signal in the k-th period, that is, in the k-th period, the modulation circuit selects the output of the CMPDHR(k) * N / M-th delay unit relative to the counter value equal to CMPD - 1 or CMPD as the falling edge of the PWM signal to output, thereby realizing high-resolution of the PWM signal period by delaying the rising edge (or the third modulation signal corresponding to the rising edge) or the falling edge (or the fourth modulation signal corresponding to the falling edge) of the first pulse width modulation signal S_IN.

[0089] In summary, the present invention provides a modulation circuit and a pulse width modulation method, wherein the modulation circuit includes: a delay module, including a plurality of delay units connected in series, configured to receive a first pulse width modulation signal at an input end and generate a second pulse width modulation signal at an output end; a delay unit detection module, configured to detect the number of delay units included in a clock cycle to output a first value representing the number of delay units; a calibration module, generating a selection signal according to a signal representing the desired resolution information and the first value; the delay module selects the output of the corresponding delay unit as an output according to the selection signal, thereby delaying the rising edge or falling edge of the first pulse width modulation signal to output the second pulse width modulation signal. The pulse width modulation method can be implemented based on the modulation circuit, inputting the first pulse width modulation signal into the delay module; generating a selection signal according to the signal representing the desired resolution information and the first value, selecting one of the delay units as the output of the signal, thereby delaying the rising edge or falling edge of the original PWM signal. The present invention can dynamically adjust the number of delay modules required for a clock cycle in real time, thereby improving the design accuracy; and does not require a DLL module for implementation, thereby saving the chip area occupied by the DLL design and avoiding errors caused by the DLL module routing the clock cluster.

[0090] Although the embodiments or implementations are described and explained separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that the embodiments or implementations can be replaced and integrated between them. If one of the embodiments or implementations is not clearly recorded, reference can be made to another recorded embodiment.

[0091] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A modulation circuit, characterized in that: include: The delay module comprises a plurality of delay units connected in series in sequence, and is configured to receive a first pulse width modulation signal at an input end and generate a second pulse width modulation signal at an output end; A delay unit detection module is configured to detect the number of delay units included in a clock cycle; as well as A calibration module generates a selection signal according to a signal representing the desired resolution information and the number of delay units detected; The delay module selects the output of the corresponding delay unit as the output according to the selection signal, thereby delaying the rising edge or the falling edge of the first pulse width modulation signal to output the second pulse width modulation signal.

2. The modulation circuit according to claim 1, characterized in that: The modulation circuit further includes: The pulse width modulation signal generating circuit is configured to receive a clock signal and generate the first pulse width modulation signal, wherein the resolution of the first pulse width modulation signal is one clock cycle.

3. The modulation circuit according to claim 1, characterized in that: The number of delay units included in the delay module is determined according to the number of theoretical delay times of the delay units within a clock cycle.

4. The modulation circuit according to claim 1, characterized in that: The calibration module generates the selection signal according to the ratio of the first value to the second value and according to the product of the ratio and a third value, wherein the first value represents the number of delay units detected within a clock cycle, the second value represents the number of time units included in a clock cycle, the third value is the signal representing the expected resolution information, and the time unit is the theoretical delay time of the delay unit.

5. The modulation circuit according to claim 1, characterized in that: The delay unit detection module is configured to receive a delay detection signal and delay signals generated by each delay unit, and generate a first value representing the number of delay units detected in one clock cycle according to each delay signal during an effective level period of the delay detection signal.

6. The modulation circuit according to claim 5, characterized in that: The delay unit detection module includes holding units with the same number as the delay units, each of which receives the output of a corresponding delay unit. When a transition edge of the delay unit output signal is detected during the effective level period of the delay detection signal, the step level after the transition edge is maintained.

7. The modulation circuit according to claim 6, characterized in that: The delay unit detection module further includes a counting unit for counting the number of the step levels included in the effective level period of the delay detection signal to obtain the first value, wherein the effective level of the delay detection signal is one clock cycle.

8. The modulation circuit according to claim 7, characterized in that: Each holding unit is a D flip-flop, the data port of each holding unit receives the output of a corresponding delay unit, the clock input port of each holding unit receives the delay detection signal, and each holding unit outputs to the counting unit.

9. The modulation circuit according to claim 5, characterized in that: The modulation circuit further includes a first synchronization module, which is used to synchronize the first pulse width modulation signal with a clock signal.

10. The modulation circuit according to claim 9, characterized in that: The modulation circuit also includes a second synchronization module for synchronizing the delay detection signal and the clock signal, wherein the synchronized delay detection signal includes a valid level of one clock cycle, and the synchronized delay detection signal lags behind the synchronized first pulse width modulation signal by one clock cycle.

11. The modulation circuit according to claim 1, characterized in that: The delay unit detection module calibrates the number of the delay units included in one clock cycle once at every preset time interval.

12. A pulse width modulation method, characterized in that: The following steps are involved: Inputting the first pulse width modulation signal into a delay module, wherein the delay module comprises a plurality of delay units connected in series; Detecting the number of delay units included in one clock cycle; generating a selection signal according to an input signal representing the desired resolution information and the first value; The output of the corresponding delay unit is selected for output according to the selection signal, thereby delaying the rising edge or the falling edge of the first pulse width modulation signal to output a second pulse width modulation signal.

13. The pulse width modulation method according to claim 12, characterized in that: The pulse width modulation method further comprises: A clock signal is received to generate the first pulse width modulation signal, wherein a resolution of the first pulse width modulation signal is a period of the clock signal.

14. The pulse width modulation method according to claim 12, characterized in that: The selection signal is generated according to a ratio of a first value to a second value and according to a product of the ratio and a third value, wherein the first value represents the number of delay units detected within a clock cycle, the second value represents the number of theoretical delay times of delay units included in a clock cycle, and the third value represents an input signal representing desired resolution information.

15. The pulse width modulation method according to claim 12, characterized in that: A delay detection signal and delay signals generated by delay units connected in series are received, and the first value is generated according to each delay signal during the effective level period of the delay detection signal.

16. The pulse width modulation method according to claim 15, characterized in that: The first pulse width modulation signal and the delay detection signal are synchronized with the clock signal respectively, wherein after synchronization, the delay detection signal includes a valid level of a clock cycle.

17. The pulse width modulation method according to claim 16, characterized in that: The synchronized delayed detection signal lags behind the synchronized first pulse width modulation signal by one clock cycle.

18. The pulse width modulation method according to claim 12, characterized in that: The number of the delay units included in one clock cycle is calibrated once at every preset time interval.

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