Self-protection circuit, splicing circuit, operational amplifier circuit and current mirror circuit

Abstract

The invention provides a self-protection circuit, a splicing circuit, an operational amplifier circuit and a current mirror circuit. The self-protection circuit is configured to receive a first power supply, and includes a first transistor, a first switching element, and a control unit. The first transistor comprises a first input end, a first output end and a first control end. The first input is configured to receive a first power source. The first output end is electrically connected with the grounding end. The first switch element is electrically connected with the first input end and the grounding end. The control unit is electrically connected with the first switch element and is configured to control the first switch element to be turned on before the first power supply supplies power to the first transistor. After the first power supply continuously supplies power to the first transistor, the first switching element is controlled to be turned off.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuits, and in particular to a self-protection circuit, a cascade circuit, an operational amplifier circuit and a current mirror circuit. Background Art

[0002] In order to prevent the surge from affecting the components in the circuit, parasitic capacitors are generally used to guide the surge to the ground, or the characteristics of the diode are used to guide the reverse surge to the ground.

[0003] However, although the above method can avoid the negative impact of surges, when the circuit is operating normally, since the parasitic capacitor or diode is still electrically connected to the circuit, the component characteristics of the parasitic capacitor or diode will affect the overall operation of the circuit and can only protect against surges in one direction. Summary of the invention

[0004] In view of the above, a self-protection circuit is provided. In some embodiments, a self-protection circuit is configured to receive a first power supply, and the self-protection circuit includes a first transistor, a first switch element and a control unit. The first transistor includes a first input terminal, a first output terminal and a first control terminal. The first input terminal is configured to receive the first power supply, and the first output terminal is electrically connected to the ground terminal. The first switch element is electrically connected to the first input terminal and the ground terminal. The control unit is electrically connected to the first switch element, and is configured to control the first switch element to be turned on before the first power supply supplies power to the first transistor, and control the first switch element to be turned off after the first power supply continues to supply power to the first transistor.

[0005] In some embodiments, the control unit controls the first switch element to be turned on before the first power source stops supplying power to the first transistor.

[0006] In some embodiments, the self-protection circuit further includes a second switch element and a third switch element. The second switch element is electrically connected between the first control terminal and the ground terminal. The third switch element is electrically connected between the first power supply and the first input terminal. The control unit is electrically connected to the second switch element and the third switch element respectively to control the second switch element and the third switch element to be turned on or off respectively.

[0007] In some embodiments, the control unit controls the first switch element to be turned on before the first power source stops supplying power to the first transistor.

[0008] In some embodiments, the control unit controls the second switch element and the third switch element to be turned on so that the first power supply supplies power to the first transistor, and controls the second switch element and the third switch element to be turned off so that the first power supply does not supply power to the first transistor.

[0009] In some embodiments, the control unit controls the first switch element to be turned on before controlling the third switch element to be turned on.

[0010] A stacking circuit is also provided, which is configured to receive a first power supply, and the stacking circuit includes a first transistor, a second transistor, a first switch element, a second switch element and a control unit. The first transistor includes a first input terminal, a first output terminal and a first control terminal. The first input terminal is configured to receive the first power supply. The second transistor includes a second input terminal, a second output terminal and a second control terminal. The first output terminal is electrically connected to the second input terminal, and the second output terminal is electrically connected to the ground terminal. The first switch element is electrically connected to the first input terminal and the ground terminal respectively. The second switch element is electrically connected to the second input terminal and the ground terminal respectively. The control unit is electrically connected to the first switch element and the second switch element respectively, and is configured to control the first switch element and the second switch element to be turned on before the first power supply is supplied to the first transistor, and control the first switch element and the second switch element to be turned off after the first power supply is continuously supplied to the first transistor.

[0011] An operational amplifier circuit is also provided, which is configured to receive a first power supply, and the operational amplifier circuit includes a current mirror circuit, a first transistor, a first switch element and a control unit. The first transistor includes a first input terminal, a first output terminal and a first control terminal. The first input terminal and the first control terminal are respectively electrically connected to the current mirror circuit, the first input terminal is configured to receive the first power supply, and the first output terminal is electrically connected to the ground terminal. The first switch element is electrically connected to the first input terminal and the ground terminal. The control unit is electrically connected to the first switch element and is configured to control the first switch element to be turned on before the first power supply supplies power to the first transistor, and control the first switch element to be turned off after the first power supply continues to supply power to the first transistor.

[0012] A current mirror circuit is also provided, which is configured to receive a first power supply, and the current mirror circuit includes a first transistor, a second transistor, a first switch element and a control unit. The first transistor includes a first input terminal, a first output terminal and a first control terminal. The first input terminal is configured to receive the first power supply, the first control terminal is electrically connected to the first input terminal, and the first output terminal is electrically connected to the ground terminal. The second transistor includes a second input terminal, a second output terminal and a second control terminal. The first control terminal is connected to the second control terminal, and the second output terminal is electrically connected to the ground terminal. The first switch element is electrically connected between the first input terminal and the ground terminal. The control unit is electrically connected to the first switch element, and is configured to control the first switch element to be turned on before the first power supply supplies power to the first transistor, and control the first switch element to be turned off after the first power supply continues to supply power to the current mirror circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A circuit diagram of a self-protection circuit in some embodiments is shown.

[0014] Figure 2 A circuit schematic diagram of a stacked circuit is shown in some embodiments.

[0015] Figure 3 A circuit schematic diagram of a current mirror circuit in some embodiments is shown.

[0016] Figure 4 FIG. 4 is a circuit diagram of an operational amplifier circuit in some embodiments.

[0017] Figure 5 The timing diagram of the first switch element, the second switch element, and the third switch element when the first power supply is supplied in some embodiments is shown.

[0018] Figure 6 FIG. 4 shows a timing diagram of the first switching element, the second switching element, and the third switching element when the first power source is stopped in some embodiments.

[0019] Explanation of symbols

[0020] V out10 ,V out20 ,V out30 ,V out40 : First Power Supply

[0021] V out50 : Second power supply

[0022] G10, G20, G30, G40: Ground terminal

[0023] 10,40,61,80: First transistor

[0024] 41,62,71: Second transistor

[0025] 72: The third transistor

[0026] 30,31,32,33: Control unit

[0027] 20,50,63,90: First switch element

[0028] 21,51,73: Second switch element

[0029] 22,52: Third switch element

[0030] 53: Fourth switch element

[0031] 60,70: Current mirror circuit

[0032] 101,401,611,801: First input

[0033] 102,402,612,802: First output terminal

[0034] 103,403,613,803: First control terminal

[0035] 411,621,711: Second input

[0036] 412,622,712: Second output terminal

[0037] 413,623,713: Second control terminal

[0038] 721: Third input terminal

[0039] 722: Third output terminal

[0040] 723: Third control terminal DETAILED DESCRIPTION

[0041] See also Figure 1 As shown, in some embodiments, the self-protection circuit is configured to receive a first power supply V out10 The self-protection circuit includes a first transistor 10, a first switch element 20, and a control unit 30.

[0042] See also Figure 1 As shown, the first transistor 10 includes a first input terminal 101, a first output terminal 102 and a first control terminal 103. The first input terminal 101 is configured to receive a first power supply V out10 , the first output terminal 102 is electrically connected to the ground terminal G10. In some embodiments, the first transistor 10 can be a bipolar junction transistor (BJT) or a field effect transistor (FET). In some embodiments, the first transistor 10 is an N-channel enhancement type MOSFET, the first input terminal 101 is a drain, the first output terminal 102 is a source, and the first control terminal 103 is a gate.

[0043] See also Figure 1 As shown, the first switch element 20 is electrically connected to the first input terminal 101 and the ground terminal G10 respectively. In some embodiments, the first switch element 20 can be a bipolar transistor or a field effect transistor. In some embodiments, the first switch element 20 is an N-channel enhancement MOSFET, the drain of the first switch element 20 is electrically connected to the first input terminal 101, and the source of the first switch element 20 is electrically connected to the ground terminal G10.

[0044] See also Figure 1 As shown, the control unit 30 is electrically connected to the first switch element 20 and is configured to out10 Before power is supplied to the first transistor 10, the first switch element 20 is controlled to be turned on, and the first power source V out10After the first transistor 10 is continuously supplied with power, the first switch element 20 is controlled to be turned off. In some embodiments, the control unit 30 is a control circuit such as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc. that can output corresponding electrical signals.

[0045] See also Figure 1 and Figure 5 As shown, in the first power supply V out10 Before starting to supply power to the first transistor 10, the control unit 30 first controls the first switch element 20 to be turned on, so that the first power source V out10 Before the first transistor 10 starts to be powered, the current flows through the first switch element 20 and is output to the ground terminal G10. out10 After the first transistor 10 is continuously supplied with power, the control unit 30 controls the first switch element 20 to be turned off. In this way, when the first switch element 20 is turned on, the first transistor 10 can be prevented from being damaged by an instantaneous excessive current, and when the first switch element 20 is turned off, its element characteristics can be prevented from affecting the overall circuit. Figure 6 As shown, in some embodiments, at the first power supply V out10 Before stopping supplying power to the first transistor 10 , the control unit 30 will also control the first switch element 20 to be turned on to prevent the surge generated when the power supply is stopped from affecting the first transistor 10 .

[0046] See also Figure 1 As shown, in some embodiments, the self-protection circuit further includes a second switch element 21 and a third switch element 22. The second switch element 21 is electrically connected between the first control terminal 103 and the ground terminal G10. The third switch element 22 is electrically connected to the first power source V out10 and the first input terminal 101. The control unit 30 is electrically connected to the second switch element 21 and the third switch element 22, respectively, to control the second switch element 21 and the third switch element 22 to be turned on or off. out10 can flow into the first transistor 10, and when the second switch element 21 and the third switch element 22 are turned off, the first power supply V out10 Therefore, the control unit 30 controls the second switch element 21 and the third switch element 22 to be turned on or off to determine the first power source V out10 Whether it flows into the first transistor 10. As described above, when the first power source V out10 Before power is supplied to the first transistor 10 (i.e., before the second switch element 21 and the third switch element 22 are turned on under the control of the control unit 30), the first switch element 20 must be turned on first. out10After the first transistor 10 is continuously supplied with power, the first switch element 20 is turned off. out10 Before stopping supplying power to the first transistor 10 (ie, before the second switch element 21 and the third switch element 22 are turned off under the control of the control unit 30 ), the first switch element 20 needs to be turned on first.

[0047] In some embodiments, through the control of the control unit 30, at least the first switch element 20 needs to be turned on before the third switch element 22 is turned on, regardless of whether the second switch element 21 is turned on before the first switch element 20 is turned on. That is, the turn-on sequence of the first switch element 20, the second switch element 21 and the third switch element 22 can be the first switch element 20, the third switch element 22, the second switch element 21, or the first switch element 20, the second switch element 21, the third switch element 22, or after the first switch element 20 is turned on, the second switch element 21 and the third switch element 22 are turned on at the same time.

[0048] In some embodiments, the second switch element 21 and the third switch element 22 may be bipolar transistors or field effect transistors.

[0049] See also Figure 2 As shown, in some embodiments, the aforementioned self-protection circuit can be applied to a stacked circuit. The stacked circuit is configured to receive a first power supply V out20 The cascade circuit includes a first transistor 40 , a second transistor 41 , a first switch element 50 , a second switch element 51 and a control unit 31 .

[0050] See also Figure 2 As shown, the first transistor 40 includes a first input terminal 401, a first output terminal 402 and a first control terminal 403. The first input terminal 401 receives a first power supply V out20 The second transistor 41 includes a second input terminal 411, a second output terminal 412 and a second control terminal 413. The first output terminal 402 is electrically connected to the second input terminal 411, and the second output terminal 412 is electrically connected to the ground terminal G20. The first switch element 50 is electrically connected to the first input terminal 401 and the ground terminal G20. The second switch element 51 is electrically connected to the second input terminal 411 and the ground terminal G20. The control unit 31 is electrically connected to the first switch element 50 and the second switch element 51, and is configured to out20 Before power is supplied to the first transistor 40, the first switch element 50 and the second switch element 51 are controlled to be turned on, and the first power source V out20 After power is continuously supplied to the first transistor 40 , the first switch element 50 and the second switch element 51 are controlled to be turned off.

[0051] At the first power supply Vout20 Before powering the first transistor 40, the first switch element 50 and the second switch element 51 must be turned on. out20 After the first transistor 40 is continuously supplied with power, the first switch element 50 and the second switch element 51 are turned off. out20 The first power source V out20 When power supply starts, the first transistor 40 and the second transistor 41 are damaged. out20 When power is continuously supplied to the first transistor 40 and the second transistor 41 , the control unit 31 controls the first switch element 50 and the second switch element 51 to be turned off to prevent the device characteristics of the first switch element 50 and the second switch element 51 from affecting the operation of the cascade circuit.

[0052] In some embodiments, the control unit 31 is configured to out20 Before stopping supplying power to the first transistor 40, the first switch element 50 and the second switch element 51 are controlled to be turned on. out20 The surge generated when the power supply is cut off affects the stacked circuit.

[0053] In some embodiments, the stacking circuit includes a third switch element 52 and a fourth switch element 53. The third switch element 52 is electrically connected between the first control terminal 403 and the ground terminal G20. The fourth switch element 53 is electrically connected between the second control terminal 413 and the ground terminal G20. The control unit 31 is electrically connected to the third switch element 52 and the fourth switch element 53, and the control unit 31 is used to control the third switch element 52 and the fourth switch element 53 to be turned on or off.

[0054] In some embodiments, under the control of the control unit 31, at least the first switch element 50 and the second switch element 51 need to be turned on before the third switch element 52 and the fourth switch element 53 are turned on. That is, the turn-on sequence of the first switch element 50, the second switch element 51, the third switch element 52 and the fourth switch element 53 can be the first switch element 50, the second switch element 51, the third switch element 52, the fourth switch element 53, or the first switch element 50 and the second switch element 51 are turned on at the same time and then the third switch element 52 and the fourth switch element 53 are turned on at the same time.

[0055] In some embodiments, the first switch element 50, the second switch element 51, the third switch element 52, the fourth switch element 53, the first transistor 40 and the second transistor 41 may be bipolar transistors or field effect transistors. In some embodiments, the first switch element 50, the second switch element 51, the third switch element 52, the fourth switch element 53, the first transistor 40 and the second transistor 41 are N-channel enhancement MOSFETs, the first input terminal 401 and the second input terminal 411 are drains, the first output terminal 402 and the second output terminal 412 are sources, and the first control terminal 403 and the second control terminal 413 are gates.

[0056] See also Figure 3 As shown, in some embodiments, the aforementioned self-protection circuit can be applied to a current mirror circuit 60. The current mirror circuit 60 is configured to receive a first power supply V out30 The current mirror circuit 60 includes a first transistor 61, a second transistor 62, a first switch element 63 and a control unit 32. The first transistor 61 includes a first input terminal 611, a first output terminal 612 and a first control terminal 613. The first control terminal 613 is electrically connected to the first input terminal 611. The first input terminal 611 is configured to receive a first power supply V out30 , the first output terminal 612 is electrically connected to the ground terminal G30. The second transistor 62 includes a second input terminal 621, a second output terminal 622 and a second control terminal 623, the first control terminal 613 is electrically connected to the second control terminal 623, and the second output terminal 622 is electrically connected to the ground terminal G30. The first switch element 63 is electrically connected to the first input terminal 611 and the ground terminal G30 respectively. The control unit 32 is electrically connected to the first switch element 63 and is configured to be connected to the first power supply V out30 Before supplying power to the first transistor 61, the first switch element 63 is controlled to be turned on, and the first power source V out30 After power is continuously supplied to the first transistor 61 , the first switch element 63 is controlled to be turned off.

[0057] The current mirror circuit 60 starts to receive the first power supply V out30 Before, the control unit 32 controls the first switch element 63 to be turned on, so that the first power source V out30 When entering the first transistor 61, the first power supply V out30 will flow along the first switch element 63 to the ground terminal G30, thereby preventing the first power source V out30 The moment when the current mirror circuit 60 is entered, the first transistor 61 or the second transistor 62 is damaged. out30 After continuously supplying power to the current mirror circuit 60 , the control unit 32 controls the first switch element 63 to be turned off, so as to reduce the influence of the element characteristics of the first switch element 63 on the operation of the current mirror circuit 60 .

[0058] In addition, in some embodiments, when the first power supply V out30 Before stopping supplying power to the current mirror circuit 60, the control unit 32 controls the first switch element 63 to be turned on to prevent the first power source V out30 When the power supply is stopped, the current mirror circuit 60 is negatively affected.

[0059] In some embodiments, the first transistor 61, the second transistor 62, and the first switch element 63 may be bipolar transistors or field effect transistors. In some embodiments, the first transistor 61, the second transistor 62, and the first switch element 63 are all N-channel enhancement MOSFETs, the first input terminal 611 and the second input terminal 621 are both drains, the first output terminal 612 and the second output terminal 622 are both sources, and the first control terminal 613 and the second control terminal 623 are both gates.

[0060] See also Figure 4 As shown, in some embodiments, the aforementioned self-protection circuit can be applied to an operational amplifier circuit. The operational amplifier circuit is configured to receive a first power supply V out40 The operational amplifier circuit includes a current mirror circuit 70, a first transistor 80, a first switch element 90, and a control unit 33.

[0061] The first transistor 80 includes a first input terminal 801, a first output terminal 802 and a first control terminal 803. The first input terminal 801 and the first control terminal 803 are electrically connected to the current mirror circuit 70 respectively. The first input terminal 801 is configured to receive a first power source V out40 The first output terminal 802 is electrically connected to the ground terminal G40. The first switch element 90 is electrically connected to the first input terminal 801 and the ground terminal G40. The control unit 33 is electrically connected to the first switch element 90 and is configured to out40 Before supplying power to the first transistor 80, the first switch element 90 is controlled to be turned on, and the first power source V out40 After power is continuously supplied to the first transistor 80 , the first switch element 90 is controlled to be turned off.

[0062] The operational amplifier circuit receives the first power supply V out40 Before that, the control unit 33 will first control the first switch element 90 to be turned on, so that the first power source V out40 The current flows through the first switch element 90 and then flows into the ground terminal G40, thereby preventing the first power source V out40 When the first power supply V out40 When power is continuously supplied to the operational amplifier circuit, the control unit 33 controls the first switch element 90 to be turned off, so that the element characteristics of the first switch element 90 will not affect the operation of the operational amplifier circuit.

[0063] In some embodiments, when the first power supply V out40 Before stopping supplying power to the operational amplifier circuit, the control unit 33 controls the first switch element 90 to be turned on to prevent the first power source V out40 When the power supply is stopped, it has a negative impact on the operational amplifier circuit.

[0064] In some embodiments, the current mirror circuit 70 of the operational amplifier circuit is configured to receive the second power supply V out50 The current mirror circuit 70 includes a second transistor 71, a third transistor 72 and a second switch element 73. The second transistor 71 includes a second input terminal 711, a second output terminal 712 and a second control terminal 713. The second control terminal 713 is electrically connected to the second input terminal 711. The second input terminal 711 is configured to receive a second power supply V out50 The second output terminal 712 is electrically connected to the ground terminal G40. The third transistor 72 includes a third input terminal 721, a third output terminal 722 and a third control terminal 723. The second control terminal 713 is electrically connected to the third control terminal 723. The third input terminal 721 is configured to receive a second power supply V out50 The third output terminal 722 is electrically connected to the ground terminal G40. The second switch element 73 is electrically connected to the third input terminal 721 and the ground terminal G40 respectively. The control unit 33 is electrically connected to the second switch element 73. The operation and embodiment of the current mirror circuit 70 are as mentioned above and will not be described again.

[0065] In some embodiments, the first transistor 80, the second transistor 71, the third transistor 72, the first switch element 90 and the second switch element 73 may be bipolar transistors or field effect transistors. In some embodiments, the first transistor 80, the second transistor 71, the third transistor 72, the first switch element 90 and the second switch element 73 are all N-channel enhancement MOSFETs. The first input terminal 801, the second input terminal 711 and the third input terminal 721 are all drains, the first output terminal 802, the second output terminal 712 and the third output terminal 722 are all sources, and the first control terminal 803, the second control terminal 713 and the third control terminal 723 are all gates.

[0066] According to the self-protection circuit of an embodiment of the present disclosure, the control unit 30 is used to control the first switch element 20 to be turned on or off, so that the self-protection circuit starts to receive the first power supply V out10 , or stop receiving the first power supply V out10 When the first switch element 20 is turned on, the self-protection circuit has a self-protection function. When the self-protection circuit continues to receive the first power supply V out10 When the self-protection circuit is turned off, the first switch element 20 is cut off, so that the element characteristics of the first switch element 20 will not affect the operation of the self-protection circuit.

Claims

1. A self-protection circuit, configured to receive a first power supply, the self-protection circuit comprising: a first transistor, comprising a first input terminal, a first output terminal and a first control terminal, the first input terminal being configured to receive the first power source, and the first output terminal being electrically connected to a ground terminal; a first switch element electrically connected to the first input terminal and the ground terminal; and A control unit is electrically connected to the first switch element and configured to control the first switch element to be turned on before the first power source supplies power to the first transistor, and to control the first switch element to be turned off after the first power source continues to supply power to the first transistor. 2 . The self-protection circuit as claimed in claim 1 , wherein the control unit controls the first switch element to be turned on before the first power source stops supplying power to the first transistor.

3. The self-protection circuit according to claim 1, further comprising: a second switch element, electrically connected between the first control terminal and the ground terminal; and a third switch element, electrically connected between the first power source and the first input terminal; The control unit is electrically connected to the second switch element and the third switch element respectively, so as to control the second switch element and the third switch element to be turned on or off respectively. 4 . The self-protection circuit as claimed in claim 3 , wherein the control unit controls the first switch element to be turned on before the first power source stops supplying power to the first transistor.

5. The self-protection circuit as described in claim 3, wherein the control unit controls the second switch element and the third switch element to be turned on so that the first power supply supplies power to the first transistor, and controls the second switch element and the third switch element to be turned off so that the first power supply does not supply power to the first transistor. 6 . The self-protection circuit as claimed in claim 3 , wherein the control unit controls the first switch element to be turned on before controlling the third switch element to be turned on.

7. A stacked circuit, configured to receive a first power source, the stacked circuit comprising: a first transistor, comprising a first input terminal, a first output terminal and a first control terminal, wherein the first input terminal is configured to receive the first power source; a second transistor, comprising a second input terminal, a second output terminal and a second control terminal, the first output terminal being electrically connected to the second input terminal, and the second output terminal being electrically connected to a ground terminal; a first switch element, electrically connected to the first input terminal and the ground terminal respectively; a second switch element, electrically connected to the second input terminal and the ground terminal respectively; and A control unit is electrically connected to the first switch element and the second switch element respectively, and is configured to control the first switch element and the second switch element to be turned on before the first power supply supplies power to the first transistor, and to control the first switch element and the second switch element to be turned off after the first power supply continues to supply power to the first transistor.

8. The stacked circuit as claimed in claim 7, comprising: a third switch element, electrically connected between the first control terminal and the ground terminal; and a fourth switch element, electrically connected between the second control terminal and the ground terminal; The control unit is electrically connected to the third switch element and the fourth switch element respectively, and the control unit is used to control the third switch element and the fourth switch element to be turned on or off respectively.

9. An operational amplifier circuit, configured to receive a first power supply, the operational amplifier circuit comprising: a current mirror circuit; a first transistor, comprising a first input terminal, a first output terminal and a first control terminal, the first input terminal and the first control terminal are electrically connected to the current mirror circuit respectively, the first input terminal is configured to receive the first power source, and the first output terminal is electrically connected to a ground terminal; a first switch element electrically connected to the first input terminal and the ground terminal; and A control unit is electrically connected to the first switch element and configured to control the first switch element to be turned on before the first power source supplies power to the first transistor, and to control the first switch element to be turned off after the first power source continues to supply power to the first transistor.

10. A current mirror circuit, configured to receive a first power supply, the current mirror circuit comprising: a first transistor, comprising a first input terminal, a first output terminal and a first control terminal, wherein the first input terminal is configured to receive the first power source, the first control terminal is electrically connected to the first input terminal, and the first output terminal is electrically connected to a ground terminal; a second transistor, comprising a second input terminal, a second output terminal and a second control terminal, the first control terminal being connected to the second control terminal, and the second output terminal being electrically connected to the ground terminal; a first switch element, electrically connected between the first input terminal and the ground terminal; and A control unit is electrically connected to the first switch element and configured to control the first switch element to be turned on before the first power source supplies power to the first transistor, and to control the first switch element to be turned off after the first power source continues to supply power to the current mirror circuit.

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