Successive approximation type analog-to-digital converter for wide voltage range sampling and conversion method

Abstract

The invention provides a wide voltage range sampling successive approximation type analog-to-digital converter and a conversion method, and the method comprises the steps: selecting a multiplexing I / O channel to configure input voltage signals with different analog quantities, and configuring a plurality of programmable switch capacitors with corresponding amplification factors according to the range of the input voltage signals, the PGA amplification factor configuration module is used for configuring switching logic to control the amplification factor of the sampling capacitor, the operational amplifier circuit is used for amplifying a sampling voltage signal output by the sampling capacitor and then outputting the sampling voltage signal to the SAR-ADC module, and the SAR-ADC module is used for converting an input analog voltage signal into a digital signal with required precision by using a binary search principle and outputting the digital signal. According to the invention, the input voltage signal is amplified according to the required amplification gear and then is sent to the rear-stage SAR-ADC module for successive approximation type analog-to-digital conversion, so that the effects of realizing wide voltage range sampling, being suitable for differential sampling of different voltage inputs and effectively reducing conversion errors are achieved.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and specifically to a successive approximation analog-to-digital converter and conversion method with wide voltage range sampling. Background Technology

[0002] A Successive Approximation Register (SAR) analog-to-digital converter (ADC) is an ADC that uses a binary algorithm to search and gradually convert analog signals into digital signals. Compared to traditional ADCs, its circuit principle is simpler, its circuit structure is less complex, and it has many advantages such as low power consumption, small size, high precision, moderate resolution and speed, and short sampling delay. It is an economical ADC implementation solution and is therefore widely used in embedded systems, such as the MCU / SOC design of portable handheld devices like instruments and meters.

[0003] See Figure 1 , Figure 1 This is a typical SAR-ADC circuit structure diagram, which includes: a capacitor DAC circuit, a comparator circuit, a SAR logic circuit, and a data latch. In the capacitor DAC circuit, the voltage on the sampling capacitor is compared with the reference voltage step by step from the high bit to the low bit through the comparator circuit. The SAR logic circuit provides additional digital code to the internal DAC in each clock cycle and obtains the corresponding digital code based on the comparison result between the voltage on the sampling capacitor and the internal DAC voltage. Until the conversion is completed, the corresponding digital signal is output and encoded into the digital latch for storage.

[0004] However, the typical SAR-ADC circuit described above has the following limitations when used in practical measurement systems:

[0005] 1) In single-ended sampling applications, the measurement range is only 0 to VREF. However, the power supply VCC of the chip system and IO is usually higher than the input reference voltage VREF, which causes the ADC to fail to correctly sample the system power supply voltage VCC.

[0006] 2) In differential sampling applications, the measurement range is -VREF to VREF. However, the common-mode range of differential sampling is limited at this time. The input differential signal cannot be a high level near VREF at the same time. This means that the ADC circuit must be limited to specific application scenarios. Otherwise, additional peripheral circuits are needed to solve the problem, making the circuit design more complicated.

[0007] 3) Due to the inherent accuracy error of the ADC, when acquiring small signals, such as voltage signals close to 0V or 100uV, the circuit may exhibit relatively large deviations.

[0008] Therefore, there is a need for a successive approximation analog-to-digital converter and conversion method that can achieve wide voltage range sampling, is suitable for differential sampling of different voltage inputs, and effectively reduces conversion errors. Summary of the Invention

[0009] This invention provides a successive approximation analog-to-digital converter and conversion method with wide voltage range sampling, which is mainly used to solve the problems of limited sampling range and limited sampling accuracy of existing successive approximation analog-to-digital converters, thereby achieving the effect of wide voltage range sampling, differential sampling applicable to different voltage inputs, and effectively reducing conversion errors.

[0010] The present invention achieves the above objectives through the following technical solutions:

[0011] A successive approximation analog-to-digital converter (ADC) with wide voltage range sampling includes an I / O interface module, a PGA module, a PGA amplification factor configuration module, and a SAR-ADC module. The I / O interface module has multiplexed I / O channels for configuring different analog input voltage signals by selecting the multiplexed I / O channels. The PGA module includes a sampling circuit, a PGA amplification circuit, and an operational amplifier circuit. The sampling circuit includes a sampling switch and a sampling capacitor. The sampling capacitor is connected to the input voltage signal through the sampling switch, and its two ends are connected in parallel with the PGA amplification circuit. The PGA amplification circuit includes several programmable switched capacitors connected in parallel. Each programmable switched capacitor is configured with a corresponding amplification factor according to the range of the input voltage signal. The PGA amplification factor configuration module configures the switching logic to control the amplification factor of the sampling capacitor. The operational amplifier circuit is connected to the sampling capacitor and amplifies the sampled voltage signal output by the sampling capacitor before outputting it to the SAR-ADC module. The SAR-ADC module uses a binary search principle to convert the input analog voltage signal into a digital signal of the required precision for output.

[0012] A further approach is that the I / O interface module adopts a multiplexed I / O model, which allows a single thread to monitor multiple multiplexed I / O channels simultaneously.

[0013] A further embodiment is that the programmable switched capacitor includes a capacitor and two control switches with opposite switching logic, wherein the capacitor is connected in parallel and in series with the two control switches, respectively.

[0014] As can be seen, the two control switches are used to realize whether the programming capacitor is short-circuited and whether the programming capacitor is connected as a sampling capacitor, thereby realizing the entry and exit of the capacitor in the circuit.

[0015] A further embodiment is that the PGA amplifier circuit includes three sets of programmable switched capacitors, and the amplification factor relationship of their capacitors is as follows:

[0016] C10=C, C11=3C, C12=4C, C13=16C

[0017] Wherein, C10 is the sampling capacitor value, C11 to C13 are the sampling capacitor values ​​in the three groups of programmable switched capacitors respectively, and C is the reference capacitor value.

[0018] A further embodiment is that the operational amplifier circuit includes a multi-channel amplifier and its feedback control circuit. The multi-channel amplifier receives the sampled voltage signal and a common-mode voltage signal. The feedback control circuit includes a charge transfer capacitor and several switching switches. The charge transfer capacitor is connected in parallel between the input and output terminals of the multi-channel amplifier. The several switching switches are connected in series or in parallel across the charge transfer capacitor, respectively, to control the circuit to perform differential common-mode negative feedback or sampled charge transfer by changing the switch state to switch the short-circuit or connection of the charge transfer capacitor.

[0019] A further embodiment is that the PGA amplification factor configuration module includes a configuration register and a PGA decoding circuit. The amplification gain code is input through the configuration register, and the PGA decoding circuit generates the switching logic by the amplification gain code.

[0020] The amplification gain encoding corresponds one-to-one with the amplification levels of the PGA module, including:

[0021] GAIN<1:0>=00 corresponds to the lowest setting, at which point the magnification is C10 / C3=1.

[0022] GAIN<1:0>=01 corresponds to the second lowest setting, at which point the magnification is (C10+C11) / C3=4.

[0023] GAIN<1:0>=10 corresponds to the second-highest magnification level, at which point the magnification factor is (C10+C11+C12) / C3=8.

[0024] GAIN<1:0>=11 corresponds to the highest gear level, at which point the magnification is (C10+C11+C12+C13) / C3=24.

[0025] Wherein, C3 is the charge transfer capacitance value, and its value is: C3 = C.

[0026] A further embodiment is that the PGA module is provided with a first PGA circuit and a second PGA circuit with identical circuit structures. The first PGA circuit and the second PGA circuit are respectively connected to the first input voltage signal and the second input voltage signal from the I / O interface module. Both of them include the sampling circuit and the PGA amplification circuit, and respectively output the first sampled voltage signal and the second voltage sampled signal to the non-inverting input terminal and the inverting input terminal of the multi-channel amplifier. The inverting output terminal of the multi-channel amplifier outputs the first voltage amplification signal and the non-inverting output terminal outputs the second voltage amplification signal to the input terminal of the SAR-ADC module.

[0027] A further approach is that, in single-ended non-amplification mode, the first PGA circuit receives a first input voltage signal from the I / O interface module, and the second PGA circuit receives a center-level signal. At this time, the maximum voltage sampling value of the SAR-ADC module is:

[0028] VMAX = VCL + VREF

[0029] Wherein, VCL is the center level signal value, and VREF is the reference voltage value of the ADC input in the SAR-ADC module.

[0030] A further approach is that, in single-ended amplification mode, the first PGA circuit receives a first input voltage signal from the I / O interface module, and the second PGA circuit receives a zero-level signal. At this time, the SAR-ADC module gradually approximates the true input voltage value:

[0031]

[0032] Wherein, VI is the first input voltage signal value, N is the amplification factor of the PGA amplification circuit, and ΔV is the conversion error of the circuit.

[0033] A successive approximation analog-to-digital converter (ADC) with wide voltage range sampling, applied to the aforementioned wide voltage range sampling successive approximation ADC, includes:

[0034] S1: The system is powered on, and the input enable signal enables the analog-to-digital converter and establishes the system's bias current and voltage.

[0035] S2: Start the analog-to-digital converter, select the amplification mode by controlling the state of the sampling switch, sample the input voltage signal by the sampling capacitor, and short-circuit the input and output terminals of the multi-channel amplifier by controlling the state of the switching switch to form differential common-mode negative feedback and output common-mode voltage signal.

[0036] S3: By controlling the state of the sampling switch, the sampling capacitor is put into a discharging state. At the same time, the programmable switching capacitor is in the corresponding amplification phase according to its configuration. By controlling the state of the switching switch, the charge transfer capacitor is connected. The charge transfer capacitor transfers the sampling charge output by the sampling capacitor and outputs a sampling voltage signal to the SAR-ADC module.

[0037] S4: The programmable switched capacitor is kept in its amplified phase, and the sampling switch is controlled to be turned off. The SAR-ADC module performs analog-to-digital conversion on the sampled voltage signal.

[0038] Therefore, the present invention has the following beneficial effects:

[0039] 1. This invention, by setting up a PGA amplification circuit and a PGA amplification factor configuration module, amplifies the input voltage signal according to the required amplification level before sending it to the subsequent SAR-ADC module for successive approximation analog-to-digital conversion. Compared to the traditional scheme that directly performs analog-to-digital conversion with a measurement range of only 0 to VREF, this invention can measure a maximum value of VCL+VREF in single-ended sampling applications, and can acquire voltages higher than VREF. For example, this invention is suitable for scenarios where the power supply VCC of the chip system and I / O is higher than the input reference voltage VREF, enabling the analog-to-digital converter to correctly sample the system's power supply voltage VCC.

[0040] 2. This invention utilizes an I / O interface module with multiplexed channels and a PGA module with two symmetrically structured PGA circuits to configure different analog input voltage signals by selecting different multiplexed channels. Compared to traditional analog-to-digital conversion schemes that only measure the range from -VREF to VREF, this invention can acquire a set of differential signals close to the power supply end. For example, it can differentially acquire the voltage across the resistor at the battery terminal that measures the battery charging and discharging current, thereby calculating the battery charging and discharging current.

[0041] 3. This invention amplifies small signals using an integrated switched-capacitor PGA before sending them to a subsequent SAR-ADC module for successive approximation analog-to-digital conversion. This allows the converted voltage to be recalculated using the amplification factor, resulting in an input signal with minimal conversion error. For example, a traditional analog-to-digital converter has a conversion error of 2mV, while this invention amplifies the signal by 24 times, reducing the error to only 0.083mV. This demonstrates that this invention significantly reduces conversion error and improves measurement accuracy, enabling high-precision acquisition of weak small signals.

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the SAR-ADC circuit structure in the existing technology.

[0044] Figure 2 This is a schematic diagram of a successive approximation analog-to-digital converter in an embodiment of the present invention without single-ended amplification.

[0045] Figure 3 This is a schematic diagram of a successive approximation analog-to-digital converter in single-ended amplification according to an embodiment of the present invention.

[0046] Figure 4 This is a schematic diagram of a successive approximation analog-to-digital converter in differential amplification according to an embodiment of the present invention.

[0047] Figure 5 This is a flowchart of the successive approximation analog-to-digital conversion method for wide voltage range sampling according to an embodiment of the present invention.

[0048] Figure 6 This is a system timing diagram of a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0049] Figure 7 This is a schematic diagram of the state of the signal sampling switch in step T1 of an embodiment of the present invention.

[0050] Figure 8 This is a schematic diagram of the state of the signal sampling switch in step T2 of an embodiment of the present invention.

[0051] Figure 9 This is a schematic diagram of the state of the signal sampling switch in step T3 of an embodiment of the present invention. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0053] An embodiment of a successive approximation analog-to-digital converter with wide voltage range sampling

[0054] See Figure 2-4This invention relates to a successive approximation analog-to-digital converter (ADC) with wide voltage range sampling, comprising an I / O interface module 10, a PGA module 20, a PGA amplification factor configuration module 30, and a SAR-ADC module 40. The I / O interface module 10 has multiplexed I / O channels for configuring different analog input voltage signals by selecting the multiplexed I / O channels. The PGA module 20 includes a sampling circuit, a PGA amplification circuit, and an operational amplifier circuit. The sampling circuit includes a sampling switch and a sampling capacitor. The sampling capacitor is connected to the input voltage signal through the sampling switch, and its two ends are connected to the PGA amplification factor configuration module 30. An operational amplifier circuit is connected in parallel. The PGA amplifier circuit includes several programmable switched capacitors connected in parallel. Each of the programmable switched capacitors is configured with a corresponding amplification factor according to the range of the input voltage signal. The switching logic is configured by the PGA amplification factor configuration module 30 to control the amplification factor of the sampling capacitor. The operational amplifier circuit is connected to the sampling capacitor and is used to amplify the sampling voltage signal output by the sampling capacitor and output it to the SAR-ADC module 40. The SAR-ADC module 40 is used to convert the input analog voltage signal into a digital signal of the required precision using the binary search principle.

[0055] See Figure 1 Specifically, in this embodiment, the SAR-ADC module 40 adopts the existing common SAR-ADC structure, including: a capacitor DAC circuit 41, a comparator circuit 42, a SAR logic circuit 43, and a data latch 44. The capacitor DAC circuit 41 is used to perform digital-to-analog conversion on the sampled and amplified digital signal, and to sample and hold it through a sampling capacitor. Then, the voltage on the sampling capacitor in the capacitor DAC circuit 41 is compared with the internal DAC voltage from the high bit to the low bit through the comparator circuit 42, and comparison voltages are generated one by one to perform analog-to-digital conversion in a gradually approximating manner. The SAR logic circuit 43 provides additional code to the internal DAC in each clock cycle and generates corresponding digital code according to each comparison voltage until the conversion is completed. The code is then binary encoded according to a certain rule and converted into a binary or multi-valued digital signal stream, which is output to the digital latch for temporary storage.

[0056] Specifically, the successive approximation analog-to-digital converter in this embodiment further includes a digital calibration module 50 and a data register 60. The digital calibration module 50 is used to analyze and correct the digital output of the digital signal output by the SAR-ADC module 40 through a digital calibration logic algorithm, and output the calibrated digital signal to the data register 60 for storage.

[0057] In this embodiment, the I / O interface module 10 adopts a multiplexed I / O model, which allows a single thread to monitor multiple multiplexed I / O channels simultaneously.

[0058] In each specific embodiment, the I / O interface module 10 adopts a multiplexer (MUX), which can select a signal from multiple analog input signals and forward it, and can output different selected signals to the same output line, thereby making full use of the capacity of the communication channel and greatly reducing the cost of the system.

[0059] In this embodiment, the programmable switched capacitor includes a capacitor and two control switches with opposite switching logic. The capacitor is connected in parallel and in series with the two control switches, respectively.

[0060] Specifically, in this embodiment, for example, in the first group of programmable switched capacitors, capacitor C11 is connected in parallel with the second control switch S11B. One end of C11 is connected to one end of the sampling capacitor C10, and the other end is connected in series with the first control switch S11A and then connected to the other end of the sampling capacitor C10. Furthermore, the second group of programmable switched capacitors includes capacitor C12, control switches S12A and S12B, and the third group of programmable switched capacitors includes capacitor C13, control switches S13A and S13B. The circuit structures of the second and third groups of programmable switched capacitors are consistent with the structure of the first group, and will not be described again here.

[0061] In this embodiment, the PGA amplifier circuit includes three sets of programmable switched capacitors, and the amplification factor relationship of their capacitors is as follows:

[0062] C10=C, C11=3C, C12=4C, C13=16C

[0063] Wherein, C10 is the sampling capacitor value, C11 to C13 are the sampling capacitor values ​​in the three groups of programmable switched capacitors respectively, and C is the reference capacitor value.

[0064] Specifically, in this embodiment, the addition of the above three sets of programmable switched capacitors can provide four amplification levels for the PGA module 20, including: the lowest level, the second lowest level, the second highest level, and the highest level. The lowest level is C10 = C, that is, the amplification factor remains unchanged; the second lowest level is C10 + C11 = 4C, that is, amplification by 4 times; the second lowest level is C10 + C11 + C12 = 8C, that is, amplification by 8 times; and the highest level is C10 + C11 + C12 + C13 = 24C, that is, amplification by 24 times.

[0065] Specifically, the composition of the PGA amplifier circuit described in this embodiment is only exemplary and not the only way. The number and size relationship of the programmable switched capacitors connected in parallel can be adjusted according to the required PGA amplification level.

[0066] Specifically, the aforementioned PGA amplifier circuit is the capacitor gain amplifier circuit in the first PGA circuit. The second PGA circuit is symmetrical to the first PGA circuit, and its PGA amplifier circuit includes a sampling capacitor C20 and three sets of programmable switched capacitors: the first set of programmable switched capacitors includes capacitor C21, control switches S21A and S21B; the second set of programmable switched capacitors includes capacitor C22, control switches S22A and S22B; and the third set of programmable switched capacitors includes capacitor C23, control switches S23A and S23B. Its structure and amplification relationship of capacitance values ​​are consistent with those of the aforementioned first PGA circuit, and will not be described again here.

[0067] In this embodiment, the operational amplifier circuit includes a multi-channel amplifier (OPA) and its feedback control circuit. The OPA receives the sampled voltage signal and a common-mode voltage signal. The feedback control circuit includes a charge transfer capacitor and several switching switches. The charge transfer capacitor is connected in parallel between the input and output terminals of the OPA. The switching switches are connected in series or in parallel across the charge transfer capacitor to control the circuit to perform differential common-mode negative feedback or sampled charge transfer by changing the switch state to switch the charge transfer capacitor between short circuit and connection.

[0068] Specifically, the feedback control circuit in this embodiment includes switching switches S3, S5 and S7. One end of the charge transfer capacitor C3 is connected to the non-inverting input of the multi-channel amplifier OPA through switching switch S3, and the other end is connected to the inverting output of the multi-channel amplifier OPA. Switches S5 and S7 are connected in parallel on the upper and lower sides of the charge transfer capacitor, respectively.

[0069] The multi-channel amplifier OPA also has the above-mentioned feedback control circuit connected in parallel between the inverting input terminal and the non-inverting output terminal, including charge transfer capacitor C4, switching switches S4, S6 and S8. Its circuit structure is the same as the above structure, and will not be described again here.

[0070] In this embodiment, the PGA amplification factor configuration module 30 includes a configuration register 31 and a PGA decoding circuit 32. The amplification gain code is input through the configuration register 31 and the PGA decoding circuit 32 generates the switching logic from the amplification gain code.

[0071] Specifically, in this embodiment, the capacitor relationships are as follows: C10 = C20 = C, C11 = C21 = 3C, C12 = C22 = 4C, C13 = C23 = 16C, C3 = C4 = C10 = C20 = C. Control switches S11A, S11B, S12A, S12B, S13A, S13B and S21A, S21B, S22A, S22B, S23A, S23B are generated by software through configuration register 31GAIN<1:0> and PGA decoding circuit 32, where A and B represent logical opposites. For example, when S11A is on, S11B is off. The one-to-one correspondence between the amplification gain code and the amplification levels of the PGA module 20, as well as the switch states corresponding to each switch logic, are as follows:

[0072] GAIN<1:0>=00 corresponds to the lowest gear. At this time, the switch logic is: S11A=0, S12A=0, S13A=0, S21A=0, S22A=0, S23A=0, and its amplification factor is C10 / C3=1.

[0073] GAIN<1:0>=01 corresponds to the second lowest gear. At this time, the switching logic is: S11A=1, S12A=0, S13A=0, S21A=1, S22A=0, S23A=0, and its amplification factor is (C10+C11) / C3=4.

[0074] GAIN<1:0>=10 corresponds to the second-highest position. At this time, the switching logic is: S11A=1, S12A=1, S13A=0, S21A=1, S22A=1, S23A=0, and its amplification factor is (C10+C11+C12) / C3=8.

[0075] GAIN<1:0>=11 corresponds to the highest gear position. At this time, the switching logic is: S11A=1, S12A=1, S13A=1, S21A=1, S22A=1, S23A=1, and its amplification factor is (C10+C11+C12+C13) / C3=24.

[0076] Wherein, C3 is the charge transfer capacitance value, and its value is: C3 = C.

[0077] The switching logic of the control switch is 1 to represent that the switch is on and 0 to represent that the switch is off.

[0078] In this embodiment, the PGA module 20 is provided with a first PGA circuit and a second PGA circuit with identical circuit structures. The first PGA circuit and the second PGA circuit are respectively connected to the first input voltage signal and the second input voltage signal from the I / O interface module 10. Both of them include the sampling circuit and the PGA amplification circuit, and respectively output the first sampling voltage signal and the second voltage sampling signal to the non-inverting input terminal and the inverting input terminal of the multi-channel amplifier OPA. The inverting output terminal of the multi-channel amplifier OPA outputs the first voltage amplification signal and the non-inverting output terminal outputs the second voltage amplification signal to the input terminal of the SAR-ADC module 40.

[0079] Specifically, the sampling circuit of the first PGA circuit in this embodiment includes a sampling switch S1 and a sampling capacitor C10. The sampling capacitor C10 is connected to a multiplexed I / O channel of the I / O interface module 10 through the sampling switch S1. The sampling circuit of the first PGA circuit includes a sampling switch S2 and a sampling capacitor C20, and its structure is the same as that of the first PGA circuit described above, so it will not be described again here.

[0080] A switch S9 is provided between sampling capacitor C10 and sampling capacitor C20, which is used to turn on after the sampling capacitors are charged, so as to connect sampling capacitors C10 and C20 in series for sampling charge transfer.

[0081] See Figure 2 In this embodiment, when in single-ended non-amplification mode, the first PGA circuit receives a first input voltage signal VIP from the I / O interface module 10, and the second PGA circuit receives a center level signal VCL. At this time, the maximum voltage sampling value of the SAR-ADC module 40 is:

[0082] VMAX = VCL + VREF

[0083] Wherein, VCL is the center level signal value, and VREF is the reference voltage value of the ADC input in the SAR-ADC module 40.

[0084] As can be seen, compared with the traditional single-ended sampling application with a measurement range of only 0 to VREF, the maximum measurement value of the present invention can reach VCL+VREF, thus making it applicable to scenarios where the power supply VCC of the chip system and I / O is higher than the input reference voltage VREF, enabling the analog-to-digital converter to correctly sample the system's power supply voltage VCC.

[0085] See Figure 3 In this embodiment, when in single-ended amplification mode, the first PGA circuit receives the first input voltage signal VIP from the I / O interface module 10, and the second PGA circuit receives the zero-level signal AGND. At this time, the SAR-ADC module 40 gradually approaches the true value of the input voltage:

[0086]

[0087] Wherein, VI is the first input voltage signal value, N is the amplification factor of the PGA amplification circuit, and ΔV is the conversion error of the circuit.

[0088] Specifically, this embodiment uses an example to illustrate the single-ended amplification mode. If a traditional analog-to-digital converter is used to directly acquire a 10mV voltage, the conversion error is ±2mV. If the present invention is used to first enable 24x amplification before ADC conversion, the converted voltage is:

[0089]

[0090] As can be seen, the analog-to-digital converter of this invention reduces the conversion error to only 0.083mV, greatly improving the measurement accuracy.

[0091] See Figure 4 Specifically, in this embodiment, when in differential amplification mode, the first PGA circuit and the second PGA circuit respectively access the first input voltage signal VIP and the second input voltage signal VIN from different multiplexed I / O channels of the I / O interface module 10. For example, the first input voltage signal VIP is configured as channel AN7, and the second input voltage signal VIN is configured as channel AN6.

[0092] The aforementioned differential amplifier architecture is widely used to measure the voltage across the SENSE resistor between the BATS and BAT of the CHARGER switch. By dividing the measured voltage by the SENSE resistor, the charging current of the CHARGER switch can be obtained.

[0093] An embodiment of a successive approximation analog-to-digital conversion method with wide voltage range sampling

[0094] See Figure 5 This invention relates to a successive approximation analog-to-digital converter (ADC) with wide voltage range sampling, applied to a such ADC, comprising:

[0095] S1: The system is powered on. The input enable signal EN_ADC enables the analog-to-digital converter and establishes the system's bias current and voltage.

[0096] See Figure 6 Specifically, in this embodiment, a time difference T0 is set between the input enable signal EN_ADC and the start of the analog-to-digital converter.

[0097] S2: Start the analog-to-digital converter, select the amplification mode by controlling the state of the sampling switch, sample the input voltage signal by the sampling capacitor, and short-circuit the input and output terminals of the multi-channel amplifier OPA by controlling the state of the switching switch to form differential common-mode negative feedback, and output common-mode voltage signal VCM.

[0098] See Figure 6 Specifically, in this embodiment, the input voltage signal is sampled using a switched capacitor during the T1 time period. See [link to documentation]. Figure 7 During time period T1, sampling switches S1 and S2 are on, switch S9 is off, and switching switches S7 and S8 are on, S3 and S4 are off, while S5 and S6 are on. Taking a single-ended, non-amplified application scenario as an example, the on of sampling switch S1 causes sampling capacitor C10 to sample the signal, shorting the input and output terminals of the multi-channel amplifier OPA. At this time, due to differential common-mode negative feedback, both the input and output levels are common-mode voltage signals VCM.

[0099] S3: By controlling the state of the sampling switch, the sampling capacitor is put into a discharging state. At the same time, the programmable switching capacitor is in the corresponding amplification phase according to its configuration. By controlling the state of the switching switch, the charge transfer capacitor is connected. The charge transfer capacitor transfers the sampling charge output by the sampling capacitor and outputs a sampling voltage signal to the SAR-ADC module 40.

[0100] See Figure 6 Specifically, in this embodiment, charge transfer occurs during the T2 time period. See [link to documentation]. Figure 8 During time period T2, sampling switches S1 and S2 are open, switch S9 is on, and switching switches S3 and S4 are on, while S5 and S6 are off, and S7 and S8 are off. Specifically, the on-state of switching switch S3 connects sampling capacitor C10 and charge transfer capacitor C3 (and the on-state of switching switch S4 connects sampling capacitor C20 and charge transfer capacitor C4), thereby transferring the sampled charge.

[0101] According to the law of conservation of charge, we can obtain:

[0102] (VIP-VCL)*C10=(VOP-VON)*C3

[0103] Wherein, VIP and VCL are the values ​​of the first input voltage signal and the second input voltage signal, respectively, and VOP and VON are the voltage values ​​output from the inverting output terminal and the non-inverting output terminal of the multi-channel amplifier OPA, respectively.

[0104] Specifically, in this embodiment, when in single-ended non-amplification mode, according to the law of conservation of charge, we can obtain:

[0105] VOP-VON = VIP-VCL

[0106] During the T2 time period, the SAR-ADC module 40 samples the sampling voltage signals VOP and VON.

[0107] S4: The programmable switched capacitor is kept in its amplified phase, and the sampling switch is controlled to be turned off. The SAR-ADC module 40 performs analog-to-digital conversion on the sampled voltage signal.

[0108] See Figure 6 Specifically, in this embodiment, the ADC phase conversion is performed during the T3 time period. See [link / reference]. Figure 9 The programmable switched capacitor is kept in its amplified phase, but at this time the sampling switch of the ADC in the SAR-ADC module 40 is turned off, thereby converting the sampled voltage signal VOP and the VON signal.

[0109] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A successive approximation analog-to-digital converter for sampling over a wide voltage range, characterized in that: include: An I / O interface module, a PGA module, a PGA amplification factor configuration module and a SAR-ADC module, wherein the I / O interface module is provided with a multiplexed I / O channel for configuring input voltage signals of different analog quantities by selecting the multiplexed I / O channel, the PGA module comprises a sampling circuit, a PGA amplification circuit and an operational amplifier circuit, the sampling circuit comprises a sampling switch and a sampling capacitor, the sampling capacitor is connected to the input voltage signal through the sampling switch, and its two ends are connected in parallel with the PGA amplification circuit, the PGA amplification circuit comprises a plurality of programmable switch capacitors connected in parallel, the plurality of programmable switch capacitors are respectively configured with corresponding amplification factors according to the range of the input voltage signal, and the switch logic is configured by the PGA amplification factor configuration module to control the amplification factor of the sampling capacitor, the operational amplifier circuit is connected to the sampling capacitor, and is used to amplify the sampling voltage signal output by the sampling capacitor and then output it to the SAR-ADC module, and the SAR-ADC module is used to convert the input analog voltage signal into a digital signal of required accuracy by using the binary search principle for output.

2. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 1, characterized in that: The I / O interface module adopts a multiplexed I / O model, which allows a single thread to monitor multiple multiplexed I / O channels simultaneously.

3. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 1, characterized in that: The programmable switch capacitor includes a capacitor and two control switches with opposite switching logics. The capacitor is connected in parallel and in series with the two control switches respectively.

4. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 3, characterized in that: The PGA amplifier circuit includes three groups of programmable switch capacitors, and the relationship of the amplification multiples of the capacitors is: C10=C, C11=3C, C12=4C, C13=16C Among them, C10 is the sampling capacitance value, C11 to C13 are respectively the sampling capacitance values ​​in the three groups of programmable switch capacitors, and C is the reference capacitance value.

5. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 4, characterized in that: The operational amplifier circuit includes a multi-channel amplifier and a feedback control circuit thereof. The multi-channel amplifier inputs the sampling voltage signal and a common-mode voltage signal. The feedback control circuit includes a charge transfer capacitor and a plurality of switching switches. The charge transfer capacitor is connected in parallel between the input and output ends of the multi-channel amplifier. The plurality of switching switches are respectively connected in series or in parallel at both ends of the charge transfer capacitor, and are used to control the circuit to perform differential common-mode negative feedback or sampling charge transfer by changing the switch state to switch the short-circuit or connection of the charge transfer capacitor.

6. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 5, characterized in that: The PGA amplification factor configuration module includes a configuration register and a PGA decoding circuit, and the amplification gain code is input through the configuration register, and the amplification gain code is converted into the switch logic through the PGA decoding circuit; The amplification gain code corresponds one-to-one to the amplification gear of the PGA module, including: GAIN<1:0>=00 corresponds to the lowest gear, at which time the magnification is C10 / C3=1; GAIN<1:0>=01 corresponds to the second lowest gear, and the amplification factor is (C10+C11) / C3=4; GAIN<1:0>=10 corresponds to the second highest position, and the amplification factor is (C10+C11+C12) / C3=8; GAIN<1:0>=11 corresponds to the highest gear, and the amplification factor is (C10+C11+C12+C13) / C3=24; Wherein, C3 is the charge transfer capacitance value, and its value is: C3=C.

7. The successive approximation analog-to-digital converter for wide voltage range sampling according to any one of claims 1 to 6, characterized in that: The PGA module is provided with a first PGA circuit and a second PGA circuit with the same circuit structure. The first PGA circuit and the second PGA circuit are respectively connected to the first input voltage signal and the second input voltage signal from the I / O interface module. Both of them include the sampling circuit and the PGA amplification circuit, and output the first sampling voltage signal and the second voltage sampling signal to the non-inverting input terminal and the inverting input terminal of the multi-channel amplifier respectively. The inverting output terminal of the multi-channel amplifier outputs the first voltage amplified signal, and the non-inverting output terminal outputs the second voltage amplified signal to the input terminal of the SAR-ADC module.

8. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 7, characterized in that: When in the single-ended non-amplification mode, the first PGA circuit receives a first input voltage signal from the I / O interface module, and the second PGA circuit receives a center level signal. At this time, the maximum voltage sampling value of the SAR-ADC module is: VMAX=VCL+VREF Among them, VCL is the center level signal value, and VREF is the reference voltage value of the ADC input in the SAR-ADC module.

9. The successive approximation analog-to-digital converter for wide voltage range sampling according to claim 7, characterized in that: When in single-ended amplification mode, the first PGA circuit receives a first input voltage signal from the I / O interface module, and the second PGA circuit receives a zero-level signal. At this time, the SAR-ADC module gradually approaches the true value of the input voltage: Among them, VI is the first input voltage signal value, N is the amplification factor of the PGA amplifier circuit, and ΔV is the conversion error of the circuit.

10. A successive approximation analog-to-digital conversion method for wide voltage range sampling, characterized in that: A successive approximation analog-to-digital converter for wide voltage range sampling as claimed in any one of claims 1 to 9, comprising: S1: Power on the system, input an enable signal to enable the analog-to-digital converter, and establish the bias current and voltage of the system; S2: starting the analog-to-digital converter, selecting an amplification mode by controlling the state of a sampling switch, the sampling capacitor samples the input voltage signal, and short-circuits the input and output terminals of the multi-channel amplifier by controlling the state of the switching switch to form a differential common-mode negative feedback, and outputs a common-mode voltage signal; S3: the sampling capacitor is in a discharging state by controlling the state of the sampling switch, and the programmable switch capacitor is in a corresponding amplification phase according to its configuration, and the charge transfer capacitor is connected by controlling the state of the switching switch, and the charge transfer capacitor transfers the sampling charge output by the sampling capacitor, and outputs a sampling voltage signal to the SAR-ADC module; S4: maintaining the programmable switch capacitor in its amplification phase, and controlling the sampling switch to be disconnected, and the SAR-ADC module performs analog-to-digital conversion on the sampled voltage signal.

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