A high-speed column-level single-slope analog-to-digital converter and a conversion method thereof

Abstract

The present application relates to the field of analog-digital converter, in particular to a high-speed column-level single-slope analog-digital converter and a conversion method thereof, the converter comprising two or more column-level analog-digital converter circuits, a row fullness judging circuit and a slope generator; the conversion method comprising reading a frame of pixel signals to be processed and quantizing the pixel signals; connecting the pixel signals to the column-level analog-digital converter; quantizing each column of pixels in the row in parallel; resetting the slope generator when the row fullness judging circuit is working; judging whether each row of pixels in the frame of image has been quantized or not, and processing the pixel signals of the next row or the next frame according to the judgment result. The present application optimizes the quantization process of ADC and the row time, reduces the frame time and further improves the frame rate of CMOS image sensor.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converters, and more specifically to a high-speed column-level single-slope analog-to-digital converter and its conversion method. Background Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors (CIS) are an important component of machine vision systems.

[0003] As a crucial component in data conversion within CMOS image sensors, the ADC (Analog-to-Digital Converter) directly impacts key performance indicators such as accuracy and speed of CIS products.

[0004] Currently, applications targeting high-speed targets place high demands on the speed of image sensors (CIS), specifically the readout frame rate. High-speed CIS designs primarily employ a column-level ADC architecture. This architecture offers advantages such as multi-channel parallel readout, small chip area, low power consumption, and low noise. Individual ADCs often utilize a simple and consistent SS (single-slope) ADC structure, combined with a column-level ADC architecture, achieving high speed and small footprint. The frame rate of a CMOS image sensor is related to the time required for the ADC to convert one frame of image data, i.e., the frame time. A column-level single-slope analog-to-digital converter can effectively shorten the frame time through multi-channel parallel processing, effectively dividing the frame time into multiple row times, thereby improving the CIS frame rate. Figure 1 The diagram shown is a chip structure diagram of a prior art CMOS image sensor, such as... Figure 2 As shown Figure 1 The timing diagram of the chip shown is illustrated. Common circuit architectures for reducing line time include multi-slope SS-ADCs, multi-ramp SS-ADCs, and SS-ADCs combined with time-to-digital converters (TDCs).

[0005] In existing technologies, such as the multi-slope SS-ADC described in patent publication number CN114567738A, the scheme decomposes a single slope quantization process into two parts, achieving two-step coarse and fine quantization, shortening line time, and thus improving the frame rate of CMOS image sensors. However, it suffers from the following problems: First, each quantization begins with a comparison between the initial slope voltage and the pixel voltage; when there is a large voltage difference, the required clock cycles increase exponentially. Second, each quantization of a row of pixels requires the slope generator and counter to completely traverse the entire analog and digital data ranges; it does not stop immediately after all pixels in a row have been quantized, resulting in significant time waste and low quantization efficiency.

[0006] The aforementioned problem is caused by the operating characteristics of conventional SS-ADCs, which directly limits the CIS frame rate. Summary of the Invention

[0007] In view of this, the present invention discloses a high-speed column-level single-slope analog-to-digital converter and its conversion method to further optimize row time and thus improve quantization efficiency.

[0008] A high-speed column-level single-slope analog-to-digital converter includes: two or more column-level analog-to-digital converter circuits, a row full-time determination circuit, and a ramp generator. Each column-level analog-to-digital converter circuit includes: an S / H sample-and-hold circuit, a comparator, a counter, and a latch.

[0009] Furthermore, the connection method of each column-level analog-to-digital converter circuit is as follows: the S / H sample-and-hold circuit is connected to the input terminal of the comparator and the output terminal of the ramp generator, respectively; the output terminal of the comparator is connected to the input terminal of the counter; the output terminal of the counter is connected to the input terminal of the latch; the output terminal of the latch is connected to the input terminal of the row full count determination circuit; and the output terminal of the row full count determination circuit is connected to the input terminal of the ramp generator.

[0010] A high-speed column-level single-slope analog-to-digital conversion method includes the following steps:

[0011] Step 1: The single-slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time.

[0012] Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start row timing;

[0013] Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the current row in parallel;

[0014] Step 4: When the line count full determination circuit is activated, the pixel quantization of this line ends, the ramp generator is reset, and the line time ends.

[0015] Step 5: Determine whether each row of pixels in the frame image has been overquantized; if not, access the next row of pixel signals, compare the magnitude of the current row of pixel signals to obtain the working mode of the next row of pixel signal quantization stage, return to step 2 and perform quantization of the next row according to the working mode; if yes, the quantization of the frame image ends, the frame time ends, return to step 1 and perform quantization of the next frame.

[0016] The beneficial effects of this invention include:

[0017] By adding a row full-time determination circuit, the row time ends after all pixel voltages in a row have been quantized, thereby improving the quantization efficiency of a single pixel signal. By adopting an S / H circuit, a new ramp generator, and a column-level SS-ADC architecture with a bidirectional counter architecture configured for each column, the quantization process and row time of the ADC are dynamically reduced, the frame time is reduced, and the frame rate of the CMOS image sensor is further improved. Attached Figure Description

[0018] Figure 1 This is a chip structure diagram of a current-generation CMOS image sensor.

[0019] Figure 2 This is a timing diagram of the chip operation of a current CMOS image sensor.

[0020] Figure 3 This is a chip structure diagram of the high-speed column-level single-slope analog-to-digital converter used in the embodiment;

[0021] Figure 4 This is a single-column structure diagram of the high-speed column-level single-slope analog-to-digital converter in the embodiment;

[0022] Figure 5 This is a timing diagram of the high-speed column-level single-slope analog-to-digital converter in the embodiment;

[0023] Figure 6 This is a flowchart of the high-speed column-level single-slope analog-to-digital conversion method in this invention. Detailed Implementation

[0024] To make the objectives, technical solutions, features, and advantages of the present invention clearer, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0025] Example 1 is a preferred embodiment of the high-speed column-level single-slope analog-to-digital converter of the present invention. The single-column structure of the high-speed column-level single-slope analog-to-digital converter is as follows: Figure 4 As shown in the figure, the column-level analog-to-digital converter circuit includes: an S / H sample-and-hold circuit, a comparator, a counter, and a latch.

[0026] Furthermore, the connection method of each column-level analog-to-digital converter circuit is as follows: the S / H sample-and-hold circuit is connected to the input terminal of the comparator and the output terminal of the ramp generator, respectively; the output terminal of the comparator is connected to the input terminal of the counter; the output terminal of the counter is connected to the input terminal of the latch; the output terminal of the latch is connected to the input terminal of the row full-time determination circuit; and the output terminal of the row full-time determination circuit is connected to the input terminal of the ramp generator.

[0027] Specifically, the S / H sample-and-hold circuit structure is used to change the starting voltage of the ramp voltage generated by the ramp generator, including 5 switches S1 to S5 and 1 capacitor CH; its connection method is as follows: one end of S1 is connected to the negative terminal of the comparator, and the other end is connected to the positive terminal of the comparator, one end of S2, and one end of CH respectively; the other end of S2 is connected to the positive ramp voltage output terminal of the ramp generator and one end of S3 respectively; the other end of S3 is connected to the other end of CH, one end of S4, and one end of S5 respectively; the other end of S4 is connected to the negative ramp voltage output terminal of the ramp generator; and the other end of S5 is connected to the reference voltage.

[0028] Furthermore, the full-line decision circuit is implemented by a digital logic unit or a switch array. It is triggered after the quantization of a line pixel is completed, and is used to output a control signal to stop the ramp generator from working and to reset the ramp generator.

[0029] Furthermore, the ramp generator is implemented by a digital-to-analog converter (DAC) or a switched-capacitor integrator circuit to generate a linear ramp voltage with opposite slopes.

[0030] Furthermore, the counter adopts a bidirectional counter architecture and has four working states: reset, count up, count down, and maintain count value.

[0031] Example 2 is a preferred embodiment of the high-speed column-level single-slope analog-to-digital conversion method of the present invention, and the method flowchart is as follows. Figure 6 As shown, the steps include:

[0032] Step 1: The single-slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time.

[0033] Specifically, when the exposure of an image frame ends, the pixel array in front of the analog-to-digital converter generates pixel signals, the column-level circuit starts working, and the start of frame time means that the image frame has entered the quantization stage.

[0034] Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start row timing.

[0035] Specifically, the start of line time means that the pixels in this line have entered the quantization stage.

[0036] Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the current row in parallel.

[0037] Specifically, the S / H circuit inputs the ramp signal to the positive terminal of the comparator. The comparator starts working and compares the ramp signal at the positive terminal with the pixel signal at the negative terminal. The counter performs a counting operation. The comparator output flips, indicating that the pixel signal has been quantized. The quantization process is processed in parallel.

[0038] Step 4: When the line count full determination circuit is activated, the pixel quantization of this line ends, the ramp generator is reset, and the line time ends.

[0039] Specifically, once all columns of pixels in a row have been quantized, the row count full decision circuit is triggered. At this time, the counter holds the current count value and saves it to the latch as the quantization result. The S / H sample-and-hold circuit starts working, saving the voltage value of the pixel signal in this row to the capacitor plates. This operation uses the voltage of the capacitor plates in the S / H sample-and-hold circuit as the starting value of the ramp voltage for the next row of quantization, shortening the ramp voltage's working time and improving quantization efficiency. The voltage is then compared with the value of the pixel signal in the next row to determine the direction of the ramp voltage and the counter's counting direction for the next row of quantization, ensuring that the quantization phase proceeds normally.

[0040] Furthermore, the line count full decision circuit can be implemented by a digital logic unit or a switch array. After detecting that all pixels in a line have been quantized, the ramp generator is stopped and reset, ending the line time.

[0041] Step 5: Determine whether each row of pixels in the frame image has been overquantized; if not, access the next row of pixel signals, compare the magnitude of the current row of pixel signals to obtain the working mode of the next row of pixel signal quantization stage, return to step 2 and perform quantization of the next row according to the working mode; if yes, the quantization of the frame image ends, the frame time ends, return to step 1 and perform quantization of the next frame.

[0042] Specifically, if not every row of pixels in the frame has been overquantized, the next row of pixel signals is input. These signals are compared with the current row's pixel signals stored in capacitor CH. When comparing the magnitudes of adjacent rows, if the current row's pixel signal is greater than the next row's, the comparator outputs a high level, a falling ramp is applied to the next row during the quantization phase, and the column counter counts down. If the current row's pixel signal is less than the next row's, the comparator outputs a low level, a rising ramp is applied to the next row during the quantization phase, and the column counter counts up. Quantization of the next row begins, and the quantization result of the current row is read from the latch. Once the quantization of every row of pixels in the frame is complete, the frame time ends.

[0043] Example 3 is another preferred embodiment of the high-speed column-level single-slope analog-to-digital converter of the present invention:

[0044] like Figure 3 The diagram shows the chip structure of a high-speed column-level single-slope analog-to-digital converter.

[0045] Furthermore, such as Figure 4 The diagram shown is a single-column structure diagram of the high-speed column-level single-slope analog-to-digital converter in this embodiment. The pre-amplifier structure PGA (Programmable Gain Amplifier) ​​of the digital-to-analog converter processes the pixel signals of the first column of pixels Pixel-11, Pixel-21, ..., Pixel-n1 and outputs Vsig_11, Vsig_21, ..., Vsig_n1 sequentially to the negative terminal of the comparator.

[0046] Furthermore, the ramp generator can generate linear ramp voltages with opposite and symmetrical slopes. Specifically, a positive ramp voltage Vramp+ and a negative ramp voltage Vramp- are output from ports VUP and VDOWN, respectively. Vramp+ increases linearly from Vref to Vref+Vrange, while Vramp- decreases linearly from Vref to Vref-Vrange. This ensures that during the quantization phase, regardless of whether the previous row's pixel voltage stored on the upper plate of capacitor CH is any value between Vref and Vref+Vrange, both ramps Vramp+ and Vramp- guarantee that the ramp voltage VCH connected to the positive terminal of the comparator during quantization can traverse the entire Vrange, ensuring that VCH covers the pixel voltage. The ramp generator's reset operation is set to be performed via the RST port when all pixels in a row have been quantized.

[0047] Furthermore, the comparator operates during the quantization phase, comparing the pixel signal with the ramp voltage. Based on the comparator's output VCOMP, the bidirectional counter can be controlled to operate in three states: UP (up), DOWN (down), and HOLD. After a frame of image quantization is complete, the timing control module can reset all columns of the bidirectional counter to zero.

[0048] Furthermore, the latch can latch and hold the count value of the stage counter. When all latches in a row of pixels have finished latching, the row count full decision circuit can be triggered. The circuit outputs Vramp_rst to reset the ramp generator and end the row time.

[0049] Furthermore, switches S0, S1, S2, S3, S4, and S5, along with capacitor CH, constitute the sample-and-hold circuit of this invention. The positive terminal of the upper plate of capacitor CH is connected to switches S1 and S2 and the positive terminal of the comparator, responsible for maintaining the pixel voltage and ramp voltage supplied to the comparator at different operating stages. Its lower plate is connected to switches S3, S4, and S5, and the ramp voltage can be synchronized on the upper plate through the principle of charge conservation. Switch S0 controls the input of the pixel signal; when closed, the pixel signal is input to the negative terminal of the comparator. Switch S1 is responsible for transferring the pixel to the positive terminal of the comparator after the quantization of a row of pixels, serving as the starting voltage for the ramp voltage in the next quantization. Switches S2, S3, and S4 control the input of the ramp signal. S2 is only turned on for a short period during the quantization of the first row of pixels in each frame, directly connecting Vramp+ to the positive terminal of the comparator. Switches S3 and S4 control the connection of Vramp+ and Vramp- to the lower plate of capacitor CH, respectively. Based on the principle of charge conservation in capacitors, the voltage on the upper plate of the capacitor can rise or fall synchronously with the ramp and be connected to the positive terminal of the comparator to participate in pixel quantization. Switch S5 is responsible for connecting the lower plate reset voltage Vref. The function of this voltage is to ensure that the voltage on the upper plate of the capacitor does not change abruptly when the ramp is connected, so that the ramp voltage can accurately start working from the pixel voltage of the previous row.

[0050] like Figure 5 The diagram shown is a timing diagram of the high-speed column-level single-slope analog-to-digital converter in this embodiment, including the continuous quantization process of three pixel signals in one column. The vertical axis represents the voltage value v, and the horizontal axis Time represents the timing process t. Vrange is the pixel voltage range, which is the range of voltage generated by the pixel after exposure and processed by the PGA. Vref is the starting reference voltage of this range, and the range of the pixel voltage VSIGNAL is from Vref to Vref+Vrange. Vsig_11 represents the pixel voltage generated by the first pixel in the first row and first column of the pixel array after exposure, Vsig_21 represents the pixel voltage generated by the first pixel in the second row and first column, and Vsig_31 represents the pixel voltage generated by the first pixel in the third row and first column, indicated by dashed lines. VCH represents the capacitance C. HThe voltage of the upper plate (positive terminal) is represented by a solid line ratio. t1 to t11 represent different operating stages. The operating states of VCOMP, S0, S1, S2, S3, S4, and S5 are all represented by digital logic voltages. A VCOMP logic level of 0 indicates that the positive terminal voltage is lower than the negative terminal voltage, and the comparator outputs a low level; a VCOMP logic level of 1 indicates that the positive terminal voltage is higher than the negative terminal voltage, and the comparator outputs a high level. The logic levels of S0 to S5 represent the operating state of the switch: 0 represents the switch is open, and 1 represents the switch is closed. COUNTER represents the four operating states of the comparator: reset, count up, count down, and hold. During the hold phase, the quantization results of three pixels Vsig_11, Vsig_21, and Vsig_31 are stored, i.e., the counter count results C1, C2, and C3. The timing sequence t1 to t11 includes the quantization process of three consecutive pixel signals Vsig_11, Vsig_21, and Vsig_31.

[0051] Furthermore, Vsig_11 is quantized during periods t1 to t3, specifically:

[0052] At time t1, the quantization preparation phase is initiated. During this time, the comparator, counter, and latch are reset and cleared. S5 closes the capacitor C. H The lower electrode is reset, ready to begin quantization.

[0053] Stage t2 is the pixel signal quantization stage. When S0 is closed, the pixel signal of the first row of the pixel array is connected to the negative terminal of the corresponding column comparator. At the same time, when S2 is opened, the positive ramp Vramp+ of the ramp generator is connected to capacitor C. H The upper plate is connected to the positive terminal of the comparator. At this time, the comparator is working normally, and the counter counts upward.

[0054] Stage t3 is the latching stage. When the Vramp+ voltage rises to Vsig_11, stage t3 is reached. During this stage, the comparator flips to a high level, the counter pauses counting and holds the current count value C1, and C1 is saved to the latch. Switch S2 opens, pausing the ramp voltage input to the comparator of the current column and C1. H The upper plate is closed, and switch S1 is closed to store Vsig_11 into C. H The upper plate, during which S5 remains closed throughout the process, ensures that capacitor C... H The voltage of the lower plate is Vref to ensure the normal function of charge storage.

[0055] During stages t4 to t7, the pixel signal Vsig_21 of the next row is quantized. This process is similar to that of stages t1 to t3, except that a comparison and determination stage is added before the pixel signal quantization stage to determine the overall circuit operation logic during the quantization stage. The process is as follows:

[0056] Phase t4 is the quantization preparation phase. During this time, the comparator is reset, the counter continues to hold the quantization value C1 from the previous phase, and the latch outputs the first row of pixel quantization values ​​C1. During this period, switch S0 is open, preparing for the input pixel signal Vsig_21. Switch S2 remains open from the quantization of the first row of pixels until the quantization of a frame is complete. Afterward, the input of the ramp signal is controlled by S3 and S4 in conjunction with capacitor C. H When quantization is performed by connecting the positive terminal of the comparator, the capacitor C... H The upper plate maintains the voltage Vsig_11, and S5 is closed to maintain the voltage Vref of the lower plate.

[0057] Phase t5 is the comparison and determination phase. Switch S0 is closed, and the pixel signal Vsig_21 is compared with Vsig_11 at the positive terminal of the comparator. When Vsig_21 is greater than Vsig_11, the quantization logic requires a rising ramp to be applied to the positive terminal of the comparator, causing the counter to continue counting upwards from its current value, thus completing the quantization of Vsig_21. When Vsig_21 is less than Vsig_11, a falling ramp of the same slope is applied, causing the counter to count downwards, completing the quantization. In this example, Vsig_21 is greater than Vsig_11, so the comparator signal Vcomp is at a low logic level, determining the subsequent quantization logic.

[0058] The t6 stage marks the start of the quantization phase, with S3 closed and S5 open, and capacitor C... H When the lower plate is connected to the rising ramp Vramp+, due to the conservation of capacitor charge, the voltage on the upper plate of the capacitor starts to rise from Vsig_11 and traverses Vrange, and the counter starts counting upward from C1.

[0059] Stage t7 is the latching stage. When the comparator flips, the Vcomp logic level changes, triggering a judgment and entering this stage. The counter pauses counting and holds the current count value C2, which is then saved to the latch. S3 opens the stop ramp Vramp+ and connects capacitor C. H Lower electrode plate, and close switch S5 to C. H The lower plate is reset, and then switch S1 is closed to store Vsig_21 in C. H The upper electrode plate prepares for the quantization of the next row of pixel signals.

[0060] During stages t8 to t11, Vsig_31 in the third row of pixels is quantized. The work content of this process corresponds to stages t4 to t7, which includes the quantization preparation stage, comparison and judgment stage, quantization stage, and latching stage.

[0061] Starting at time t8, the comparator is reset, the counter continues to hold the quantization value C2 from the previous stage, and the latch outputs the quantization value C2 of the second row of pixels. At this time, capacitor C... HThe upper plate maintains the voltage Vsig_21, and S5 is closed to maintain the voltage Vref of the lower plate.

[0062] In stage t9, switch S0 is closed, and the third row pixel signal Vsig_31 is input and compared with Vsig_21 at the positive terminal of the comparator. Assuming that Vsig_31 is less than Vsig_21, the comparator flips to a high level, and the circuit operation logic of the quantization stage is determined.

[0063] Quantization of Vsig_31 begins at stage t10, with S4 closed and S5 open, and capacitor C... H When the lower plate is connected to the descending ramp Vramp-, due to the conservation of capacitor charge, the voltage on the upper plate of the capacitor starts to decrease from Vsig_21 and traverses Vrange. The counter starts counting downward from C2 and continues to count.

[0064] In stage t11, the latching stage occurs. The comparator output Vcomp toggles to a low level, the counter pauses counting and holds the current count value C3, and C3 is saved to the latch. In S4, the stop ramp Vramp- is opened and capacitor C is connected. H Lower electrode plate, and close switch S5 to C. H The lower plate is reset, and then switch S1 is closed to store Vsig_31 in C. H The upper electrode plate prepares for the quantization of the fourth row of pixel signals.

[0065] Furthermore, the above process can represent the quantization process of all pixels in a frame's pixel quantization process. In this invention, the clock cycles occupied by the quantization stages of different pixels are not fixed, while the clock cycles occupied by the quantization preparation stage, comparison and determination stage, and latching stage are fixed. The line time is determined by the pixel signal in a row whose quantization stage occupies the most clock cycles, rather than by a fixed T. clk ×2 M Characterization.

[0066] Furthermore, suppose the pixel array size is n×n, and the pixel voltage being quantized in the h-th row and l-th column is V. sig (h,l), the pixel voltage quantized in the previous row is V. sig (h-1,l). The formula for calculating the line time T is:

[0067]

[0068] Among them, V sig (1, l) represents the pixel voltage being quantized in the first row and column l, V range V represents the range of pixel signals. ref T represents the initial value of the ramp voltage. clkThe clock cycle represents the circuit, M represents the resolution of the single-slope analog-to-digital converter, h is an array representing the number of rows, and l is an array representing the number of columns.

[0069] When the pixel array size n×n is very large, the frame time can be approximated as:

[0070]

[0071] Where H is the number of rows in the pixel array, with a value of n, and T clk This represents the clock period, where 2≤h≤n and 1≤l≤n.

[0072] Furthermore, it can be seen that the frame time is related to the pixel voltage difference generated by adjacent rows of pixels in the same column. In large-format image sensors, the pixel voltage difference acquired between most adjacent rows of pixels is very small compared to the entire quantization voltage range Vrange. The value of is usually very small, which will reduce most of the line time during quantization, thus reducing the frame time.

[0073] Finally, it should be noted that the above description only depicts some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of the present invention.

Claims

1. A high-speed column-level single-slope analog-to-digital converter, characterized in that, include: Two or more column-level analog-to-digital converter circuits, a row full-count determination circuit, and a ramp generator; Each column-level analog-to-digital converter circuit includes: S / H sample-and-hold circuit, comparator, counter, and latch; The connection method is as follows: the S / H sample and hold circuit is connected to the input terminal of the comparator and the output terminal of the ramp generator respectively; the output terminal of the comparator is connected to the input terminal of the counter; the output terminal of the counter is connected to the input terminal of the latch; the output terminal of the latch is connected to the input terminal of the row count full determination circuit; the output terminal of the row count full determination circuit is connected to the reset input terminal of the ramp generator. The S / H sample-and-hold circuit includes: 5 switches S1~S5 and 1 capacitor CH; the connection method is as follows: one end of S1 is connected to the negative terminal of the comparator, and the other end is connected to the positive terminal of the comparator, one end of S2, and one end of CH respectively; the other end of S2 is connected to the positive ramp voltage output terminal of the ramp generator and one end of S3 respectively; the other end of S3 is connected to the other end of CH, one end of S4, and one end of S5 respectively; the other end of S4 is connected to the negative ramp voltage output terminal of the ramp generator; and the other end of S5 is connected to the reference voltage. The row full decision circuit is implemented by a digital logic unit or a switch array. After the row full decision circuit finishes quantizing a row of pixels, it outputs a control signal to stop the ramp generator and reset the ramp generator.

2. The high-speed column-level single-slope analog-to-digital converter according to claim 1, characterized in that, The S / H sample-and-hold circuit structure is used to change the starting voltage of the ramp voltage generated by the ramp generator.

3. The high-speed column-level single-slope analog-to-digital converter according to claim 1, characterized in that, The counter adopts a bidirectional counter architecture and has four working states: reset, count up, count down, and maintain count value.

4. A high-speed column-level single-slope analog-to-digital conversion method, characterized in that, The high-speed column-level single-slope analog-to-digital converter of any one of claims 1 to 3 is employed; Including the following steps: Step 1: The single-slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time. Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start row timing; Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the current row in parallel; Step 4: When the line count full determination circuit is activated, the pixel quantization of this line ends, the ramp generator is reset, and the line time ends. Step 5: Determine whether each row of pixels in the current frame image has been overquantized; if not, access the next row of pixel signals, compare the magnitude of the current row of pixel signals to obtain the working mode of the quantization stage of the next row of pixel signals, return to step 2 and perform quantization of the next row according to the working mode; if yes, the quantization of the current frame image ends, the frame time ends, return to step 1 and perform quantization of the next frame.

5. The high-speed train-level single-slope analog-to-digital conversion method according to claim 4, characterized in that, Quantization of each column of pixels in this row includes: the S / H sample-and-hold circuit inputs a ramp signal to the comparator, the comparator compares the pixel signal of this row with the ramp signal, and the counter performs a counting operation.

6. The high-speed train-level single-slope analog-to-digital conversion method according to claim 5, characterized in that, When comparing the pixel signal sizes of two adjacent rows, if the pixel signal of the current row is greater than that of the next row, the comparator outputs a high level, the next row is connected to a falling ramp during the quantization phase, and the counter counts down; if the pixel signal of the current row is less than that of the next row, the comparator outputs a low level, the next row is connected to a rising ramp during the quantization phase, and the counter counts up.

7. The high-speed column-level single-slope analog-to-digital conversion method according to claim 4, characterized in that, The line time to end the quantization of this line includes: the counter holding the current value, the latch latching the count result, the S / H sample and hold circuit saving the voltage value of the pixel signal of this line, and using it as the starting value for the ramp generator to generate the ramp voltage when quantizing the next line.

8. The high-speed column-level single-slope analog-to-digital conversion method according to claim 4, characterized in that, The formula for calculating line time T is: ； in, Indicates the first line The pixel voltages being quantized are listed. Indicates the range of pixel signals. This indicates the initial value of the ramp voltage. Indicates the circuit clock period. This indicates the resolution of a single-slope analog-to-digital converter. Indicates the row number. Indicates the column number. The number of rows in the pixel array. Indicates the first OK The pixel voltages being quantized are listed. Indicates the first OK The column is quantizing the pixel voltage.

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