Continuous-time high-precision analog-to-digital converter and implementation method

Abstract

The invention discloses a continuous-time high-precision analog-to-digital converter and an implementation method, and the analog-to-digital converter is characterized in that the analog-to-digital converter comprises a first side differential circuit and a second side differential circuit; the first side differential circuit and the second side differential circuit have the same structure; the first side differential circuit comprises a digital-to-analog converter array channel A, a digital-to-analog converter array channel B, a comparator, a register 11 and a register 12; the digital-to-analog converter array channel A and the digital-to-analog converter array channel B have the same structure; according to the technical scheme, the two-channel digital-to-analog converter array is used, two operations of successive approximation quantization and residual voltage integration can be alternately completed in two adjacent clock periods, and two stages of parallel integration and quantization in the same clock period are realized, so that the conversion efficiency is greatly improved, and high-precision application can be realized.

Description

Technical Field

[0001] The present invention belongs to the field of analog-to-digital converter architecture design, and in particular relates to a continuous-time high-precision analog-to-digital converter and an implementation method thereof. Background Art

[0002] The Continuous-Time Noise-Shaping Successive-Approximation Register Analog-to-Digital Converter (CTNS-SAR ADC) combines noise shaping technology with a successive-approximation register analog-to-digital converter, overcoming the limitations of SAR (Successive-Approximation Register) in high-resolution and low-power applications, while eliminating the need for anti-aliasing filters, saving power and area. The traditional continuous-time noise-shaping successive-approximation register analog-to-digital converter uses a duty cycle-controlled integrator to complete SAR quantization and residual integration within one clock cycle. However, the quantization stage of successive approximation interrupts the continuous-time integration, resulting in inaccurate integration. This structure obtains an approximately ideal noise transfer function (NTF) by reducing the proportion of the quantization stage in the entire clock cycle. However, this method limits the time available for quantization to less than 5% of the entire clock cycle, and the approximation performance of the NTF will be worse in high-order cases, thereby limiting the scope of application of this structure. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a continuous-time high-precision analog-to-digital converter and an implementation method thereof.

[0004] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a continuous-time high-precision analog-to-digital converter, the analog-to-digital converter comprising: a first side differential circuit and a second side differential circuit; the first side differential circuit and the second side differential circuit have the same structure; the first side differential circuit comprises: a digital-to-analog converter array channel A, a digital-to-analog converter array channel B, a comparator, a register 11 and a register 12; the digital-to-analog converter array channel A and the digital-to-analog converter array channel B have the same structure;

[0006] The DAC array channel A is used for the clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal;

[0007] The digital-to-analog converter array channel B is used to generate a clock signal Φ RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal;

[0008] The comparator is used to control the register 11 to switch the capacitor array of the digital-to-analog converter array channel A according to the first integrated signal and the first signal to complete SAR quantization;

[0009] The digital-to-analog converter array channel A is also used to generate a clock signal Φ RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal;

[0010] The digital-to-analog converter array channel B is also used to RST When the next rising edge of arrives, the input signal VIN is processed to obtain a second signal;

[0011] The comparator is used to control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B according to the second integrated signal and the second signal to complete the SAR quantization.

[0012] Optionally, the first-side differential circuit further includes: a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a first single-pole three-throw switch and a second single-pole three-throw switch; the upper plate of the digital-to-analog converter array channel A is connected to the lower plate of the capacitor C1, the upper plate of the digital-to-analog converter array channel A is connected to the first end of the resistor R1, the upper plate of the capacitor C1 is connected to the input signal VIN, the second end of the resistor R1 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel A is connected to the first end of the first single-pole three-throw switch, and the second end of the first single-pole three-throw switch is connected to the reference level VCM. VREFN, reference level VREFP and reference level VCM; the upper plate of the digital-to-analog converter array channel B is connected to the lower plate of the capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first end of the resistor R2, the upper plate of the capacitor C2 is connected to the input signal VIN, the second end of the resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first end of the second single-pole triple-throw switch, and the second end of the second single-pole triple-throw switch is respectively connected to the reference level VREFN, the reference level VREFP and the reference level VCM.

[0013] Optionally, the digital-to-analog converter array channel A is used to RSTConnecting the lower plate of the digital-to-analog converter array channel A to the reference level VCM before the first rising edge of ;

[0014] The digital-to-analog converter array channel B is used to generate a clock signal Φ RST Before the first rising edge of arrives, the lower plate of the digital-to-analog converter array channel B is connected to the reference level VCM.

[0015] Optionally, the first-side differential circuit further includes: a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, a switch S8, an integrator 11, an integrator 12, a voltage amplifier 11, a voltage amplifier 12, a voltage amplifier 13, a voltage amplifier 14 and an adder; the first end of the switch S1 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of the switch S1 is connected to the first input end of the voltage amplifier 12, the first end of the switch S2 is connected to the upper plate of the digital-to-analog converter array channel B, and the The second end of the switch S2 is connected to the second input end of the voltage amplifier 12, the first end of the switch S3 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of the switch S3 is connected to the first input end of the integrator 11, the first end of the switch S4 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of the switch S4 is connected to the second input end of the integrator 11, the first end of the switch S5 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of the switch S5 is connected to the first input end of the voltage amplifier 11. The first end of the switch S6 is connected to the upper plate of the channel A of the digital-to-analog converter array, the second end of the switch S6 is connected to the second input end of the voltage amplifier 11, the output end of the voltage amplifier 11 is connected to the first input end of the adder, the output end of the voltage amplifier 12 is connected to the second input end of the adder, the first output end of the integrator 11 is connected to the input end of the integrator 12, the second output end of the integrator 11 is connected to the input end of the voltage amplifier 13, the output end of the voltage amplifier 13 is connected to the third input end of the adder, the output end of the integrator 12 is connected to the input end of the voltage amplifier 14, the output end of the voltage amplifier 14 is connected to the fourth input end of the adder, the output end of the adder is connected to the non-inverting input end of the comparator, the inverting input end of the comparator is grounded, the first end of the switch S7 is connected to the first output end of the comparator, the first end of the switch S8 is connected to the second output end of the comparator; the second end of the switch S7 is connected to the register 12, and the second end of the switch S8 is connected to the register 11.

[0016] Optionally, the switch S1, the switch S3, the switch S5 and the switch S7 are connected by a clock signal The switch S2, the switch S4, the switch S6 and the switch S8 are controlled by a clock signal control.

[0017] Optionally, the digital-to-analog converter array channel A and the digital-to-analog converter array channel B each include a plurality of capacitors connected in parallel; the plurality of capacitors connected in parallel are arranged in sequence according to capacitance values.

[0018] Optionally, the amplification factors of the voltage amplifier 12, the voltage amplifier 13 and the voltage amplifier 14 are obtained according to the following formula:

[0019]

[0020] in, is the amplification factor of the voltage amplifier 14, is the amplification factor of the voltage amplifier 13, is the amplification factor of the voltage amplifier 12, k0 is the first ideal coefficient, k1 is the second ideal coefficient, k2 is the third ideal coefficient, N represents the number of SAR conversions.

[0021] In a second aspect, the present invention provides a method for implementing a continuous-time high-precision analog-to-digital converter, which is implemented by the continuous-time high-precision analog-to-digital converter described in any one of the first aspects, comprising the following steps:

[0022] Through the digital-to-analog converter array channel A at the clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal;

[0023] The clock signal Φ RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal;

[0024] Controlling the register 11 to switch the capacitor array of the digital-to-analog converter array channel A through the comparator, the first integrated signal and the first signal to complete SAR quantization;

[0025] The DAC array channel A is clocked by the clock signal Φ RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal;

[0026] The DAC array channel B is passed through the clock signal Φ RSTWhen the next rising edge of arrives, the input signal VIN is processed to obtain a second signal;

[0027] The register 12 is controlled by the comparator, the second integrated signal and the second signal to switch the capacitor array of the digital-to-analog converter array channel B to complete the SAR quantization.

[0028] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0029] In the above technical solution, a two-channel digital-to-analog converter array is used to alternately complete the two operations of successive approximation quantization and residual voltage integration in two adjacent clock cycles, realizing the two stages of parallel integration and quantization in the same clock cycle, thereby greatly improving the conversion efficiency and enabling high-precision applications.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a structural schematic diagram of a first-side differential circuit of a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of a clock signal provided by an embodiment of the present invention;

[0033] Figure 3 is a structural schematic diagram of a digital-to-analog converter array channel provided by an embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of a spectrum diagram provided by an embodiment of the present invention;

[0035] Figure 5 It is a flow chart of a method for implementing a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0037] The analog-to-digital converter comprises: a first-side differential circuit and a second-side differential circuit, wherein the first-side differential circuit and the second-side differential circuit have the same structure; Figure 1 is a structural schematic diagram of a first side differential circuit of a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention, such as Figure 1As shown, the first side differential circuit includes: digital-to-analog converter array channel A (channel A), digital-to-analog converter array channel B (channel B), a comparator, a register 11 and a register 12; the digital-to-analog converter array channel A and the digital-to-analog converter array channel B have the same structure.

[0038] Optionally, refer to Figure 1 The first side differential circuit also includes: a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a first single-pole three-throw switch and a second single-pole three-throw switch; the upper plate of the digital-to-analog converter array channel A is connected to the lower plate of the capacitor C1, the upper plate of the digital-to-analog converter array channel A is connected to the first end of the resistor R1, the upper plate of the capacitor C1 is connected to the input signal VIN, the second end of the resistor R1 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel A is connected to the first end of the first single-pole three-throw switch, and the second end of the first single-pole three-throw switch is connected to the reference voltage VCM. level VREFN, reference level VREFP and reference level VCM; the upper plate of the digital-to-analog converter array channel B is connected to the lower plate of the capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first end of the resistor R2, the upper plate of the capacitor C2 is connected to the input signal VIN, the second end of the resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first end of the second single-pole triple-throw switch, and the second end of the second single-pole triple-throw switch is respectively connected to the reference level VREFN, the reference level VREFP and the reference level VCM.

[0039] Optionally, refer to Figure 1The first side differential circuit also includes: switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, switch S8, integrator 11, integrator 12, voltage amplifier 11, voltage amplifier 12, voltage amplifier 13, voltage amplifier 14 and adder; the first end of switch S1 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of switch S1 is connected to the first input end of the voltage amplifier 12, the first end of switch S2 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of switch S2 is connected to the second input end of the voltage amplifier 12, the first end of switch S3 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of switch S3 is connected to the first input end of the integrator 11, the first end of switch S4 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of switch S4 is connected to the second input end of the integrator 11, the first end of switch S5 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of switch S5 is connected to the voltage amplifier The first input terminal of the switch S6 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of the switch S6 is connected to the second input terminal of the voltage amplifier 11, the output terminal of the voltage amplifier 11 is connected to the first input terminal of the adder, the output terminal of the voltage amplifier 12 is connected to the second input terminal of the adder, the first output terminal of the integrator 11 is connected to the input terminal of the integrator 12, the second output terminal of the integrator 11 is connected to the input terminal of the voltage amplifier 13, the output terminal of the voltage amplifier 13 is connected to the third input terminal of the adder, the output terminal of the integrator 12 is connected to the input terminal of the voltage amplifier 14, the output terminal of the voltage amplifier 14 is connected to the fourth input terminal of the adder, the output terminal of the adder is connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is grounded, the first end of the switch S7 is connected to the first output terminal of the comparator, the first end of the switch S8 is connected to the second output terminal of the comparator; the second end of the switch S7 is connected to the register 12, and the second end of the switch S8 is connected to the register 11.

[0040] It is understandable that the process of determining the amplification factor of the voltage amplifier can be referred to as follows: First, the time T spent on each SAR conversion is estimated according to the process. sar , the expected input signal bandwidth is BW, and the number of SAR conversions N for effective quantization can be obtained:

[0041] N≤log 0.5 (2π·BW·T sar );

[0042] N is the largest integer that satisfies the above formula. After N is determined, sarEstimate the sampling clock period to obtain the sampling rate and determine the oversampling rate. Then determine the noise shaping order and the maximum out-of-band gain according to the required signal-to-noise-distortion ratio, and then generate the required noise transfer function NTF through MATLAB's SynthesizeNTF function. And determine the discrete domain loop filter function H(z) according to the following formula:

[0043]

[0044] Then use Matlab's d2c function to convert H(z) into a continuous time domain function H(s) to determine the ideal coefficients k0, k1, and k2. Then determine the excess loop delay t in the system d , in this design, other non-ideal factors are not considered, so The coefficient after loop compensation is determined according to the following formula:

[0045]

[0046] in, is the gain factor of the voltage amplifier 14, is the gain factor of the voltage amplifier 13, is the gain factor of the voltage amplifier 12, k0 is the first ideal coefficient, k1 is the second ideal coefficient, k2 is the third ideal coefficient, and N represents the number of conversions used for SAR.

[0047] Optionally, Figure 2 is a schematic diagram of a clock signal provided by an embodiment of the present invention, such as Figure 2 As shown, switches S1, S3, S5 and S7 are connected by a clock signal Φ CLK Control, switch S2, switch S4, switch S6 and switch S8 by clock signal Control; clock signal Φ CLK and clock signal It is a two-phase non-overlapping clock signal.

[0048] Specifically, the clock signal Φ CLK When it is high level, switch S1, switch S3, switch S5, and switch S7 are closed; the clock signal Φ CLK When it is low level, the switches S1, S3, S5 and S7 are disconnected; the clock signal When it is high level, switch S2, switch S4, switch S6, and switch S8 are closed; the clock signal When it is at a low level, the switches S2, S4, S6 and S8 are disconnected.

[0049] Optionally, both the digital-to-analog converter array channel A and the digital-to-analog converter array channel B include a plurality of capacitors connected in parallel; the plurality of capacitors connected in parallel are arranged in sequence according to capacitance values.

[0050] Understandably, Figure 3 is a schematic diagram of the structure of a digital-to-analog converter array channel provided by an embodiment of the present invention, such as Figure 3 As shown, the capacitance values ​​of the capacitors in the digital-to-analog converter array channel are arranged according to the exponential power of 2, namely 16C, 8C, 4C, 2C, C, CMSB is the capacitor with the largest capacitance value, and CLSB is the capacitor with the smallest capacitance value.

[0051] In one embodiment, the digital-to-analog converter array channel A is used to generate a clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal;

[0052] Channel B of the DAC array is used to RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal;

[0053] A comparator, used for switching the capacitor array of the digital-to-analog converter array channel A according to the first integrated signal and the first signal control register 11, so as to complete the SAR quantization;

[0054] Channel A of the DAC array is also used to RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal;

[0055] DAC array channel B is also used to RST When the next rising edge of arrives, the input signal VIN is processed to obtain a second signal;

[0056] The comparator is used to switch the capacitor array of the digital-to-analog converter array channel B according to the second integrated signal and the second signal control register 12 to complete the SAR quantization.

[0057] It can be understood that the above SAR quantization process is the ping-pong operation stage of the first side differential circuit of the continuous time high-precision analog-to-digital converter. In the ping-pong operation stage, Figure 1 As shown, since the structures of channel A and channel B are exactly the same, channel A and channel B perform integration and quantization operations alternately.

[0058] Furthermore, in the present invention, from the clock signal Φ RST Before the rising edge of RST The next rising edge of the clock signal is preceded by one clock cycle.RST In the ping-pong operation stage, Figure 1 As shown, since the structures of channel A and channel B are exactly the same, channel A and channel B perform integration and quantization operations alternately. Here, the case where channel A performs SAR quantization on the input signal VIN and channel B performs integration is taken as an example. RST After the clock cycle ends, the first residual voltage is generated on the upper plate of channel B, and the first residual voltage will be brought into the ping-pong operation stage; during the ping-pong operation stage, Φ RST Before the rising edge of the clock arrives, Φ CLK becomes low level, Φ CLK becomes a high level, thereby disconnecting S1, S3, S5, and S7, and closing S2, S4, S6, and S8. At this time, the upper plate of channel A is connected to the voltage amplifier 11 and connected to the adder to form a signal on the VRES path; the upper plate of channel B is connected to the integrator 11, and passes through the integrator 12 and the voltage amplifier 14 to form a signal on the VINT2 path, and passes through the voltage amplifier 13 to form a signal on the VINT1 path; the upper plate signal of channel B is also connected to the voltage amplifier 12 to form a signal on the VELD path, and the signals on the VRES path, the VINT1 path, the VINT2 path, and the VELD path are input into the adder to obtain the final signal. The comparator is at the clock signal Φ RST When the level is high, it is reset first, then compared with the final signal, and the comparison result is sent to register 11 to control the switching of the DAC switch array of the digital-to-analog converter array channel A. The lower plate of the digital-to-analog converter array channel B keeps the state of the previous cycle unchanged through register 12. The voltage residual generated on the upper plate of channel B at the end of this clock cycle will be carried into the next clock signal Φ RST The functions of channels A and B will also be in the clock signal Φ RST The next clock cycle of the clock signal Φ RST At the end of the clock cycle, the clock signal Φ CLK Before the falling edge, the reference voltage connected to the lower plate of the capacitor array of the digital-to-analog converter array channel responsible for successive approximation quantization is output as the quantization output digital code of the channel. The digital code of the digital-to-analog converter array channel responsible for successive approximation quantization in the first side differential circuit and the digital code of the digital-to-analog converter array channel responsible for successive approximation quantization in the second side differential circuit are added in the time domain to obtain the digital code of the continuous time high-precision analog-to-digital converter.

[0059] Optionally, before the ping-pong operation stage, the present invention further includes an initial state stage, in which the digital-to-analog converter array channel A is used to generate a clock signal Φ RSTBefore the first rising edge of , connect the lower plate of channel A of the digital-to-analog converter array to the reference level VCM;

[0060] Channel B of the DAC array is used to RST Before the first rising edge of the DAC array, the lower plate of channel B is connected to the reference level VCM.

[0061] It can be understood that the initial state stage only includes the clock signal Φ RST In one clock cycle of the clock signal Φ RST Before the first rising edge of the clock arrives, the lower plates of the two DAC array channels are all reset to the reference level VCM. CLK is high level, the clock signal Φ CLK When it is low level, S1, S3, S5, S7 are closed, and S2, S4, S6, S8 are open. The upper plate signal of channel B is amplified by 1 times through the voltage amplifier 11 and connected to the adder. This signal is the signal on the VRES path; the upper plate of channel A is connected to the integrator 11, and the generated integrated signal will be amplified by k1 times through the voltage amplifier 13 to obtain the signal on the VINT1 path, and connected to the adder. At the same time, the output signal of the integrator 11 will also be connected to the integrator 12, and amplified by k2 times by the voltage amplifier 14 to obtain the signal on the VINT2 path, and then connected to the adder; the residual voltage of the upper plate of channel A will also be connected to the voltage amplifier 12 to be amplified by k0 times, and then connected to the adder to obtain the signal on the VELD path. The adder adds the signals on the four paths of VELD, VINT1, VINT2, and VRES and inputs them into the comparator. The comparator is at the clock signal Φ RST When it is high, it is in reset state until the clock signal Φ RST The comparison result is stored in register 12, and the lower plate of the capacitor array of channel B of the digital-to-analog converter array is switched. The switching process is as follows: Figure 3 During this clock cycle, the lower plate of channel A is always connected to the VCM reference voltage.

[0062] It is worth mentioning that, according to the comparison result of the comparator, the lower board of the capacitor array of each DAC array channel is controlled by a single-pole triple-throw switch to connect to the reference level: in the reset phase, all capacitors are connected to the reference level VCM; after the Nth comparison, the comparator will output the comparison result and the control signal Φ CMP , if the comparator outputs a high level, the control signal Φ CMP At the corresponding falling edge, register 11 controls 2 5-N C capacitor (1≤N≤5) is connected to the reference level VREFN. If the comparator outputs a low level, control 25-N The capacitor C is connected to the reference voltage level VREFP.

[0063] In one embodiment, the continuous-time high-precision analog-to-digital converter designed by the present invention is designed using a 65nm standard CMOS process. The entire circuit operates at a 1.2V power supply voltage, a sampling frequency of 600MS / s, an input signal amplitude of 1.2-V Vpp, and a power consumption of 8.5mW when the input signal frequency is 3.698MHz. Figure 4 is a schematic diagram of a spectrum diagram provided by an embodiment of the present invention, such as Figure 4 As shown. Figure 4 According to the calculation, the signal harmonic noise ratio of the continuous-time high-precision analog-to-digital converter designed by the present invention is 76.8dB, the effective accuracy is 12.5 bits, and the quality factor reaches 49.8fJ / conv.-step. Figure 4 It can be seen that compared with the traditional architecture, the signal bandwidth that can be achieved by the architecture of the present invention is increased by more than 10 times, while maintaining the signal harmonic noise ratio above 75dB.

[0064] Figure 5 is a flow chart of a method for implementing a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention, such as Figure 5 As shown, the method may include the following steps:

[0065] S501, through the digital-to-analog converter array channel A, the clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal;

[0066] S502, through the digital-to-analog converter array channel B, the clock signal Φ RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal;

[0067] S503, switching the capacitor array of the digital-to-analog converter array channel A through the comparator, the first integration signal and the first signal control register 11 to complete SAR quantization;

[0068] S504, through the digital-to-analog converter array channel A, the clock signal Φ RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal;

[0069] S505, through the digital-to-analog converter array channel B, the clock signal Φ RST When the next rising edge of arrives, the input signal VIN is processed to obtain a second signal;

[0070] S506 , switching the capacitor array of the digital-to-analog converter array channel B through the comparator, the second integration signal and the second signal control register 12 to complete SAR quantization.

[0071] In the above technical solution, a two-channel digital-to-analog converter array is used to alternately complete the two operations of successive approximation quantization and residual voltage integration in two adjacent clock cycles, realizing the two stages of parallel integration and quantization in the same clock cycle, thereby greatly improving the conversion efficiency and enabling high-precision applications.

[0072] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0074] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0075] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0076] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A continuous-time high-precision analog-to-digital converter, characterized in that: The analog-to-digital converter includes: a first side differential circuit and a second side differential circuit; the first side differential circuit and the second side differential circuit have the same structure; the first side differential circuit includes: a digital-to-analog converter array channel A, a digital-to-analog converter array channel B, a comparator, a register 11 and a register 12; the digital-to-analog converter array channel A and the digital-to-analog converter array channel B have the same structure; The DAC array channel A is used for the clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal; The digital-to-analog converter array channel B is used to generate a clock signal Φ RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal; The comparator is used to control the register 11 to switch the capacitor array of the digital-to-analog converter array channel A according to the first integrated signal and the first signal to complete SAR quantization; The digital-to-analog converter array channel A is also used to generate a clock signal Φ RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal; The digital-to-analog converter array channel B is also used to RST When the next rising edge of arrives, the input signal VIN is processed to obtain a second signal; The comparator is used to control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B according to the second integrated signal and the second signal to complete the SAR quantization.

2. The continuous-time high-precision analog-to-digital converter according to claim 1, characterized in that: The first-side differential circuit further includes: a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a first single-pole three-throw switch and a second single-pole three-throw switch; the upper plate of the digital-to-analog converter array channel A is connected to the lower plate of the capacitor C1, the upper plate of the digital-to-analog converter array channel A is connected to the first end of the resistor R1, the upper plate of the capacitor C1 is connected to the input signal VIN, the second end of the resistor R1 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel A is connected to the first end of the first single-pole three-throw switch, and the second end of the first single-pole three-throw switch is respectively connected to the reference level VR EFN, reference level VREFP and reference level VCM; the upper plate of the digital-to-analog converter array channel B is connected to the lower plate of the capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first end of the resistor R2, the upper plate of the capacitor C2 is connected to the input signal VIN, the second end of the resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first end of the second single-pole triple-throw switch, and the second end of the second single-pole triple-throw switch is respectively connected to the reference level VREFN, the reference level VREFP and the reference level VCM.

3. The continuous-time high-precision analog-to-digital converter according to claim 2, characterized in that: The digital-to-analog converter array channel A is used to generate a clock signal Φ RST Connecting the lower plate of the digital-to-analog converter array channel A to the reference level VCM before the first rising edge of ; The digital-to-analog converter array channel B is used to generate a clock signal Φ RST Before the first rising edge of arrives, the lower plate of the digital-to-analog converter array channel B is connected to the reference level VCM.

4. The continuous-time high-precision analog-to-digital converter according to claim 2, characterized in that: The first-side differential circuit further includes: a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, a switch S8, an integrator 11, an integrator 12, a voltage amplifier 11, a voltage amplifier 12, a voltage amplifier 13, a voltage amplifier 14 and an adder; a first end of the switch S1 is connected to an upper plate of the digital-to-analog converter array channel A, a second end of the switch S1 is connected to a first input end of the voltage amplifier 12, a first end of the switch S2 is connected to an upper plate of the digital-to-analog converter array channel B, and the switch The second end of the switch S2 is connected to the second input end of the voltage amplifier 12, the first end of the switch S3 is connected to the upper plate of the digital-to-analog converter array channel A, the second end of the switch S3 is connected to the first input end of the integrator 11, the first end of the switch S4 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of the switch S4 is connected to the second input end of the integrator 11, the first end of the switch S5 is connected to the upper plate of the digital-to-analog converter array channel B, the second end of the switch S5 is connected to the first input end of the voltage amplifier 11 The first end of the switch S6 is connected to the upper plate of the channel A of the digital-to-analog converter array, the second end of the switch S6 is connected to the second input end of the voltage amplifier 11, the output end of the voltage amplifier 11 is connected to the first input end of the adder, the output end of the voltage amplifier 12 is connected to the second input end of the adder, the first output end of the integrator 11 is connected to the input end of the integrator 12, the second output end of the integrator 11 is connected to the input end of the voltage amplifier 13, the output end of the voltage amplifier 13 is connected to the third input end of the adder, the output end of the integrator 12 is connected to the input end of the voltage amplifier 14, the output end of the voltage amplifier 14 is connected to the fourth input end of the adder, the output end of the adder is connected to the non-inverting input end of the comparator, the inverting input end of the comparator is grounded, the first end of the switch S7 is connected to the first output end of the comparator, the first end of the switch S8 is connected to the second output end of the comparator; the second end of the switch S7 is connected to the register 12, and the second end of the switch S8 is connected to the register 11.

5. The continuous-time high-precision analog-to-digital converter according to claim 4, characterized in that: The switch S1, the switch S3, the switch S5 and the switch S7 are connected by a clock signal Φ CLK The switch S2, the switch S4, the switch S6 and the switch S8 are controlled by a clock signal Φ CLK control; the clock signal Φ CLK and the clock signal Φ CLK It is a two-phase non-overlapping clock signal.

6. The continuous-time high-precision analog-to-digital converter according to claim 4, characterized in that: The digital-to-analog converter array channel A and the digital-to-analog converter array channel B each include a plurality of capacitors connected in parallel; the plurality of capacitors connected in parallel are arranged in sequence according to the size of the capacitance value.

7. The continuous-time high-precision analog-to-digital converter according to claim 4, characterized in that: The amplification factors of the voltage amplifier 12, the voltage amplifier 13 and the voltage amplifier 14 are obtained according to the following formula: in, is the amplification factor of the voltage amplifier 14, is the amplification factor of the voltage amplifier 13, is the amplification factor of the voltage amplifier 12, k0 is the first ideal coefficient, k1 is the second ideal coefficient, k2 is the third ideal coefficient, N represents the number of SAR conversions.

8. A method for implementing a continuous-time high-precision analog-to-digital converter, for implementing the continuous-time high-precision analog-to-digital converter according to any one of claims 1 to 7, characterized in that: The following steps are involved: Through the digital-to-analog converter array channel A at the clock signal Φ RST When the rising edge of arrives, the input signal VIN is processed to obtain the first signal; The clock signal Φ RST When the rising edge of arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain a first integrated signal; Controlling the register 11 to switch the capacitor array of the digital-to-analog converter array channel A through the comparator, the first integrated signal and the first signal to complete SAR quantization; The DAC array channel A is clocked by the clock signal Φ RST When the next rising edge of arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain a second integrated signal; The DAC array channel B is passed through the clock signal Φ RST When the next rising edge of arrives, the input signal VIN is processed to obtain a second signal; The register 12 is controlled by the comparator, the second integrated signal and the second signal to switch the capacitor array of the digital-to-analog converter array channel B to complete the SAR quantization.

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