Switched capacitor comparator, analog-to-digital converter and electronic device

Abstract

The invention provides a switched capacitor comparator, an analog-to-digital converter and an electronic device, and relates to the technical field of integrated circuits, and the switched capacitor comparator comprises a switched capacitor comparator unit and a common-mode stabilization unit. The switch capacitor comparator unit is internally provided with a sampling capacitor and a comparator, and the input of the switch capacitor comparator unit comprises a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage and a common-mode bias voltage of the comparator. And the output is a comparison result of the difference between the forward input voltage and the reverse input voltage and the difference between the forward reference voltage and the reverse reference voltage. The common-mode stabilizing unit is used for simulating the sampling state of the switched capacitor comparator unit, so that the actual common-mode input voltage of the comparator is equal to the ideal common-mode input voltage, the input of the common-mode stabilizing unit comprises common-mode reference voltage, forward input voltage, reverse input voltage and the ideal common-mode input voltage, and the output of the common-mode stabilizing unit is common-mode bias voltage. The switched capacitor comparator has a wide common-mode input range and is fast in response.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a switched capacitor comparator, an analog-to-digital converter, and an electronic device. Background Art

[0002] The sub-ADC in a high-speed pipeline analog-to-digital converter (ADC) often uses a switched capacitor comparator (SC-CMP). The response speed of the switched capacitor comparator directly determines the conversion speed of the sub-ADC. High-performance switched capacitor comparators (SC-CMPs) have always been the design focus of high-speed pipeline ADCs.

[0003] There are many types of switch capacitor comparators in the related art, and the most commonly used is the fully differential switch capacitor comparator, which has the advantages of high precision, low power consumption, simple circuit structure, and small footprint. The structure of the fully differential switch capacitor comparator is as follows: Figure 1 As shown. The common-mode input voltage (VCMI) of the switched capacitor comparator and the actual common-mode input voltage (VCMX) of the comparator (CMP) seriously affect the performance of the switched capacitor comparator. It is necessary to keep VCMI, common-mode reference voltage (VCMR), ideal common-mode input voltage (VCMC) of CMP, and common-mode bias voltage (VCMS, which is also the voltage of the top plate of the capacitor) consistent with the set value VCM to achieve VCMX=VCMC. Because the speed and offset of the switched capacitor comparator are greatly affected by VCMX, it is not suitable for high-speed pipeline ADCs with variable input common mode, especially in ADC structures without sampling and holding (SHA-less). Other publicly available switched capacitor comparators, such as switched capacitor comparators based on thin-film transistor design, are also unable to achieve the effect of a wide common-mode input range.

[0004] The structure of the switched capacitor comparator with a wide common mode input range disclosed in the related art is as follows: Figure 2 As shown. Compared with the above-mentioned switched capacitor comparator, the input stage of CMP is designed with a wide input common mode range to solve the applicability problem of high-speed pipeline ADC with variable common mode. According to the different common mode levels of the input signal, different pull-up circuits and pull-down circuits are selected to realize comparators applied to low input common mode and high input common mode, and the two comparators are connected in parallel to realize application in a wide common mode input range (common mode voltage). This scheme increases the design complexity of the switched capacitor comparator, increases the parasitic capacitance of CMP, and reduces the response speed of the switched capacitor comparator. Summary of the invention

[0005] The main purpose of the present disclosure is to provide a switched capacitor comparator, an analog-to-digital converter and an electronic device to solve the technical problems of the related art that the CMP parasitic capacitance increases and the response speed slows down due to the change of the switched capacitor comparator product structure.

[0006] In order to achieve the above object, a first aspect of the present disclosure provides a switched capacitor comparator, comprising:

[0007] A switched capacitor comparator unit, having a sampling capacitor and a comparator connected in series; wherein the input of the switched capacitor comparator unit includes a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator, and the output of the switched capacitor comparator unit is a comparison result of the difference between the forward input voltage and the reverse input voltage, and the difference between the forward reference voltage and the reverse reference voltage;

[0008] A common-mode stabilization unit is used to simulate the sampling state of the switched capacitor comparator unit so that the actual common-mode input voltage of the comparator is equal to the ideal common-mode input voltage; the input of the common-mode stabilization unit includes a common-mode reference voltage, the forward input voltage, the reverse input voltage and the ideal common-mode input voltage, and the output of the common-mode stabilization unit is the common-mode bias voltage applied to the top plate of the sampling capacitor; the common-mode reference voltage is related to the forward reference voltage and the reverse reference voltage.

[0009] Furthermore, there are multiple switch capacitor comparator units, and each of the switch capacitor comparator units is connected in parallel; and,

[0010] The sampling capacitor, the forward input voltage, the reverse input voltage, the common-mode bias voltage and the common-mode reference voltage of each of the switched capacitor comparator units are the same; but the forward reference voltage and the reverse reference voltage in different switched capacitor comparator units are different.

[0011] Further, the common-mode bias voltage is in an adjustable state; and the common-mode stabilization unit is configured with the adjustable ideal common-mode input voltage, and generates the common-mode bias voltage according to the adjusted ideal common-mode input voltage, so that the common-mode bias voltage satisfies:

[0012] VCMS=VCMC+VCMR-VCMI

[0013] In the formula, VCMS represents the common-mode bias voltage, VCMC represents the ideal common-mode input voltage, VCMR represents the common-mode reference voltage, VCMR is the average of the forward reference voltage and the reverse reference voltage, VCMI represents the common-mode input voltage, and VCMI is the average of the forward input voltage and the reverse input voltage.

[0014] Further, the common-mode stabilization unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor, and an integrator; wherein,

[0015] The bottom plate of the first capacitor is divided into two paths, one path is connected to the forward input voltage through the second switch, and the other path is connected to the common-mode reference voltage through the first switch; the bottom plate of the second capacitor is also divided into two paths, one path is connected to the reverse input voltage through the third switch, and the other path is connected to the common-mode reference voltage through the fourth switch; the top plate of the first capacitor is connected in parallel with the top plate of the second capacitor and is divided into two paths, one path is connected to the output end of the integrator through the fifth switch, and the other path is connected to the input end of the integrator through the sixth switch; the reference end of the integrator is connected to the ideal common-mode input voltage, and the output end of the integrator is used as the output end of the common-mode stabilization unit and is connected to the top plate of the sampling capacitor.

[0016] Furthermore, the integrator includes a third capacitor and an operational amplifier; wherein,

[0017] Inside the integrator, the positive input terminal of the operational amplifier serves as the reference terminal of the integrator and is connected to the ideal common-mode input voltage; the negative input terminal of the operational amplifier serves as the input terminal of the integrator and is respectively connected to the top plates of the first capacitor and the second capacitor via the sixth switch; the output terminal of the operational amplifier serves as the output terminal of the integrator and is connected to the negative input terminal of the operational amplifier via the third capacitor.

[0018] Further, the first switch and the fourth switch are connected to a first control signal, the second switch and the third switch are connected to a second control signal; the fifth switch is connected to a third control signal, and the sixth switch is connected to a fourth control signal; and,

[0019] In one control cycle of the switch capacitor comparator, the third control signal has a falling edge representing shutdown information earlier than the first control signal, and the fourth control signal has a falling edge representing shutdown information earlier than the second control signal, and the first control signal, the second control signal, the third control signal, and the fourth control signal are non-overlapping signals; and

[0020] The capacitance values ​​of the first capacitor and the second capacitor are equal.

[0021] Furthermore, the switched capacitor comparator further includes a first voltage buffer; wherein,

[0022] The output end of the common mode stabilization unit is connected to the top plate of the sampling capacitor in the switch capacitor comparator unit via the first voltage buffer.

[0023] Furthermore, within a control cycle of the switch capacitor comparator, the third control signal, the first control signal, the fourth control signal, and the second control signal successively present falling edges representing shutdown information; and the initial states of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all open; the capacitor switch comparator further includes a controller; and the controller performs the following steps to complete the voltage comparison function:

[0024] In response to a falling edge of the third control signal representing shutdown information, the fifth switch is controlled to be turned off, and the output end of the common-mode stabilization unit is controlled to be connected to the top plate of the sampling capacitor;

[0025] In response to the first control signal having a falling edge representing shutdown information, the first switch and the fourth switch are controlled to be turned off, the bottom plate of the sampling capacitor is controlled to be connected to the corresponding positive reference voltage and the reverse reference voltage for sampling, the common mode reference voltage is obtained according to the sampling result, and the bottom plates of the first capacitor and the second capacitor are controlled to be connected to the common mode reference voltage;

[0026] In response to a falling edge of the fourth control signal representing shutdown information, the sixth switch is controlled to be turned off, so that the top plates of the first capacitor and the second capacitor are both connected to the input end of the integrator;

[0027] In response to the second control signal having a falling edge representing shutdown information, the second switch and the third switch are controlled to be turned off, and the bottom plate of the sampling capacitor is controlled to be connected to the corresponding forward input voltage and the reverse input voltage;

[0028] In response to the running time reaching the set threshold time that makes the actual common-mode input voltage of the comparator equal to the ideal common-mode input voltage, the comparison result of the difference between the forward input voltage and the reverse input voltage and the difference between the forward reference voltage and the reverse reference voltage is obtained through the switched capacitor comparator unit.

[0029] A second aspect of the present disclosure provides an analog-to-digital converter, comprising the above-mentioned switched capacitor comparator.

[0030] A third aspect of the present disclosure provides an electronic device, comprising the above analog-to-digital converter.

[0031] The switched capacitor comparator provided in the embodiment of the present disclosure can be applied to a high-speed pipeline ADC with a variable common mode. The goal of wide common mode input is achieved by adding a common mode stabilization unit to control the common mode input voltage of the switched capacitor comparator unit without modifying the product structure of the switched capacitor comparator. The sampling state of the switched capacitor comparator unit is simulated by the common mode stabilization unit until the actual common mode input voltage of the comparator is equal to the ideal common mode input voltage. The actual common mode input voltage can be adjusted according to the ideal common mode input voltage of the input common mode stabilization unit, ensuring the goal of variable input common mode and wide common mode input range (0.5-1.3V), thereby achieving the technical effects of wide common mode input range, small CMP parasitic capacitance and fast response speed, thereby solving the technical problems of increased CMP parasitic capacitance and slowed response speed caused by changing the product structure of the switched capacitor comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 Schematic diagram of the structure of a fully differential switched capacitor comparator;

[0034] Figure 2 is a schematic diagram of a switched capacitor comparator structure with a wide common-mode input range;

[0035] Figure 3 A schematic diagram of the structure of a switched capacitor comparator provided in an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of the structure of another switched capacitor comparator provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of a circuit structure of a common-mode stabilization unit provided in an embodiment of the present disclosure;

[0038] Figure 6 A schematic diagram of a circuit structure of an integrator provided in an embodiment of the present disclosure;

[0039] Figure 7 It is the timing diagram of each control signal in a control cycle;

[0040] Figure 8 A complete circuit diagram of a switched capacitor comparator provided in an embodiment of the present disclosure.

[0041] Fig. 9 A schematic block diagram of an analog-to-digital converter provided in an embodiment of the present disclosure;

[0042] Fig.10 A schematic block diagram of an electronic device provided in an embodiment of the present disclosure.

[0043] Reference numerals

[0044] VRP-forward reference voltage; VRN-reverse reference voltage; VINP-forward input voltage; VINN-reverse input voltage; VCM-sampling capacitor top plate voltage; VCMX-actual common mode input voltage;

[0045] VCMR-common mode reference voltage; VCMC-ideal common mode input voltage; VCMS-common mode bias voltage; VCMI-common mode input voltage; VOP-comparator positive output node; VON-comparator negative output node; VXP-comparator positive input node; VXN-comparator negative input node; ckh-first control signal; cks-second control signal; ckha-third control signal; cksa-fourth control signal; GND-ground; VDD-external power supply; OUTP-SR latch positive output node; OUTN-SR latch negative output node point; 111-seventh switch; 112-eighth switch; 113-ninth switch; 114-tenth switch; 115-eleventh switch; 116-twelfth switch; 117-fourth capacitor; 118-fifth capacitor; 119-comparator; 121-first switch; 122-second switch; 123-third switch; 124-fourth switch; 125-fifth switch; 126-sixth switch; 127-first capacitor; 128-second capacitor; 129a-third capacitor; 129b-operational amplifier; 130-first voltage buffer; 131-second voltage buffer. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] In the present disclosure, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0049] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this disclosure can be understood according to specific circumstances.

[0050] In addition, the terms "disposed", "provided with", "connected", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0051] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0052] In order to be suitable for high-speed pipeline ADC with variable common-mode input, the related art often needs to change the product structure of the switched capacitor comparator when improving the disclosed switched capacitor comparator, which brings about a series of problems such as a significant increase in the design complexity of the switched capacitor comparator, an increase in CMP parasitic capacitance, and a decrease in the response speed of the switched capacitor comparator. That is, the related art has the technical problems of an increase in CMP parasitic capacitance and a slow response speed caused by changing the product structure of the switched capacitor comparator.

[0053] In order to solve the above problems, an embodiment of the present disclosure provides a switched capacitor comparator. Figure 3 Schematic diagram of the structure of a switched capacitor comparator provided by an embodiment of the present disclosure. Figure 3 As shown, the switched capacitor comparator 100 includes a switched capacitor comparator unit 110 and a common mode stabilization unit 120 .

[0054] The switched capacitor comparator unit 110 has a sampling capacitor and a comparator 119 connected in series. The input of the switched capacitor comparator unit 110 includes a forward reference voltage VRP, a reverse reference voltage VRN, a forward input voltage VINP, a reverse input voltage VINN, and a common mode bias voltage VCMS of the comparator 119. The output of the switched capacitor comparator unit 110 is a comparison result of the difference between the forward input voltage VINP and the reverse input voltage VINN and the difference between the forward reference voltage VRP and the reverse reference voltage VRN. The switched capacitor comparator unit 110 is used to implement the voltage comparison function of the forward input voltage VINP and the reverse input voltage VINN.

[0055] The common mode stabilization unit 120 is used to simulate the sampling state of the switched capacitor comparator unit 110, so that the actual common mode input voltage VCMX of the comparator 119 is equal to the ideal common mode input voltage VCMC. The input of the common mode stabilization unit 120 includes the common mode reference voltage VCMR, the positive input voltage VINP, the reverse input voltage VINN and the ideal common mode input voltage VCMC, and the output of the common mode stabilization unit 120 is the common mode bias voltage VCMS applied to the top plate of the sampling capacitor. The common mode reference voltage VCMR is related to the positive reference voltage VRP and the reverse reference voltage VRN.

[0056] It should be noted that the common-mode stabilization unit 120 can be implemented by software programming or hardware, with the purpose of making the actual common-mode input voltage VCMX of the comparator 119 equal to the ideal common-mode input voltage VCMC. The switched capacitor comparator unit 110 can adopt a fully differential switched capacitor comparator or other off-the-shelf switched capacitor comparator products, for example, a switched capacitor comparator based on a thin film transistor design, and the embodiments of the present disclosure are not limited to this.

[0057] The common-mode reference voltage VCMR is related to the forward reference voltage VRP and the reverse reference voltage VRN, which means that the common-mode reference voltage VCMR can be set to the average or sum of the forward reference voltage VRP and the reverse reference voltage VRN, as well as other relationships, such as a multiple relationship. The embodiments of the present disclosure are not limited to this.

[0058] The switched capacitor comparator of the disclosed embodiment is applicable to any application scenario of the existing analog-to-digital converter. For example, in a high-speed pipeline ADC, the switched capacitor comparator of the disclosed embodiment can achieve the purpose of a wide common-mode input range without changing the product structure of the switched capacitor comparator, compared with the prior art, without causing an increase in CMP parasitic capacitance and a slow response speed, and has obvious technical advantages over the existing switched capacitor comparator with a wide common-mode input range.

[0059] exist Figure 3 Based on the structure of the switched capacitor comparator shown, preferably, the switched capacitor comparator further includes a first voltage buffer 130. The output end of the common mode stabilization unit 120 is connected to the top plate of the sampling capacitor in the switched capacitor comparator unit 110 via the first voltage buffer 130. The first voltage buffer 130 is used to prevent the load from interfering with the signal source, maintain the amplitude and shape of the signal, and enhance the current of the output signal, improve the driving capability of the output current, and improve the bandwidth.

[0060] Figure 4 FIG. 1 is a schematic diagram of another structure of a switched capacitor comparator provided in an embodiment of the present disclosure. Figure 4 As shown, there are multiple switched capacitor comparator units 110, the number is n, and each switched capacitor comparator unit 110 is connected in parallel. Among them, the sampling capacitor, the positive input voltage VINP, the reverse input voltage VINN, the common mode bias voltage VCMS and the common mode reference voltage VCMR of each switched capacitor comparator unit 110 are the same. However, the positive reference voltage VRP and the reverse reference voltage VRN in different switched capacitor comparator units 110 are different to obtain different output results. For example, VCMR = (VRP + VRN) / 2, but VRP and VRN are different, for example, VRP = 1.4 and VRN = 0.4 in the first switched capacitor comparator unit, and VRP = 1.2 and VRN = 0.6 in the second switched capacitor comparator unit.

[0061] As a preferred embodiment, for the common-mode stabilization unit 120, the output common-mode bias voltage VCMS is in an adjustable state. In addition, the common-mode stabilization unit 120 is configured with an adjustable ideal common-mode input voltage VCMC, and generates a target common-mode bias voltage VCMS according to the adjusted ideal common-mode input voltage VCMC, so that the common-mode bias voltage VCMS satisfies:

[0062] VCMS=VCMC+VCMR-VCMI

[0063] Wherein, VCMC represents the ideal common-mode input voltage VCMC, VCMR represents the common-mode reference voltage VCMR, VCMR is the average of the forward reference voltage VRP and the reverse reference voltage VRN, VCMI represents the common-mode input voltage, VCMI is the average of the forward input voltage VINP and the reverse input voltage VINN.

[0064] Through the above formula, the common-mode stabilizing unit 120 achieves the design goal of VCMX=VCMC.

[0065] Figure 5 Schematic diagram of a circuit structure of the common mode stabilization unit 120 provided in an embodiment of the present disclosure. Figure 5 As shown, the common mode stabilization unit 120 includes a first switch 121, a second switch 122, a third switch 123, a fourth switch 124, a fifth switch 125, a sixth switch 126, a first capacitor 127, a second capacitor 128, and an integrator 129. Among them, the bottom plate of the first capacitor 127 is divided into two paths, one path is connected to the positive input voltage VINP through the second switch 122, and the other path is connected to the common mode reference voltage VCMR through the first switch 121. The bottom plate of the second capacitor 128 is also divided into two paths, one path is connected to the reverse input voltage VINN through the third switch 123, and the other path is connected to the common mode reference voltage VCMR through the fourth switch 124. The top plate of the first capacitor 127 is connected in parallel with the top plate of the second capacitor 128 and is divided into two paths, one path is connected to the output end of the integrator 129 through the fifth switch 125, and the other path is connected to the input end of the integrator 129 through the sixth switch 126. The reference end of the integrator 129 is connected to the ideal common mode input voltage VCMC, and the output end of the integrator 129 is connected to the top plate of the sampling capacitor as the output end of the common mode stabilization unit 120. The common mode stabilization unit 120 of the circuit structure has the advantages of simple structure and fast response speed.

[0066] exist Figure 5 Based on the structure of the switched capacitor comparator shown, preferably, the switched capacitor comparator further includes a second voltage buffer 131. The input terminal of the second voltage buffer 131 is connected to the output terminal of the integrator 129, and the output terminal thereof is connected to the fifth switch 125. The second voltage buffer 131 is designed to provide an interface between the input and the output to reduce the loss of the signal during the transmission process due to factors such as resistance and capacitance, and optimize the signal transmission.

[0067] Figure 6 FIG. 1 is a schematic diagram of a circuit structure of the integrator 129 provided in an embodiment of the present disclosure. Figure 6As shown, the integrator 129 includes a third capacitor 129a and an operational amplifier 129b. In the integrator 129, the positive input terminal of the operational amplifier 129b serves as the reference terminal of the integrator 129 and is connected to the ideal common-mode input voltage VCMC, and the reverse input terminal serves as the input terminal of the integrator 129 and is connected to the top plates of the first capacitor 127 and the second capacitor 128 respectively through the sixth switch 126; the output terminal of the operational amplifier 129b serves as the output terminal of the integrator 129 and is connected to the negative input terminal of the operational amplifier 129b through the third capacitor 129a. The capacitance value of the third capacitor 129a determines the step size of the common-mode bias voltage VCMS.

[0068] For the first switch 121 to the sixth switch 126, preferably, the first switch 121 and the fourth switch 124 are connected to the first control signal ckh, the second switch 122 and the third switch 123 are connected to the second control signal cks; the fifth switch 125 is connected to the third control signal ckha, and the sixth switch 126 is connected to the fourth control signal cksa. Moreover, within a control cycle of the switch capacitor comparator, the third control signal ckha has a falling edge representing the shutdown information earlier than the first control signal ckh, and the fourth control signal cksa has a falling edge representing the shutdown information earlier than the second control signal cks, and the first control signal ckh, the second control signal cks, the third control signal ckha, and the fourth control signal cksa are non-overlapping signals. The setting of the control signal ensures that the control function of the switch capacitor comparator is effective.

[0069] For the first capacitor 127 and the second capacitor 128 , preferably, the capacitance values ​​of the first capacitor 127 and the second capacitor 128 are equal, so that the sampling state effect of the analog switched capacitor comparator unit 110 is better.

[0070] It should be noted that the integrator 129 is not limited to Figure 6 The circuit structure in the embodiment can be replaced by other types of integrating devices or integrating circuits to realize the functions of the integrator 129 of the present disclosure, which is also within the protection scope of the present disclosure.

[0071] Figure 7 The timing diagram of each control signal within a control cycle provided by the embodiment of the present disclosure. Figure 7 As shown, in one control cycle (dashed box) of the switched capacitor comparator, the third control signal ckha, the first control signal ckh, the fourth control signal cksa, and the second control signal cks successively appear falling edges representing shutdown information. The first switch 121, the second switch 122, the third switch 123, the fourth switch 124, the fifth switch 125, and the sixth switch 126 are all initially open, and are closed after receiving the falling edge of the corresponding control signal, and are opened again after receiving the rising edge of the corresponding control signal.

[0072] Preferably, the switched capacitor comparator further comprises a controller. In one control cycle, the controller performs the following steps to complete the voltage comparison function:

[0073] S1. In response to the falling edge of the third control signal ckha representing the shutdown information, the fifth switch 125 is controlled to be turned off, and the output end of the common mode stabilization unit 120 is connected to the top plate of the sampling capacitor;

[0074] S2. In response to the first control signal ckh having a falling edge representing shutdown information, the first switch 121 and the fourth switch 124 are controlled to be turned off, and the bottom plate of the sampling capacitor is controlled to be connected to the corresponding positive reference voltage VRP and the reverse reference voltage VRN for sampling, and the common mode reference voltage VCMR is obtained according to the sampling result, and the bottom plates of the first capacitor 127 and the second capacitor 128 are controlled to be connected to the common mode reference voltage VCMR;

[0075] S3. In response to the falling edge of the fourth control signal cksa representing the shutdown information, the sixth switch 126 is controlled to be turned off, so that the top plates of the first capacitor 127 and the second capacitor 128 are connected to the input terminal of the integrator 129;

[0076] S4. In response to the falling edge of the second control signal cks representing the shutdown information, the second switch 122 and the third switch 123 are controlled to be turned off, and the bottom plate of the sampling capacitor is controlled to be connected to the corresponding positive input voltage VINP and the reverse input voltage VINN;

[0077] S5. In response to the running time reaching the set threshold time that makes the actual common-mode input voltage VCMX of the comparator 119 equal to the ideal common-mode input voltage VCMC, the comparison result of the difference between the forward input voltage VINP and the reverse input voltage VINN and the difference between the forward reference voltage VRP and the reverse reference voltage VRN is obtained through the switched capacitor comparator unit.

[0078] It should be noted that the above steps can be executed in a control system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0079] Figure 8 Schematic diagram of a complete circuit of a switched capacitor comparator provided by an embodiment of the present disclosure. The switched capacitor comparator unit is a fully differential switched capacitor comparator, such as Figure 8As shown, the switch capacitor comparator unit includes a seventh switch 111, an eighth switch 112, a ninth switch 113, a tenth switch 114, an eleventh switch 115, a twelfth switch 116, a fourth capacitor 117, a fifth capacitor 118, and a comparator 119. The fourth capacitor 117 and the fifth capacitor 118 are both sampling capacitors, and the capacitance values ​​of the two are equal. The bottom plate of the fourth capacitor 117 is divided into two paths, one path is connected to the positive input voltage VINP through the eighth switch 112, and the other path is connected to the positive reference voltage VRP through the seventh switch 111. The top plate of the fourth capacitor 117 is also divided into two paths, one path is connected to the positive input terminal of the comparator 119, and the other path is connected to the output terminal of the common mode stabilization unit 110 through the eleventh switch 115; the bottom plate of the fifth capacitor 118 is divided into two paths, one path is connected to the reverse input voltage VINN through the ninth switch 113, and the other path is connected to the negative reference voltage VRN through the tenth switch 114. The top plate of the fifth capacitor 118 is also divided into two paths, one path is connected to the positive input terminal of the comparator 119, and the other path is connected to the output terminal of the common mode stabilization unit 110 through the twelfth switch 116. The seventh switch 111 and the tenth switch 114 are connected to the first control signal ckh; the eighth switch 112 and the ninth switch 113 are connected to the second control signal cks. The eleventh switch 115 and the twelfth switch 116 are connected to the third control signal ckha.

[0080] From the above description, it can be seen that the present disclosure achieves the following technical effects:

[0081] 1. A common-mode stabilization module 120 is used to detect a common-mode input voltage VCMI (including a positive input voltage VINP and a reverse input voltage VINN) and a common-mode reference voltage VCMR. The voltage value of the top plate of the capacitor when the switched capacitor comparator samples the common-mode reference voltage VCMR is generated according to the ideal input common-mode voltage VCMC required by the comparator positive input node VXP and the comparator negative input node VXN, i.e., VCMS. The voltage value is then output through the first voltage buffer 130 to the sampling circuits of all switched capacitor comparator units 110 in the sub-ADC. The goal of the common-mode stabilization circuit 120 is to make VCMS = VCMC + VCMR - VCMI.

[0082] 2. The common-mode stabilization module 120 simulates the sampling state of the switched capacitor comparator unit 110, and then achieves the above goal through the integrator 129. In the ckh phase, the switched capacitor comparator unit 110 samples the reference voltage of the comparator 119, and the bottom plates of the sampling capacitors are respectively connected to the positive input node VXP and the negative input node VXN of the comparator, and the top plates are connected to VCMS. At this time, the bottom plates of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 are connected to VCMR=(VRP+VRN) / 2, and the top plates are also connected to VCMS. In the cks phase, the bottom plate of the sampling capacitor of the switched capacitor comparator unit 110 and the bottom plates of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 are all connected to the input, the top plate of the sampling capacitor of the switched capacitor comparator unit 110 is connected to the input of the comparator 119, and the top plates of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 are connected to the negative input terminal of the integrator amplifier. According to the virtual short of the op amp input, the charge generated on the capacitor due to the difference between the common-mode levels in the ckh phase is transferred to the integrating capacitor, i.e., the third capacitor 129a, so the output of the integrating amplifier changes. After several cycles of integration adjustment, VCMS=VCMC+VCMR-VCMI is finally realized, thereby achieving the design goal of VCMX=VCMC.

[0083] The present disclosure also provides an analog-to-digital converter, such as Fig. 9 As shown, the analog-to-digital converter 10 includes the above-mentioned switched capacitor comparator 100. It should be noted that, for the sake of clarity and simplicity, the embodiment of the present disclosure does not provide all the components of the analog-to-digital converter 10. To achieve the necessary functions of the analog-to-digital converter 10, those skilled in the art can provide and set other components not shown according to specific needs, and the embodiment of the present disclosure does not limit this.

[0084] The present disclosure also provides an electronic device, for example, Fig.10As shown, the electronic device 1 includes a processor 20 and an analog-to-digital converter 10. The processor 20 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips. The general-purpose processor may be a microprocessor or any conventional processor.

[0085] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device 1, those skilled in the art may provide and set other components not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0086] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A switched capacitor comparator, characterized in that: include: A switched capacitor comparator unit, having a sampling capacitor and a comparator connected in series; wherein the input of the switched capacitor comparator unit includes a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator, and the output of the switched capacitor comparator unit is a comparison result of the difference between the forward input voltage and the reverse input voltage, and the difference between the forward reference voltage and the reverse reference voltage; A common-mode stabilization unit is used to simulate the sampling state of the switched capacitor comparator unit so that the actual common-mode input voltage of the comparator is equal to the ideal common-mode input voltage; the input of the common-mode stabilization unit includes a common-mode reference voltage, the forward input voltage, the reverse input voltage and the ideal common-mode input voltage, and the output of the common-mode stabilization unit is the common-mode bias voltage applied to the top plate of the sampling capacitor; the common-mode reference voltage is related to the forward reference voltage and the reverse reference voltage.

2. The switched capacitor comparator according to claim 1, wherein: The number of the switch capacitor comparator units is multiple, and each of the switch capacitor comparator units is connected in parallel; and, The sampling capacitor, the forward input voltage, the reverse input voltage, the common-mode bias voltage and the common-mode reference voltage of each of the switched capacitor comparator units are the same; but the forward reference voltage and the reverse reference voltage in different switched capacitor comparator units are different.

3. The switched capacitor comparator according to claim 1 or 2, characterized in that: The common-mode bias voltage is in an adjustable state; and the common-mode stabilization unit is configured with the adjustable ideal common-mode input voltage, and generates the common-mode bias voltage according to the adjusted ideal common-mode input voltage, so that the common-mode bias voltage satisfies: VCMS=VCMC+VCMR-VCMI In the formula, VCMS represents the common-mode bias voltage, VCMC represents the ideal common-mode input voltage, VCMR represents the common-mode reference voltage, VCMR is the average of the forward reference voltage and the reverse reference voltage, VCMI represents the common-mode input voltage, and VCMI is the average of the forward input voltage and the reverse input voltage.

4. The switched capacitor comparator according to claim 1 or 2, characterized in that: The common-mode stabilization unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor, and an integrator; wherein, The bottom plate of the first capacitor is divided into two paths, one path is connected to the forward input voltage through the second switch, and the other path is connected to the common-mode reference voltage through the first switch; the bottom plate of the second capacitor is also divided into two paths, one path is connected to the reverse input voltage through the third switch, and the other path is connected to the common-mode reference voltage through the fourth switch; the top plate of the first capacitor is connected in parallel with the top plate of the second capacitor and is divided into two paths, one path is connected to the output end of the integrator through the fifth switch, and the other path is connected to the input end of the integrator through the sixth switch; the reference end of the integrator is connected to the ideal common-mode input voltage, and the output end of the integrator is used as the output end of the common-mode stabilization unit and is connected to the top plate of the sampling capacitor.

5. The switched capacitor comparator according to claim 4, characterized in that: The integrator includes a third capacitor and an operational amplifier; wherein, Inside the integrator, the positive input terminal of the operational amplifier serves as the reference terminal of the integrator and is connected to the ideal common-mode input voltage; the negative input terminal of the operational amplifier serves as the input terminal of the integrator and is respectively connected to the top plates of the first capacitor and the second capacitor via the sixth switch; the output terminal of the operational amplifier serves as the output terminal of the integrator and is also connected to the negative input terminal of the operational amplifier via the third capacitor.

6. The switched capacitor comparator according to claim 5, characterized in that: The first switch and the fourth switch are connected to the first control signal, the second switch and the third switch are connected to the second control signal; the fifth switch is connected to the third control signal, and the sixth switch is connected to the fourth control signal; and, In one control cycle of the switch capacitor comparator, the third control signal has a falling edge representing shutdown information earlier than the first control signal, and the fourth control signal has a falling edge representing shutdown information earlier than the second control signal, and the first control signal, the second control signal, the third control signal, and the fourth control signal are non-overlapping signals; and The capacitance values ​​of the first capacitor and the second capacitor are equal.

7. The switched capacitor comparator according to any one of claims 1, 2, 5 and 6, characterized in that: Also includes a first voltage buffer; wherein, The output end of the common mode stabilization unit is connected to the top plate of the sampling capacitor in the switch capacitor comparator unit via the first voltage buffer.

8. The switched capacitor comparator according to claim 6, characterized in that: In one control cycle of the switch capacitor comparator, the third control signal, the first control signal, the fourth control signal, and the second control signal successively present falling edges representing shutdown information; and the initial states of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all open; the capacitor switch comparator further includes a controller, and the controller executes the following steps to complete the voltage comparison function: In response to a falling edge of the third control signal representing shutdown information, the fifth switch is controlled to be turned off, and the output end of the common-mode stabilization unit is controlled to be connected to the top plate of the sampling capacitor; In response to the first control signal having a falling edge representing shutdown information, the first switch and the fourth switch are controlled to be turned off, the bottom plate of the sampling capacitor is controlled to be connected to the corresponding positive reference voltage and the reverse reference voltage for sampling, the common mode reference voltage is obtained according to the sampling result, and the bottom plates of the first capacitor and the second capacitor are controlled to be connected to the common mode reference voltage; In response to a falling edge of the fourth control signal representing shutdown information, the sixth switch is controlled to be turned off, so that the top plates of the first capacitor and the second capacitor are both connected to the input end of the integrator; In response to the second control signal having a falling edge representing shutdown information, the second switch and the third switch are controlled to be turned off, and the bottom plate of the sampling capacitor is controlled to be connected to the corresponding forward input voltage and the reverse input voltage; In response to the running time reaching the set threshold time that makes the actual common-mode input voltage of the comparator equal to the ideal common-mode input voltage, the comparison result of the difference between the forward input voltage and the reverse input voltage and the difference between the forward reference voltage and the reverse reference voltage is obtained by the switched capacitor comparator unit.

9. An analog-to-digital converter, characterized in that: A switched capacitor comparator comprising any one of claims 1-8.

10. An electronic device, characterized in that: Includes the analog-to-digital converter as claimed in claim 9.

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