High-precision ramp generator and two-step single-slope analog-to-digital converter

Abstract

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and in particular relates to a high-precision ramp generator and a two-step single-slope analog-to-digital converter. Background Technology

[0002] Single-slope analog-to-digital converters (SS-ADCs) are widely used in modern CMOS (Complementary Metal Oxide Semiconductor) image sensors. The ramp generator, a crucial component of the SS-ADC, is responsible for generating the quantization ramp, which, in conjunction with comparators and counters, quantizes the pixel signal. Its performance determines the accuracy and conversion speed of the SS-ADC, directly impacting the image sensor's resolution and readout frame rate.

[0003] As CMOS image sensor pixel arrays become larger and their performance improves, the overall readout circuit architecture using only column-parallel ADCs is no longer sufficient to meet application requirements. To improve performance, various SS-ADCs have been designed and used, such as multi-slope SS-ADCs, multi-ramp SS-ADCs, and TDC-compatible SS-ADCs. All of these SS-ADC structures can be collectively referred to as two-step SS-ADCs, with multi-slope two-step SS-ADCs being the most widely used and studied. Its principle is to divide the quantization of a pixel signal into two steps: the M-bit precision quantization process is divided into C-bit coarse quantization and F-bit fine quantization, satisfying M = C + F. First, the voltage range of the pixel signal is found using the coarse quantization ramp. The characteristic of a coarse ramp is a large voltage span; let the quantization range be V. range Then the voltage change of the coarse-quantized ramp in each step is V. range / 2 C By defining a specific small interval and then connecting a fine ramp, the clock cycles required for quantization can be reduced from 2... M Optimized to 2 C +2 F This method achieves M-bit precision signal quantization while significantly increasing quantization speed. Its drawback lies in the high complexity of the ramp generator design; when the coarse quantization ramp bit depth is 2... C At that time, 2 is required. C The presence of fine-slope voltages with the same slope but different voltage ranges places high demands on the design complexity and power consumption of the ramp generator. Therefore, as a crucial component for achieving two-step quantization in SS-ADC, the ramp generator needs further improvement and optimization. Summary of the Invention

[0004] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high-precision ramp generator and a two-step single-slope analog-to-digital converter.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A high-precision ramp generator has both a DAC-type ramp generator operating mode and a capacitor-integrating ramp generator operating mode, including...

[0007] A bandgap reference source circuit is used to generate a reference voltage V. bg ;

[0008] Voltage-to-current conversion circuit, used to convert reference voltage V bg Converted to a stable current I c and mirror current I c Provided to the weighted current DAC current source array and the charge / discharge current regulation circuit;

[0009] A weighted current DAC current source array is used to output a stepped voltage V in DAC-type ramp generator operation mode. dac ;

[0010] The charge / discharge current regulation circuit is used to output the charge / discharge current I when the capacitor integrating ramp generator is in operation mode. charge ;

[0011] The mode switching circuit is used to switch between DAC-type ramp generator operating modes based on the trapezoidal ramp voltage V. dac Outputs a periodically varying stepped ramp signal; and in the capacitor-integrating ramp generator operating mode, it is based on the charging and discharging current I. charge Output a linearly varying ramp signal; and

[0012] Bias circuit, used to generate ramp-on voltage V ref Provided to the mode switching circuit.

[0013] Furthermore, the voltage-to-current conversion circuit includes an operational amplifier A1 and a resistor R. BG And PMOS transistor P0, the non-inverting output terminal of operational amplifier A1 is connected to reference voltage V. bg The inverting input terminal of the operational amplifier A1 is connected to a resistor R. BG Grounded; the inverting input terminal of the operational amplifier A1 is also electrically connected to the drain of the PMOS transistor P0, the output terminal of the operational amplifier A1 is electrically connected to the gate of the PMOS transistor P0, and the source of the PMOS transistor P0 is connected to the power supply voltage.

[0014] Furthermore, the weighted current DAC current source array includes a resistor R. DACThe circuit comprises an n-stage mirror current source circuit, each of which includes a mirror transistor unit and a current source control switch. The sources of all n mirror transistor units are connected to the power supply voltage, and the gates of all n mirror transistor units are electrically connected to the output terminal of operational amplifier A1. The drain of each mirror transistor unit is connected to resistor R through a current source control switch. DAC The first terminal is electrically connected, and the resistor R DAC The second end is grounded.

[0015] Furthermore, each stage of the current mirror circuit comprises 2 mirror transistor units. i-1 A parallel reference PMOS transistor, where i represents the stage of the mirror current source circuit, 1≤i≤n.

[0016] Furthermore, the charge / discharge current regulation circuit includes a PMOS transistor P1, an NMOS transistor N0, an NMOS transistor N1, and an NMOS transistor N2. The source of the PMOS transistor P1 is connected to the power supply voltage, and the gate of the PMOS transistor P1 is electrically connected to the output terminal of the operational amplifier A1. The drain of the PMOS transistor P1 is electrically connected to the drain and gate of the NMOS transistor N0, the drain of the NMOS transistor N1, and the gate of the NMOS transistor N2. The sources of the NMOS transistors N0, N1, and N2 are all grounded. The gate of the NMOS transistor N1 is connected to the mode control signal Vbn, and the drain of the NMOS transistor N2 is used to output the charge / discharge current I. charge When the high-precision ramp generator operates in DAC-type ramp generator mode, the control signal Vbn turns on the NMOS transistor N1; when the high-precision ramp generator operates in capacitor-integrating ramp generator mode, the control signal Vbn turns off the NMOS transistor N1.

[0017] Furthermore, the aspect ratio of the NMOS transistor N2 is obtained by reducing or increasing the aspect ratio of the NMOS transistor N0 by a predetermined ratio.

[0018] Furthermore, the mode switching circuit includes

[0019] The ramp signal output buffer circuit is used as a buffer drive stage in the DAC-type ramp generator operating mode to drive the stepped ramp voltage V. dac To generate a stepped ramp voltage; and to function as an integration circuit in the capacitor-integrating ramp generator operating mode, with the ramp initiation voltage V. ref Using the reference voltage, the charging and discharging current I charge Forming a linear ramp voltage; and

[0020] Switched capacitor circuit, including ramp sampling capacitor C sThis is used to connect the stepped ramp signal to the ramp sampling capacitor C when the DAC-type ramp generator is in operation mode. s The upper plate will hold the ramp-start voltage V. ref Connect the ramp sampling capacitor C s The lower plate outputs the ramp signal; and in the capacitor integrating ramp generator operating mode, the linear ramp voltage is connected to the ramp sampling capacitor C. s The lower plate utilizes the principle of charge conservation in capacitance to output a linear ramp voltage as the ramp signal V. ramp .

[0021] Furthermore, the ramp signal output buffer circuit includes an operational amplifier A2 and a linear ramp capacitor C. RAMP Input control switch Input control switch Capacitor control switch and capacitor control switch The operational amplifier A2 is an input-output rail-to-rail operational amplifier, and the non-inverting input terminal of the operational amplifier A2 is controlled by an input switch. The ramp-start voltage V output from the bias circuit ref The non-inverting input of the operational amplifier A2 is also controlled by an input switch. The stepped voltage V output from the current source array of the connected current-weighted DAC is... dac The inverting input of the operational amplifier A2 is connected to the charging / discharging current I output by the charging / discharging current regulation circuit. charge The inverting input of the operational amplifier A2 is controlled by a capacitor-controlled switch. and linear ramp capacitance C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor-controlled switch. It is electrically connected to its output terminal;

[0022] When the high-precision ramp generator is operating in DAC type ramp generator mode, the input control switch... Turn on, input control switch Closed, capacitor-controlled switch Turn on the capacitor control switch. Closed; when the high-precision ramp generator is operating in capacitor integrating ramp generator mode, the input control switch is closed. Close, input control switch Turn on the capacitor control switch. Closed, capacitor-controlled switch Open.

[0023] Furthermore, the switched capacitor circuit also includes a capacitor control switch. Capacitor control switch and capacitor control switch The ramp sampling capacitor C s The lower electrode plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. s The lower electrode plate also controls the switch via a capacitor. The ramp-start voltage V output from the bias circuit ref The slope sampling capacitor C s The upper plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. s The upper plate also serves as the output terminal of a high-precision ramp generator, outputting a linear ramp voltage V. ramp ;

[0024] When the high-precision ramp generator operates in DAC-type ramp generator mode, the capacitor-controlled switch... and capacitor control switch Closed, capacitor-controlled switch Turn on; when the high-precision ramp generator is operating in capacitor integrating ramp generator mode, the capacitor control switch is on. and capacitor control switch Turn on the capacitor control switch. closure.

[0025] A two-step single-slope analog-to-digital converter includes a ramp generator, a column comparator, a counter, a memory, and a digital logic control module. The ramp generator is a high-precision ramp generator. The non-inverting input of the column comparator is electrically connected to the output of the ramp generator, and the inverting input of the column comparator is used to connect to the pixel signal V output from the pixel output terminal. sig The output of the column comparator is electrically connected to a counter, the counter is electrically connected to a memory, the memory is used to output the analog-to-digital conversion result, and the memory is also electrically connected to a digital logic control module, which is used to generate control signals, and the control signals are used to switch the working mode of the ramp generator.

[0026] In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, which significantly reduces the quantization time. Furthermore, a single output stage can be used to combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design and improving the compatibility of the ramp generator. This invention also solves the linearity and stability problems introduced by stepped ramps in high-speed and high-precision applications, and reduces design complexity. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0028] Figure 1 This is a structural block diagram of an embodiment of the high-precision ramp generator of the present invention.

[0029] Figure 2 This is a circuit diagram of a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, and a mode switching circuit.

[0030] Figure 3 This is the equivalent ramp generator circuit when the embodiment operates in DAC-type ramp generator mode.

[0031] Figure 4 This is the equivalent ramp generator circuit when the embodiment operates in the capacitor integrating ramp generator mode.

[0032] Figure 5 This is a structural block diagram of an embodiment of the two-step single-slope analog-to-digital converter of the present invention.

[0033] Figure 6 This is a timing diagram of the relevant voltages in a two-step SS-ADC.

[0034] The diagrams in the instruction manual are labeled as follows:

[0035] Bandgap reference source circuit-1; Voltage-to-current conversion circuit-2; Weighted current DAC current source array-3; Charge / discharge current regulation circuit-4; Mode switching circuit-5; Ramp signal output buffer circuit-51; Switched capacitor circuit-52; Bias circuit-6; Mirror transistor units-PM1, PM2, ..., PMn; Control switch Ramp generator - 100; Pixel output terminal - 200; Column comparator - 300; Counter - 400; Memory - 500; Digital logic control module - 600. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] Currently, ramp generators can be implemented in two main ways. One type utilizes current integration within a capacitor to generate a ramp voltage, known as a capacitor-integrating ramp generator. This type can produce a continuous linear ramp signal, and different ramp rates can be achieved depending on the capacitor size and charging / discharging current. Its advantages include adjustable ramp voltage slope, simple structure, good linearity, and good noise performance. However, its voltage accuracy is not high, and the continuous voltage form has poor compatibility with complex SS-ADC structures such as two-step converters, making accurate sampling difficult. The other approach uses a digital-to-analog converter (DAC). DAC-type ramp generators can generate stepped voltages as ramp signals. They offer high voltage accuracy and excellent ramp resolution, but as the DAC bit depth increases, its structure becomes increasingly complex, introducing significant stability, speed, and noise issues in different applications.

[0038] A patent publication describes a two-step single-slope analog-to-digital converter (SS-ADC) with a multi-slope architecture. It employs two different precision current-controlled DACs to generate the slope, dividing the single quantization into two coarse and fine quantization operations, significantly improving the conversion speed of the SS-ADC. It also uses capacitive coupling to access the slope signal, accommodating the switching and connection between coarse and fine slope voltages, thus solving the problems of high slope generator complexity and slope connection in traditional two-step SS-ADCs. However, in the application of high-speed, large-array CMOS image sensors, the system operating frequency and the number of bits in the DAC are increased, resulting in a significant decrease in slope linearity and a surge in design difficulty under limited area and power consumption requirements. Furthermore, the effects of DAC-type slope voltage settling time and glitches / noise are difficult to resolve under high-speed and high-precision requirements.

[0039] Please see Figure 1 , Figure 1 This is a structural block diagram of an embodiment of the high-precision ramp generator of the present invention. The high-precision ramp generator of this embodiment includes a bandgap reference source circuit 1, a voltage-to-current conversion circuit 2, a weighted current DAC current source array 3, a charge / discharge current control circuit 4, a mode switching circuit 5, and a bias circuit 6. The high-precision ramp generator of this embodiment has two operating modes: a DAC-type ramp generator operating mode and a capacitor-integrating ramp generator operating mode. When coarse quantization is required, the high-precision ramp generator operates in the DAC-type ramp generator operating mode; when fine quantization is required, the high-precision ramp generator operates in the capacitor-integrating ramp generator operating mode.

[0040] Please see Figure 2 The bandgap reference source circuit 1 is used to generate a temperature-independent reference voltage V. bg The voltage-to-current conversion circuit 2 is used to convert the reference voltage V bgConverted to a stable current I c and mirror the current I c The current source array 3 for the weighted current DAC and the charging / discharging current regulation circuit 4 are provided. The voltage-to-current conversion circuit 2 may include an operational amplifier A1 and a resistor R. BG And PMOS transistor P0, the non-inverting output terminal of operational amplifier A1 is connected to reference voltage V. bg The inverting input terminal of the operational amplifier A1 is connected to a resistor R. BG Grounded. The inverting input terminal of the operational amplifier A1 is also electrically connected to the drain of the PMOS transistor P0, the output terminal of the operational amplifier A1 is electrically connected to the gate of the PMOS transistor P0, and the source of the PMOS transistor P0 is connected to the power supply voltage.

[0041] Using the above structure, operational amplifier A1 and resistor R BG Together with the PMOS transistor P0, they form a negative feedback loop, which can convert the reference voltage V... bg Convert to a stable size of V bg / R BG Current I c And through the gate voltage V of the P0 transistor G Mirror the current I c The current source array 3 and the charge / discharge current regulation circuit 4 are provided to generate the required ramp voltage.

[0042] Please continue reading. Figure 2 The weighted current DAC current source array 3 only operates in the DAC-type ramp generator operating mode, and is used to output a stepped voltage V in the DAC-type ramp generator operating mode. dac The weighted current DAC current source array 3 may include a resistor R. DAC The circuit consists of an n-stage mirror current source circuit, where n represents the number of DAC bits in the DAC-type ramp generator. Each of the aforementioned mirror current source circuits includes a mirror transistor unit and a current source control switch; that is, the n-stage mirror current source circuit includes mirror transistor units PM1, PM2, ..., PMn, and a current source control switch. Current source control switch ...current source control switch Each stage of the current mirror circuit includes 2 mirror transistor units. i-1 The current mirror circuit consists of 1 parallel reference PMOS transistors, where i represents the stage number of the current mirror circuit, 1 ≤ i ≤ n. That is, the first-stage current mirror circuit's transistor unit PM1 includes one reference PMOS transistor, the second-stage current mirror circuit's transistor unit PM2 includes two reference PMOS transistors connected in parallel, ..., and so on, with the nth-stage current mirror circuit's transistor unit PMn including 2...n-1 A reference PMOS transistor connected in parallel.

[0043] The sources of all n image transistor units are connected to the power supply voltage, and the gates of all n image transistor units are electrically connected to the output terminal of operational amplifier A1. The drain of each image transistor unit is controlled by a current source to switch and resistor R. DAC The first terminal is electrically connected; specifically, the drain of the mirror transistor unit PM1 is controlled by a current source to switch. With resistance R DAC The first terminal is electrically connected, and the drain of the mirror transistor unit PM2 is controlled by a current source to switch. With resistance R DAC The first terminal is electrically connected, ..., and so on. The drain of the mirror transistor unit PMn is controlled by a current source to switch. With resistance R DAC The first terminal is electrically connected. The resistor R... DAC The second terminal is grounded. By periodically controlling the switches of each current source, different magnitudes of current can be conducted, thereby affecting the resistance R. DAC The upper part generates a stepped ramp voltage V with a defined voltage value. dac .

[0044] Please continue reading. Figure 2 The charging / discharging current regulation circuit 4 only operates in the capacitor integrating ramp generator operating mode, and is used to output the charging / discharging current I in the capacitor integrating ramp generator operating mode. charge The charging / discharging current regulation circuit 4 may include a PMOS transistor P1, an NMOS transistor N0, an NMOS transistor N1, and an NMOS transistor N2. The aspect ratio of the NMOS transistor N2 is obtained by reducing or increasing the aspect ratio of the NMOS transistor N0 by a predetermined ratio. The source of the PMOS transistor P1 is connected to the power supply voltage, and the gate of the PMOS transistor P1 is electrically connected to the output terminal of the operational amplifier A1. The drain of the PMOS transistor P1 is electrically connected to the drain and gate of the NMOS transistor N0, the drain of the NMOS transistor N1, and the gate of the NMOS transistor N2. The sources of the NMOS transistors N0, NMOS transistor N1, and NMOS transistor N2 are all grounded. The gate of the NMOS transistor N1 is connected to the mode control signal Vbn, and the drain of the NMOS transistor N2 is used to output the charging / discharging current I. charge .

[0045] Using the above structure, NMOS transistor N1 acts as a switch. When the high-precision ramp generator operates in capacitor integrating ramp generator mode, the control signal Vbn turns off NMOS transistor N1. This allows the charge / discharge current regulation circuit 4 to operate normally, controlling the current through PMOS transistor P1 and voltage Vbn. GThe current is mirrored, and its magnitude is controlled by a current mirror structure composed of NMOS transistors N0 and N2 to generate a charging and discharging current I. charge Using the width-to-length ratio of NMOS transistor N0 as the standard unit, scaling the width-to-length ratio of NMOS transistor N2 by a ratio of 1:x allows control over the magnitude of the charging / discharging current and the slope of the linear ramp. When the high-precision ramp generator operates in DAC-type ramp generator mode, the control signal Vbn turns on NMOS transistor N1, thereby stopping the charging / discharging current regulation circuit 4 from working.

[0046] The mode switching circuit 5 has two operating modes: a DAC-type ramp generator operating mode and a capacitor-integrating ramp generator operating mode. In the DAC-type ramp generator operating mode, it is used to adjust the ramp voltage V according to the slope. dac Outputs a periodically varying stepped ramp signal; and in the capacitor-integrating ramp generator operating mode, it is based on the charging and discharging current I. charge The output is a linearly varying ramp signal. The bias circuit 6 is used to generate the ramp initiation voltage V. ref Provided to mode switching circuit 5.

[0047] In this embodiment, the mode switching circuit 5 includes a ramp signal output buffer circuit 51 and a switched capacitor circuit 52. The ramp signal output buffer circuit 51 is used as a buffer drive stage in the DAC-type ramp generator operating mode to drive the stepped ramp voltage V. dac To generate a stepped ramp voltage; and to function as an integration circuit in the capacitor-integrating ramp generator operating mode, with the ramp initiation voltage V. ref Using the reference voltage, the charging and discharging current I charge A linear ramp voltage is formed.

[0048] The ramp signal output buffer circuit 51 may include an operational amplifier A2 and a linear ramp capacitor C. RAMP Input control switch Input control switch Capacitor control switch and capacitor control switch The operational amplifier A2 is an input-output rail-to-rail operational amplifier, and the non-inverting input terminal of the operational amplifier A2 is controlled by an input switch. The ramp-start voltage V output from the bias circuit 6 ref The non-inverting input of the operational amplifier A2 is also controlled by an input switch. The stepped voltage V output from the current source array 3 of the connected current-weighted DAC is... dac The inverting input of the operational amplifier A2 is connected to the charging / discharging current I output by the charging / discharging current regulation circuit 4. chargeThe inverting input of the operational amplifier A2 is controlled by a capacitor-controlled switch. and linear ramp capacitance C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor-controlled switch. It is electrically connected to its output terminal.

[0049] The aforementioned ramp signal output buffer circuit 51 has two operating states. When the high-precision ramp generator operates in DAC-type ramp generator mode, the input control switch... Turn on, input control switch Close, and simultaneously, the capacitor controls the switch. Turn on the capacitor control switch. When closed, the above circuit functions as a buffer driver stage, driving the V output from the preceding DAC. dac This forms a stepped slope signal.

[0050] When the high-precision ramp generator operates in capacitor integrating ramp generator mode, the input control switch... Close, input control switch Turn on, and simultaneously, the capacitor control switch Closed, capacitor-controlled switch Turn on the circuit to make it work as an integrator circuit, through capacitor C. RAMP Matching the connected charging and discharging current I charge A linear ramp voltage is formed.

[0051] The switched capacitor circuit 52 includes a ramp sampling capacitor C. s This is used to connect the stepped ramp signal to the ramp sampling capacitor C when the DAC-type ramp generator is in operation mode. s The upper plate will hold the ramp-start voltage V. ref Connect the ramp sampling capacitor C s The lower plate outputs the ramp signal; and in the capacitor integrating ramp generator operating mode, the linear ramp voltage is connected to the ramp sampling capacitor C. s The lower plate utilizes the principle of charge conservation in capacitance to output a linear ramp voltage as the ramp signal V. ramp .

[0052] The switched capacitor circuit 52 may further include a capacitor control switch. Capacitor control switch and capacitor control switch The ramp sampling capacitor C s The lower electrode plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. sThe lower electrode plate also controls the switch via a capacitor. The ramp-start voltage V output from the bias circuit 6 ref The slope sampling capacitor C s The upper plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. s The upper plate also serves as the output terminal of the high-precision ramp generator, outputting the ramp voltage V. ramp .

[0053] When the high-precision ramp generator operates in DAC-type ramp generator mode, the capacitor-controlled switch... and capacitor control switch Closed, capacitor-controlled switch Turn on the ramp signal output buffer circuit 51 and connect the stepped ramp signal to the ramp sampling capacitor C. s The upper plate of the capacitor controls the output of the coarse ramp voltage. When the high-precision ramp generator operates in capacitor integrating ramp generator mode, the capacitor controls the switch. and capacitor control switch Turn on the capacitor control switch. Close the circuit and connect the linear ramp voltage output by the ramp signal output buffer circuit 51 to the ramp sampling capacitor C. s Lower electrode plate.

[0054] The working principle of this embodiment is as follows:

[0055] During the coarse quantization stage, the high-precision ramp generator operates in DAC-type ramp generator mode, providing the coarse quantization ramp. Its equivalent ramp generator circuit is as follows: Figure 3 As shown. At this time, the control signal Vbn is high, turning on the NMOS transistor N1, thereby turning off the charge / discharge current regulation circuit 4, and the capacitor charge / discharge ramp does not participate in the operation. Simultaneously, the input control switch... Turn on, input control switch Close the circuit and reduce the output voltage V of the weighted current DAC current source array 3. dac Connect to ramp signal output buffer circuit 51. Voltage V dac Switch controlled by current source Current source control switch ...current source control switch The controlled n-way mirror current source circuit in resistor R DAC The current flowing through it generates the current source that controls the switch. Current source control switch ...current source control switch The control signal is controlled by the timing control module, thereby controlling the mirror transistors PM1 to PMN to mirror images of size I in sequence. c 2I c 4I c 、……、2 n-1 I c The current supplied to resistor R DAC This allows for the implementation of stepped ramp voltages, either rising or falling. Resistor R DAC The voltage generated needs to pass through the ramp signal output buffer circuit 51 to drive subsequent circuits with different loads. At this time, the input control switch... Turn on, input control switch Closed, capacitor-controlled switch Turn on the capacitor control switch. Closed; the ramp signal output buffer circuit 51 is equivalent to a unity-gain amplifier, together forming a current-controlled DAC for operation. Then, the capacitor controls the switch. and capacitor control switch Closed, capacitor-controlled switch Turn on the current-controlled DAC output stepped ramp and connect it to the ramp sampling capacitor C. s The upper plate outputs a periodically varying stepped ramp signal to provide a coarse ramp voltage for the two-step SS-ADC.

[0056] During the fine-graining stage, the high-precision ramp generator operates in capacitor-integrating ramp generator mode, providing the fine-graining ramp. Its equivalent ramp generator circuit is as follows: Figure 4 As shown. At this time, the control signal Vbn is low, causing NMOS transistor N1 to be turned off. The current mirror structure formed by NMOS transistors N0 and N2 works normally, and the charge / discharge current regulation circuit 4 generates the charge / discharge current I. charge This is provided to the inverting input of operational amplifier A2. Simultaneously, the input control switch... Close, input control switch Turn on, stop the DAC type ramp generator and turn V ref Connect to the non-inverting input of operational amplifier A2. Capacitor-controlled switch. Closed, capacitor-controlled switch When turned on, the ramp signal output buffer circuit 51 is equivalent to an integration circuit. Then, the capacitor controls the switch. and capacitor control switch Turn on the capacitor control switch. Close the circuit and connect the linear ramp voltage output from the integral circuit to the ramp sampling capacitor C. s The lower plate, at this time the output ramp voltage V rampThis is used to provide a finely quantized linear ramp voltage for a two-step SS-ADC. According to the principle of charge conservation, the output ramp voltage V at this time... ramp for:

[0057]

[0058] Where t represents the time occupied by the ramp generator when it is working as a capacitor integrating ramp generator, that is, the time for fine quantization.

[0059] In this embodiment, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, which significantly reduces the quantization time. Furthermore, a single output stage can be used to combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design and improving the compatibility of the ramp generator. This solves the linearity and stability problems introduced by stepped ramps in high-speed and high-precision applications, and reduces design complexity.

[0060] Please see Figure 5 , Figure 5 This is a structural block diagram of an embodiment of the two-step single-slope analog-to-digital converter of the present invention. The two-step single-slope analog-to-digital converter of this embodiment includes a ramp generator 100, a column comparator 300, a counter 400, a memory 500, and a digital logic control module 600. The ramp generator 100 employs a high-precision ramp generator as described in any of the above embodiments. The non-inverting input terminal of the column comparator 300 is electrically connected to the output terminal of the ramp generator, and the inverting input terminal of the column comparator 300 is used to connect to the pixel signal V output by the pixel output terminal 200. sig The output of the column comparator 300 is electrically connected to the counter 400, which is in turn electrically connected to the memory 500. The memory 500 is used to output the analog-to-digital conversion result and is also electrically connected to the digital logic control module 600. The digital logic control module 600 generates control signals to switch the operating mode of the ramp generator. The output signal of the column comparator 300 controls the operating state of the counter 400. The memory 500 temporarily stores pixel quantization values. During the two-step SS-ADC operation, the memory 500 needs to store the C-bit coarse quantization value and the F-bit fine quantization value, and then merge them to output the quantized data D. The digital logic control module 600 generates control signals based on the state of the memory 500 to switch the operating mode of the ramp generator, completing the switching between the two operating states during coarse and fine quantization and the reset operation after quantization.

[0061] The working principle of this embodiment is as follows:

[0062] Please see Figure 5 and Figure 6At the start of quantization, counter 400 and ramp generator 100 begin operating simultaneously. Ramp generator 100 initially operates in DAC-type ramp generator mode, providing a periodic ramp signal with significant voltage changes (i.e., a coarse ramp voltage) which is then connected to the non-inverting input of column comparator 300. The inverting input of column comparator 300 is connected to the pixel signal V to be quantized. SIG The voltage is then compared with the coarse ramp voltage for coarse quantization. The advantage of using a DAC-type ramp generator in the coarse quantization stage is that its ramp voltage has a defined value for each clock cycle, which can be determined by the ramp sampling capacitor C in the switched capacitor circuit 52. S The ramp voltage value at the end of coarse quantization is mounted on the upper plate, which facilitates the connection to fine quantization and enables a fine ramp to traverse the entire quantization range V. range This reduces the design complexity of the ramp generator. At startup, the ramp generator's coarse-ramp is determined by a voltage range of V. range The highest value begins to decrease until it traverses the entire quantization interval; during this process, the pixel signal V can be found. SIG The voltage range, i.e., its lower limit voltage V. FL up to its upper limit voltage V FH In the figure, the coarse quantification slope descends to V. FL When the column comparator 300 flips from high to low, the counter 400 completes the coarse quantization stage and saves the count value to the memory 500. At this time, the digital logic control module 600 is triggered to switch the operating state of the ramp generator 100, and the voltage V... FL The sampling capacitor C mounted on the slope S On the upper electrode, coarse quantization is completed. Subsequently, counter 400 and the stress generator begin operating, and ramp generator 100 switches to capacitor-integrating ramp generator mode, outputting a linear ramp for fine quantization, thus initiating fine quantization. Figure 4 It can be seen that the linear ramp connected to the non-inverting input of the column comparator 300 will be determined by V FL Start with slope It increases linearly over time and rises to V. FH The fine quantization is completed. When the column comparator 300 flips from low to high, the counter 400 completes the counting of the fine quantization stage and saves the count value to the memory 500. The quantization process of a pixel signal is completed by merging the count values ​​of coarse and fine quantization.

[0063] In this embodiment, the ramp generator 100 combines the functions of a DAC-type ramp generator and a capacitor-integrating ramp generator, decomposing the quantization process into two stages: coarse quantization and fine quantization. During the two-step quantization process, the ramp generator 100 outputs a stepped ramp signal in the coarse quantization stage and a linear ramp signal in the fine quantization stage. This compensates for the incompatibility of using a linear ramp in the coarse quantization stage and introduces a linear ramp in the fine quantization stage, solving the linearity and stability problems introduced by the stepped ramp in high-speed, high-precision applications. Furthermore, it improves the conversion speed of the SS-ADC and the frame rate of the image sensor, enhances the accuracy and stability of the ramp generator in two-step SS-ADC applications, and reduces design complexity.

[0064] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A high precision ramp generator characterized by: Having a DAC type ramp generator working mode and a capacitor integration type ramp generator working mode, comprising Bandgap reference source circuit for generating a reference voltage V bg ; a voltage-current conversion circuit for converting a reference voltage V bg into a stable current I c and a mirror current I c to a current DAC current source array and charge-discharge current regulation circuit; a current DAC current source array for outputting a staircase step voltage V dac ; The charging and discharging current regulation circuit is used for outputting charging and discharging current I when the capacitor integral type slope generator works in the mode charge ; a mode switching circuit for outputting a periodic change of the ladder type ramp signal in the DAC type ramp generator mode according to the ladder type ramp voltage V dac a periodic change of the ladder type ramp signal; and outputting a linear change of the ramp signal in the capacitor integration type ramp generator mode according to the charge-discharge current I charge a linear change of the ramp signal; And a bias circuit for generating a ramp start voltage V ref is provided to the mode switching circuit.

2. The high precision ramp generator of claim 1, wherein: The voltage-current conversion circuit comprises an operational amplifier A1, a resistor R BG and a PMOS tube P0, a non-inverting output terminal of the operational amplifier A1 is connected with a reference voltage V bg , an inverting input terminal of the operational amplifier A1 is grounded through a resistor R BG , the inverting input terminal of the operational amplifier A1 is also electrically connected with a drain of the PMOS tube P0, an output terminal of the operational amplifier A1 is electrically connected with a gate of the PMOS tube P0, and a source of the PMOS tube P0 is connected with a power supply voltage.

3. The high precision ramp generator of claim 2, wherein: The current DAC current source array comprises resistors R DAC and n-stage mirror current source circuits, each of the mirror current source circuits comprises a mirror tube unit and a current source control switch, the sources of the n mirror tube units are connected to a power supply voltage, the gates of the n mirror tube units are electrically connected to the output terminal of the operational amplifier A1, the drain of each mirror tube unit is electrically connected to the first end of the resistor R DAC through a current source control switch, and the second end of the resistor R DAC is grounded.

4. The high precision ramp generator of claim 3, wherein: The mirror tube unit of each stage of the mirror current source circuit respectively comprises 2 i-1 parallel reference PMOS tubes, wherein i represents the stage number of the mirror current source circuit, 1≤i≤n.

5. The high precision ramp generator of claim 3, wherein: The charging and discharging current regulation circuit comprises a PMOS tube P1, an NMOS tube N0, an NMOS tube N1 and an NMOS tube N2, the source of the PMOS tube P1 is connected with a power supply voltage, the gate of the PMOS tube P1 is electrically connected with the output terminal of an operational amplifier A1, the drain of the PMOS tube P1 is respectively electrically connected with the drain of the NMOS tube N0, the gate of the NMOS tube N0, the drain of the NMOS tube N1 and the gate of the NMOS tube N2, the sources of the NMOS tube N0, the NMOS tube N1 and the NMOS tube N2 are all grounded, the gate of the NMOS tube N1 is connected with a mode control signal Vbn, and the drain of the NMOS tube N2 is used for outputting a charging and discharging current I charge When the high-precision slope generator works in the DAC type slope generator working mode, the control signal Vbn makes the NMOS tube N1 conductive; when the high-precision slope generator works in the capacitor integration type slope generator working mode, the control signal Vbn makes the NMOS tube N1 cut off.

6. The high precision ramp generator of claim 5, wherein: The width-length ratio of the NMOS tube N2 is obtained by reducing or enlarging the width-length ratio of the NMOS tube N0 by a predetermined ratio.

7. A high precision ramp generator as claimed in any one of claims 1 to 6, characterized in that: The mode switching circuit comprises a slope signal output buffer circuit for operating as a buffer driving stage when the DAC type slope generator is in operation, driving the ladder type slope voltage V dac forms a ladder type slope voltage; and operates as an integration operation circuit when the capacitor integration type slope generator is in operation, integrating the slope start voltage V ref is a reference voltage, and is formed by charging and discharging the current I charge forms a linear slope voltage; And Switched capacitor circuit, comprising a ramp sampling capacitor C s , for inputting a staircase ramp signal to the upper plate of the ramp sampling capacitor C s when the DAC type ramp generator is in operation mode, inputting a ramp start voltage V ref to the lower plate of the ramp sampling capacitor C s for outputting a ramp signal; and inputting a linear ramp voltage to the lower plate of the ramp sampling capacitor C s when the capacitor integration type ramp generator is in operation mode, outputting a linear ramp voltage as a ramp signal V ramp by means of the principle of conservation of charge.

8. The high precision ramp generator of claim 7, wherein: The ramp signal output buffer circuit includes an operational amplifier A2 and a linear ramp capacitor C. RAMP Input control switch Input control switch Capacitor control switch and capacitor control switch The operational amplifier A2 is an input / output rail-to-rail operational amplifier, and the non-inverting input terminal of the operational amplifier A2 is controlled by an input switch. The ramp-start voltage V output from the bias circuit ref The non-inverting input of the operational amplifier A2 is also controlled by an input switch. The stepped voltage V output from the current source array of the connected current-weighted DAC is... dac The inverting input of the operational amplifier A2 is connected to the charging / discharging current I output by the charging / discharging current control circuit. charge The inverting input of the operational amplifier A2 is controlled by a capacitor-controlled switch. and linear ramp capacitance C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor-controlled switch. It is electrically connected to its output terminal; When the high precision ramp generator is operating in the DAC type ramp generator mode of operation, the input control switch open, the input control switch closed, the capacitor control switch open, the capacitor control switch closed; when the high precision ramp generator is operating in the capacitor integration type ramp generator mode of operation, the input control switch closed, the input control switch open, the capacitor control switch closed, the capacitor control switch open.

9. The high precision ramp generator of claim 8, wherein: The switched capacitor circuit also includes a capacitor control switch. Capacitor control switch and capacitor control switch The ramp sampling capacitor C s The lower electrode plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. s The lower electrode plate also controls the switch via a capacitor. The ramp-start voltage V output from the bias circuit ref The slope sampling capacitor C s The upper plate is controlled by a capacitor to switch. The ramp sampling capacitor C is electrically connected to the output terminal of operational amplifier A2. s The upper plate also serves as the output terminal of a high-precision ramp generator, outputting a linear ramp voltage V. ramp ; When the high-precision ramp generator is working in the DAC-type ramp generator working mode, the capacitor control switch and the capacitor control switch is closed, the capacitor control switch is opened; when the high-precision ramp generator is working in the capacitor integration-type ramp generator working mode, the capacitor control switch and the capacitor control switch is opened, the capacitor control switch is closed.

10. A two-step single-slope analog-to-digital converter, characterized by: The application relates to a high-precision slope generator, which comprises a slope generator, a column comparator, a counter, a memory and a digital logic control module, wherein the slope generator is as claimed in any one of claims 1 to 9; the non-inverting input end of the column comparator is electrically connected with the output end of the slope generator, the inverting input end of the column comparator is used for connecting the pixel signal V output by the pixel output end sig ; the output end of the column comparator is electrically connected with the counter, the counter is electrically connected with the memory, the memory is used for outputting the analog-digital conversion result, the memory is further electrically connected with the digital logic control module, the digital logic control module is used for generating a control signal, and the control signal is used for switching the working mode of the slope generator.

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