NR receiving end LDPC decoding method based on domain specific instruction set

Abstract

A NR receiving end LDPC decoding method based on a domain-specific instruction set comprises the steps that on the basis of a Min-Sum algorithm, check node information and variable node information are updated through RISC-V-based domain-specific instruction set circulation, hard decision is carried out according to updated variable nodes to obtain code words, and finally the code words are checked and output through a check matrix. The LDPC decoder based on the domain-specific instruction set is realized through the communication domain-specific vector instruction set, and the decoding performance is ensured while the data throughput is improved.

Description

Technical Field

[0001] The present invention relates to a technology in the field of information processing, specifically to a NR receiving end low-density parity check code (LDPC) decoding method based on a field-specific instruction set. Background Art

[0002] As a linear block code, low-density parity-check (LDPC) codes have a flexible structure that can adapt to different channel conditions and data transmission requirements, meeting the complex and diverse business scenarios of 5G. However, the existing GPU-based LDPC decoding technology has limited in-depth optimization capabilities for specific communication algorithms, and it is difficult to make more sophisticated resource allocation and optimization for specific tasks, which restricts GPU decoding in terms of performance and scalability. At the same time, the GPU processing process involves the transmission of a large amount of data between the host and the device. These data transmissions are usually transmitted through the PCIe bus, which is slow and brings significant delay overhead. Summary of the invention

[0003] In view of the shortcomings of the prior art, which has low flexibility and cannot customize special optimization solutions for different protocols, resulting in limited performance and efficiency, complex and inefficient algorithm modification process, and difficulty in flexibly responding to new application requirements, the present invention proposes an NR receiving-end LDPC decoding method based on a domain-specific instruction set. The LDPC decoder based on the domain-specific instruction set is implemented through a communication field-specific vector instruction set, which improves data throughput while ensuring decoding performance.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to an NR receiving end LDPC decoding method based on a domain-specific instruction set. Based on a minimum sum (Min-Sum) algorithm, the check node information and the variable node information are updated cyclically through a domain-specific instruction set based on RISC-V, a hard decision is made according to the updated variable nodes to obtain a codeword, and finally the codeword is checked and output through a check matrix.

[0006] The input parameters received by each instruction set in the RISC-V-based domain-specific instruction set include: a source operand, a destination operand, a mask identifier and a vector length.

[0007] When only some elements in a vector need to participate in the calculation, a mask is used. The mask identifier has three states: enabling the mask, disabling the mask, and writing to the mask register. The mask register can be written through vector logic judgment instructions such as VSLE and VSGT. When the mask needs to be enabled, the mask identifier can be set to the corresponding state.

[0008] The RISC-V-based domain-specific instruction set includes:

[0009] VAND: source operand 1 and source operand 2 are ANDed one by one;

[0010] VOR: source operand 1 and source operand 2 are ORed one by one;

[0011] VBRDCST: Fill a vector with a scalar number;

[0012] VSLL: vector element logical shift left;

[0013] VSRL: logical right shift of vector elements;

[0014] VSRA: vector element arithmetic right shift;

[0015] VSEQ: Checks whether source operand 1 and source operand 2 are equal bit by bit;

[0016] VSNE: Checks whether source operand 1 and source operand 2 are not equal bit by bit;

[0017] VSLTU: Bitwise check whether the element of unsigned source operand 1 is less than the element at the corresponding position of unsigned source operand 2;

[0018] VSLT: Bitwise check whether the element of the signed source operand 1 is less than the element of the corresponding position of the signed source operand 2;

[0019] VSLEU: Bitwise check whether the element of unsigned source operand 1 is less than or equal to the element at the corresponding position of unsigned source operand 2;

[0020] VSLE: Bitwise check whether the element of signed source operand 1 is less than or equal to the element at the corresponding position of signed source operand 2;

[0021] VSGTU: Bitwise check whether the element of unsigned source operand 1 is greater than the element of the corresponding position of unsigned source operand 2;

[0022] VSGT: Bitwise check whether the element of signed source operand 1 is greater than the element of the corresponding position of signed source operand 2;

[0023] VMNOT: Mask register inversion;

[0024] VADD: bitwise addition of source operand 1 and source operand 2;

[0025] VRANGE: Generates an arithmetic progression of specified length starting from 0;

[0026] VRSUB: Bitwise subtraction of source operand 2 and source operand 1;

[0027] VSUB: subtract source operand 1 from source operand 2 bit by bit;

[0028] VMUL: bitwise multiplication of source operand 1 and source operand 2;

[0029] VMULH: Multiply source operand 1 and source operand 2 bit by bit, and take the high bit of the result;

[0030] VMULHU: Multiply source operand 1 and source operand 2 bit by bit, and take the low bit of the result;

[0031] VMULHSU: bitwise unsigned multiplication of source operand 1 and source operand 2, taking the high bit of the result;

[0032] VMULADD: Multiply source operand 1 and source operand 2 bit by bit, and then add the result of the multiplication to the destination operand 2 bit by bit;

[0033] VMULSUB: Multiply source operand 1 and source operand 2 bit by bit, and subtract the result from destination operand 2 bit by bit.

[0034] VADDMUL: Add source operand 1 and source operand 2 bit by bit, and then multiply the result by destination operand 2 bit by bit;

[0035] VSUBMUL: Subtract source operand 1 from source operand 2 bit by bit, and multiply the result by destination operand 2 bit by bit.

[0036] VDIV: bitwise division of source operand 1 and source operand 2;

[0037] VREM: Bitwise modulus of source operand 1 and source operand 2;

[0038] VDIVU: bitwise division of unsigned source operand 1 and unsigned source operand 2;

[0039] VREMU: bitwise modulus of unsigned source operand 1 and unsigned source operand 2;

[0040] VSHUFFLE: The data in source vector operand 1 is reordered according to the indices in source vector operand 2. Technical Effects

[0041] The present invention realizes LDPC decoding through a field-specific instruction set, and all operations are vector parallel calculations; 8-bit fixed-point numbers are used for all decoding calculations; each time the value of the variable node is updated during the decoding process, the data is arithmetic shifted right by 2 bits to avoid overflow. All configurable parameters in the NR protocol are supported, and different processing instructions are selected according to the number of variable nodes in each row of the check matrix based on the characteristics of the base graph specified in the NR protocol; compared with the prior art, the field-specific instruction set of the present invention is hardware optimized for the calculation requirements of LDPC decoding, which is highly customizable and can flexibly modify the algorithm to adapt to different protocols; the use of 8-bit fixed-point numbers can make more full use of hardware resources, facilitate parallel calculations, and significantly improve the processing speed and efficiency of decoding; arithmetic shifting the data right by 2 bits can effectively avoid overflow caused by insufficient bits, so that the data maintains sufficient accuracy and ensures the bit error rate of the decoder; different processing instruction sets are selected according to the number of variable nodes in each row of the check matrix, which can minimize the delay caused by data movement. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a flow chart of the present invention;

[0043] Figure 2 To move the variable nodes of each row to the intermediate variable diagram;

[0044] Figure 3 This is the module principle block diagram of the LDPC decoder;

[0045] Figure 4 A flowchart for selecting a check node processing instruction set for different values ​​of the variable node number N;

[0046] Figure 5 This is a schematic diagram of the bit error rate curve of the LDPC decoder. DETAILED DESCRIPTION

[0047] like Figure 1 As shown, a NR receiving end LDPC decoding method based on a domain-specific instruction set involved in this embodiment includes:

[0048] Step 1: Initialization: Set the variable node to its initial value Replaced by the initial probability information L(P i ),i=1,2,…,n, specifically: L(q i→j )=L(P i ),L(r j→i )=0. Each variable node of the check matrix needs to be cyclically shifted to the right, specifically including:

[0049] 1. Generate Z using the VRANGE command c Index V of length 0, the instruction is expressed as V 0 =VRANGE(V 0 ,Z c );

[0050] 2. Let c equal the rise factor Z c The difference between the number of bits S that need to be cyclically shifted, that is, c = Z c -S, use the VSUB instruction to subtract c from each element of the index. The instruction is represented by V 0 =VSUB(V 0 ,c,Z c );

[0051] 3. Use the VADD instruction to add Z to the first c elements of the index c , the instruction is expressed as V 0 =VADD(V 0 ,Z c ,c);

[0052] 4. Use VSHUFFLE to extract the index from the input vector V using the index generated in the previous two steps. 1 The number at the corresponding position is taken to the specified register V 2 In the example, the instruction is represented by V 2 =VSHUFFLE(V 2 ,V 0 ,V 1 ,GATHER,Zc ) .

[0053] The second step is to update the information of the check node. The update of the check node j and the variable node i connected to it in the lth iteration is: Where: V(j)\i is the set of other variable nodes connected to the check node j except the i-th variable node, α is a constant parameter, and the constant parameter satisfies 0< α<1, in this embodiment, α=0.5, represents the external information transmitted from check node j to variable node i at the kth iteration, represents the external information transmitted by variable node i to check node j at the kth iteration. The collective vector minimum value is updated through domain-specific instructions, with vector V 1 With V 2 Taking comparison as an example, the implementation specifically includes:

[0054] 1. Use the VSLE instruction to change the vector V 1 With V 2 Compare the size bit by bit. When V 2 The elements in V are smaller than 1 When the corresponding position in the mask register is set to 1, the instruction is represented by VSLE (V 1 ,V2 ,MASKWRITE,Z c );

[0055] 2. Read the mask register and use the VXOR instruction to make V 1 With V 1 Perform bitwise XOR operation on itself to clear the bits to be updated. The instruction is represented by V 1 =VXOR(V 1 ,V 1 ,MASKREAD,Z c );

[0056] 3. Read the mask register and use the VADD instruction to set V 1 With V 2 Add, complete the minimum value update, the instruction is expressed as V 1 =VADD(V 1 ,V 2 ,MASKREAD,Z c );

[0057] 4. After the minimum value is updated, let V 1 The elements in are arithmetic shifted right by 2 bits to avoid overflow. The instruction is represented by V 1 =VSRA(V 1 ,2,Z c ).

[0058] The third step is to update the information of the variable node. The update of the variable node i and the check node j connected to it in the lth iteration is: This is reflected in the domain-specific instruction set: Where: C(i) is the set of all check nodes connected to the i-th variable node; represents the external information transmitted from check node j to variable node i at the kth iteration, represents the external information transmitted from variable node i to check node j at the kth iteration, P i Represents the log-likelihood ratio of each information bit.

[0059] Step 4: According to the updated variable node Make a hard decision and get the codeword in: is the posterior probability information of variable node i at the kth iteration. The hard decision is reflected by the domain-specific instruction set as follows:

[0060] 1. Use VSLE command Each bit of is compared with 0. When the element in is less than 0, the corresponding position in the mask register is set to 1. The instruction is expressed as

[0061] 2. Use VBRDCST to Each position of is 0, and the instruction is expressed as

[0062] 3. Read the mask register and use VBRDCST to The corresponding position in is set to 1, and the instruction is expressed as Hard verdict completed.

[0063] Step 5: Loop through steps 2 to 4 until all nodes are traversed and the check matrix is ​​used to determine Is it 0 and output the code word.

[0064] The check matrix is ​​composed of the base graph (BG) and the expansion factor Z c To describe, BG is two fixed-size matrices given in the protocol, namely the first base graph BG1 and the second base graph BG2, where: the first base graph BG1 has a size of 46×68, which is usually suitable for scenarios with high throughput requirements, high bit rates, and long code lengths; the second base graph BG2 has a size of 42×52, which is usually suitable for scenarios with low throughput requirements, low bit rates, and short code lengths. Each non-zero element in the base graph BG is expanded to Z c ×Z c A circular shift matrix of size Z, where each 0 is expanded to Z c ×Z c The full-zero matrix of different sizes can flexibly support different code lengths and code rates.

[0065] The instruction set of the present invention does not support dynamic memory application, so vectors must be pre-defined to save intermediate results. The number and position of non-zero elements in the base graph BG are fixed, and the number of variable nodes in each row of the base graph BG can be counted. The number of variable nodes in a row of the first base graph BG1 is at most 19, with a total of 9 possible values. The number of non-zero elements in each row of the second base graph BG2 is at most 10, with a total of 6 possible values. The pre-defined 19 vectors for each row are used to save intermediate results.

[0066] It can be known that the calculations in the LDPC decoding process mainly include vector addition, vector subtraction, vector circular shift, vector element size comparison, vector XOR, and vector arithmetic right shift. The VADD, VSUB, VSLE, VSHUFFLE, and VXOR instructions in the instruction set can be used for operations. The input data are all 8-bit signed fixed-point numbers, of which 1 bit is the sign bit and 7 are decimal places.

[0067] After specific practical experiments, the decoder's bit error rate between -5dB and 5dB signal-to-noise ratio was tested with a code length of 1600 bits and a code rate of 0.6631 as parameters and a maximum number of iterations of 5. The present invention is applied to the NR system and the physical layer design of the entire system has been completed. After obtaining the input 8-bit fixed-point data from the descrambling module at the front stage of the SCH channel, the entire LDPC decoding operation process uses the field-specific instruction set in the present invention for parallel operation processing. It works stably in multiple tests. After comparing with the data in matlab, the LDPC decoder in the present invention can stably decode information bits when the signal-to-noise ratio is greater than 1dB. The bit error rate performance is as follows: Figure 5 shown.

[0068] Compared with the prior art, this method is designed and implemented through a domain-specific instruction set combined with the computing characteristics of the communication system, and is specifically optimized for the computing requirements of LDPC decoding. The algorithm can be flexibly modified to adapt to different communication protocols. The implemented LDPC decoder can fully support all configurable parameters in the NR protocol, and is optimized for the characteristics of LDPC coding design in the NR protocol. According to the characteristics of the fixed position and number of variable nodes in the check matrix specified by the protocol, the delay caused by the data movement operation in the actual calculation process is effectively reduced by selecting a suitable processing instruction set based on the number of variable nodes in each row. It also uses 8-bit fixed-point calculations to make more full use of hardware resources and support large-scale parallel computing, thereby significantly improving the decoding processing speed and efficiency. The mechanism of arithmetic right shift of data by 2 bits is adopted to effectively avoid overflow problems caused by insufficient bit numbers, ensuring data accuracy and low bit error rate. The overall design can significantly improve the LDPC decoding rate and reduce processing delays, which not only meets the high performance requirements of 5G NR communications, but is also suitable for a variety of systems with high communication reliability and performance requirements. The communication field-specific instruction set in the present invention can be used in communication algorithms to provide parallel acceleration functions for communication algorithms, and has a wide range of application scenarios.

[0069] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A NR receiving end LDPC decoding method based on a domain-specific instruction set, characterized in that: Based on the Min-Sum algorithm, the check node information and variable node information are updated through a RISC-V-based domain-specific instruction set loop, and a hard decision is made based on the updated variable nodes to obtain the codeword. Finally, the codeword is checked and output through the check matrix. The input parameters received by each instruction set in the RISC-V-based domain-specific instruction set include: a source operand, a destination operand, a mask identifier and a vector length.

2. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 1, characterized in that: When only some elements in a vector need to participate in the calculation, a mask is used. The mask identifier has three states: enabling the mask, disabling the mask, and writing to the mask register. The mask register is written through a vector logic judgment instruction. When the mask needs to be enabled, the mask identifier is set to the corresponding state.

3. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 1 or 2, characterized in that: The RISC-V-based domain-specific instruction set includes: VAND: AND operation of source operand 1 and source operand 2 one by one; VOR: OR operation of source operand 1 and source operand 2 one by one; VBRDCST: Fill vector with scalar number; VSLL: Logical left shift of vector elements; VSRL: Logical right shift of vector elements; VSRA: Arithmetic right shift of vector elements; VSEQ: Bitwise determination of whether source operand 1 and source operand 2 are equal; VSNE: Bitwise determination of whether source operand 1 and source operand 2 are unequal; VSLTU: Bitwise determination of whether the element of unsigned source operand 1 is less than the element at the corresponding position of unsigned source operand 2; VSLT: Bitwise determination of whether the element of signed source operand 1 is less than the element at the corresponding position of signed source operand 2 Position element; VSLEU: bitwise check whether the element of unsigned source operand 1 is less than or equal to the corresponding position element of unsigned source operand 2; VSLE: bitwise check whether the element of signed source operand 1 is less than or equal to the corresponding position element of signed source operand 2; VSGTU: bitwise check whether the element of unsigned source operand 1 is greater than the corresponding position element of unsigned source operand 2; VSGT: bitwise check whether the element of signed source operand 1 is greater than the corresponding position element of signed source operand 2; VMNOT: invert the mask register; VADD: bitwise addition of source operand 1 and source operand 2; VRANGE: generate an arithmetic progression of the specified length starting from 0; VRSUB : Subtract source operand 2 from source operand 1 bit by bit; VSUB: Subtract source operand 1 from source operand 2 bit by bit; VMUL: Multiply source operand 1 from source operand 2 bit by bit; VMULH: Multiply source operand 1 from source operand 2 bit by bit, and take the high bit of the result; VMULHU: Multiply source operand 1 from source operand 2 bit by bit, and take the low bit of the result; VMULHSU: Multiply source operand 1 from source operand 2 bit by bit without sign, and take the high bit of the result; VMULADD: Multiply source operand 1 from source operand 2 bit by bit, and add the multiplication result to destination operand 2 bit by bit; VMULSUB: Multiply source operand 1 from source operand 2 bit by bit, and add the multiplication result to destination operand 2 Bitwise subtraction; VADDMUL: bitwise addition of source operand 1 and source operand 2, and bitwise multiplication of the addition result with destination operand 2; VSUBMUL: bitwise subtraction of source operand 1 and source operand 2, and bitwise multiplication of the addition result with destination operand 2; VDIV: bitwise division of source operand 1 and source operand 2; VREM: bitwise remainder of source operand 1 and source operand 2; VDIVU: bitwise division of unsigned source operand 1 and unsigned source operand 2; VREMU: bitwise remainder of unsigned source operand 1 and unsigned source operand 2; VSHUFFLE: data in source vector operand 1 is rearranged according to the index in source vector operand 2.

4. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to any one of claims 1 to 3, characterized in that: include: Step 1: Initialization: Set the variable node to its initial value Replaced by the initial probability information L(P i ),i=1,2,…,n, specifically: L(q i→j )=L(P i ),L(r j→i )=0, where each variable node of the check matrix needs to be cyclically shifted to the right; The second step is to update the information of the check node. The update of the check node j and the variable node i connected to it in the lth iteration is: Where: V(j)\i is the set of other variable nodes connected to the check node j except the i-th variable node, α is a constant parameter, represents the external information transmitted from check node j to variable node i at the kth iteration, represents the external information transmitted from variable node i to check node j at the kth iteration; The third step is to update the information of the variable node. The update of the variable node i and the check node j connected to it in the lth iteration is: Step 4: According to the updated variable node Make a hard decision and get the codeword in: is the posterior probability information of variable node i at the kth iteration; Step 5: Loop through steps 2 to 4 until all nodes are traversed and the check matrix is ​​used to determine Is it 0 and output the code word.

5. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 4 is characterized in that: The rightward circular shift is implemented by a domain-specific instruction set, specifically including:

1. Generate Z using the VRANGE command c The length index V0, the instruction is expressed as V0 = VRANGE (V0, Z c ); 2. Let c equal the rise factor Z c The difference between the number of bits S that need to be cyclically shifted, that is, c = Z c -S, use the VSUB instruction to subtract c from each element of the index. The instruction is expressed as V0 = VSUB (V0, c, Z c ); 3. Use the VADD instruction to add Z to the first c elements of the index c , the instruction is expressed as V0 = VADD (V0, Z c ,c); 4. Use VSHUFFLE to fetch the corresponding position of the input vector V1 into the specified register V2 using the index generated in the previous two steps. The instruction is expressed as V2 = VSHUFFLE (V2, V0, V1, GATHER, Z c ).

6. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 4 is characterized in that: The second step is implemented through a domain-specific instruction set, specifically including:

1. Use the VSLE instruction to compare the vectors V1 and V2 bit by bit. When the element in V2 is smaller than V1, set the corresponding position in the mask register to 1. The instruction is expressed as VSLE(V1, V2, MASKWRITE, Z c ); 2. Read the mask register and use the VXOR instruction to perform a bitwise XOR operation on V1 and V1 itself, clearing the bits to be updated. The instruction is expressed as V1 = VXOR (V1, V1, MASKREAD, Z c ); 3. Read the mask register and use the VADD instruction to add V1 and V2 to complete the update of the minimum value. The instruction is expressed as V1 = VADD (V1, V2, MASKREAD, Z c ); 4. After the minimum value is updated, the elements in V1 are shifted right by 2 bits to avoid overflow. The instruction is expressed as V1 = VSRA (V1, 2, Z c ).

7. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 4 is characterized in that: The third step is implemented through a domain-specific instruction set, specifically: Where: C(i) is the set of all check nodes connected to the i-th variable node; represents the external information transmitted from check node j to variable node i at the kth iteration, represents the external information transmitted from variable node i to check node j at the kth iteration, P i Represents the log-likelihood ratio of each information bit.

8. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 4 is characterized in that: The fourth step is implemented through a domain-specific instruction set, specifically including:

1. Use VSLE command Each bit of is compared with 0. When the element in is less than 0, the corresponding position in the mask register is set to 1. The instruction is expressed as 2. Use VBRDCST to Each position of is 0, and the instruction is expressed as 3. Read the mask register and use VBRDCST to The corresponding position in is set to 1, and the instruction is expressed as Hard verdict completed.

9. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 4 is characterized in that: The check matrix is ​​composed of the base graph (BG) and the expansion factor Z c To describe, BG is two fixed-size matrices given in the protocol, namely the first base graph BG1 and the second base graph BG2, where: the first base graph BG1 has a size of 46×68, which is usually suitable for scenarios with high throughput requirements, high bit rates, and long code lengths; the second base graph BG2 has a size of 42×52, which is usually suitable for scenarios with low throughput requirements, low bit rates, and short code lengths. Each non-zero element in the base graph BG is expanded to Z c ×Z c A circular shift matrix of size Z, where each 0 is expanded to Z c ×Z c The full-zero matrix of different sizes can flexibly support different code lengths and code rates.

10. The NR receiving end LDPC decoding method based on a domain-specific instruction set according to claim 9 is characterized in that: Dynamic memory application is achieved by pre-defining vectors to save intermediate results. Specifically, the number and position of non-zero elements in the base graph BG are fixed, and the number of variable nodes in each row of the base graph BG can be counted. The number of variable nodes in a row of the first base graph BG1 is at most 19, with a total of 9 possible values. The number of non-zero elements in each row of the second base graph BG2 is at most 10, with a total of 6 possible values. The pre-defined 19 vectors for each row are used to save intermediate results.

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