Logic circuit configuration method and device for network packet processing, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a logic circuit configuration method and device for network packet processing, electronic equipment and a storage medium, and relates to the technical field of computer communication. Obtaining byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host and a preset logic condition, and determining configuration information corresponding to one or more computing grids according to the byte structure information and the logic condition of the network packet, and respectively writing the configuration information corresponding to the one or more calculation grids into the corresponding blank calculation grids to obtain one or more calculation grid instances, generating logic circuit information according to the one or more calculation grid instances, and configuring the logic circuit information into a hardware network card. According to the method provided by the embodiment of the invention, the logic circuit information in the hardware network card can be flexibly modified.

Description

Technical Field

[0001] The present application relates to the field of battery management technology, and in particular to a logic circuit configuration method, device, electronic device and storage medium for network packet processing. Background Art

[0002] Berkeley Packet Filter (BPF) is a virtual machine that can be used to filter network packets. The core concept of BPF for filtering network packets is based on the filtering program telling the operating system which network packets need to be retained, so that the operating system only transmits the network packets that need to be retained to the user space and filters out the rest of the network packets.

[0003] The related technology can reduce the burden of the central processing unit (CPU) by providing a BPF logic circuit in a hardware chip and running the BPF logic circuit in the chip to replace the BPF program of the software in the operating system. However, the BPF logic circuit in the chip cannot be flexibly modified. Summary of the invention

[0004] The embodiments of the present application provide a logic circuit configuration method, device, electronic device and storage medium for network packet processing, so as to achieve the effect of flexibly modifying logic circuit information.

[0005] In a first aspect, an embodiment of the present application provides a logic circuit configuration method for network packet processing, comprising:

[0006] Construct one or more blank calculation cells;

[0007] Obtain byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host;

[0008] Get the preset logical conditions;

[0009] Determine configuration information corresponding to one or more computing cells according to the byte structure information and logic conditions of the network packet;

[0010] Write the configuration information corresponding to one or more calculation cells into the corresponding blank calculation cells respectively to obtain one or more calculation cell instances;

[0011] generating logic circuit information according to one or more computational grid instances;

[0012] Configure the logic circuit information into the hardware network card.

[0013] In a second aspect, an embodiment of the present application provides a network packet processing method, which is applied to a hardware network card as described in any of the above items, wherein the hardware network card is configured with logic circuit information, and the method includes:

[0014] Obtaining the network packets to be processed and the preset processing actions;

[0015] Performing operations on the network packets to be processed based on the logic circuit information to obtain processing results;

[0016] If the processing result is a first preset value, performing a preset processing action on the network packet to be processed;

[0017] If the processing result is the second preset value, the preset processing action is not executed on the network packet to be processed.

[0018] In a third aspect, an embodiment of the present application provides a logic circuit configuration device for network packet processing, including: applied to an electronic device, including:

[0019] A construction module is used to construct one or more blank calculation cells;

[0020] An acquisition module, used for acquiring byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host;

[0021] The acquisition module is also used to obtain preset logical conditions;

[0022] A processing module, used to determine configuration information corresponding to one or more computing grids according to byte structure information and logic conditions of the network packet;

[0023] The processing module is further used to write the configuration information corresponding to the one or more calculation cells into the corresponding blank calculation cells respectively to obtain one or more calculation cell instances;

[0024] The processing module is further used to generate logic circuit information according to one or more computational grid instances;

[0025] The processing module is also used to configure the logic circuit information into the hardware network card.

[0026] In a fourth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0027] Memory stores computer-executable instructions;

[0028] The processor executes the computer-executable instructions stored in the memory, so that the processor executes various possible implementations of the first aspect and / or the second aspect as described above.

[0029] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement various possible implementations of the first aspect and / or the second aspect as described above.

[0030] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements various possible implementations of the first aspect and / or the second aspect as described above.

[0031] The logic circuit configuration method, device, electronic device and storage medium for network packet processing provided in the embodiments of the present application construct one or more computing grid instances, obtain logic circuit information based on the computing grid instances, and configure the logic circuit information to the hardware network card to process network packets through the hardware network card. The present application can flexibly construct different logic circuit information by constructing different computing grid instances, and can flexibly change the logic circuit information in the hardware network card. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0033] Figure 1 A schematic diagram of a scenario provided for an embodiment of the present application;

[0034] Figure 2 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 1 ;

[0035] Figure 3 The calculation grid template for the example;

[0036] Figure 4 The network packet structure is an example;

[0037] Figure 5 The packet format of an example Ethernet frame;

[0038] Figure 6 The packet format of an IP data packet is shown as an example;

[0039] Figure 7 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 2 ;

[0040] Figure 8 An example packet of an Ethernet frame;

[0041] Fig. 9 The calculation grid instance for the example;

[0042] Fig.10 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 3 ;

[0043] Fig.11 A schematic diagram of coordinate information of a calculation grid instance for example;

[0044] Fig.12 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 4 ;

[0045] Fig.13 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 5 ;

[0046] Fig.14 A logic circuit information for example;

[0047] Fig.15 Schematic diagram of the process of network packet processing method provided in the embodiment of the present application Figure 1 ;

[0048] Fig.16 Another logic circuit information for example;

[0049] Fig.17 A schematic diagram of the structure of a logic circuit configuration device for network packet processing provided in an embodiment of the present application;

[0050] Fig.18 A schematic diagram of the structure of a network packet processing device provided in an embodiment of the present application;

[0051] Fig.19 A schematic diagram of the structure of the electronic device provided in this application.

[0052] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0054] First, the terms involved in this application are explained:

[0055] BPF: Berkeley Packet Filter, a primitive interface of the data link layer on Unix-like systems, providing the sending and receiving of primitive link layer packets;

[0056] Network packet: refers to the data unit transmitted in a computer network, which contains information such as source address, destination address, protocol type, etc.

[0057] The present application first constructs one or more blank computing cells, and then determines the configuration information corresponding to the computing cell based on the byte structure information of the network packet to be processed and the preset logical conditions, and then writes the configuration information corresponding to the computing cell into the corresponding blank computing cell to obtain one or more computing cell instances, and then generates logic circuit information based on the obtained computing cell instances, and finally configures the logic circuit information into the hardware network card.

[0058] Figure 1 A schematic diagram of a scenario provided in an embodiment of the present application, such as Figure 1 The computing device ① is the execution subject of this application, which can be selected as a server, a chip or a board, wherein the chip can be an artificial intelligence (AI) chip, and the AI ​​chip includes at least one hardware processor. The computing device 1 constructs the obtained one or more blank computing grid instances into logic circuit information.

[0059] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0060] Figure 2 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 1 ,like Figure 2 As shown, the method includes:

[0061] S201: Construct one or more blank calculation cells.

[0062] Combined with the scene example, Figure 3 For example, the calculation grid template is Figure 3 The calculation cell template includes multiple fields, each field can be filled with corresponding content. When no content is filled in the field, it can be used as a blank calculation cell.

[0063] S202: Obtain byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host.

[0064] In combination with the scenario example, the network packets that need to be filtered by any BPF virtual machine in the host can be regarded as the network packets to be processed. Figure 4 For example, the network packet structure is Figure 4 As shown, network packets are based on the seven-layer reference model of Open System Interconnect (OSI), that is, data is transmitted from the transport layer to the network layer, then to the data link layer, and finally through the physical layer. From top to bottom, they are packaged into segments, data packets, and frames. Finally, the physical layer transmits them in binary code. The segments include the Transmission Control Protocol (TCP) and the User Datagram Protocol (UDP), the data packets also include the Internet Protocol Address (IP), and the frames also include the Media Access Control Address (MAC).

[0065] There are many formats of network packets. Figure 5 The packet format of an Ethernet frame is as follows: Figure 5 As shown in the figure, the packet format of the Ethernet frame includes 8 fields, namely: Preamble, Start Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), Ethernet type, Data content Payload, Padding and Framecheck sequence (FCS). Preamble is a string of binary data, such as 1010…10, which can be used for synchronization. SFD indicates the start of the data after synchronization, such as 1010…11; DA can be the target MAC address, which can be a 6-byte hardware code; SA is the 6-byte hardware code MAC address of the source; Ethernet type represents the length or category; Data content Payload is the data content to be transmitted in the network packet; Padding represents: the packet length of the Ethernet frame is between 46 and 1500 bytes, so if the packet length does not meet the requirements, padding must be performed; FCS can be used to confirm whether the transmitted data is wrong.

[0066] Figure 6 The packet format of an IP data packet is as follows: Figure 6As shown in the figure, the packet format of the IP data packet includes 15 fields, namely: Version, Internet Header Length (IHL), type of service, total length, identification, flag, fragment offset, time to live, protocol, header checksum, source IP address, destination IP address, padding and data.

[0067] S203: Obtaining a preset logical condition.

[0068] Combined with the scenario example, the logical condition is an operation to judge the bytes of the packet, for example, Figure 5 The network packet of the Ethernet frame of the example makes a judgment that the ninth byte is not equal to "0xA5".

[0069] S204: Determine configuration information corresponding to one or more computing cells according to the byte structure information and logic conditions of the network packet.

[0070] Combined with the scene example, combined with Figure 3 In the example calculation grid template, the configuration information corresponding to the calculation grid is the content corresponding to each field, for example, field 1 corresponds to content 1, field 2 corresponds to content 2, field 3 corresponds to content 3, and field 4 corresponds to content 4.

[0071] S205: Write the configuration information corresponding to one or more calculation cells into the corresponding blank calculation cells respectively to obtain one or more calculation cell instances.

[0072] Combined with the scenario example, for each calculation grid template, the corresponding contents of field 1, field 2, field 3, field 4, etc. can be written into the corresponding fields respectively. Specifically, content 1 is written into field 1, content 2 is written into field 2, content 3 is written into field 3, and content 4 is written into field 4 to obtain a calculation grid instance.

[0073] S206: Generate logic circuit information according to one or more computing grid instances.

[0074] Combined with the scenario example, the obtained computing grid instances are connected to obtain the corresponding logic circuit information. For example, the computing grid instances are connected through an "OR gate" or an "AND gate", and the obtained logic circuit information can be Field Programmable Gate Array (FPGA) circuit information.

[0075] S207: configuring the logic circuit information into the hardware network card.

[0076] Combined with the scenario example, the FPGA circuit information obtained above is written into the hardware network card, such as the FPGA smart network card.

[0077] Since FPGA is a chip whose internal structure can be re-edited to achieve the purpose of use, the FPGA circuit information written to the FPGA smart network card in this example can be flexibly changed so that the FPGA smart network card can process any network packet.

[0078] Optionally, the blank calculation cell includes multiple preset information names, wherein the multiple preset information names include at least associated calculation cell positions, network packet byte positions, operands, and operation value information; accordingly, the configuration information includes multiple content information, wherein the multiple content information includes at least associated calculation cell position information, network packet byte position information, operand information, and operation value information.

[0079] Combined with the scene example, combined with Figure 3 In the example calculation grid template, field 1 can be the associated calculation grid position, which refers to the position of the calculation grid that needs to be calculated with the current calculation grid, so the associated calculation grid position information can be determined as the content information corresponding to the associated calculation grid position. For example, if the current calculation grid needs to be calculated with calculation grid m, the position information of the position of calculation grid m can be determined as the associated calculation grid position information of the current calculation grid. Field 1 can be the network packet byte position, which refers to the position information of the byte that the current calculation grid needs to calculate in the network packet, and the content information corresponding to the network packet byte position can be the network packet byte position information. For example, if the current calculation grid needs to calculate the content of the ninth byte in the network packet, position 9 can be determined as the network packet byte position information. Field 3 and Field 4 are the preset operand information and operation value information, respectively. The operand information and operation value information can be indicated in the preset logical condition.

[0080] This example mainly clarifies the information of each field of the calculation grid template, which can ensure that the structures of all the calculation grid instances obtained are the same, making the logic circuit information obtained based on the calculation grid instances later clearer.

[0081] Optional, Figure 7Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 2 ,like Figure 7 As shown, S204 includes:

[0082] S701: Determine, according to the byte structure information and logic conditions of the network packet, the associated calculation cell position information, the network packet byte position information, the operand information and the operation value information corresponding to one or more calculation cells.

[0083] Combined with the scene example, Figure 8 For example, the Ethernet frame packet example is Figure 8 As shown, the packet instance of the Ethernet frame contains the content from Byte1 to Byte22, taking hexadecimal data as an example. Take the logical condition: Byte 9 is AB as an example. From the network packet instance of the example, the byte structure information can be known, and based on the logical condition, it can be known that the logical condition has only one judgment instruction, so it corresponds to a calculation grid instance. First, a blank calculation grid corresponding to the logical condition is created. From the logical condition, it can be known that the logical condition only needs to determine whether Byte 9 is the destination address. There are no other calculation grids to calculate with it, so the associated calculation grid position information does not exist and can be empty. The network packet byte position information is the required byte, that is, Byte 9. From the logical condition, it can be known that the operation of the logical condition is equal, so the operand information can be "equal", and the value of the equal operation with Byte 9 is AB, so the operation value information can be AB.

[0084] Accordingly, S205 includes:

[0085] S702: Write the associated calculation cell position information, key byte position information, operand information and operation value information corresponding to each calculation cell into the associated calculation cell position, network packet byte position, operand and operation value corresponding position of the corresponding blank calculation to obtain each calculation cell instance.

[0086] Combined with the scenario example, write "empty" into the "associated calculation grid position", write "9" into the network packet byte position, write "equal" into the "operand position", and write "AB" into the operation value information to obtain the calculation grid instance corresponding to the logical condition.

[0087] Based on the method provided in this example, the content corresponding to each field in the blank calculation cell can be obtained, and the content corresponding to each field can be written into the corresponding field, thereby achieving the purpose of obtaining a calculation cell instance.

[0088] Optionally, the associated calculation cell position is an OR gate calculation cell position, the associated calculation cell position information is OR gate calculation cell position information, and the operand information includes a plurality of preset comparison logic information.

[0089] Combined with the scenario example, the operation corresponding to the associated calculation cell position can be determined as an "OR" operation, so the associated calculation cell position can be an OR gate calculation cell position, that is, the position of the calculation cell that performs an "OR" operation with the current calculation cell. Taking the above-mentioned logical condition: byte 9 is AB as an example, there are no other calculation cells that perform an "OR" operation with the calculation cell corresponding to the logical condition, so the OR gate calculation cell position information is empty. Comparison logic information includes: greater than (>), greater than or equal to (>=), less than (<), less than or equal to (<=), not equal to (!=), equal to (==), etc. The comparison logic information corresponding to the above-mentioned logical condition is equal to (==), so the operand information is equal to (==). Fig. 9 For example, the calculation grid instance is Fig. 9 , the OR gate calculation grid position information is empty, the network packet byte position information is "9", the operand information is "==", and the operation value information is "AB". Based on the method provided in this example, the calculation grid instance corresponding to each logical condition can be obtained.

[0090] Optional, Fig.10 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 3 ,like Fig.10 As shown, S701 includes:

[0091] S1001. Determine key bytes and sequence information of the key bytes in the network packet according to byte structure information of the network packet.

[0092] Combined with the scenario example, take the logical condition: byte 9 is AB, and byte 14 is CD or byte 15 is not CD as an example, the key bytes in the logical condition are byte 9, byte 14 and byte 15, from which it can be obtained that the sequence information of byte 9, byte 14 and byte 15 in the network packet are 9, 14 and 15 respectively.

[0093] S1002: Determine the sequence information of the key bytes in the network packet as the network packet position information.

[0094] Combined with the scenario example, based on the above logical condition: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be known that the logical condition corresponds to three different computing grid instances, so "9", "14" and "15" can be used as the network packet location information corresponding to the three different computing grid instances.

[0095] S1003: Based on the logical condition, determine whether the key bytes need to be ORed to obtain a determination result corresponding to the key bytes.

[0096] Combined with the scenario example, it can be seen from the logical information of the above example that byte 9 does not need to be ORed, so the judgment result representation corresponding to byte 9 does not need to be ORed, and byte 14 and byte 15 need to be ORed, so the judgment result representation corresponding to byte 14 and byte 15 needs to be ORed.

[0097] S1004. Based on the judgment result corresponding to the key bytes, a coordinate system is established to determine the coordinate information of the calculation grid corresponding to the key bytes.

[0098] Combined with the scene example, Fig.11 The coordinate information diagram of the calculation grid instance is shown as follows: Fig.11 As shown, the coordinate information of the calculation grid corresponding to each key byte can be determined based on the two-dimensional coordinate system. For example, the calculation grid instance corresponding to byte 9 does not need to be ORed, so the coordinate information of the calculation grid instance corresponding to byte 9 can be first determined to be (1,1). The calculation grid instance corresponding to byte 14 and the calculation grid instance corresponding to byte 15 need to be ORed. One of the calculation grid instances can be placed horizontally with the calculation grid instance corresponding to byte 9, and the other calculation grid instance can be placed vertically. For example, the coordinate information of the calculation grid instance corresponding to byte 14 is determined to be (2,1), and the coordinate information of the calculation grid instance corresponding to byte 15 is determined to be (2,2).

[0099] S1005. If the judgment result corresponding to the key byte indicates that an OR operation is required, obtain the coordinate information of the calculation grids corresponding to other key bytes that are to be OR-operated with the key byte, and determine the coordinate information of the calculation grids corresponding to the other key bytes as the OR gate calculation grid position information.

[0100] Combined with the scenario example, according to the above logical conditions, byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be known that the calculation grid instance corresponding to byte 14 and the calculation grid instance corresponding to byte 15 need to be ORed. Fig.11 The coordinates of the calculation grid instance corresponding to byte 14 and the calculation grid instance corresponding to byte 15 are (2,1) and (2,2) respectively. The calculation grid instance corresponding to byte 14 can be used as a reference, and the OR gate calculation grid position of the calculation grid can be filled in blank, and the coordinates (2,1) can be filled in the OR gate calculation grid position of the calculation grid instance corresponding to byte 15, which can represent the OR operation of the above two calculation grids.

[0101] S1006: If the judgment result corresponding to the key byte indicates that an OR operation is not required, the preset first coordinate information is determined as the OR gate calculation grid position information.

[0102] Combined with the scene example, the preset first coordinate information can be determined to be empty. From the above logical conditions: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be seen that the calculation grid instance corresponding to byte 9 does not need to be OR-operated, so the OR gate calculation grid position of the calculation grid instance corresponding to byte 9 is filled in with empty.

[0103] S1007. Determine target comparison logic information based on the logic condition, and determine the target comparison logic information as operand information.

[0104] Combined with the scenario example, based on the above logical conditions: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be seen that the target comparison logic information is equal, equal and not equal, so the operand information of the calculation grid instance corresponding to byte 9 is equal, the operand information of the calculation grid instance corresponding to byte 14 is equal, and the operand information of the calculation grid instance corresponding to byte 15 is not equal.

[0105] S1008. Based on the logical conditions, determine the target comparison content, and determine the target comparison content as operation value information.

[0106] Combined with the scenario example, based on the above logical conditions: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be known that the operation value information is AB, CD, and CD in sequence. Therefore, the operation value information of the calculation grid instance corresponding to byte 9 is AB, the operation value information of the calculation grid instance corresponding to byte 14 is CD, and the operation value information of the calculation grid instance corresponding to byte 15 is CD.

[0107] Based on the method provided in this example, the content filled in each field in the calculation grid can be accurately obtained, and the correctness of the obtained calculation grid can be guaranteed.

[0108] Optional, Fig.12 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 4 , the operand information includes a plurality of preset action information;

[0109] In combination with the scenario example, the action information may be operations such as "replacement" and updating of a Cyclic Redundancy Check (CRC) code.

[0110] Accordingly, if Fig.12 As shown, S701 includes:

[0111] S1201: Determine the key bytes and the sequence information of the key bytes in the network packet according to the byte structure information of the network packet.

[0112] Combined with the scenario example, take the logical condition: replace byte 9 with CD as an example. The key byte of the residence in the logical condition is byte 9, and the sequence information is 9.

[0113] S1202: Determine the sequence information of the key bytes in the network packet as the network packet position information.

[0114] Combined with the scenario example, based on the above logical condition, the sequence information of the key byte is 9, so "9" can be used as the network packet position information corresponding to the calculation grid instance.

[0115] S1203: Based on the logical condition, determine whether the key bytes need to be ORed to obtain a determination result corresponding to the key bytes.

[0116] Combined with the scenario example, it can be seen from the logic information of the above example that byte 9 does not need to be ORed, so the judgment result corresponding to byte 9 indicates that no OR operation is required.

[0117] S1204: Based on the judgment result corresponding to the key bytes, a coordinate system is established to determine the coordinate information corresponding to the key bytes.

[0118] Combined with the scenario example, we can first determine that the coordinate information of the calculation grid instance corresponding to byte 9 is (1,1).

[0119] S1205: If the judgment result corresponding to the key byte indicates that an OR operation is required, the coordinate information corresponding to other key bytes that are subjected to an OR operation with the key byte is obtained, and the coordinate information corresponding to the other key bytes is determined as the OR gate calculation grid position information; if the judgment result corresponding to the key byte indicates that an OR operation is not required, the preset first coordinate information is determined as the OR gate calculation grid position information.

[0120] In combination with the scenario example, it is determined that the calculation grid instance corresponding to byte 9 does not need to be OR-operated with other calculation grid instances, so the space represented by the first coordinate information can be determined as the OR gate calculation grid position information.

[0121] S1206: Based on the logical condition, determine the target action information, and determine the target action information as operand information.

[0122] Combined with the scenario example, based on the above logical conditions: replacing byte 9 with CD, it can be determined that the target action information is replacement, so the operand information is replacement.

[0123] S1207: Based on the logical condition, determine the target comparison content, and determine the target comparison content as operation value information.

[0124] Combined with the scenario example, based on the above logical conditions: replacing byte 9 with CD, it can be determined that the target content is CD, so the calculated numerical information is CD.

[0125] Based on the method provided in this example, the calculation grid can not only perform comparison logic operations, but also perform some practical operations, which can improve the calculation ability of the calculation grid.

[0126] Optional, Fig.13 Schematic diagram of the process of configuring a logic circuit for network packet processing provided in an embodiment of the present application Figure 5 ,like Fig.13 As shown, S206 includes:

[0127] S1301: Based on the OR gate calculation grid position information in the calculation grid instance, determine whether the calculation grid instance needs to perform an OR operation.

[0128] Combined with the scene example, Fig.14 is an example of logic circuit information, based on the logic conditions of the above example: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, such as Fig.14 As shown, the calculation grid instance corresponding to byte 9 can be determined as calculation grid instance 1, the calculation grid instance corresponding to byte 14 can be determined as calculation grid instance 2, and the calculation grid instance corresponding to byte 15 can be determined as calculation grid instance 3. The OR gate calculation grid position information in the three calculation grid instances is "empty", "empty" and "(2,1)" respectively, where (2,1) is the coordinate information of calculation grid instance 2. Therefore, it can be seen that calculation grid instance 1 does not need to be ORed with other calculation grid instances, and calculation grid instance 2 needs to be ORed with calculation grid instance 3.

[0129] S1302: If the calculation cell instance needs to be ORed, the calculation cell instance is determined as the first calculation cell instance, and the calculation cell that needs to be ORed with the first calculation cell instance is determined as the target calculation cell instance corresponding to the first calculation cell instance.

[0130] In combination with the scenario example, since calculation grid instance 2 needs to perform an OR operation with calculation grid instance 3, calculation grid instance 2 can be determined as the first calculation grid instance, and calculation grid instance 3 can be determined as the target calculation grid instance corresponding to the first calculation grid instance. Conversely, calculation grid instance 3 can be determined as the first calculation grid instance, and calculation grid instance 2 can be determined as the target calculation grid instance corresponding to the first calculation grid instance.

[0131] S1303: If the calculation grid instance does not need to perform an OR operation, the calculation grid instance is determined as the second calculation grid instance.

[0132] In combination with the scenario example, the calculation grid instance 1 does not need to be ORed with other calculation grid instances, so the calculation grid instance 1 can be used as the second calculation grid instance.

[0133] S1304: After the first calculation cell instance is connected with the corresponding target calculation cell instance through an OR gate, it is connected with the other first calculation cell and the second calculation cell instance through an AND gate to obtain logic circuit information.

[0134] Combined with the scene example, combined with Fig.14 , connect the calculation grid instance 2 with the calculation grid instance 3 through an OR gate, and then connect the calculation grid instance 2 with the calculation grid instance 1 through an AND gate to obtain the final logic circuit information.

[0135] Based on the method provided in this example, the connection of each computing grid instance can be completed to achieve the purpose of obtaining logic circuit information.

[0136] This embodiment can construct different computing grid instances through different logical information, and construct different computing grid instances into different logical circuit information, and can flexibly construct different logical circuit information. The obtained logical circuit information is FPGA. FPGA is a chip whose internal structure can be re-edited to achieve the purpose of use. Therefore, the FPGA circuit information written into the FPGA smart network card in this embodiment can be flexibly changed so that the FPGA smart network card can process any network packet.

[0137] Fig.15 Schematic diagram of the process of network packet processing method provided in the embodiment of the present application Figure 1 , the method is applied to the hardware network card as above, where the hardware network card is configured with logic circuit information, such as Fig.15 As shown, the method includes:

[0138] S1501, obtaining a network packet to be processed and a preset processing action.

[0139] Combined with the scenario example, the above Figure 8 The exemplary network packet is determined as a network packet to be processed, and the processing actions include forwarding, deleting, and other processing actions. Forwarding can be determined as a preset processing action.

[0140] S1502: Perform operations on the network packet to be processed based on the logic circuit information to obtain a processing result.

[0141] Combined with the scenario example, based on the above Fig.14The logic circuit information of the example performs operations on the network packet to be processed. Specifically, the ninth byte of the network packet to be processed is indeed AB, so the operation result of the calculation grid instance 1 is "1"; the 14th byte of the network packet to be processed is indeed CD, so the operation result of the calculation grid instance 2 is "1"; the 15th byte of the network packet to be processed is 98, so the operation result of the calculation grid instance 3 is "1". The calculation grid instance 2 and the calculation grid instance 3 are "1" after the OR gate operation, and the final processing result after the AND gate operation with the calculation grid instance 1 is "1".

[0142] S1503: If the processing result is the first preset value, a preset processing action is executed on the network packet to be processed.

[0143] In combination with the scenario example, the first preset value is "1". Based on the processing result obtained above, if the processing result is the first preset value, the network packet to be processed is forwarded.

[0144] S1504: If the processing result is the second preset value, then the preset processing action is not executed on the network packet to be processed.

[0145] Combined with the scenario example, the second preset value is "0". Figure 8 The example network packet is determined as a network packet to be processed. Another example logic condition is: byte 9 is CD or byte 15 is greater than 0, and byte 9 is less than EF, and byte 7 is the source MAC address. The logic circuit information that can be obtained is as follows: Fig.16 As shown, Fig.16 Another example of logic circuit information is shown in FIG. Fig.16 , based on the above logical conditions, four calculation grid instances can be obtained, namely, calculation grid instance 4 corresponding to byte 9, calculation grid instance 5 corresponding to byte 15, calculation grid instance 6 corresponding to byte 9, and calculation grid instance 7 corresponding to byte 7. Among them, calculation grid instance 4 and calculation grid instance 5 need to perform OR gate operation, while calculation grid instance 6 and calculation grid instance 7 do not need OR gate operation. Therefore, the coordinate information of calculation grid instance 4, calculation grid instance 6 and calculation grid instance 7 are (1,1), (1,2) and (1,3) respectively, and the coordinate information of calculation grid instance 5 is (1,2). The OR gate calculation grid position information of calculation grid instance 4, calculation grid instance 6 and calculation grid instance 7 is empty, and the OR gate calculation grid position information of calculation grid instance 5 is the coordinate information of calculation grid instance 4 (1,1). The operand of calculation grid instance 4 is equal to, and the operand value is CD; the operand of calculation grid instance 5 is greater than, and the operand value is 0; the operand of calculation grid instance 6 is less than, and the operand value is EF; the operand of calculation grid instance 7 is equal to, and the operand value is SA. Combined Figure 8In the example of a network packet to be processed, byte 9 is AB, so the calculation result of calculation grid instance 4 is "0"; byte 15 is 98, so the calculation result of calculation grid instance 5 is "1"; byte 9 is AB, so the calculation result of calculation grid instance 6 is "1"; byte 7 is the preamble, so the calculation result of calculation grid instance 7 is "0", so the final processing result is "0". When the final processing result is 0, the network packet to be processed is not forwarded.

[0146] Based on the method provided in this example, the network packets to be processed can be processed by the hardware smart network card instead of by the central processing unit (CPU) and software program, which can speed up the processing efficiency of network packets, save CPU usage, and avoid network congestion.

[0147] Fig.17 A schematic diagram of the structure of a logic circuit configuration device for network packet processing provided in an embodiment of the present application, such as Fig.17 As shown, the logic circuit configuration device for network packet processing provided by this embodiment includes:

[0148] A construction module 171, used to construct one or more blank calculation cells;

[0149] An acquisition module 172, used for acquiring byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host;

[0150] The acquisition module 172 is also used to acquire a preset logical condition;

[0151] The processing module 173 is used to determine the configuration information corresponding to one or more computing cells according to the byte structure information and the logic condition of the network packet;

[0152] The processing module 173 is further used to write the configuration information corresponding to the one or more calculation cells into the corresponding blank calculation cells respectively, so as to obtain one or more calculation cell instances;

[0153] The processing module 173 is further used to generate logic circuit information according to one or more calculation grid instances;

[0154] The processing module 173 is also used to configure the logic circuit information into the hardware network card.

[0155] Optionally, the blank calculation cell includes multiple preset information names, wherein the multiple preset information names include at least associated calculation cell positions, network packet byte positions, operands, and operation value information; accordingly, the configuration information includes multiple content information, wherein the multiple content information includes at least associated calculation cell position information, network packet byte position information, operand information, and operation value information.

[0156] Optionally, the processing module 173 is specifically used to determine the associated calculation grid position information, network packet byte position information, operand information and operation value information corresponding to one or more calculation grids according to the byte structure information and logical conditions of the network packet;

[0157] The processing module 173 is also specifically used to write the associated calculation cell position information, key byte position information, operand information and operation value information corresponding to each calculation cell into the associated calculation cell position, network packet byte position, operand and corresponding position of the operation value of the corresponding blank calculation to obtain each calculation cell instance.

[0158] Optionally, the associated calculation cell position is an OR gate calculation cell position, the associated calculation cell position information is OR gate calculation cell position information, and the operand information includes a plurality of preset comparison logic information.

[0159] Optionally, the processing module 173 is further configured to determine the sequence information of the key bytes in the network packet as the network packet position information;

[0160] The processing module 173 is further used to determine whether the key bytes need to be ORed based on the logical conditions to obtain the determination result corresponding to the key bytes;

[0161] The processing module 173 is further configured to establish a coordinate system based on the judgment result corresponding to the key bytes to determine the coordinate information corresponding to the key bytes;

[0162] The processing module 173 is further configured to obtain coordinate information corresponding to other key bytes that are to be OR-operated with the key bytes if the judgment result corresponding to the key bytes indicates that an OR operation is required, and determine the coordinate information corresponding to the other key bytes as the OR gate calculation grid position information;

[0163] The processing module 173 is further configured to determine the preset first coordinate information as the OR gate calculation grid position information if the judgment result corresponding to the key byte indicates that an OR operation is not required;

[0164] The processing module 173 is further configured to determine target comparison logic information based on the logic condition, and determine the target comparison logic information as operand information;

[0165] The processing module 173 is further specifically used to determine the target comparison content based on the logical condition, and determine the target comparison content as the operation value information.

[0166] Optionally, the processing module 173 is further configured to determine whether the calculation grid instance needs to be OR-operated based on the OR gate calculation grid position information in the calculation grid instance;

[0167] The processing module 173 is further configured to determine the calculation cell instance as the first calculation cell instance if the calculation cell instance needs to be OR-operated, and determine the calculation cell that needs to be OR-operated with the first calculation cell instance as the target calculation cell instance corresponding to the first calculation cell instance;

[0168] The processing module 173 is further configured to determine the calculation grid instance as a second calculation grid instance if the calculation grid instance does not need to be OR-operated;

[0169] The processing module 173 is further configured to connect the first computing cell instance with the corresponding target computing cell instance through an OR gate, and then connect the first computing cell instance with the other first computing cell instance and the second computing cell instance through an AND gate to obtain logic circuit information.

[0170] The logic circuit configuration device for network packet processing provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be described in detail here.

[0171] Fig.18 A schematic diagram of the structure of a network packet processing device provided in an embodiment of the present application is shown in FIG. Fig.18 As shown, the network packet processing device provided in this embodiment includes:

[0172] The acquisition module 181 is used to acquire the network packet to be processed and the preset processing action;

[0173] The processing module 182 is used to perform operations on the network packet to be processed based on the logic circuit information to obtain a processing result;

[0174] The processing module 182 is further configured to execute a preset processing action on the network packet to be processed if the processing result is a first preset value;

[0175] The processing module 182 is further configured to not execute a preset processing action on the network packet to be processed if the processing result is a second preset value.

[0176] The network packet processing device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be described in detail here.

[0177] Fig.19 This is a schematic diagram of the structure of the electronic device provided in this application. Fig.19 As shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the device 50 also includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus 504.

[0178] In a specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above method.

[0179] The specific implementation process of the processor 501 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0180] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0181] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0182] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0183] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0184] An embodiment of the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0185] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0186] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0187] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0188] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0189] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0190] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0191] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0192] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application, are not limited to the precise structures described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A logic circuit configuration method for network packet processing, characterized in that: Used in electronic equipment, including: Construct one or more blank calculation cells; Obtain byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host; Get the preset logical conditions; Determine configuration information corresponding to one or more computing cells according to the byte structure information and logic conditions of the network packet; Writing the configuration information corresponding to the one or more calculation cells into corresponding blank calculation cells respectively to obtain one or more calculation cell instances; generating logic circuit information according to the one or more computational grid instances; The logic circuit information is configured into the hardware network card.

2. The method according to claim 1, characterized in that The blank calculation cell includes a plurality of preset information names, wherein the plurality of preset information names at least include associated calculation cell positions, network packet byte positions, operands, and operand values; correspondingly, the configuration information includes a plurality of content information, wherein the plurality of content information at least includes associated calculation cell position information, network packet byte position information, operand information, and operand value information.

3. The method according to claim 2, characterized in that The step of determining configuration information corresponding to one or more computing grids according to the byte structure information and the logical condition of the network packet includes: Determine, according to the byte structure information and logic conditions of the network packet, the associated calculation grid position information, the network packet byte position information, the operand information and the operation value information corresponding to one or more calculation grids; Accordingly, the step of writing the configuration information corresponding to the one or more calculation cells into corresponding blank calculation cells respectively to obtain one or more calculation cell instances includes: The associated calculation cell position information, key byte position information, operand information and operation value information corresponding to each calculation cell are respectively written into the associated calculation cell position, network packet byte position, operand and corresponding position of the operation value of the corresponding blank calculation to obtain each calculation cell instance.

4. The method according to claim 3, characterized in that The associated calculation cell position is an OR gate calculation cell position, the associated calculation cell position information is OR gate calculation cell position information, and the operand information includes a plurality of preset comparison logic information.

5. The method according to claim 4, characterized in that The step of determining, according to the byte structure information and logical conditions of the network packet, the associated calculation grid position information, the network packet byte position information, the operand information and the operation value information corresponding to one or more calculation grids comprises: Determine the key bytes and the sequence information of the key bytes in the network packet according to the byte structure information of the network packet; Determine the sequence information of the key bytes in the network packet as the network packet position information; Based on the logical condition, determine whether the key byte needs to be OR-operated to obtain a determination result corresponding to the key byte; Based on the judgment result corresponding to the key byte, a coordinate system is established to determine the coordinate information of the calculation grid corresponding to the key byte; If the judgment result corresponding to the key byte indicates that an OR operation is required, obtaining coordinate information of calculation grids corresponding to other key bytes that are to be OR-operated with the key byte, and determining the coordinate information of calculation grids corresponding to the other key bytes as the OR gate calculation grid position information; If the judgment result corresponding to the key byte indicates that an OR operation is not required, the preset first coordinate information is determined as the OR gate calculation grid position information; Based on the logic condition, determine target comparison logic information, and determine the target comparison logic information as the operand information; Based on the logical condition, a target comparison content is determined, and the target comparison content is determined as the operation value information.

6. The method according to claim 4, characterized in that The generating logic circuit information according to the one or more computing grid instances includes: Determining whether the computing grid instance needs to perform an OR operation based on the OR gate computing grid position information in the computing grid instance; If the calculation grid instance needs to be OR-operated, the calculation grid instance is determined as the first calculation grid instance, and the calculation grid that needs to be OR-operated with the first calculation grid instance is determined as the target calculation grid instance corresponding to the first calculation grid instance; If the calculation grid instance does not need to be OR-operated, the calculation grid instance is determined as the second calculation grid instance; After the first computing cell instance is connected with the corresponding target computing cell instance through an OR gate, it is then connected with other first computing cells and the second computing cell instance through an AND gate to obtain the logic circuit information.

7. A network packet processing method, characterized in that: Applied to the hardware network card according to any one of claims 1 to 5, wherein the hardware network card is configured with the logic circuit information, the method comprising: Obtaining the network packets to be processed and the preset processing actions; Performing operations on the network packet to be processed based on the logic circuit information to obtain a processing result; If the processing result is a first preset value, executing the preset processing action on the network packet to be processed; If the processing result is a second preset value, the preset processing action is not performed on the to-be-processed network packet.

8. A logic circuit configuration device for network packet processing, characterized in that: Used in electronic equipment, including: A construction module is used to construct one or more blank calculation cells; An acquisition module, used for acquiring byte structure information of a to-be-processed network packet corresponding to any virtual machine of the host; The acquisition module is also used to obtain preset logical conditions; A processing module, used to determine configuration information corresponding to one or more computing cells according to the byte structure information and logic conditions of the network packet; The processing module is further used to write the configuration information corresponding to the one or more calculation cells into the corresponding blank calculation cells respectively to obtain one or more calculation cell instances; The processing module is further used to generate logic circuit information according to the one or more computing grid instances; The processing module is also used to configure the logic circuit information into the hardware network card.

9. An electronic device, characterized in that: include: Memory and processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the logic circuit configuration method for network packet processing as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the logic circuit configuration method for network packet processing as described in any one of claims 1 to 7.

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