Logic circuit configuration method, apparatus, electronic device, and storage medium for network packet processing

Abstract

This application provides a method, apparatus, electronic device, and storage medium for configuring logic circuits for network packet processing, relating to the field of computer communication technology. The method includes: constructing one or more blank computing cells; obtaining the byte structure information and preset logical conditions of a network packet to be processed corresponding to any virtual machine on the host; determining, based on the byte structure information and logical conditions of the network packet, associated computing cell location information, network packet byte location information, operand information, and arithmetic value information corresponding to one or more computing cells, and writing them respectively into the corresponding blank computing cells to obtain one or more computing cell instances; generating logic circuit information based on the one or more computing cell instances; and configuring the logic circuit information into the hardware network interface card (NIC). The method of this application embodiment can flexibly modify the logic circuit information in the hardware NIC.

Description

Technical Field

[0001] This application relates to the field of battery management technology, and in particular to a logic circuit configuration method, apparatus, electronic device, and storage medium for network packet processing. Background Technology

[0002] Berkeley Packet Filter (BPF) is a virtual machine used to filter network packets. The core concept of BPF is that the filter tells the operating system which network packets to keep, so the operating system only transmits the necessary packets to user space, filtering out the rest.

[0003] Related technologies reduce the burden on the central processing unit (CPU) by providing BPF logic circuits in the hardware chip and running the BPF logic circuits in the chip to replace the BPF program in the operating system software. However, the BPF logic circuits in the chip cannot be flexibly modified. Summary of the Invention

[0004] This application provides a logic circuit configuration method, apparatus, electronic device, and storage medium for network packet processing, so as to achieve the effect of flexibly modifying logic circuit information.

[0005] In a first aspect, embodiments of this application provide a logic circuit configuration method for network packet processing, including:

[0006] Construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, the network packet byte position, the operand, and the operation value;

[0007] Obtain the byte structure information of the network packet to be processed corresponding to any virtual machine on the host;

[0008] Retrieve the preset logical conditions;

[0009] Based on the byte structure information and logical conditions of the network packet, determine the associated computation cell position information, network packet byte position information, operand information and computational value information corresponding to one or more computation cells;

[0010] Write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding positions of the associated computation cell position, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain one or more computation cell instances.

[0011] Generate logic circuit information based on one or more computation lattice instances;

[0012] Configure the logic circuit information into the hardware network card.

[0013] Secondly, embodiments of this application provide a network packet processing method applied to a hardware network interface card (NIC) as described in any of the preceding claims, wherein the hardware NIC is configured with logic circuit information, and the method includes:

[0014] Obtain the network packets to be processed and the preset processing actions;

[0015] The network packets to be processed are calculated based on the logic circuit information to obtain the processing result;

[0016] If the processing result is the first preset value, then the preset processing action is performed on the network packet to be processed;

[0017] If the processing result is the second preset value, then the preset processing action will not be performed on the network packet to be processed.

[0018] Thirdly, embodiments of this application provide a logic circuit configuration device for network packet processing, comprising: applied to an electronic device, including:

[0019] The construction module is used to construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, the network packet byte position, the operand, and the operation value;

[0020] The acquisition module is used to acquire the byte structure information of the network packet to be processed corresponding to any virtual machine on the host.

[0021] The acquisition module is also used to acquire preset logical conditions;

[0022] The processing module is used to determine the associated computation cell position information, network packet byte position information, operand information and operation value information corresponding to one or more computation cells based on the byte structure information and logical conditions of the network packet;

[0023] The processing module is also used to write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding position of the associated computation cell, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain one or more computation cell instances.

[0024] The processing module is also used to generate logic circuit information based on one or more computation lattice instances;

[0025] The processing module is also used to configure logic circuit information into the hardware network card.

[0026] Fourthly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0027] The memory stores the instructions that the computer executes;

[0028] The processor executes computer execution instructions stored in memory, causing the processor to perform various possible implementations of the first and / or second aspects described above.

[0029] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement various possible implementations of the first and / or second aspects described above.

[0030] Sixthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements various possible implementations of the first and / or second aspects described above.

[0031] The logic circuit configuration method, apparatus, electronic device, and storage medium for network packet processing provided in this application construct one or more computing grid instances, obtain logic circuit information based on the computing grid instances, and configure the logic circuit information into a hardware network interface card (NIC) to process network packets through the hardware NIC. This application allows for the flexible construction of different logic circuit information by building different computing grid instances, and enables flexible modification of the logic circuit information in the hardware NIC. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 This is a schematic diagram of a scenario provided for an embodiment of this application;

[0034] Figure 2 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 1 ;

[0035] Figure 3 Example calculation grid template;

[0036] Figure 4 Here is an example of a network packet structure;

[0037] Figure 5 The packet format for an example Ethernet frame;

[0038] Figure 6 This is an example of the packet format for an IP data packet;

[0039] Figure 7 A packet instance for an example Ethernet frame;

[0040] Figure 8 Example of a computed lattice instance;

[0041] Figure 9 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 2 ;

[0042] Figure 10 A schematic diagram showing the coordinate information of a sample calculation grid instance;

[0043] Figure 11 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 3 ;

[0044] Figure 12 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 4 ;

[0045] Figure 13 This is an example of logic circuit information;

[0046] Figure 14 Flowchart of the network packet processing method provided in the embodiments of this application Figure 1 ;

[0047] Figure 15 This is another example of logic circuit information;

[0048] Figure 16 This is a schematic diagram of the structure of a logic circuit configuration device for network packet processing provided in an embodiment of this application;

[0049] Figure 17 This is a schematic diagram of the network packet processing device provided in the embodiments of this application;

[0050] Figure 18 A schematic diagram of the structure of the electronic device provided in this application.

[0051] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0053] First, let me explain the terms used in this application:

[0054] BPF: Berkeley Packet Filter is a raw interface of the data link layer on Unix-like systems, providing the sending and receiving of raw link layer packets;

[0055] A network packet is a data unit transmitted in a computer network that contains information such as source address, destination address, and protocol type.

[0056] This application first constructs one or more blank computing cells, then determines the configuration information corresponding to the computing cells based on the byte structure information of the network packets to be processed and the preset logical conditions, then writes the configuration information corresponding to the computing cells into the corresponding blank computing cells to obtain one or more computing cell instances, then generates logical circuit information based on the obtained computing cell instances, and finally configures the logical circuit information into the hardware network card.

[0057] Figure 1 This is a schematic diagram of a scenario provided for an embodiment of this application, such as... Figure 1 The computing device ① is the executing entity of this application and can be a server, a chip, or a board. The chip can be an Artificial Intelligence (AI) chip, which includes at least one hardware processor. The computing device 1 constructs logic circuit information by obtaining one or more blank computing lattice instances.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0059] Figure 2 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 1 ,like Figure 2 As shown, the method includes:

[0060] S201: Construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, the network packet byte position, the operand, and the operation value.

[0061] Combined with scenario examples, Figure 3 Example calculation grid template, such as Figure 3 The calculation cell template includes multiple fields, each of which can be filled with corresponding content. When no content is filled in a field, it can be treated as a blank calculation cell.

[0062] Optional, combined Figure 3 In the example calculation grid template, field 1 can be the associated calculation grid position, which refers to the position of the calculation grid that needs to be operated on with the current calculation grid. Therefore, the associated calculation grid position information can be determined as the content information corresponding to the associated calculation grid position. For example, if the current calculation grid needs to be operated on with calculation grid m, the position information of calculation grid m can be determined as the associated calculation grid position information of the current calculation grid. Field 1 can also be the network packet byte position, which refers to the position information of the byte that the current calculation grid needs to operate on in the network packet. The content information corresponding to the network packet byte position can be the network packet byte position information. For example, if the current calculation grid needs to operate on the content of the ninth byte in the network packet, then position 9 can be determined as the network packet byte position information. Fields 3 and 4 are the preset operand information and operation value information, respectively. The operand information and operation value information can be specified in the preset logical conditions.

[0063] This example clarifies the information of each field in the computation grid template, ensuring that all obtained computation grid instances have the same structure, making the logic circuit information obtained based on the computation grid instances clearer and more understandable.

[0064] S202: Obtain the byte structure information of the network packet to be processed corresponding to any virtual machine on the host.

[0065] Based on the scenario example, any network packet that needs to be filtered in any BPF virtual machine on the host can be taken as a network packet to be processed. Figure 4 Example network packet structure, such as Figure 4As shown, network packets are transmitted according to the Open Systems Interconnection (OSI) seven-layer reference model. Data is transmitted from the transport layer to the network layer, then to the data link layer, and finally through the physical layer. From top to bottom, data packets are packaged into segments, data packets, and frames. Finally, the physical layer transmits the data in binary code. Segments include Transmission Control Protocol (TCP) and User Datagram Protocol (UDP). Data packets also include Internet Protocol Addresses (IP). Frames also include Media Access Control Addresses (MACs).

[0066] There are many formats for network packets. Figure 5 The packet format for an example Ethernet frame, such as Figure 5 As shown, the Ethernet frame packet format includes eight fields: Preamble, Start Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), Ether type, Payload, Padding, and Frame Check Sequence (FCS). The Preamble is a string of binary data, such as 1010…10, used for synchronization. SFD indicates the start of the data after synchronization, such as 1010…11. DA can be the destination MAC address, or a 6-byte hardware code. SA is the source MAC address (6 bytes). The Ether type indicates the length or type. The Payload contains the data to be transmitted in the network packet. Padding indicates that since Ethernet frame packet lengths range from 46 to 1500 bytes, padding is necessary if the packet length is insufficient. The FCS is used to check for errors in the transmitted data.

[0067] Figure 6 Example IP packet encapsulation format, such as Figure 6As shown, the packet format of an IP packet includes 15 fields: Version, Internet Header Length (IHL), type of service, Total Length, Identification, Flag, Fragment offset, Time to Live, Protocol, Header Checksum, Source Address, Destination Address, Padding, and Data.

[0068] S203: Obtain the preset logical conditions.

[0069] Based on the scenario example, the logical condition involves operations that evaluate the bytes of the packet; for example, for... Figure 5 The example Ethernet frame performs a check on network packets to determine if the ninth byte is not equal to "0xA5".

[0070] S204: Based on the byte structure information and logical conditions of the network packet, determine the associated computation cell position information, network packet byte position information, operand information, and computational value information corresponding to one or more computation cells.

[0071] Combined with scenario examples, Figure 3 The example calculation grid template specifies the configuration information for each field, such as field 1 corresponding to content 1, field 2 corresponding to content 2, field 3 corresponding to content 3, and field 4 corresponding to content 4.

[0072] S205: Write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding positions of the associated computation cell position, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain one or more computation cell instances.

[0073] Based on the scenario example, for each calculation grid template, the corresponding content of field 1, field 2, field 3, and field 4 can be written into the corresponding fields respectively. Specifically, content 1 is written into field 1, content 2 into field 2, content 3 into field 3, and content 4 into field 4 to obtain the calculation grid instance.

[0074] Figure 7 Example of a packet in an Ethernet frame, such as Figure 7As shown, an Ethernet packet instance contains content from Byte1 to Byte22, using hexadecimal data as an example. Taking the logical condition: Byte 9 is AB as an example. From the example network packet instance, we know the byte structure information, and based on the logical condition, we know that this logical condition has only one judgment instruction, so it corresponds to one calculation cell instance. First, a blank calculation cell corresponding to this logical condition is created. From the logical condition, we know that this logical condition only needs to determine whether Byte 9 is the destination address; there are no other calculation cells for it, so the associated calculation cell position information does not exist and can be empty. The network packet byte position information is the required byte, i.e., Byte 9. From the logical condition, we know that the operation of this logical condition is equality, so the operand information can be "equal to," and the value of the equality operation with Byte 9 is AB, so the operation value information can be AB.

[0075] Write "empty" to the "associative calculation cell position", write "9" to the network packet byte position, write "equal to" to the "operand position", and write "AB" to the operation value information to obtain the calculation cell instance corresponding to the logical condition.

[0076] Based on the method provided in this example, the content corresponding to each field in the blank calculation cell can be obtained, and the content corresponding to each field can be written into the corresponding field to achieve the purpose of obtaining the calculation cell instance.

[0077] S206: Generate logic circuit information based on one or more computation lattice instances.

[0078] By connecting the obtained computation lattice instances in the context of a scenario, the corresponding logic circuit information can be obtained. For example, connecting the computation lattice instances using an OR gate or an AND gate can yield logic circuit information that can be Field Programmable Gate Array (FPGA) circuit information.

[0079] S207: Configure the logic circuit information into the hardware network card.

[0080] Based on the scenario example, the FPGA circuit information obtained above is written into the hardware network card, such as the FPGA smart network card.

[0081] Since an FPGA is a chip whose internal structure can be re-edited to achieve a specific purpose, the FPGA circuit information written into the FPGA smart network card in this example can be flexibly changed so that the FPGA smart network card can process any network packets.

[0082] Optionally, the associated computation cell position is the OR gate computation cell position, the associated computation cell position information is the OR gate computation cell position information, and the operand information includes multiple preset comparison logic information.

[0083] Based on the scenario example, the operation corresponding to the associated computation cell position can be determined as an "OR" operation. Therefore, the associated computation cell position can be the OR gate computation cell position, that is, the position of the computation cell that performs an "OR" operation with the current computation cell. Taking the above logical condition: byte 9 is AB as an example, there are no other computation cells that perform an "OR" operation with the computation cell corresponding to the logical condition, so the OR gate computation cell position information is empty. Comparison logic information includes: greater than (>), greater than or equal to (>=), less than (<), less than or equal to (<=), not equal to (!=), equal to (==), etc. The comparison logic information corresponding to the above logical condition is equal to (==), so the operand information is equal to (==). Figure 8 Example of a computed lattice instance, such as Figure 8 The OR gate computation cell position information is empty, the network packet byte position information is "9", the operand information is "==", and the operand number information is "AB". Based on the method provided in this example, the computation cell instance corresponding to each logical condition can be obtained.

[0084] Optional, Figure 9 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 2 ,like Figure 9 As shown, S204 includes:

[0085] S901. Based on the byte structure information of the network packet, determine the key byte and its sequence number within the network packet.

[0086] Taking a scenario example, with the logical condition that byte 9 is AB and byte 14 is CD or byte 15 is not CD, the key bytes in the logical condition are bytes 9, 14 and 15. From this, we can obtain the sequence information of bytes 9, 14 and 15 in the network packet as 9, 14 and 15 respectively.

[0087] S902. Determine the sequence information of the key byte in the network packet as the network packet location information.

[0088] Based on the above logical conditions, byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be seen that this logical condition corresponds to three different computation grid instances. Therefore, “9”, “14” and “15” can be used as the network packet location information corresponding to the three different computation grid instances.

[0089] S903. Based on logical conditions, determine whether the key section needs to be ORed to obtain the judgment result corresponding to the key section.

[0090] Based on the scenario example, it can be seen from the logical information in the example above that byte 9 does not need to be ORed, so the judgment result representation corresponding to byte 9 does not need to be ORed. Bytes 14 and 15 need to be ORed, so the judgment result representation corresponding to byte 14 and 15 needs to be ORed.

[0091] S904. Based on the judgment result corresponding to the key section, establish a coordinate system to determine the coordinate information of the calculation grid corresponding to the key section.

[0092] Combined with scenario examples, Figure 10 This is a schematic diagram showing the coordinate information of a sample calculation grid instance, such as... Figure 10 As shown, the coordinate information of the computation cell corresponding to each key byte can be determined based on a two-dimensional coordinate system. For example, if the computation cell instance corresponding to byte 9 does not need to be ORed, the coordinate information of the computation cell instance corresponding to byte 9 can be determined as (1,1). The computation cell instances corresponding to byte 14 and byte 15 need to be ORed. One of the computation cell instances can be placed horizontally with the computation cell instance corresponding to byte 9, and the other computation cell instance can be placed vertically. For example, the coordinate information of the computation cell instance corresponding to byte 14 can be determined as (2,1), and the coordinate information of the computation cell instance corresponding to byte 15 can be determined as (2,2).

[0093] S905. If the judgment result representation corresponding to the key section needs to be ORed, then obtain the coordinate information of the calculation cell corresponding to other key sections that are ORed with the key section, and determine the coordinate information of the calculation cell corresponding to other key sections as the OR gate calculation cell position information.

[0094] Based on the scenario example and the logical conditions above, byte 9 is AB, and byte 14 is CD or byte 15 is not CD. Therefore, the computed cell instance corresponding to byte 14 and the computed cell instance corresponding to byte 15 need to be ORed. Figure 10 The coordinates of the computational grid instance corresponding to byte 14 and the computational grid instance corresponding to byte 15 are (2,1) and (2,2) respectively. The computational grid instance corresponding to byte 14 can be used as the reference. The OR gate computational grid position of the computational grid corresponding to it can be filled with an empty space. The coordinates (2,1) can be filled in the OR gate computational grid position of the computational grid instance corresponding to byte 15. This can represent the above two computational grids performing an OR operation.

[0095] S906. If the judgment result representation corresponding to the keyword section does not require an OR operation, then the preset first coordinate information is determined as the OR gate calculation grid position information.

[0096] Based on the scenario example, the preset first coordinate information can be determined to be empty. According to the above logical conditions: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, it can be seen that the calculation cell instance corresponding to byte 9 does not need to be ORed. Therefore, the OR gate calculation cell position of the calculation cell instance corresponding to byte 9 should be filled with an empty cell.

[0097] S907. Based on logical conditions, determine the target comparison logic information and identify the target comparison logic information as operand information.

[0098] Based on the above logical conditions, and considering the scenario example: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, we can see that the target comparison logic information is equal to, equal to and not equal to in sequence. Therefore, the operand information of the calculation cell instance corresponding to byte 9 is equal to, the operand information of the calculation cell instance corresponding to byte 14 is equal to, and the operand information of the calculation cell instance corresponding to byte 15 is not equal to.

[0099] S908. Based on logical conditions, determine the target comparison content and define the target comparison content as computational numerical information.

[0100] Based on the scenario example and the above logical conditions—byte 9 being AB, and byte 14 being CD or byte 15 not being CD—we can deduce that the calculated numerical information is AB, CD, and CD in sequence. Therefore, the calculated numerical information of the calculation cell instance corresponding to byte 9 is AB, the calculated numerical information of the calculation cell instance corresponding to byte 14 is CD, and the calculated numerical information of the calculation cell instance corresponding to byte 15 is CD.

[0101] Based on the method provided in this example, the content filled in each field of the calculation cell can be accurately obtained, ensuring the correctness of the obtained calculation cell.

[0102] Optional, Figure 11 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 3 The operand information includes multiple preset action information;

[0103] Based on scenario examples, action information can include operations such as "replacement" and updating the Cyclic Redundancy Check (CRC) code.

[0104] Accordingly, such as Figure 11 As shown, S204 includes:

[0105] S1101: Determine the key byte and its sequence number within the network packet based on the byte structure information of the network packet.

[0106] Taking the scenario example, with the logical condition of replacing byte 9 with CD, the key byte in the logical condition is byte 9, and the sequence information is 9.

[0107] S1102: Determine the sequence information of the key byte in the network packet as the network packet location information.

[0108] Based on the example scenario, since the sequence information of the logical condition key byte is 9, "9" can be used as the network packet position information corresponding to the calculation grid instance.

[0109] S1103: Based on logical conditions, determine whether the key section needs to be ORed to obtain the judgment result corresponding to the key section.

[0110] Based on the scenario example, it can be seen from the logical information in the example above that byte 9 does not need to be ORed, so the judgment result corresponding to byte 9 does not need to be ORed.

[0111] S1104: Based on the judgment result corresponding to the keyword section, establish a coordinate system to determine the coordinate information corresponding to the keyword section.

[0112] Based on the scenario example, we can first determine the coordinates of the computational grid instance corresponding to byte 9 as (1,1).

[0113] S1105: If the judgment result representation corresponding to the key section needs to be ORed, then obtain the coordinate information of other key sections that are ORed with the key section, and determine the coordinate information of other key sections as the OR gate calculation grid position information; if the judgment result representation corresponding to the key section does not need to be ORed, then determine the preset first coordinate information as the OR gate calculation grid position information.

[0114] Based on the scenario example, it is determined that the computational grid instance corresponding to byte 9 does not need to be ORed with other computational grid instances. Therefore, the empty space represented by the first coordinate information can be determined as the OR gate computational grid position information.

[0115] S1106: Based on logical conditions, determine the target action information and identify the target action information as operand information.

[0116] Based on the above logical conditions and the scenario example: replacing byte 9 with CD determines that the target action information is replacement, therefore the operand information is replacement.

[0117] S1107: Based on logical conditions, determine the target comparison content and define the target comparison content as computational numerical information.

[0118] Based on the above logical conditions and the scenario example: by replacing byte 9 with CD, we can determine that the target content is CD, so the calculated numerical information is CD.

[0119] Based on the method provided in this example, computation lattices can not only perform comparative logic operations, but also perform some practical operations, thereby improving the computational capabilities of computation lattices.

[0120] Optional, Figure 12 A flowchart illustrating the logic circuit configuration method for network packet processing provided in this application embodiment. Figure 4 ,like Figure 12 As shown, S206 includes:

[0121] S1201: Based on the OR gate computation cell position information in the computation cell instance, determine whether the computation cell instance needs to perform an OR operation.

[0122] Combined with scenario examples, Figure 13 As an example of logic circuit information, based on the logic conditions of the example above: byte 9 is AB, and byte 14 is CD or byte 15 is not CD, such as Figure 14 As shown, the computational grid instance corresponding to byte 9 can be identified as computational grid instance 1, the computational grid instance corresponding to byte 14 as computational grid instance 2, and the computational grid instance corresponding to byte 15 as computational grid instance 3. The OR gate computational grid position information in the three computational grid instances are "empty", "empty", and "(2,1)" respectively, where (2,1) is the coordinate information of computational grid instance 2. Therefore, it can be concluded that computational grid instance 1 does not need to be ORed with other computational grid instances, while computational grid instance 2 needs to be ORed with computational grid instance 3.

[0123] S1202: If a computational lattice instance needs to be ORed, then the computational lattice instance is determined as the first computational lattice instance, and the computational lattice that needs to be ORed with the first computational lattice instance is determined as the target computational lattice instance corresponding to the first computational lattice instance.

[0124] Based on the scenario example, since computational grid instance 2 needs to be ORed with computational grid instance 3, computational grid instance 2 can be designated as the first computational grid instance, and computational grid instance 3 can be designated as the target computational grid instance corresponding to the first computational grid instance. Alternatively, computational grid instance 3 can be designated as the first computational grid instance, and computational grid instance 2 can be designated as the target computational grid instance corresponding to the first computational grid instance.

[0125] S1203: If the computation lattice instance does not need to be ORed, then the computation lattice instance is determined as the second computation lattice instance.

[0126] Based on the scenario example, since computational grid instance 1 does not need to be ORed with other computational grid instances, computational grid instance 1 can be used as the second computational grid instance.

[0127] S1204: After connecting the first computation cell instance with the corresponding target computation cell instance using an OR gate, connect it with other first computation cells and instance second computation cell instances using an AND gate to obtain logic circuit information.

[0128] Combined with scenario examples, Figure 13 By connecting computation grid instance 2 and computation grid instance 3 with an OR gate, and then connecting computation grid instance 2 and computation grid instance 1 with an AND gate, the final logic circuit information can be obtained.

[0129] Based on the method provided in this example, the connection of each computation lattice instance can be completed to obtain logic circuit information.

[0130] This embodiment can construct different computational lattice instances through different logical information, and construct different computational lattice instances into different logical circuit information. Different logical circuit information can be flexibly constructed, and the obtained logical circuit information is FPGA. FPGA is a chip whose internal structure can be re-edited to achieve the purpose of use. Therefore, the FPGA circuit information written into the FPGA smart network card in this embodiment can be flexibly changed so that the FPGA smart network card can process arbitrary network packets.

[0131] Figure 14 Flowchart of the network packet processing method provided in the embodiments of this application Figure 1 This method is applied to hardware network cards as described above, where the hardware network card is configured with logic circuit information, such as... Figure 14 As shown, the method includes:

[0132] S1401. Obtain the network packets to be processed and the preset processing actions.

[0133] Combined with scenario examples, the above can be... Figure 8 The example network packet is identified as a network packet to be processed. The processing actions include forwarding, deletion, etc. Forwarding can be identified as a preset processing action.

[0134] S1402. Perform calculations on the network packets to be processed based on the logic circuit information to obtain the processing results.

[0135] Based on the above, and in conjunction with scenario examples, Figure 13The example logic circuit information performs operations on the network packets to be processed. Specifically, the ninth byte of the network packet to be processed is indeed AB, so the result of the operation in Grid Example 1 is "1"; the 14th byte of the network packet to be processed is indeed CD, so the result of the operation in Grid Example 2 is "1"; the 15th byte of the network packet to be processed is 98, so the result of the operation in Grid Example 3 is "1". Grid Example 2 and Grid Example 3 are ORed together to get "1", and then ANDed with Grid Example 1 to get the final result of "1".

[0136] S1403. If the processing result is the first preset value, then the preset processing action is performed on the network packet to be processed.

[0137] Based on the scenario example, the first preset value is "1". Based on the processing result obtained above, if the processing result is the first preset value, then the network packet to be processed will be forwarded.

[0138] S1404. If the processing result is the second preset value, then the preset processing action will not be performed on the network packet to be processed.

[0139] Based on the scenario example, the second preset value is "0". The above can be... Figure 7 The example network packet is identified as a network packet to be processed. The example logic conditions are: byte 9 is CD or byte 15 is greater than 0, and byte 9 is less than EF, and byte 7 is the source MAC address. The resulting logic circuit information is as follows: Figure 15 As shown, Figure 15 This is another example of logic circuit information. (By...) Figure 15 Based on the above logical conditions, four computational grid instances can be obtained: computational grid instance 4 corresponding to byte 9, computational grid instance 5 corresponding to byte 15, computational grid instance 6 corresponding to byte 9, and computational grid instance 7 corresponding to byte 7. Computational grid instance 4 and computational grid instance 5 require an OR gate operation, while computational grid instance 6 and computational grid instance 7 do not. Therefore, the coordinates of computational grid instance 4, computational grid instance 6, and computational grid instance 7 are (1,1), (1,2), and (1,3) respectively, and the coordinate of computational grid instance 5 is (1,2). The OR gate computational grid positions of computational grid instance 4, computational grid instance 6, and computational grid instance 7 are empty, and the OR gate computational grid position of computational grid instance 5 is the coordinate of computational grid instance 4 (1,1). The operand of computational grid instance 4 is equal to, and the operand value is CD; the operand of computational grid instance 5 is greater than, and the operand value is 0; the operand of computational grid instance 6 is less than, and the operand value is EF; the operand of computational grid instance 7 is equal to, and the operand value is SA. Combined with... Figure 7In the example network packet to be processed, byte 9 is AB, so the result of the operation in grid instance 4 is "0"; byte 15 is 98, so the result of the operation in grid instance 5 is "1"; byte 9 is AB, so the result of the operation in grid instance 6 is "1"; byte 7 is the preamble, so the result of the operation in grid instance 7 is "0", therefore the final processing result is "0". When the final processing result is 0, the network packet to be processed is not forwarded.

[0140] Based on the method provided in this example, network packets can be processed by a hardware smart network card instead of by a central processing unit (CPU) and software programs. This can speed up the processing of network packets, save CPU usage, and avoid network congestion.

[0141] Figure 16 This is a schematic diagram of the structure of a logic circuit configuration device for network packet processing provided in an embodiment of this application, as shown below. Figure 16 As shown, the logic circuit configuration device for network packet processing provided in this embodiment includes:

[0142] Module 161 is used to construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, the network packet byte position, the operand, and the operation value;

[0143] The acquisition module 162 is used to acquire the byte structure information of the network packet to be processed corresponding to any virtual machine of the host.

[0144] The acquisition module 162 is also used to acquire preset logical conditions;

[0145] Processing module 163 is used to determine the associated computation cell position information, network packet byte position information, operand information and computational value information corresponding to one or more computation cells based on the byte structure information and logical conditions of the network packet;

[0146] The processing module 163 is also used to write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding position of the associated computation cell, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain one or more computation cell instances.

[0147] Processing module 163 is also used to generate logic circuit information based on one or more computation lattice instances;

[0148] The processing module 163 is also used to configure logic circuit information into the hardware network card.

[0149] Optionally, the blank calculation cell includes multiple preset information names, wherein the multiple preset information names include at least the associated calculation cell position, the network packet byte position, the operand, and the calculated value; correspondingly, the configuration information includes multiple content information, wherein the multiple content information includes at least the associated calculation cell position information, the network packet byte position information, the operand information, and the calculated value information.

[0150] Optionally, the processing module 163 is specifically used to determine the associated computation cell position information, network packet byte position information, operand information and computational value information corresponding to one or more computation cells based on the byte structure information and logical conditions of the network packet;

[0151] The processing module 163 is further used to write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding position of the associated computation cell, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain each computation cell instance.

[0152] Optionally, the associated computation cell position is the OR gate computation cell position, the associated computation cell position information is the OR gate computation cell position information, and the operand information includes multiple preset comparison logic information.

[0153] Optionally, the processing module 163 is further used to determine the sequence information of the key byte in the network packet as the network packet location information;

[0154] The processing module 163 is also used to determine whether the key section needs to be ORed based on logical conditions in order to obtain the judgment result corresponding to the key section.

[0155] The processing module 163 is further used to establish a coordinate system based on the judgment result corresponding to the keyword section to determine the coordinate information corresponding to the keyword section;

[0156] The processing module 163 is further used to obtain the coordinate information of other key sections that are ORed with the key section if the judgment result representation corresponding to the key section needs to be ORed, and to determine the coordinate information of other key sections as the OR gate calculation grid position information.

[0157] The processing module 163 is further used to determine the preset first coordinate information as the OR gate calculation grid position information if the judgment result representation corresponding to the key section does not need to be ORed.

[0158] The processing module 163 is further used to determine the target comparison logic information based on logical conditions, and to determine the target comparison logic information as operand information;

[0159] The processing module 163 is further used to determine the target comparison content based on logical conditions, and to determine the target comparison content as computational numerical information.

[0160] Optionally, the processing module 163 is further used to determine whether the computational grid instance needs to perform an OR operation based on the OR gate computational grid position information in the computational grid instance;

[0161] The processing module 163 is further configured to, if a computational grid instance needs to be ORed, determine the computational grid instance as the first computational grid instance and determine the computational grid that needs to be ORed with the first computational grid instance as the target computational grid instance corresponding to the first computational grid instance.

[0162] The processing module 163 is further configured to determine the computational grid instance as the second computational grid instance if the computational grid instance does not need to be subjected to an OR operation.

[0163] The processing module 163 is further configured to connect the first computation grid instance with the corresponding target computation grid instance via an OR gate, and then connect it with other first computation grid instances and instance second computation grid instances via an AND gate to obtain logic circuit information.

[0164] The logic circuit configuration device for network packet processing provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0165] Figure 17 This is a schematic diagram of the network packet processing device provided in the embodiments of this application, as shown below. Figure 17 As shown, the network packet processing device provided in this embodiment includes:

[0166] The acquisition module 171 is used to acquire network packets to be processed and preset processing actions;

[0167] The processing module 172 is used to perform calculations on the network packets to be processed based on logic circuit information to obtain the processing results;

[0168] The processing module 172 is also used to perform a preset processing action on the network packet to be processed if the processing result is a first preset value.

[0169] The processing module 172 is also used to not perform preset processing actions on the network packets to be processed if the processing result is the second preset value.

[0170] The network packet processing device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0171] Figure 18 A schematic diagram of the structure of the electronic device provided in this application. Figure 18 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0172] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0173] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0174] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0175] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0176] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0177] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0178] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0179] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0180] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0181] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0182] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0183] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0184] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0185] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0186] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations may be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A logic circuit configuration method for network packet processing, characterized in that, Applied to electronic devices, including: Construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, the network packet byte position, the operand, and the operation value; Obtain the byte structure information of the network packet to be processed corresponding to any virtual machine on the host; Retrieve preset logical conditions; Based on the byte structure information and logical conditions of the network packet, determine the associated computation cell location information, network packet byte location information, operand information, and computational value information corresponding to one or more computation cells. The associated computation cell position information, key byte position information, operand information, and operand value information of each computation cell are written into the corresponding positions of the associated computation cell position, network packet byte position, operand, and operand value of the corresponding blank computation, respectively, to obtain one or more computation cell instances. Based on the one or more computation lattice instances, generate logic circuit information; Configure the logic circuit information into the hardware network card.

2. The method according to claim 1, characterized in that, The associated computation cell position is the OR gate computation cell position, the associated computation cell position information is the OR gate computation cell position information, and the operand information includes multiple preset comparison logic information.

3. The method according to claim 2, characterized in that, The step of determining the associated computation grid location information, network packet byte location information, operand information, and computational value information corresponding to one or more computation grids based on the byte structure information and logical conditions of the network packet includes: Based on the byte structure information of the network packet, determine the key byte and the sequence information of the key byte in the network packet; The sequence information of the keyword byte in the network packet is determined as the network packet location information; Based on the logical conditions, determine whether the keyword section needs to be ORed to obtain the judgment result corresponding to the keyword section; Based on the judgment result corresponding to the keyword section, a coordinate system is established to determine the coordinate information of the calculation grid corresponding to the keyword section; If the judgment result corresponding to the keyword section indicates that an OR operation is required, then the coordinate information of the calculation cell corresponding to other keyword sections that are ORed with the keyword section is obtained, and the coordinate information of the calculation cell corresponding to the other keyword sections is determined as the position information of the OR gate calculation cell. If the judgment result corresponding to the keyword section does not require an OR operation, then the preset first coordinate information is determined as the OR gate calculation grid position information; Based on the aforementioned logical conditions, target comparison logic information is determined, and the target comparison logic information is identified as the operand information. Based on the aforementioned logical conditions, the target comparison content is determined, and the target comparison content is identified as the computational numerical information.

4. The method according to claim 2, characterized in that, The step of generating logic circuit information based on the one or more computation lattice instances includes: Based on the OR gate computation grid position information in the computation grid instance, determine whether the computation grid instance needs to perform an OR operation; If the computational lattice instance needs to be ORed, then the computational lattice instance is determined as the first computational lattice instance, and the computational lattice that needs to be ORed with the first computational lattice instance is determined as the target computational lattice instance corresponding to the first computational lattice instance. If the computational lattice instance does not require an OR operation, then the computational lattice instance is determined as the second computational lattice instance; After connecting the first computational grid instance with the corresponding target computational grid instance using an OR gate, it is then connected with other first computational grid instances and instance second computational grid instances using an AND gate to obtain the logic circuit information.

5. A network packet processing method, characterized in that, Applied to a hardware network interface card as described in any one of claims 1 to 4, wherein the hardware network interface card is configured with the logic circuit information, the method includes: Obtain the network packets to be processed and the preset processing actions; The network packets to be processed are calculated based on the logic circuit information to obtain the processing result; If the processing result is the first preset value, then the preset processing action is performed on the network packet to be processed; If the processing result is the second preset value, then the preset processing action will not be performed on the network packet to be processed.

6. A logic circuit configuration device for network packet processing, characterized in that, Applied to electronic devices, including: A construction module is used to construct one or more blank computation cells, wherein the blank computation cells include multiple preset information names, wherein the multiple preset information names include at least the associated computation cell position, network packet byte position, operand, and computation value; The acquisition module is used to acquire the byte structure information of the network packet to be processed corresponding to any virtual machine on the host. The acquisition module is also used to acquire preset logical conditions; The processing module is used to determine the associated computation grid position information, network packet byte position information, operand information and computational value information corresponding to one or more computation grids based on the byte structure information and logical conditions of the network packet; The processing module is also used to write the associated computation cell position information, key byte position information, operand information and operation value information corresponding to each computation cell into the corresponding position of the associated computation cell, network packet byte position, operand and operation value of the corresponding blank computation, so as to obtain one or more computation cell instances. The processing module is also used to generate logic circuit information based on the one or more computation lattice instances; The processing module is also used to configure the logic circuit information into the hardware network card.

7. An electronic device, characterized in that, include: Memory and processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the logic circuit configuration method for network packet processing as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the logic circuit configuration method for network packet processing as described in any one of claims 1 to 4.

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