A trigger type CMOS image sensor and a method for implementing the same

Abstract

The present application relates to the technical field of image sensor, in particular to a trigger type CMOS image sensor and its implementation method; the control circuit includes an output circuit for outputting photoelectric signal and a readout circuit for inputting photoelectric signal, the output circuit includes a reset tube S4, a transfer tube S5, an output tube S6, a source follower tube S10, a comparison unit, a switch S8, a switch S7 and a photoelectric signal storage capacitor; the present application adopts a pixel level photoelectric signal storage and comparison mode, determines the change of a single pixel between a previous image and a later image, quantizes the change signal and identifies the position information, greatly shortens the quantization and processing time, greatly reduces the power consumption and improves the frame frequency, and has important significance for target detection, tracking, border monitoring and other event discovery application scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, in particular to a trigger type CMOS image sensor and an implementation method thereof. BACKGROUND

[0002] CMOS image sensors are widely used in space exploration, earth observation, industrial monitoring and consumer electronics, and through various types of complex light collection, they can achieve target acquisition, detection perception and imaging shooting and other application requirements.

[0003] The existing CMOS image sensor is divided into global and rolling shutter two exposure modes, the global exposure mode means that when the aperture is opened, all pixel points on the CMOS image sensor can start exposure at the same time, and when the aperture is closed, all pixels end exposure at the same time; the rolling shutter exposure mode is a line-by-line scanning and exposure mode, that is, after all the pixels in the previous line are exposed at the same time, all the pixels in the next line are exposed at the same time, and all the lines are exposed until all the lines are exposed; however, regardless of the change of the exposure mode, the full array data needs to be read out completely, which has the disadvantages of large readout power consumption and low readout frame frequency, thereby limiting the performance of the CMOS image sensor in high-speed and low-power applications.

[0004] The circuit structure block diagram of the CMOS image sensor in the prior art is shown in Figure 6 , and the timing diagram is shown in Figure 7 , Figure 1 The pixel-level circuit in the prior art includes switches S4, S5 and S6; as shown in Figure 7 , in the first stage, the switch S6 is low, and the switches S4 and S5 are high, so as to reset the photodiode, and at the same time, the reset signal is stored in the FD point; in the second stage, the switch S6 is high, and the switches S4 and S5 are low, so as to disconnect the reset of the photodiode, and read out the reset signal; in the third stage, the switches S6 and S5 are high, and the switch S4 is low, so as to transfer the photodiode signal from the photodiode to the FD point; in the fourth stage, the switch S6 is high, and the switch is turned on, and the switches S4 and S5 are both low, and the switch is disconnected, so as to read out the photodiode signal.

[0005] The above-mentioned traditional image sensor circuit needs to read out the data of each pixel one by one in each image capture process, and combine these data to generate a picture, however, in actual application, only a small part of the position in a single picture often changes, although this, the traditional image sensor circuit still needs to read out all the pixel data of the whole picture, which not only leads to a large waste of power consumption, but also reduces the frame frequency of the system. SUMMARY

[0006] In view of the problems mentioned in the prior art, the application provides a trigger type CMOS image sensor and an implementation method thereof, which feeds back pixel level results to control logic, quantizes and processes only the changed positions, greatly improves the useful information acquisition rate, and improves the frame frequency and reduces the power consumption.

[0007] In order to achieve the above-mentioned purpose, the application adopts the following technical solutions:

[0008] The application provides a trigger type CMOS image sensor, which comprises a photodiode and a control circuit.

[0009] The photodiode is arranged on an upper layer chip, and the control circuit is arranged on a lower layer chip, wherein the upper layer chip and the lower layer chip adopt a 3D stacking structure, and the upper layer chip and the lower layer chip are interconnected through bonding.

[0010] The control circuit comprises an output circuit for outputting a photoelectric signal and a readout circuit for inputting the photoelectric signal, and the output circuit comprises a reset transistor S4, a transfer transistor S5, an output transistor S6, a source follower transistor S10, a comparison unit, a switch S8 and a switch S7, and a photoelectric signal storage capacitor.

[0011] The drain of the reset transistor S4 and the drain of the source follower transistor S10 are connected to VDD, the source of the transfer transistor S5 is connected to the photodiode on the upper layer of the chip and then connected to ground, the drain of the transfer transistor S5 and the source of the reset transistor S4 are connected to an FD point, the FD point is connected to the gate of the source follower transistor S10, the source of the source follower transistor S10 and the source of the output transistor S6 are connected to the switch S7 and the switch S8, and the drain of the output transistor S6 outputs the photoelectric signal.

[0012] One end of the photoelectric signal storage capacitor is connected to the switch S7 and then connected to ground, and the other end is also connected to one port of the comparison unit, and the other port of the comparison unit is connected to the switch S8.

[0013] As a further improvement of the application, the port of the comparison unit connected to the switch S8 is used to receive the photoelectric signal of the last time, and the port connected to the switch S7 is used to receive the photoelectric signal of the previous time.

[0014] As a further improvement of the application, the comparison unit comprises a first comparator, a second comparator and an XOR gate, two input ends of the XOR gate receive the photoelectric signal of the first comparator and the photoelectric signal of the second comparator respectively, and the output end of the XOR gate outputs an indication signal to the logic control.

[0015] The positive terminal of the first comparator is connected to the negative terminal of the second comparator to receive the photoelectric signal of the last time, and the negative terminal of the first comparator is connected to the positive terminal of the second comparator to receive the photoelectric signal of the previous time.

[0016] As a further improvement of the present application, when the previous photoelectric signal is inconsistent with the latter photoelectric signal, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit to convert the previous photoelectric signal.

[0017] As a further improvement of the present application, when the previous photoelectric signal is consistent with the latter photoelectric signal, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit to not convert the previous photoelectric signal.

[0018] As a further improvement of the present application, the readout circuit comprises an analog front end, an analog-to-digital converter, and a counter; the input end of the analog front end is connected to the output circuit, the output end of the analog front end is connected to the analog-to-digital converter, and the output end of the analog-to-digital converter is connected to the counter.

[0019] As a further improvement of the present application, a copper column interconnection structure is adopted between the upper chip and the lower chip.

[0020] An implementation method of a trigger type CMOS image sensor, comprising the following steps:

[0021] S1, after the previous exposure is completed, the output circuit makes the switch S7 closed and the switch S8 disconnected, and the previous photoelectric signal stored in the FD is stored in the photoelectric signal storage capacitor through the source follower S10 and the switch S7;

[0022] S2, after the latter exposure is completed, the output circuit makes the switch S8 closed and the switch S7 disconnected, and the latter photoelectric signal is located at one port of the comparison unit, and the previous photoelectric signal stored in the photoelectric signal storage capacitor is located at the other port;

[0023] S3, the comparison unit compares the received previous photoelectric signal and the latter photoelectric signal, inputs the previous photoelectric signal to the negative end of the first comparator and the positive end of the second comparator, and inputs the latter photoelectric signal to the positive end of the first comparator and the negative end of the second comparator, and compares whether the previous photoelectric signal and the latter photoelectric signal are consistent.

[0024] S4, if the previous photoelectric signal and the latter photoelectric signal are consistent, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit to not convert the previous photoelectric signal and realizes high-speed image generation; if the previous photoelectric signal and the latter photoelectric signal are inconsistent, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit to convert the previous photoelectric signal, and realizes high-speed image generation after conversion.

[0025] As a further improvement of the present application, the specific process of step S4 is:

[0026] If the previous photoelectric signal is less than the next photoelectric signal, then the first comparator XOR gate outputs 1, the second comparator outputs 0, and the XOR gate outputs 1;

[0027] If the previous photoelectric signal is greater than the next photoelectric signal, then the first comparator outputs 0, the second comparator outputs 1, and the XOR gate outputs 1;

[0028] If the previous photoelectric signal is equal to the next photoelectric signal, then the first comparator outputs 0, the second comparator outputs 0, and the XOR gate outputs 0.

[0029] As a further improvement of the present application, the comparison unit needs to be reset before step S3.

[0030] Compared with the prior art, the present application has the following technical effects:

[0031] For the application scenario of long-time work for target tracking, gaze imaging, etc., and only a small part of the target has abnormal changes, compared with the problem of large power consumption of the traditional image sensor and low system frame frequency, by using difference signal recognition and state reduction comparison at the pixel level, the change signal is recognized at the pixel level, only the change signal is quantized and processed, the processing requirement of the readout circuit is reduced, unnecessary full-frame operation is effectively avoided, thereby greatly improving the acquisition efficiency of useful information, not only reducing the power consumption, but also improving the frame frequency, so that the image sensor can more efficiently capture target dynamics in the task. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a schematic diagram of the image sensor stack of the present application;

[0033] Figure 2 It is a schematic diagram of the specific structure of the image sensor of the present application;

[0034] Figure 3 It is a schematic diagram of the comparison unit structure of the present application;

[0035] Figure 4 It is a timing diagram of the image sensor of the present application;

[0036] Figure 5 It is a schematic diagram of the working process of the image sensor of the present application;

[0037] Figure 6 It is a schematic diagram of the image sensor structure of the prior art;

[0038] Figure 7 It is a timing diagram of the image sensor of the prior art.

[0039] Reference numerals: 10, output circuit; 20, analog front end; 30, analog-digital converter; 40, counter; 11, comparison unit first port; 12, photoelectric signal storage capacitor; 13, comparison unit; 14, photodiode; 15, comparison unit second port; 16, XOR gate output port; 17, first comparator; 18, second comparator; 19, XOR gate. DETAILED DESCRIPTION

[0040] Hereinafter, only certain exemplary embodiments will be described simply. As can be recognized by those skilled in the art, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0041] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0042] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0043] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection, or communication; can be directly connected, or indirectly connected through intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] In the present application, unless specifically stated and limited otherwise, the "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "on", "above" and "under" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher in horizontal height than the second feature. The "under", "below" and "under" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is lower in horizontal height than the second feature.

[0045] It should be understood that the terms "comprises" and "comprising" when used in this specification and the following claims indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0046] It should also be understood that the terms used in the present application specification are only for the purpose of describing particular embodiments and are not intended to limit the present application. As used in the present application specification and the following claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It should be further understood that the term "and / or" used in the present application specification is intended to refer to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0048] Various structural diagrams according to the disclosed embodiments of the present application are shown in the accompanying drawings. These drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and some details may be omitted. The shapes of various regions, layers and their relative size and positional relationship shown in the drawings are only exemplary, and in actuality may be deviated due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0049] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0050] As Figure 1As shown, the application is a trigger type CMOS image sensor, which comprises a photodiode 14 and a control circuit; the photodiode 14 is arranged on an upper layer chip, and the control circuit is arranged on a lower layer chip; the upper layer chip and the lower layer chip adopt a 3D stacking structure, and the upper layer chip and the lower layer chip are interconnected through bonding; in the embodiment, the 3D stacking is adopted to ensure that the photodiode 14 has sufficient light sensing area, and at the same time, the control circuit has more sufficient area space.

[0051] As shown in the embodiment, Figure 2 and Figure 4 As shown, the control circuit comprises an output circuit 10 for outputting a photoelectric signal and a readout circuit for inputting the photoelectric signal; the output circuit 10 comprises a reset transistor S4, a transfer transistor S5, an output transistor S6, a source follower transistor S10, a comparison unit 13, a switch S8, a switch S7 and a photoelectric signal storage capacitor 12; the drains of the reset transistor S4 and the source follower transistor S10 are connected to VDD; the source of the transfer transistor S5 is connected to the photodiode 14 on the upper layer of the chip and then grounded; the drain of the transfer transistor S5 is connected to the source of the reset transistor S4 and then to the FD point; the FD point is connected to the gate of the source follower transistor S10; the source of the source follower transistor S10 and the source of the output transistor S6 are connected to the switch S7 and the switch S8; and the drain of the output transistor S6 outputs the photoelectric signal.

[0052] One end of the photoelectric signal storage capacitor 12 is connected to the switch S7 and then grounded, and the other end is also connected to one port of the comparison unit; the other port of the comparison unit is connected to the switch S8. The port of the comparison unit connected to the switch S8 is used to receive the photoelectric signal of the previous time, and the port connected to the switch S7 is used to receive the photoelectric signal of the later time. In the embodiment, the comparison unit comprises two ports, which are a comparison unit first port 11 and a comparison unit second port 15; when comparing, the comparison unit first port 11 is used to receive the photoelectric signal of the previous time, and the comparison unit second port 15 is used to receive the photoelectric signal of the later time; the voltages of the photoelectric signal of the previous time and the photoelectric signal of the later time are compared by the comparison unit 13 to determine whether the photoelectric signal of the previous time needs to be quantized.

[0053] As shown in the embodiment, Figure 3As shown, the comparison unit includes a first comparator 17, a second comparator 18, and an XOR gate 19. The two inputs of the XOR gate 19 receive the photoelectric signal from the first comparator 17 and the photoelectric signal from the second comparator 18, respectively. The output of the XOR gate 19 outputs an indication signal to the logic control. The positive terminal of the first comparator 17 is connected to the negative terminal of the second comparator 18 to receive the subsequent photoelectric signal, and the negative terminal of the first comparator 17 is connected to the positive terminal of the second comparator 18 to receive the previous photoelectric signal. In this embodiment, the first comparator 17 and the second comparator 18 are preferably hysteresis comparators. The voltage magnitudes of the previous and subsequent photoelectric signals are determined by whether the first comparator 17 and the second comparator 18 flip. The output port 16 of the XOR gate is used to output the indication signal.

[0054] This invention can effectively identify photoelectric differences between pixels in two consecutive frames. It compares the photoelectric signals from the two exposures in a pixel-level comparator. If the photoelectric signal of the previous exposure is inconsistent with the photoelectric signal of the next exposure, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit to quantize and process the previous photoelectric signal. If the photoelectric signal of the previous exposure is consistent with the photoelectric signal of the next exposure, the XOR gate outputs an indication signal to the logic control, which controls the readout circuit not to quantize and process the previous photoelectric signal. This invention does not require full-frame output and comparison of the differences between the two images to determine the location of the event, and has low latency and lower power consumption.

[0055] The readout circuit includes a simulator front-end, an analog-to-digital converter, and a counter; the input terminal of the simulator front-end is connected to the output circuit, the output terminal of the simulator front-end is connected to the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to the counter. The readout circuit structure in this embodiment is prior art and will not be elaborated upon here.

[0056] The upper-layer chip and the lower-layer chip are interconnected using a copper pillar structure. The copper pillar interconnect structure used in this embodiment is preferred due to its high conductivity, good thermal conductivity, and low resistance.

[0057] like Figure 5 As shown, this invention proposes a method for implementing a triggered CMOS image sensor, comprising the following steps:

[0058] S1. After the previous exposure is completed, switch S7 is closed and switch S8 is opened. The previous photoelectric signal stored in FD is stored in photoelectric signal storage capacitor 12 through source follower tube S10 and switch S7.

[0059] S2. After the next exposure is completed, switch S8 is closed and switch S7 is opened. The next photoelectric signal is located at the second port 15 of the comparison unit, while the previous photoelectric signal is located at the first port 11 of the comparison unit and stored in the photoelectric signal storage capacitor 12.

[0060] S3, the first comparator 17, the second comparator 18 and the XOR gate 19 are reset before comparison, so the output values of the first comparator 17, the second comparator 18 and the XOR gate 19 are 0.

[0061] S4, when comparing, if the voltages of the first port 11 and the second port 15 of the comparison unit are basically the same, the first comparator 17 and the second comparator 18 do not flip, the first comparator 17 and the second comparator 18 maintain the reset state output of 0, and the output port 16 of the XOR gate is 0.

[0062] If the voltage of the first port 11 of the comparison unit is higher than the voltage of the second port 15 of the comparison unit, the first comparator 17 does not flip, the output is 0, the second comparator 18 flips, the output is 1, and the output port 16 of the XOR gate is 1.

[0063] If the voltage of the first port 11 of the comparison unit is lower than the voltage of the second port 15 of the comparison unit, the first comparator 17 flips, the output is 1, the second comparator 18 does not flip, the output is 0, and the output port 16 of the XOR gate is 0.

[0064] The present application converts the three output states of the first comparator 17 and the second comparator 18 into two states of high and low through the XOR gate 19, realizes the state reduction of the comparator result, satisfies the simplified control of the control logic, so when the high and low levels of the output port 16 of the XOR gate are used as the indication signal of the control logic, no quantization and processing are performed when the indication signal is 0, and the input is input to the readout circuit to perform quantization and processing when the indication signal is 1, and the position information is marked at the same time, the change information is substituted into the original image, high frame frequency, low power consumption event triggered imaging is realized.

[0065] The basic principles and main features of the present application and the advantages of the present application are shown and described above, and it is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0066] Furthermore, it should be understood that although the specification is described in terms of embodiments, each of which contains only one independent technical solution, the specification is described in this way only for the sake of clarity, and the skilled person should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that the skilled person can understand. The above is only to illustrate the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made on the basis of the technical solutions according to the technical idea of the present application falls within the protection scope of the claims of the present application.

Claims

1. A trigger type CMOS image sensor characterized by comprising: The application relates to a photoelectric signal output circuit and a photoelectric signal output method. The photoelectric diode is arranged on an upper layer chip, and the control circuit is arranged on a lower layer chip; the upper layer chip and the lower layer chip adopt a 3D stacking structure, and the upper layer chip and the lower layer chip are interconnected through bonding. The control circuit comprises an output circuit for outputting a photoelectric signal and a readout circuit for inputting the photoelectric signal; the output circuit comprises a reset tube S4, a transfer tube S5, an output tube S6, a source follower tube S10, a comparison unit, a switch S8 and a switch S7, and a photoelectric signal storage capacitor. The drain electrodes of the reset tube S4 and the source follower tube S10 are connected to VDD; the source electrode of the transfer tube S5 is connected to the photoelectric diode on the upper layer chip of the chip and then connected to the ground; the drain electrode of the transfer tube S5 and the source electrode of the reset tube S4 are connected to an FD point; the FD point is connected to the gate electrode of the source follower tube S10; the source electrode of the source follower tube S10 and the source electrode of the output tube S6 are connected to the switch S7 and the switch S8; and the drain electrode of the output tube S6 outputs the photoelectric signal. One end of the photoelectric signal storage capacitor is connected to the switch S7 and then connected to the ground, and the other end is connected to one port of the comparison unit; the other port of the comparison unit is connected to the switch S8. The comparison unit comprises a first comparator, a second comparator and an exclusive OR gate; the two input ends of the exclusive OR gate receive the photoelectric signal of the first comparator and the photoelectric signal of the second comparator respectively; the output end of the exclusive OR gate outputs an indication signal to a logic control; and the positive end of the first comparator is connected to the negative end of the second comparator for receiving a later photoelectric signal, and the negative end of the first comparator is connected to the positive end of the second comparator for receiving an earlier photoelectric signal.

2. The trigger type CMOS image sensor according to claim 1, wherein The port of the comparison unit connected to the switch S8 is used for receiving the later photoelectric signal, and the port connected to the switch S7 is used for receiving the earlier photoelectric signal.

3. The trigger type CMOS image sensor according to claim 1, wherein When the comparison is performed, if the earlier photoelectric signal is inconsistent with the later photoelectric signal, the exclusive OR gate outputs an indication signal to the logic control, and the readout circuit is controlled to convert the earlier photoelectric signal.

4. The trigger type CMOS image sensor according to claim 1, wherein When the comparison is performed, if the earlier photoelectric signal is consistent with the later photoelectric signal, the exclusive OR gate outputs an indication signal to the logic control, and the readout circuit is controlled not to convert the earlier photoelectric signal.

5. The trigger-type CMOS image sensor according to claim 1, wherein The readout circuit comprises an analog front end, an analog-digital converter and a counter; the input end of the analog front end is connected to the output circuit, the output end of the analog front end is connected to the analog-digital converter, and the output end of the analog-digital converter is connected to the counter.

6. The trigger-type CMOS image sensor according to claim 1, wherein The upper layer chip and the lower layer chip adopt a copper column interconnection structure.

7. The method according to any one of claims 1 to 6, wherein the method is implemented in a trigger-type CMOS image sensor. The application further discloses a photoelectric signal output method. S1: after the exposure of the earlier photoelectric signal is completed, the switch S7 is closed, the switch S8 is disconnected, the earlier photoelectric signal stored in the FD is stored in the photoelectric signal storage capacitor through the source follower tube S10 and the switch S7; S2: after the exposure of the later photoelectric signal is completed, the switch S8 is closed, the switch S7 is disconnected, the later photoelectric signal is located at one port of the comparison unit, and the earlier photoelectric signal stored in the photoelectric signal storage capacitor is located at the other port. S3, the comparison unit compares the received previous photoelectric signal and the subsequent electric signal, inputs the previous photoelectric signal to the negative end of the first comparator and the positive end of the second comparator, inputs the subsequent photoelectric signal to the positive end of the first comparator and the negative end of the second comparator, and compares whether the previous photoelectric signal and the subsequent electric signal are consistent; S4, if the previous photoelectric signal and the subsequent electric signal are consistent, the XOR gate outputs an indication signal to the logic control, controls the readout circuit to not convert the previous photoelectric signal and realizes high-speed image generation; if the previous photoelectric signal and the subsequent electric signal are inconsistent, the XOR gate outputs an indication signal to the logic control, controls the readout circuit to convert the previous photoelectric signal, and realizes high-speed image generation after conversion.

8. The method of claim 7, wherein the method further comprises: forming a first contact hole in the first insulating layer and the first metal layer; and forming a second contact hole in the second insulating layer and the second metal layer. The specific process of step S4 is: If the previous photoelectric signal is less than the subsequent photoelectric signal, the first comparator XOR gate outputs 1, the second comparator outputs 0, and the XOR gate outputs 1; If the previous photoelectric signal is greater than the subsequent photoelectric signal, the first comparator outputs 0, the second comparator outputs 1, and the XOR gate outputs 1; If the previous photoelectric signal is equal to the subsequent photoelectric signal, the first comparator outputs 0, the second comparator outputs 0, and the XOR gate outputs 0.

9. The method of claim 7, wherein the method further comprises: forming a first contact hole in the first layer of the first substrate; and forming a second contact hole in the second layer of the second substrate. The comparison unit needs to be reset before step S3.

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