Abnormality processing method and optical line terminal

Abstract

The invention provides an exception handling method and an optical line terminal, and relates to the technical field of communication. The method comprises the following steps: when an FPGA (Field Programmable Gate Array) in an optical line terminal identifies that a first ONU (Optical Network Unit) is abnormal according to the reporting condition of an abnormal alarm message reported by the first ONU, collecting state information of the first ONU; and sending an interrupt signal to a management CPU in the OLT, so that the management CPU obtains the state information of the first ONU from the FPGA, and processes the abnormality in the first ONU according to the state information of the first ONU. Therefore, the abnormality in the ONU can be handled in time.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an exception handling method and an optical line terminal. Background Art

[0002] At present, the method for processing abnormal alarms of optical network units (ONUs) in optical access networks is to send abnormal alarm messages to the management CPU in the optical line terminal (OLT) for processing. During the sending process, the abnormal alarm message needs to pass through the FPGA chip and the switching chip in the OLT before it can reach the management CPU.

[0003] Since there are many components to be passed through during the entire transmission process, the processing delay of abnormal alarms is naturally increased, which leads to poor timeliness in processing abnormal alarms of ONUs in optical access networks, which is contrary to the growing demand for high-speed and reliable optical access networks. In addition, since there are many components that need to be passed through when sending abnormal alarm messages from ONUs to OLT, the reliability of OLT board management of ONUs is reduced.

[0004] Therefore, how to handle the abnormality of ONU in a timely manner is one of the technical issues worth considering. Summary of the invention

[0005] In view of this, the present application provides an exception handling method and an optical line terminal, which are used to handle the exception of the ONU in a timely manner.

[0006] Specifically, the present application is implemented through the following technical solutions:

[0007] According to a first aspect of the present application, there is provided an exception handling method, which is applied to a field programmable gate array FPGA in an optical line terminal OLT, and the method comprises:

[0008] When an abnormality occurs in the first optical network unit (ONU) according to the reporting status of the abnormality alarm message reported by the first optical network unit (ONU), the status information of the first ONU is collected;

[0009] An interrupt signal is sent to a management CPU in the OLT, so that the management CPU obtains the status information of the first ONU from the FPGA, and processes an abnormality in the first ONU according to the status information of the first ONU.

[0010] According to a second aspect of the present application, there is provided an exception handling method, which is applied to a management CPU in an optical line terminal OLT, and the method comprises:

[0011] Receiving an interrupt signal sent by the FPGA in the OLT;

[0012] Acquire the status information of the first optical network unit ONU from the FPGA, wherein the status information of the first ONU is collected by the FPGA after identifying that the first ONU is abnormal according to the reporting status of the abnormal alarm message reported by the first ONU;

[0013] An abnormality in the first ONU is processed according to the status information of the first ONU.

[0014] According to a third aspect of the present application, an optical line terminal is provided, comprising an FPGA and a management CPU, wherein the FPGA is used to execute the exception handling method provided in the first aspect of the present application, and the management CPU is used to execute the exception handling method provided in the second aspect of the present application.

[0015] Beneficial effects of the embodiments of the present application:

[0016] In the abnormal alarm processing method and optical line terminal provided by the embodiment of the present application, the FPGA in the OLT collects the status information of the first ONU when it identifies that the first ONU is abnormal according to the reporting situation of the abnormal alarm message reported by the first ONU; sends an interrupt signal to the management CPU in the OLT, so that the management CPU obtains the status information of the first ONU from the FPGA, and processes the abnormality in the first ONU according to the status information of the first ONU. Therefore, the abnormal alarm message in the present application no longer needs to pass through the FPGA and the switching chip in sequence to finally reach the management CPU. It only needs to be notified directly by the FPGA to handle the abnormality when it identifies the existence of the abnormality based on the message reporting situation of the first ONU. Therefore, the method can handle the abnormal alarm of the ONU more quickly and accurately, and on this basis, improve the stability and reliability of the network where the ONU is located, and also improve the management efficiency of the ONU. Moreover, in the present application, the FPGA triggers the abnormal alarm of the ONU to the management CPU in an interrupt manner, and the interrupt manner belongs to a high-priority alarm. Therefore, the management CPU can respond to the interrupt signal in a timely manner, so as to handle the abnormality in the ONU in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of an exception handling method provided in an embodiment of the present application;

[0018] Figure 2a It is a schematic diagram of the internal logic of an FPGA provided in an embodiment of the present application;

[0019] Figure 2b This is a schematic diagram of an abnormal alarm reporting provided by an embodiment of the present application;

[0020] Figure 3 It is a logic diagram of interrupt triggering and interrupt mask triggering provided by an embodiment of the present application;

[0021] Figure 4 It is a logical schematic diagram of clearing status information provided by an embodiment of the present application;

[0022] Figure 5 It is a flowchart of another exception handling method provided in an embodiment of the present application;

[0023] Figure 6 It is a structural schematic diagram of an optical line terminal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0025] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more corresponding listed items.

[0026] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0027] The exception handling method provided by this application is described in detail below.

[0028] See also Figure 1 , Figure 1 This is a flowchart of an exception handling method provided by the present application. The method can be applied to a field programmable gate array FPGA in an optical line terminal OLT. When the FPGA implements the above method, it can include the following steps:

[0029] Step 101: When it is identified that an abnormality occurs in the first ONU according to the reporting status of the abnormality alarm message reported by the first ONU, the status information of the first ONU is collected.

[0030] In this step, the optical line terminal can manage multiple ONUs, and accordingly, the first ONU can be any ONU among the multiple ONUs. The logic layer 1 of the FPGA is provided with multiple OLT ports, and each OLT port is respectively connected to the downstream ODN (optical distribution network) and ONU, as shown in FIG2 . As can be seen from FIG2 , the FPGA also includes a logic layer 2 for abnormal analysis and caching, which will be described in detail later. The logic layer 3 included in the FPGA includes the first register, the second register and the third register described later, which are used to assist the management CPU in handling the abnormality of the ONU.

[0031] Specifically, the FPGA can exchange messages with the corresponding ONUs through each OLT port to detect and analyze the status of each ONU, and then identify whether each ONU has an abnormality based on the acquired status of each ONU, and collect the status information of the ONU when any ONU identifies an abnormality. Optionally, the status information may include, but is not limited to, an ONU identifier and the type of abnormality that occurred.

[0032] Optionally, this embodiment proposes that the OLT can identify whether an abnormality has occurred in the first ONU based on the reporting status of the abnormal alarm message reported by the first ONU in the following method: if the abnormal alarm message sent by the first ONU is received at the detection time point, or if any message reported by the first ONU is not received at the detection time point, it can be confirmed that the first ONU has an abnormality this time; the number of statistical abnormalities is updated, and when the number of abnormalities reaches the set number, it is identified that an abnormality has occurred in the first ONU, otherwise, it is identified that no abnormality has occurred in the first ONU, and wait for the next identification of whether it is abnormal at the next detection time point.

[0033] Specifically, the above detection time point can be obtained by negotiation between the OLT and each ONU, and the detection time points corresponding to different ONUs can be the same or different, which can be determined according to actual conditions. For ease of understanding, taking the first ONU as an example for explanation, it can be agreed with the first ONU that detection is performed every 1s. If the current time point 10:10 is the detection time point, the next detection time point is 10:12. If the current time point 10:10 does not receive any message reported by the first ONU, or the received message is the above abnormal alarm message, the number of abnormal times of the first ONU can be accumulated 1 time, if the next detection time point 10:12 still does not receive any message from the first ONU, the above abnormal number is accumulated 2 times, and so on. If the number of times is set to 4 times, when the above abnormal number is greater than 4 times, the OLT can identify that the first ONU is abnormal, so that the OLT can collect the status information of the first ONU.

[0034] Step 102: Send an interrupt signal to a management CPU in the OLT, so that the management CPU obtains the status information of the first ONU from the FPGA, and processes an abnormality in the first ONU according to the status information of the first ONU.

[0035] In this step, in order to handle the exception occurring in the first ONU in time, this embodiment proposes to use an interruption method, that is, the FPGA sends an interruption signal to the management CPU in the OLT. Since the use of an interruption method to trigger the exception handling belongs to a higher priority processing method, after the management CPU detects the interruption signal, it can suspend the work currently being processed, and then handle the exception occurring in the first ONU. That is, the management CPU can obtain the state information of the first ONU collected in advance by the FPGA from the FPGA, and then handle the exception occurring in the first ONU based on the state information, thereby achieving the purpose of timely handling the exception occurring in the first ONU.

[0036] In the implementation of the exception handling method provided by the present application, the FPGA in the OLT collects the status information of the first ONU when it identifies that the first ONU has an abnormality according to the reporting situation of the abnormal alarm message reported by the first ONU; sends an interrupt signal to the management CPU in the OLT, so that the management CPU obtains the status information of the first ONU from the FPGA, and processes the abnormality in the first ONU according to the status information of the first ONU. Therefore, the abnormal alarm message in the present application no longer needs to pass through the FPGA and the switching chip in sequence to finally reach the management CPU. It only needs to be notified directly by the FPGA to handle the abnormality when it identifies the existence of an abnormality based on the message reporting situation of the first ONU. Therefore, the method can handle the abnormal alarm of the ONU more quickly and accurately, and on this basis, improve the stability and reliability of the network where the ONU is located, and also improve the management efficiency of the ONU. Moreover, in the present application, the FPGA uses an interrupt method to trigger the abnormal alarm of the ONU to the management CPU, and the interrupt method belongs to a high-priority alarm. Therefore, the management CPU can respond to the interrupt signal in time, so as to handle the abnormality in the ONU in time.

[0037] Optionally, the above-mentioned FPGA includes a first register, also refer to Figure 2; after collecting the status information of the first ONU, this embodiment may also include the following process: writing the status information of the first ONU into the first register, so that the management CPU reads the status information of the first ONU from the first register.

[0038] Specifically, in order to conveniently store the collected state information of the first ONU and facilitate the management CPU to obtain the state information of the first ONU to perform abnormal processing of the first ONU, it is proposed to configure the above-mentioned first register in the FPGA.

[0039] On this basis, under normal circumstances, each ONU managed by the OLT will not often have abnormalities, so when the first ONU is identified to be abnormal, the state information of the first ONU can be directly written into the first register. After the state information of the first ONU is written into the first register, step 102 can be executed to trigger an interrupt signal to the management CPU, so that after the management CPU detects the interrupt signal, it reads the state information of the first ONU from the first register.

[0040] In addition, in actual applications, when the FPGA reports the alarm interruption of the first ONU, other ONUs may have abnormalities, but at this time the management CPU may not have time to respond to the alarm interruptions of other ONUs. In view of this, this embodiment proposes to set a cache in the above-mentioned FPGA, and can also refer to Figure 2. On this basis, the step of writing the status information of the first ONU into the first register can be performed according to the following process: writing the status information of the first ONU into the cache; when the cache time of the cache reaches the set time, writing the status information currently recorded in the cache into the first register, wherein the above-mentioned set time is greater than the time required for the management CPU to process the ONU abnormality; clearing the cache.

[0041] Specifically, the FPGA may obtain the status information of multiple ONUs at the same time point, or obtain the status information of multiple ONUs at adjacent time points. Therefore, in order to facilitate the storage of the status information of these ONUs, the first register may be set to be composed of multiple register groups, each register group storing the status information of one ONU. In this way, it is convenient to store the status information of multiple ONUs collected at adjacent time points.

[0042] Furthermore, in order to avoid the management CPU from triggering an interrupt again while currently responding to the last abnormal alarm of the ONU, thereby affecting the processing of the last abnormal alarm of the ONU, this embodiment proposes that the collected status information of the first ONU is first written into the above-mentioned cache; at the same time, the FPGA will time the cache, that is, after executing the last read-out of the status information from the cache, the cache is re-timed, and the timing time is the above-mentioned cache time. Therefore, the cache time can be judged. Since the set time is the time required for the management CPU to process the ONU abnormality, when the cache time reaches the set time, it indicates that the management CPU has processed the abnormal alarm of the ONU. At this time, the status information of each ONU currently recorded can be read from the cache and then written into the first register. After the writing is successful, the above-mentioned cache is cleared and the timing process is performed again.

[0043] It should be noted that the specific value of the above-mentioned set time can be adjusted dynamically. For example, the time required for the management CPU to process the exception of a single ONU can be estimated. Then, each time the status information currently recorded in the cache is read out, the status information of the number of ONUs currently recorded can be counted. Based on the statistical number and the time required for the management CPU to process the exception of a single ONU, the above-mentioned set time can be calculated for determining the next cache time.

[0044] It is worth noting that in order to ensure the timeliness of ONU abnormal alarm processing, the above-mentioned set time also needs to have a time upper limit, that is, the cache time of the status information recorded in the cache cannot be too long. Under normal circumstances, the time upper limit is generally about 1s. From the perspective of the time upper limit, the management CPU handles abnormal alarms very quickly.

[0045] Further, step 102 may be performed according to the following process: when the status information of the current record in the cache is written into the first register, an interrupt signal is sent to the management CPU in the OLT.

[0046] Specifically, when the current recorded status information read from the cache is written to the first register, an interrupt signal can be triggered so that the management CPU reads the recorded status information from the first register to perform exception processing in the ONU. Specifically, since the status information includes the ONU identifier, the management CPU can perform exception processing corresponding to the exception type and other information included in the status information on the corresponding ONU according to the ONU identifier in each status information.

[0047] Optionally, in this embodiment, the FPGA may perform the step of sending an interrupt signal to the management CPU in the OLT according to the following process: the FPGA triggers the interrupt signal by pulling down the CPU-GPIO pin connected to the management CPU to report the ONU abnormality. For details, please refer to Figure 3 shown.

[0048] Optionally, this embodiment may further provide the following process: when a clear instruction sent by the management CPU is received, the state information of the target ONU is cleared from the first register, and the target ONU includes the first ONU.

[0049] Specifically, in actual applications, when the management CPU performs abnormal processing of the ONU, it can adopt a synchronous method or an asynchronous method. When the synchronous method is adopted, the status information is read from the first register and then the abnormal processing in the ONU is performed based on the status information; after the processing is completed, a clear instruction is sent to the first register. Based on this, when the management CPU completes the abnormal processing of a certain ONU, the status information of the ONU does not need to be stored in the above-mentioned first register. Therefore, when it is confirmed that the management CPU has completed the abnormal processing of the target ONU, the above-mentioned clear instruction is sent. In this way, when the FPGA receives the clear instruction, it can delete the status information of the target ONU from the first register. Even if the synchronous method is adopted, the response speed is improved by adopting the interrupt method for abnormal alarm processing, and the abnormal alarm message sent by the ONU does not need to be sent to the management CPU, and the timely processing of abnormal alarm can be realized while saving the sending time.

[0050] Optionally, the above exception handling completion may include exception handling success.

[0051] It should be noted that when the first register includes status information of multiple ONUs, the management CPU can notify the FPGA after processing the abnormalities of each ONU indicated by the status information in the first register. In this way, the FPGA can directly clear the first register.

[0052] It should be noted that the above-mentioned exception handling completion may also include exception handling failure (failed to handle successfully). Specifically, when the management CPU handles the exception of a certain ONU, there may be a situation where the exception cannot be handled successfully. In this case, since the state information of the ONU cannot be stored in the first register all the time, at this time, this embodiment proposes that when the management CPU has processed all ONUs included in the first register (including the situation where the exception handling of a certain ONU is unsuccessful), it sends a clear instruction to the FPGA to instruct the FPGA to clear the first register.

[0053] In addition, when the management CPU uses an asynchronous method to perform an exception process of the ONU, for example, the management CPU includes multiple threads, namely a write thread and a management thread, and the write thread reads the status information from the first register, and then the management thread performs an exception process of the ONU based on the status information read by the write thread. Based on this, when the processing method of the write thread and the management thread is asynchronous, the write thread can send a clear instruction to the FPGA after reading the status information from the first register. In this way, when the FPGA receives the clear instruction, it can delete the status information of the target ONU from the first register.

[0054] Accordingly, when the first register includes status information of multiple ONUs, after the above-mentioned writing process reads the status information of the above-mentioned multiple ONUs from the first register, a clearing instruction can be sent to the FPGA. In this way, when the FPGA receives the clearing instruction, the status information of the target ONU can be deleted from the first register. In this way, the FPGA can write the status information collected subsequently into the first register to trigger an interrupt signal, so that the management CPU can respond to the abnormal alarm of the ONU corresponding to the newly written status information in a timely manner.

[0055] Furthermore, the above-mentioned FPGA also includes a second register, please refer to Figure 2; according to the following method, it is determined that the clear instruction sent by the management CPU is received: when it is detected that the management CPU writes a set value to the second register, it is determined that the clear instruction sent by the management CPU is received.

[0056] Specifically, after the management process in the management CPU processes the ONU, or after the write thread in the management CPU reads the status information of all ONUs in the first register, the management process or the write process can write a set value to the second register in the FPGA, refer to Figure 4 As shown, for example, the setting value written by the management CPU is 1, so after the FPGA detects that the second register is written with the above value, it can clear the first register.

[0057] After the FPGA reads the set value from the second register, the second register will be restored to an initial state to facilitate the management CPU to perform the next write operation.

[0058] Optionally, in this embodiment, the FPGA also includes a third register, also refer to Figure 2, the third register is used to store the ONU identifier of the second ONU, and the second ONU is the ONU for which the management CPU refuses to perform exception processing; on this basis, step 102 can be performed according to the following process: read the ONU identifier of the second ONU from the third register; when the ONU identifier of the first ONU is inconsistent with the ONU identifier of the second ONU, send an interrupt signal to the management CPU in the OLT.

[0059] Specifically, in actual applications, there may be a situation where an exception of a certain ONU cannot be processed or a certain exception frequently occurs in a certain ONU. Even if the FPGA reports such exceptions to the management CPU for exception processing, it may not achieve a good processing effect. Based on this, this embodiment proposes that the management CPU can send the ONU identifier of the ONU with such an exception (for the convenience of description, it is recorded as the second ONU) to the FPGA to inform the FPGA that the subsequent management CPU will refuse to respond to the exception of the second ONU. In this way, before reporting the ONU exception, the FPGA first identifies the ONU. When it is identified that the ONU identifier of the ONU with the exception is consistent with the ONU identifier of the second ONU, the state information of the ONU will not be written into the cache or the first register, so that the interrupt signal for the ONU will not be initiated.

[0060] In order to realize the above process, the third register is configured in the FPGA. In this way, after the management CPU screens out the second ONU, it can write the ONU ID of the second ONU into the third register. Please refer to Figure 3As shown, interrupt shielding processing is performed. On this basis, when the FPGA recognizes that an abnormality occurs in the first ONU, it can read the identifier of the second ONU from the third register, and then determine whether the ONU identifier of the first ONU is consistent with the ONU identifier of the second ONU. When they are consistent, the process ends, that is, the interrupt for the second ONU is shielded; when they are inconsistent, the step of sending an interrupt signal to the management CPU is executed. In this way, the waste of the abnormality processing resources of the management CPU is avoided.

[0061] In addition, the management CPU can also output the abnormal processing status of the second ONU to facilitate operation and maintenance personnel to check and handle the abnormality.

[0062] Therefore, in this application, after the ONU abnormal alarm is sent to the FPGA, the FPGA triggers abnormal processing to the management CPU by interruption. This method can not only monitor the status of the ONU in real time, but also reduce the time lag of abnormal detection, achieve the purpose of rapid response and abnormal alarm of abnormal ONU, and improve stability. In addition, the abnormal alarm message of the ONU only needs to be reported to the FPGA, and does not need to be sent to the management CPU. The FPGA reports the abnormality to the management CPU by interruption. In this way, not only the number of devices that the abnormal alarm message has to pass through is reduced, but also the purpose of abnormal alarm is achieved, and the reliability of the entire PON network is improved.

[0063] In addition, after the FPGA reports an interrupt to the management CPU, the management CPU will interrupt some operations on the FPGA, for example, operations such as configuration information sent to the ONU through the FPGA; this is conducive to protecting the on-site environment of the FPGA. For example, the ONU abnormality type is that the OLT fails to configure the ONU, but the configuration process is that the management CPU first writes the configuration information to the internal register of the FPGA to store it inside the FPGA, and then sends it to the ONU. Therefore, after the OLT fails to send the configuration, the management CPU will pause and then send the configuration operation, which is conducive to protecting the on-site environment of the FPGA. In addition, since the status information of the above-mentioned configuration failure has been stored in the first register, it is also convenient for the management CPU to read the status information of the configuration that failed to be sent from the first register to perform exception processing.

[0064] Based on the same inventive concept, an exception handling method is also provided, referring to Figure 5 The flowchart of the exception handling method shown in FIG. 1 is a flowchart of the exception handling method shown in FIG. 1 . The method can be applied to a management CPU in an optical line terminal. When the management CPU implements the method, the steps shown in FIG. 1 may include:

[0065] Step 501: Receive an interrupt signal sent by the FPGA in the OLT.

[0066] In this step, when the FPGA recognizes that an abnormality occurs in the ONU, an interrupt signal can be sent to the management CPU in the OLT in an interrupt manner. For details, please refer to the relevant description on the FPGA side, which will not be described in detail here.

[0067] Step 502: Acquire status information of a first optical network unit ONU from the FPGA, wherein the status information of the first ONU is collected by the FPGA after identifying that an abnormality occurs in the first ONU based on a reporting condition of an abnormality alarm message reported by the first ONU.

[0068] In this step, the FPGA includes a first register, and the first register is used to store the state information of the ONU collected by the FPGA, so the management CPU can obtain the state information of the first ONU from the first register. In addition, the relevant description of the FPGA collecting the state information of the first ONU can refer to the relevant embodiments of the FPGA side, and this embodiment does not limit this.

[0069] Step 503: Process the abnormality in the first ONU according to the status information of the first ONU.

[0070] In this step, after acquiring the status information of the first ONU, the management CPU can process the exception in the first ONU according to the exception type included in the status information of the first ONU. Optionally, the above-mentioned status information can also include environmental information of the first ONU. When performing the exception processing, the management CPU can also consider the environmental information of the first ONU and select a suitable method to process the exception occurring in the first ONU.

[0071] In the implementation of the above exception handling method, the management CPU in the optical line terminal receives the interrupt signal sent by the FPGA in the OLT; obtains the status information of the first optical network unit ONU from the FPGA, wherein the status information of the first ONU is collected by the FPGA after identifying the first ONU as abnormal according to the reporting situation of the abnormal alarm message reported by the first ONU; and handles the abnormality in the first ONU according to the status information of the first ONU. Since the above abnormality is notified to the management CPU by the FPGA through an interrupt, it can ensure that the management CPU handles the abnormality in the first ONU in a timely manner.

[0072] Optionally, in this embodiment, after executing step 502, the following process may also be executed: generating an abnormal alarm event of the first ONU according to the status information of the first ONU; and writing the abnormal alarm event of the first ONU into an abnormal alarm queue.

[0073] Further, step 503 may be performed according to the following process: reading the abnormal alarm event of the first ONU from the abnormal alarm queue through the management process in the management CPU, and processing the abnormality in the first ONU according to the state information of the first ONU included in the abnormal alarm event.

[0074] In this step, after the FPGA triggers the interrupt signal, the management CPU will generate an interrupt processing task, and the abnormal alarm processing of the ONU can be asynchronously performed. For example, the write thread in the management CPU generates the abnormal alarm event of the ONU from the collected state information of each ONU, and writes it into the abnormal alarm queue. When performing the abnormal processing, it is implemented by the management process in the management CPU, that is, the management process reads the abnormal alarm event written earlier from the abnormal alarm queue according to the first-in-first-out principle, and then processes the abnormality in the corresponding ONU based on the state information included in the abnormal alarm event. This not only realizes the timely response to the interrupt triggered by the FPGA, but also ensures the timely processing of the abnormality of the ONU.

[0075] In addition, there may be a situation where the FPGA continuously triggers abnormal interrupt signals of multiple ONUs. After the management CPU continuously receives multiple interrupt signals, it needs to perform exception processing in sequence. Therefore, in order to facilitate exception processing, this embodiment proposes to obtain the corresponding ONU status information based on multiple interrupt signals, generate respective abnormal alarm events, and then write the abnormal alarm events into the abnormal alarm queue in sequence. Since the management process is dedicated to the abnormal processing of ONUs, the management process can read the abnormal alarm events from the abnormal alarm queue and perform corresponding abnormal processing.

[0076] Optionally, in this embodiment, step 502 can be performed according to the following process: when the status information stored in the first register is read from the cache and written after the FPGA writes the status information of the first ONU into the cache in the FPGA and determines that the cache time of the cache reaches the set time, the currently stored status information is obtained from the first register in the FPGA, and the read status information includes the status information of the first ONU.

[0077] Specifically, in order to avoid the situation where, after the FPGA triggers an interrupt for a certain ONU, an interrupt is triggered again after the first ONU is identified to be abnormal at an adjacent time point, affecting the abnormal processing of the ONU by the management CPU, this embodiment proposes that the state information of the first ONU is written into the cache, and when the cache time set for the cache reaches the set time, the state information of each ONU in the cache is written into the first register, and then an interrupt is triggered based on at least one ONU (including the first ONU). Moreover, since the above-mentioned set time is not less than the time when the management CPU handles the last abnormality, the management CPU can obtain the state information of the above-mentioned at least one ONU from the first register after detecting the interrupt signal.

[0078] On this basis, step 503 may be performed according to the following process: when a plurality of status information is read, the abnormalities in the ONU indicated by each of the plurality of status information read are processed respectively.

[0079] On this basis, when the CPU reads the status information of multiple ONUs from the first register, an abnormal alarm event can be generated based on the status information of each ONU, and then written into the abnormal alarm queue respectively. In this way, the management process will perform abnormal processing on the ONUs corresponding to the abnormal alarm events read out from the abnormal alarm queue in turn.

[0080] Optionally, based on the above embodiment, the present embodiment further provides the following process: after the status information is read from the first register, a clear instruction is sent to the FPGA to instruct the FPGA to clear the status information of the target ONU from the first register.

[0081] Specifically, in one embodiment, in order to further improve the response speed of abnormal alarms, the management CPU can trigger a clear indication to the FPGA after reading the status information of each ONU recorded in the first register. In this way, after the FPGA clears the status information in the first register, it can write the status information collected in the cache into the first register, so that the management CPU can respond to the abnormal alarm of the ONU corresponding to the newly written status information in a timely manner.

[0082] In another embodiment, the management CPU can send a clear notification after the exception handling is completed. Specifically, the above-mentioned exception handling completion includes successful exception handling and unsuccessful exception handling. On this basis, when the management process handles the exception of a certain ONU, if the handling is successful, then there is no need to store the state information of the ONU in the first register; in addition, the management CPU may not be able to handle the situation successfully. For this situation, the state information of the ONU cannot be stored in the first register all the time. Based on this, this embodiment proposes that the management CPU can send a clear instruction to the FPGA when it has processed all ONUs included in the first register (target ONUs, the target ONUs include the situation where the exception handling of a certain ONU is unsuccessful).

[0083] Of course, when the first register includes status information of multiple ONUs, the management CPU can send a clear instruction to the FPGA after processing all ONUs included in the first register (including the case where an ONU exception is not successfully processed) to instruct the FPGA to clear the first register.

[0084] On this basis, the step of sending a clear instruction to the FPGA can be performed according to the following process: by writing a set value to the second register in the FPGA to trigger sending the clear instruction to the FPGA. The set value is used to instruct the FPGA to clear the first register. Figure 4 The specific value of the setting value can be determined according to actual conditions, and this embodiment does not limit this.

[0085] Specifically, after the write process of the management CPU reads the recorded status information of each ONU from the first register, the clear notification can be triggered by writing the above-mentioned set value into the second register.

[0086] After the management process in the management CPU executes the abnormalities of all ONUs recorded in the first register, the management process can write the above set value to the second register to trigger the clear notification.

[0087] Optionally, the present embodiment may also provide the following process: if a setting exception is identified in the second ONU based on the status information of the second ONU, the number of exception processing times previously counted for the setting exception occurring in the second ONU is updated; when the updated number of exception processing times reaches the set number, the ONU identifier of the second ONU is written to the third register in the FPGA to indicate a subsequent refusal to respond to the abnormal alarm of the second ONU.

[0088] Specifically, in actual applications, there may be a situation where the management CPU handles the setting exceptions occurring in the second ONU (any one of the multiple ONUs managed by the optical line terminal) a large number of times, that is, after handling the above-mentioned setting exception in the second ONU this time, it is still subsequently received that the above-mentioned setting exception has occurred in the second ONU. For such a situation, the management CPU may propose to subsequently refuse to respond to the above-mentioned setting exception occurring in the second ONU. Based on this, the management CPU proposes that after obtaining the status information of the second ONU, the exception occurring in the second ONU can be identified. When the exception occurring is the above-mentioned setting exception, the setting exception is first processed, and then the number of exception processing times of the above-mentioned setting exception occurring that has been pre-counted for the second ONU is updated; when the updated number of exception processing times reaches the set number, the ONU identifier of the second ONU can be written to the third register included in the FPGA to inform the FPGA to subsequently refuse to respond to the exception alarm of the second ONU, that is, to perform interrupt shielding processing on the second ONU, refer to Figure 3 As shown, this saves the exception handling resources of the management CPU, so as to facilitate exception handling for other ONUs.

[0089] It should be noted that the management CPU may use PCIE to interact with the first register, the second register, and the third register.

[0090] In addition, the exception processing performed by the management CPU may include, but is not limited to, management operations such as ONU offline or re-registration.

[0091] Based on the same inventive concept, the present application also provides an optical line terminal, including an FPGA and a management CPU, referring to Figure 6 The FPGA is used to execute the exception handling method corresponding to any one of the embodiments described above on the FPGA side, and the management CPU is used to execute the exception handling method corresponding to any one of the embodiments described above on the management CPU side.

[0092] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0093] The implementation process of the functions and effects of each unit / module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0094] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can refer to the partial description of the method embodiments. The device embodiments described above are merely schematic, wherein the units / modules described as separate components may or may not be physically separated, and the components displayed as units / modules may or may not be physical units / modules, that is, they may be located in one place, or they may be distributed on multiple network units / modules. Some or all of the units / modules may be selected according to actual needs to achieve the purpose of the present application. A person of ordinary skill in the art can understand and implement it without creative work.

[0095] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An exception handling method, characterized in that: The method is applied to a field programmable gate array FPGA in an optical line terminal OLT, comprising: When an abnormality occurs in the first optical network unit (ONU) according to the reporting status of the abnormality alarm message reported by the first optical network unit (ONU), the status information of the first ONU is collected; An interrupt signal is sent to a management CPU in the OLT, so that the management CPU obtains the status information of the first ONU from the FPGA, and processes an abnormality in the first ONU according to the status information of the first ONU.

2. The method according to claim 1, characterized in that The FPGA includes a first register; after collecting the status information of the first ONU, the method further includes: The status information of the first ONU is written into the first register, so that the management CPU reads the status information of the first ONU from the first register.

3. The method according to claim 2, characterized in that The FPGA also includes a cache; Writing the status information of the first ONU into the first register includes: Writing the status information of the first ONU into the cache; When the cache time of the cache reaches a set time, the status information of the current record in the cache is written into the first register, and the set time is greater than the time required by the management CPU to process the ONU abnormality; clearing the cache; Sending an interrupt signal to a management CPU in the OLT includes: When the status information currently recorded in the cache is written into the first register, an interrupt signal is sent to the management CPU in the OLT.

4. The method according to claim 2 or 3, characterized in that: The method further comprises: When a clear instruction sent by the management CPU is received, the status information of the target ONU is cleared from the first register, and the target ONU includes the first ONU.

5. The method according to claim 4, characterized in that The FPGA also includes a second register; Determine that a clear instruction sent by the management CPU is received by the following method: When it is detected that the management CPU writes a set value to the second register, it is determined that a clear instruction sent by the management CPU is received.

6. The method according to claim 1, characterized in that The FPGA also includes a third register, the third register being used to store an ONU identifier of a second ONU, where the second ONU is an ONU for which the management CPU refuses to perform exception processing; Sending an interrupt signal to a management CPU in the OLT includes: Read the ONU identification of the second ONU from the third register; When the ONU identifier of the first ONU is inconsistent with the ONU identifier of the second ONU, an interrupt signal is sent to the management CPU in the OLT.

7. An exception handling method, characterized in that: Applied to a management CPU in an optical line terminal OLT, the method comprises: Receiving an interrupt signal sent by the FPGA in the OLT; Acquire the status information of the first optical network unit ONU from the FPGA, wherein the status information of the first ONU is collected by the FPGA after identifying that the first ONU is abnormal according to the reporting status of the abnormal alarm message reported by the first ONU; An abnormality in the first ONU is processed according to the status information of the first ONU.

8. The method according to claim 7, characterized in that After acquiring the status information of the first ONU from the FPGA, the method further includes: Generate an abnormal alarm event of the first ONU according to the status information of the first ONU; Writing the abnormal alarm event of the first ONU into the abnormal alarm queue; Processing an exception in the first ONU according to the status information of the first ONU includes: The abnormal alarm event of the first ONU is read from the abnormal alarm queue by the management process in the management CPU, and the abnormality in the first ONU is processed according to the state information of the first ONU included in the abnormal alarm event.

9. The method according to claim 7, characterized in that: Acquiring the status information of the first ONU from the FPGA includes: When the status information stored in the first register is read out and written from the cache after the FPGA writes the status information of the first ONU into the cache in the FPGA and determines that the cache time of the cache reaches the set time, the currently stored status information is obtained from the first register in the FPGA, and the read status information includes the status information of the first ONU; Processing an exception in the first ONU according to the status information of the first ONU includes: When a plurality of status information are read, the abnormalities in the ONU indicated by the plurality of status information are processed respectively.

10. The method according to claim 9, characterized in that Also includes: After the status information is read from the first register, a clear instruction is sent to the FPGA to instruct the FPGA to clear the status information of the target ONU from the first register.

11. The method according to claim 10, characterized in that Sending a clear indication to the FPGA includes: The sending of the clear indication to the FPGA is triggered by writing a set value into the second register in the FPGA.

12. The method according to claim 7, characterized in that Also includes: If it is identified according to the status information of the second ONU that a setting abnormality occurs in the second ONU, the number of abnormal processing counts previously performed for the setting abnormality occurring in the second ONU is updated; When the updated number of exception processing times reaches the set number, the ONU identifier of the second ONU is written into the third register in the FPGA to indicate a subsequent refusal to respond to the exception alarm of the second ONU.

13. An optical line terminal, characterized in that: The system comprises an FPGA and a management CPU, wherein the FPGA is used to execute the exception handling method described in any one of claims 1 to 6, and the management CPU is used to execute the exception handling method described in any one of claims 7 to 12.

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