Display substrate and display device

Abstract

The display substrate comprises a first area and a second area, and the first area is located on the side, close to the edge of the display substrate, of the second area; the second region comprises a plurality of first transistors, and the first transistors are electrically connected with the first electrode; the display substrate comprises a substrate, a lead-out wire located in a first area, a conductive pad located between a film layer where the lead-out wire is located and the substrate, and a first insulating layer located between a film layer where the conductive pad is located and a film layer where the lead-out wire is located. In the direction perpendicular to the plane where the display substrate is located, the conductive pads are overlapped with the lead-out wires, and first insulating layers are arranged between the conductive pads and the lead-out wires. Due to the existence of the conductive pad, the thinned part of the first insulating layer at the side wall position of the conductive pad and the position near the side wall can be used as a weak part of electrostatic discharge on the lead-out wire. When static electricity forms a path in the lead-out wire, the static electricity easily breaks down a weak part in the first insulating layer, so that the static electricity is released.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Electrostatic protection is one of the main research topics in the display field. Static electricity may damage the components in the display screen and affect the display performance of the display device. With the development of display technology, narrow-border display and ultra-narrow-border display have gradually become mainstream displays. However, in narrow-border display substrates and ultra-narrow-border display substrates, static electricity is more likely to enter the interior of the display substrate and damage the components. As the borders of display substrates become narrower, existing electrostatic protection structures face challenges.

[0003] Therefore, how to obtain a reliable electrostatic protection structure on a display substrate is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display substrate and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display substrate, the display substrate comprising a first area and a second area, the first area being located on a side of the second area close to an edge of the display substrate; the second area comprising a plurality of first transistors, the first transistors being electrically connected to a first electrode; the display substrate comprising a substrate, a lead-out wire located in the first area, a conductive pad located between a film layer where the lead-out wire is located and the substrate, and a first insulating layer located between a film layer where the conductive pad is located and a film layer where the lead-out wire is located; along a direction perpendicular to a plane where the display substrate is located, the conductive pad overlaps with the lead-out wire, and a first insulating layer is included between the conductive pad and the lead-out wire.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising a display substrate provided in the first aspect.

[0007] In the embodiment of the present application, due to the presence of the conductive pad, the places where the thickness of the first insulating layer is reduced at the side wall of the conductive pad and the position near the side wall can be used as sacrificial points for the static discharge on the lead wire, which are called weak points. At least part of the weak points of the first insulating layer are located between the conductive pad and the lead wire. When static electricity exists at the edge of the display substrate, the static electricity can enter the lead wire. Since there is a weak point in the part of the first insulating layer located between the lead wire and the conductive pad, the static electricity can easily break through the weak point in the first insulating layer in the process of forming a path in the lead wire, thereby achieving the release of static electricity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 A schematic diagram of a display substrate provided in an embodiment of the present application;

[0010] Figure 2 A schematic diagram of another display substrate provided in an embodiment of the present application;

[0011] Figure 3 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0012] Figure 4 for Figure 3 A schematic cross-sectional view along the A1-A2 direction;

[0013] Figure 5 A schematic diagram of a display substrate provided in an embodiment of the present application;

[0014] Figure 6 A schematic diagram of another display substrate provided in an embodiment of the present application;

[0015] Figure 7 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0016] Figure 8 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0017] Fig. 9 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0018] Fig.10 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0019] Fig.11 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0020] Fig.12 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application;

[0021] Fig.13 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0022] Fig.14 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0023] Fig.15 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0024] Fig.16 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0025] Fig.17 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0026] Fig.18 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0027] Fig.19 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0028] Fig. 20 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0029] Fig.21 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0030] Fig. 22 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0031] Fig.23 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0032] Fig.24 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0033] Fig.25 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0034] Fig.26 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0035] Fig. 27 for Figure 3 A schematic cross-sectional view along the B1-B2 direction;

[0036] Fig.28 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0037] Fig.29 for Fig.28 A schematic cross-sectional view along the C1-C2 direction;

[0038] Fig.30 for Fig.28 A schematic cross-sectional view along the C1-C2 direction;

[0039] Fig.31 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0040] Fig.32 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0041] Fig.33 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0042] Fig.34 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0043] Fig.35 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0044] Fig.36 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0045] Fig.37 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0046] Fig.38 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0047] Fig.39 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0048] Fig.40 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0049] Fig.41 for Figure 1and Figure 2 A detailed schematic diagram of a local area in FIG.

[0050] Fig.42 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0051] Fig.43 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application;

[0052] Fig.44 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0053] Fig.45 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0054] Fig.46 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0055] Fig.47 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0056] Fig.48 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0057] Fig.49 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0058] Fig.50 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in FIG.

[0059] Fig.51 A schematic diagram of an overlap between a lead wire and a conductive pad in a display substrate provided in an embodiment of the present application;

[0060] Fig.52 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0061] Fig.53 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0062] Fig.54 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0063] Fig.55 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0064] Fig.56 for Fig.54 A schematic cross-sectional view along the D1-D2 direction;

[0065] Fig.57 for Fig.55 A schematic cross-sectional view along the F1-F2 direction;

[0066] Fig.58 for Fig.54 Another cross-sectional schematic diagram along the D1-D2 direction;

[0067] Fig.59 for Fig.55 Another cross-sectional schematic diagram along the F1-F2 direction;

[0068] Fig.60 for Fig.54 Another cross-sectional schematic diagram along the D1-D2 direction;

[0069] Fig.61 for Fig.55 Another cross-sectional schematic diagram along the F1-F2 direction;

[0070] Fig.62 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0071] Fig.63 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0072] Fig.64 A partial schematic diagram of a display substrate provided in an embodiment of the present application;

[0073] Fig.65 A schematic diagram of a display device provided in an embodiment of the present application;

[0074] Fig.66 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0076] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0077] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0078] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0079] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0080] It should be understood that although the terms first, second, etc. may be used to describe regions, directions, lead wires, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish regions, directions, lead wires, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first region may also be referred to as the second region, and similarly, the second region may also be referred to as the first region. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0081] The display substrate provided in the embodiment of the present application is applied to a display device and can be used as a substrate for controlling pixel light emission in the display device.

[0082] The display substrate may include light-emitting elements in the pixels. For example, the display substrate may be a display substrate including an organic light-emitting diode (OLED). The display substrate may also be combined with the light-emitting elements in the pixels by plugging, welding, bonding, etc. For example, the display substrate may be combined with light-emitting elements such as sub-millimeter light-emitting diodes (Mini-LED) and micro light-emitting diodes (Micro-LED). In addition, the display substrate may also be applied to display devices such as liquid crystal displays (LCDs) and electrophoretic displays (EPDs) that realize display by regulating the optical path of light. In this case, the display substrate may realize the regulation of the optical paths of light in different pixels. This application does not limit this.

[0083] In order to achieve the regulation of pixel light emission in the display device, the display substrate includes a pixel circuit or a pixel control transistor, which is electrically connected to the first electrode and outputs a signal for controlling light emission to the corresponding pixel through the first electrode. For example, when the display substrate includes an organic light emitting diode (OLED), the first electrode may be the anode of the OLED. In addition, the display substrate also includes a second electrode, which may be the cathode of the OLED; when the display substrate is combined with Mini-LED or Micro-LED, the first electrode may be an electrode electrically connected to the anode of the Mini-LED / Micro-LED; when the display substrate is applied to a display device such as LCD or EPD, the first electrode may be a pixel electrode. The first electrode is an electrode used for light emission control.

[0084] Figure 1 A schematic diagram of a display substrate provided in an embodiment of the present application, Figure 2 A schematic diagram of another display substrate provided in an embodiment of the present application.

[0085] like Figure 1 and Figure 2 As shown, the display substrate 01 includes a first region R1 and a second region R2, and the first region R1 is located on a side of the second region R2 close to the edge of the display substrate 01. The display substrate 01 may be a narrow-frame display substrate 01, in which case the first region R1 is a frame region for setting peripheral circuits and peripheral wiring, and the second region R2 is a display region for performing light-emitting display. In this case, the first electrode E1 may be located in the second region R2 and not in the first region R1. The display substrate 01 may also be a frameless display substrate 01 or an extremely narrow-frame display substrate 01, in which case the first region R1 and the second region R2 are both regions for performing light-emitting display and the first region R1 is closer to the edge of the display substrate 01 than the second region R2. In this case, the first region R1 and the second region R2 may both include the first electrode E1.

[0086] The second region R2 includes a plurality of first transistors T1, and the first transistors T1 are electrically connected to the first electrode E1. Whether the first electrode E1 can receive a signal to control the pixel to emit light may depend on the state of the first transistor T1. When the first electrode E1 is electrically connected to the pixel circuit, the first transistor T1 may be a transistor in the pixel circuit that is directly electrically connected to the first electrode E1; when the first electrode E1 is electrically connected to the pixel control transistor, the first electrode E1 may be a pixel control transistor. It should be noted that the first transistor T1 is electrically connected to the first electrode E1, which may mean that the first transistor T1 is directly connected to the first electrode E1 through a conductive structure, rather than that the first transistor T1 needs to be electrically connected to the first electrode E1 through a control structure.

[0087] In some embodiments, Figure 1As shown, the first transistor T1 is electrically connected to the first electrode E1 of the second region R2. In these embodiments, the first region R1 of the display substrate 01 does not include the first electrode E1, and the second region R2 includes the first electrode E1.

[0088] In some embodiments, Figure 2 As shown, the first transistor T1 is electrically connected to the first electrode E1 of the first region R1 and the second region R2. In these embodiments, the first region R1 and the second region R2 of the display substrate 01 both include the first electrode E1.

[0089] Figure 3 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in Figure 4 for Figure 3 Schematic diagram of the cross section along the A1-A2 direction.

[0090] In the embodiments of the present application, Figure 3 and Figure 4 , the display substrate 01 includes a substrate 10, lead wires 20, a conductive pad 30 and a first insulating layer 40. Figure 4 As shown, the lead wire 20 is located on one side of the substrate 10, and the conductive pad 30 is located between the film layer where the lead wire 20 is located and the substrate 10. When preparing the display substrate 01, the lead wire 20 is prepared after the conductive pad 30 is prepared; the first insulating layer 40 is located between the film layer where the conductive pad 30 is located and the film layer where the lead wire 20 is located. When preparing the display substrate 01, the first insulating layer 40 is prepared after the conductive pad 30 is prepared and before the first insulating layer 40 is prepared.

[0091] The lead wire 20 is located in the first region R1, that is, the lead wire 20 is located in the region near the edge of the display substrate 01. The lead wire 20 may include at least a portion of the functional signal lines 20' such as data lines, power lines, reset lines, and clock lines, and the lead wire 20 may be used to electrically connect to an external test fixture, then at least a portion of the functional signal lines 20' may be electrically connected to the external test fixture, thereby realizing the performance test of the display substrate 01. Among them, the overall extension direction of the lead wire 20 may be substantially parallel to the arrangement direction of the first region R1 and the second region R2 where it is located.

[0092] Please refer to Figure 4Since the first insulating layer 40 is prepared after the conductive pad 30, when the first insulating layer 40 is prepared, the first insulating layer 40 has a similar climbing phenomenon at the side wall of the conductive pad 30, resulting in the main structural performance of the first insulating layer 40 including the first insulating layer 40 being thinned at the side wall and the vicinity of the side wall. For example, relative to the thickness of the first insulating layer 40 at a flat position, such as Figure 4 As shown, the thickness of the first insulating layer 40 at the side wall of the conductive pad 30 is reduced, and the thickness of the first insulating layer 40 at the edge of the upper surface of the conductive pad 30 is also reduced. The places where the thickness of the first insulating layer 40 is reduced at the side wall of the conductive pad 30 and the places near the side wall are called weak points P1.

[0093] like Figure 3 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the conductive pad 30 overlaps with the lead wire 20; and a first insulating layer 40 is included between the conductive pad 30 and the lead wire 20, and at least part of the weak point P1 of the first insulating layer 40 is also located between the conductive pad 30 and the lead wire 20. Among them, the conductive pad 30 and the lead wire 20 can both conduct electricity.

[0094] When static electricity exists at the edge of the display substrate 01, the static electricity can enter the lead wire 20. For example, when the edge of the display substrate 01 is ground, at least part of the static electricity generated by the grinding can enter the lead wire 20. Since there is a weak point P1 in the first insulating layer 40 between the lead wire 20 and the conductive pad 30, the static electricity can easily break through the weak point P1 in the first insulating layer 40 during the process of forming a path in the lead wire 20, thereby achieving the release of static electricity.

[0095] In the embodiment of the present application, in order to make the lead wire 20 overlap with the weak point P1 of the first insulating layer 40 so that the static electricity in the lead wire 20 can break through the weak point P1, the lead wire 20 should overlap with at least part of the side wall of the conductive pad 30 in the direction perpendicular to the display substrate 01. For example, Figure 3 As shown, the lead wires 20 extend along the column direction and the lead wires 20 overlap with the upper and lower sidewalls of the conducting pads 30 .

[0096] The first region R1 may at least partially surround the second region R2, for example, Figure 1 and Figure 2 As shown, the first region R1 surrounds the second region R2. Then the arrangement direction of the second region R2 and a part of the first region R1 is different from the arrangement direction of the second region R2 and another part R1. For example, Figure 1 and Figure 2As shown, the arrangement direction of the second region R2 and the first regions R1 on the left and right sides is parallel to the row direction, and the arrangement direction of the second region R2 and the first regions R1 on the upper and lower sides is parallel to the column direction.

[0097] Figure 5 A schematic diagram of a display substrate provided in an embodiment of the present application.

[0098] In some embodiments of the present application, Figure 5 As shown, the lead wires 20 and the conductive pads 30 that overlap each other in a direction perpendicular to the plane where the display substrate 01 is located are located in the first type first region R1a, and the first type first region R1a is a region in the first region that is arranged along the first arrangement direction X1 with the second region R2. That is, the lead wires 20 and the conductive pads 30 that overlap each other are relatively concentratedly arranged in the first region R1 located on the same side of the second region R2.

[0099] Figure 6 A schematic diagram of another display substrate provided in an embodiment of the present application.

[0100] In some embodiments of the present application, Figure 6 As shown, the first region R1 includes a first type first region R1a and a second type first region R1b; along the first arrangement direction X1, the first type first region R1a is located on one side of the second region R2; along the second arrangement direction X2, the second type first region R1 is located on one side of the second region R2, and the first arrangement direction X1 intersects with the second arrangement direction X2. For example, the first type first region R1a and the second region R2 are arranged along the first arrangement direction X1 and are located at the lower side of the second region R2, and the second type second region R1b and the second region R2 are arranged along the second direction X2 and are located on the left and right sides of the second region R2.

[0101] In this embodiment, both the first type first region R1a and the second type first region R1b include lead wires 20 and conductive pads 30, that is, the overlapping lead wires 20 and conductive pads 30 are dispersedly disposed in the first region R1 located on different sides of the second region R2.

[0102] Among them, the lead wires 20 are dispersedly arranged in the first areas R1 located on different sides of the second area R2, which can reduce the wiring difficulty of the lead wires 20; and the number density of the lead wires 20 in a first area R2 can be reduced to reduce the difficulty of electrical connection with an external test fixture and improve the accuracy of electrical connection with an external test fixture. In this embodiment, the conductive pads 30 are also dispersedly arranged in different first areas R1 where the lead wires 20 are located, so that the lead wires 20 dispersedly arranged in the first areas R1 located on different sides of the second area R2 can all have corresponding weak points P1 for electrostatic discharge.

[0103] It should be noted that the technical solutions provided in the following embodiments are applicable to the case where the overlapping lead wires 20 and conductive pads 30 are only located in the first type first region R1a, and are also applicable to the case where both the first type first region R1a and the second type first region R1b include overlapping lead wires 20 and conductive pads 30.

[0104] Figure 7 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present application. Figure 8 A cross-sectional schematic diagram of a portion of a display substrate provided in an embodiment of the present application. Figure 7 and Figure 8 The structure filled with patterns is a conductor or semiconductor structure, and the structure filled with white is an insulating structure.

[0105] In some embodiments of the present application, Figure 7 and Figure 8 As shown, the conductive pad 30 includes at least two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located. On the one hand, the conductive pad 30 can be made thicker as a whole; on the other hand, the at least two parts stacked in the conductive pad 30 can be etched separately, so the process difficulty of separately preparing each part with a large sidewall inclination angle is small, and it is easy to make the sidewall of the conductive pad 30 have a larger inclination angle.

[0106] In a technical solution corresponding to these embodiments, as Figure 7 As shown, the conductive pad 30 includes a first portion 31 and a second portion 32 stacked in a direction perpendicular to the plane where the display substrate 01 is located, the first portion 31 is a conductor or a semiconductor, and the second portion 32 is a conductor or a semiconductor. In one implementation, the first portion 31 and the second portion 32 can be electrically connected to increase the possibility of the lead wire 20 discharging to the conductive pad 30.

[0107] In a technical solution corresponding to these embodiments, as Figure 8 As shown, the conductive pad 30 includes a first part 31 and a third part 33 stacked in a direction perpendicular to the plane where the display substrate 01 is located. The first part 31 is a conductor or a semiconductor and the third part 33 is an insulator. The first part 31 is located on the side of the third part 33 close to the first insulating layer 40. Then, the first part 31 as a conductor or a semiconductor is closer to the first insulating layer 40, and it is easier for the first part 31 and the first insulating layer 40 to form electrical conduction at the weak point P1.

[0108] The semiconductor part in the conductive pad 30 may be a heavily doped semiconductor. It should be noted that when the conductive pad 30 includes only the semiconductor part except the insulating part, the semiconductor part may be a heavily doped structure to ensure that it has a certain conductivity.

[0109] It should be noted that the conductive pad 30 may include two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located, or may include three parts or more parts.

[0110] In some embodiments of the present application, Figure 4 As shown, the conducting pad 30 may also include only the first portion 31 , and the preparation difficulty of the conducting pad 30 is low.

[0111] It should be noted that the following embodiments and drawings are mainly described using the example that the conductive pad 30 only includes the first part 31, but the following embodiments are also applicable to the case where the conductive pad 30 includes the first part 31 and the second part 32, and the conductive pad 30 includes the first part 31 and the third part 33.

[0112] Fig. 9 A schematic cross-sectional view of a partial area of ​​a display substrate provided in an embodiment of the present application.

[0113] like Fig. 9 As shown, the display substrate 01 includes a first film layer F1, and the first film layer F1 includes a first structure 30' in the second region R2. The conductive pad 30 includes at least a first portion 31, and the first portion 31 is located in the first film layer F1. The first film layer F1 of the display substrate 01 includes a first portion 31 located in the first region R1 and a first structure 30' located in the second region R2.

[0114] In some embodiments of the present application, Fig. 9 As shown, the thickness H1 of the first portion 31 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness H2 of the first structure 30' in the direction perpendicular to the plane where the display substrate 01 is located. It should be noted that the thickness H1 of the first portion 31 refers to the thickness of the portion thereof on the relatively flat and parallel bearing surface of the substrate 10 in the direction perpendicular to the plane where the display substrate 01 is located; the thickness H2 of the first structure 30' refers to the thickness of the portion thereof on the relatively flat and parallel bearing surface of the substrate 10 in the direction perpendicular to the plane where the display substrate 01 is located.

[0115] In these embodiments, the thickness of the first film layer F1 in the direction perpendicular to the plane where the display substrate 01 is located is differentially designed, and the thickness H1 of the first part 31 of the conductive pad 30 is relatively larger. When the thickness H1 of the first part 31 of the conductive pad 30 is relatively larger, it is beneficial to achieve a greater thickness of the conductive pad 30 in the direction perpendicular to the plane where the display substrate 01 is located, which is more conducive to the first insulating layer 40 forming a weak point P1 at the side wall position and the position near the side wall of the conductive pad 30, and the thickness of the first insulating layer 40 at the weak point P1 has the opportunity to be thinner. Therefore, when the thickness H1 of the first part 31 in the first film layer F1 is greater than the thickness H2 of the first structure 30' in the first film layer F1, it is more conducive to the static electricity at the edge position of the display substrate 01 being released at the position of the conductive pad 30 and the position near the conductive pad 30, further reducing the influence of the static electricity at the edge of the display substrate 01 on other functional structures in the display substrate 01 including the functional signal line, so that the display substrate 01 has a good display effect.

[0116] Fig.10 A schematic cross-sectional view of a partial area of ​​a display substrate provided in an embodiment of the present application.

[0117] In some embodiments of the present application, Fig.10 As shown, the sidewall inclination angle of the first portion 31 is greater than the sidewall inclination angle of the first structure 30'. The sidewall inclination angle refers to the angle between the sidewall and the plane where the substrate 10 is located. Fig.10 As shown, the sidewall inclination angle of the first portion 31 is α and the sidewall inclination angle of the first structure 30' is β, then α>β. The sidewall inclination angle of the first portion 31 is greater than the sidewall inclination angle of the first structure 30', that is, the sidewall of the first portion 31 is more vertical than the sidewall of the first structure 30'.

[0118] In these embodiments, the sidewall inclination angles of the structures included in the first film layer F1 are designed differently, and the sidewall inclination angle of the first part 31 belonging to the conductive pad 30 is relatively larger. When the sidewall inclination angle of the first part 31 is relatively larger, the thickness of the first insulating layer 40 attached to the sidewall of the first part 31 is thinner, which is more conducive to the first insulating layer 40 forming a weak point P1 at the sidewall position and the position near the sidewall of the conductive pad 30, and the thickness of the first insulating layer 40 at the weak point P1 has the opportunity to be thinner. Therefore, when the sidewall inclination angle of the first part 31 is greater than the sidewall inclination angle of the first structure 30', it is more conducive to the static electricity at the edge position of the display substrate 01 to be released at the position of the conductive pad 30 and the position near the conductive pad 30, further reducing the influence of the static electricity at the edge of the display substrate 01 on other functional structures in the display substrate 01 including the functional signal line, so that the display substrate 01 has a good display effect.

[0119] It should be noted that the inclination angle of the side wall of the conductive pad 30 that overlaps with the lead wire 20 will affect the characteristics of the weak point P1. Therefore, the above-mentioned side wall inclination angle and the following side wall inclination angle both refer to the inclination angle of the side wall that overlaps with the lead wire 20 in a direction perpendicular to the plane of the display substrate 01.

[0120] Fig.11 A schematic cross-sectional view of a partial area of ​​a display substrate provided in an embodiment of the present application.

[0121] In some embodiments of the present application, Fig.11 As shown, the surface of the conductive pad 30 away from the substrate 10 includes at least one protrusion 300. It can be understood that the conductive pad 30 is prepared on one side of the substrate 10 and the protrusion 300 is located on the surface of the conductive pad 30 away from the substrate 10. Therefore, the at least one protrusion 300 included in the conductive pad 30 is a protrusion 300 away from the direction of the substrate 10. When the first insulating layer 40 is subsequently prepared, the thickness of the portion of the first insulating layer 40 overlapping with the protrusion 300 is thinned, and a weak point P1 is easily formed. And in the direction perpendicular to the plane where the display substrate 01 is located, the lead wire 20 overlaps with the protrusion 300 included in the conductive pad 30. Therefore, the lead wire 20 also overlaps with the weak point P1 where the protrusion 300 is located, which is easy to achieve static discharge.

[0122] In addition, since the conductive pad 30 includes the protrusion 300 , if part of the static electricity in the display substrate 01 is gathered on the conductive pad 30 , the conductive pad 30 can easily achieve tip discharge, which is beneficial to release part of the static electricity at the edge of the display substrate 01 .

[0123] Optionally, the protrusion 300 included on the surface of the conductive pad 30 away from the substrate 10 may be a tip structure.

[0124] Fig.12 A schematic cross-sectional view of a partial area of ​​a display substrate provided in an embodiment of the present application.

[0125] In some embodiments of the present application, Fig.12 As shown, the thickness H of the portion of the first insulating layer 40 located between the conductive pad 30 and the lead wire 20 is less than the thickness H4 of the portion of the first insulating layer 40 located in the second region R2. Fig.12, the first insulating layer 40 includes a first insulating portion 41 and a second insulating portion 42, the first insulating portion 41 is located between the conductive pad 30 and the lead wire 20 and the second insulating portion 42 is located in the second region R2, and the thickness H3 of the first insulating portion 41 is less than the thickness H4 of the second insulating portion 42. It should be noted that the thickness H3 of the first insulating portion 41 refers to the thickness of the portion thereof on the relatively flat and parallel bearing surface of the substrate 10 in a direction perpendicular to the plane where the display substrate 01 is located; the thickness H4 of the second insulating portion 42 refers to the thickness of the portion thereof on the relatively flat and parallel bearing surface of the substrate 10 in a direction perpendicular to the plane where the display substrate 01 is located.

[0126] In these embodiments, the thickness of the first insulating layer 40 in the direction perpendicular to the plane where the display substrate 01 is located is differentially designed, and the thickness H3 of the first insulating portion 41 located between the conductive pad 30 and the lead wire 20 is relatively smaller. When the thickness H3 of the first insulating portion 41 of the first insulating layer 40 is relatively smaller, it is more conducive to making the thickness of the first insulating layer 40 at the side wall position and the position near the side wall of the conductive pad 30 thinner when preparing the first insulating layer 40, and obtaining a more ideal weak point P1, and thus obtaining a weak point P1 that is more conducive to forming an electrostatic discharge path.

[0127] In some embodiments of the present application, the first insulating layer 40 is an inorganic material film layer, that is, the first insulating layer 40 is a film layer formed by inorganic materials. In the display substrate 01, the thickness of the inorganic material film layer is usually thin, which can avoid excessive stress and cracks when the inorganic material film layer is thick, and the inorganic material film layer has the advantages of being easy to etch. The first insulating layer 40 is an inorganic material film layer in the display substrate 01, that is, the first insulating layer 40 is a thin insulating layer in the display substrate 01, so that the first insulating layer 40 can overlap with the side wall position and the position near the side wall of the conductive pad 30 to easily realize the weak point P1.

[0128] It should be noted that the components, thickness, side wall inclination angle, inclusion or exclusion of protrusions, thickness of the first insulating layer 40 and other solutions of the conductive pad 30 in the display substrate 01 provided in the above embodiments of the present application are also applicable to the following embodiments.

[0129] Fig.13 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0130] In some embodiments of the present application, Fig.13As shown, the first transistor T1 includes a semiconductor layer SC and a gate G1, and a first insulating layer 40 is included between the semiconductor layer SC and the gate G1. It can be understood that the first insulating layer 40 includes a portion located in the first region R1 and between the lead wire 20 and the conductive pad 30, and includes a portion located in the second region R2 and between the semiconductor layer SC and the gate G1 of the first transistor T1. That is, in these embodiments, the first insulating layer 40 includes a first insulating portion 41 and a second insulating portion 42, the first insulating portion 41 is located between the lead wire 20 and the conductive pad 30, and the second insulating portion 42 is located between the gate G1 of the first transistor T1 and the semiconductor layer SC.

[0131] In these embodiments, at least a portion of the conductive pad 30 and the semiconductor layer SC are located in the same film layer, and at least a portion of the lead wire 20 and the gate G1 are located in the same film layer. Then, at least a portion of the conductive pad 30 and the gate G1 of the first transistor T1 are prepared at the same time, and at least a portion of the lead wire 20 and the semiconductor layer SC of the first transistor T1 are prepared at the same time. Fig.13 As shown, the film layer where the semiconductor layer SC of the first transistor T1 is located includes a first portion 31 and a first structure 30 ′. The first portion 31 is the first portion 31 of the conductive pad 30 , and the first structure 30 ′ is reused as the semiconductor layer SC of the transistor.

[0132] In order to ensure the control effect of the gate G1 of the transistor on the channel of the semiconductor layer SC, generally only one film layer of inorganic material is included between the gate G1 and the semiconductor layer SC as an insulating layer, and the thickness of the insulating layer is relatively thin. Therefore, at least part of the conductive pad 30 in these embodiments is located in the same film layer as the semiconductor layer SC of the first transistor T1, the first insulating layer 40 is located in the same film layer as the insulating layer between the gate G1 of the first transistor T1 and the semiconductor layer SC, and at least part of the lead wire 20 is located in the same film layer as the gate G1 of the first transistor T1. In this case, it is easy to obtain a weak point P1 for electrostatic discharge between the lead wire 20 and the conductive pad 30 without increasing the process difficulty.

[0133] Among them, the semiconductor layer SC of the first transistor T1 includes a channel and a source region and a drain region, the source region and the drain region are heavily doped regions, and the portion of the conductive pad 30 that is located in the same film layer as the semiconductor layer SC can also be a heavily doped semiconductor structure, that is, the portion of the conductive pad 30 that is located in the same film layer as the semiconductor layer SC can also be prepared by deposition, etching, doping and other processes at the same time as the source region, drain region, etc. of the semiconductor layer SC included in the first transistor T1.

[0134] Fig.14 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0135] In a technical solution corresponding to these embodiments, as Fig.14 As shown, the conductive pad 30 includes a first portion 31 and a second portion 32, wherein the first portion 31 is a semiconductor and is located in the same film layer as the semiconductor layer SC of the first transistor T1, and the second portion 32 is a conductor and is located between the first portion 31 and the substrate 10. In the present technical solution, a conductor film layer is included between the film layer where the semiconductor layer SC of the first transistor T1 is located and the substrate 10, and the film layer includes the second portion 32 in the conductive pad 30.

[0136] For example, the second portion 32 is a metal structure or a metal composite structure, and the film layer where the semiconductor layer SC of the first transistor T1 is located and the substrate include a metal film layer or a metal composite film layer, and the metal film layer or the metal composite film layer includes the second portion 32 of the conductive pad 30 .

[0137] Fig.15 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0138] In one implementation, Fig.15 As shown, the first transistor T1 may be a dual-gate transistor including a top gate and a bottom gate, that is, the first transistor T1 includes a top gate G11 located on a side of its semiconductor layer SC away from the substrate 10 and a bottom gate G12 located on a side close to the substrate 10. In this implementation, the lead wire 20 and the top gate G11 of the first transistor T1 are located in the same film layer, the first portion 31 of the conductive pad 30 and the semiconductor layer SC of the first transistor T1 are located in the same film layer, and the second portion 32 of the conductive pad 30 and the bottom gate G12 of the first transistor T1 are located in the same film layer.

[0139] Fig.16 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0140] In a technical solution corresponding to these embodiments, as Fig.16 As shown, the conductive pad 30 includes a first portion 31 and a third portion 33, wherein the first portion 31 is a semiconductor and is located in the same film layer as the semiconductor layer SC of the first transistor T1, and the third portion 33 is an insulator and is located between the first portion 31 and the substrate 10. In the present technical solution, an insulating film layer is included between the film layer where the semiconductor layer SC of the first transistor T1 is located and the substrate 10, and the film layer includes the third portion 33 in the conductive pad 30.

[0141] Fig.17 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0142] In one implementation, Fig.17As shown, the insulating layer between the film layer where the semiconductor layer SC of the first transistor T1 is located and the substrate 10 may include a buffer layer (not shown in the figure) and / or a light shielding layer LS, wherein the buffer layer between the semiconductor layer SC of the first transistor T1 and the substrate 10 can prevent impurities in the substrate 10 from entering the semiconductor layer SC and affecting the performance of the semiconductor layer SC; the light shielding layer LS between the semiconductor layer SC of the first transistor T1 and the substrate 10 can overlap with the channel of the semiconductor layer SC to prevent external light from irradiating the semiconductor layer SC and affecting the performance of the semiconductor layer SC. In this implementation, the first part 31 of the conductive pad 30 is located in the same film layer as the semiconductor layer SC of the first transistor T1, and the third part 33 of the conductive pad 30 is located in the same film layer as the above-mentioned buffer layer and / or light shielding layer LS.

[0143] In a technical solution corresponding to these embodiments, the first transistor T1 may be a top-bottom dual-gate structure, that is, the first transistor T1 includes a top gate G11 located on the side of its semiconductor layer SC away from the substrate 10 and a bottom gate G12 located on the side close to the substrate 10. In this implementation, the lead wire 20 is located in the same film layer as the top gate G11 of the first transistor T1, the first portion 31 of the conductive pad 30 is located in the same film layer as the semiconductor layer SC of the first transistor T1, and the third portion 33 of the conductive pad 30 is located in the same film layer as the insulating layer between the bottom gate G12 of the first transistor T1 and the semiconductor layer SC. In this implementation, the conductive pad 30 may also include a second portion 32, wherein the second portion 32 may be located in the same film layer as the bottom gate G12 of the first transistor T1.

[0144] Fig.18 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0145] In a technical solution corresponding to these embodiments, as Fig.18 As shown, the first portion 31 of the conductive pad 30 and the semiconductor layer SC of the first transistor T1 are located in the same film layer, and the thickness of the first portion 31 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the semiconductor layer SC included in the first transistor T1 in the direction perpendicular to the plane where the display substrate 01 is located. That is, the semiconductor layer SC included in the first transistor T1 is a first structure 30' located in the same film layer as the first portion 31, and the thickness H1 of the first portion 31 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness H2 of the first structure 30' in the direction perpendicular to the plane where the display substrate 01 is located.

[0146] In the present technical solution, at least part of the process steps for preparing the first part 31 are the same process steps as at least part of the process steps for preparing the semiconductor layer SC of the first transistor T1, thereby reducing the difficulty of preparing the first part 31; and the thickness H1 of the first part 31 is greater than the thickness H2 of the semiconductor layer SC of the first transistor T1, so that a thicker conductive pad 30 can be obtained, which makes it easier to obtain the weak point P1 for electrostatic release.

[0147] In one implementation, the conductive pad 30 includes at least two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located, and the thickness of the two parts can be greater than the thickness of the structure in the second region R2 that is located in the same film layer. For example, in addition to the first part 31 that is in the same layer as the semiconductor layer SC of the first transistor T1, the conductive pad 30 also includes a second part 32 that is in the same layer as the bottom gate G12 of the first transistor T1, wherein the thickness of the second part 32 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the bottom gate G12 of the first transistor T1 in the direction perpendicular to the plane where the display substrate 01 is located. For example, in addition to the first part 31 that is in the same layer as the semiconductor layer SC of the first transistor T1, the conductive pad 30 also includes a third part 33 that is in the same layer as the buffer layer and / or the light shielding layer LS on the side of the semiconductor layer SC of the first transistor T1 facing the substrate 10, wherein the thickness of the third part 33 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the above-mentioned buffer layer and / or the light shielding layer LS in the direction perpendicular to the plane where the display substrate 01 is located.

[0148] Fig.19 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0149] In a technical solution corresponding to these embodiments, as Fig.19 As shown, the first portion 31 of the conductive pad 30 and the semiconductor layer SC of the first transistor T1 are located in the same film layer, and the sidewall inclination angle α of the first portion 31 is greater than the sidewall inclination angle β of the semiconductor layer SC included in the first transistor T1. That is, the semiconductor layer SC included in the first transistor T1 is a first structure 30' located in the same film layer as the first portion 31, and the sidewall inclination angle α of the first portion 31 is greater than the sidewall inclination angle β of the first structure 30'.

[0150] In the present technical solution, at least part of the process steps for preparing the first part 31 are the same process steps as at least part of the process steps for preparing the semiconductor layer SC of the first transistor T1, thereby reducing the difficulty of preparing the first part 31; and the side wall inclination angle α of the first part 31 is greater than the side wall inclination angle β of the semiconductor layer SC of the first transistor T1, so that a conductive pad 30 with a larger inclination angle of at least part of the side wall can be obtained, which makes it easier to obtain the weak point P1 for electrostatic release.

[0151] In one implementation, the conductive pad 30 includes at least two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located, and the sidewall inclination angles of the two parts can be greater than the sidewall inclination angle of the structure in the second region R2 that is located in the same film layer. For example, in addition to the first part 31 that is in the same layer as the semiconductor layer SC of the first transistor T1, the conductive pad 30 also includes a second part 32 that is in the same layer as the bottom gate G12 of the first transistor T1, wherein the sidewall inclination angle of the second part 32 is greater than the sidewall inclination angle of the bottom gate G12 of the first transistor T1. For example, in addition to the first part 31 that is in the same layer as the semiconductor layer SC of the first transistor T1, the conductive pad 30 also includes a third part 33 that is in the same layer as the buffer layer and / or the light shielding layer LS on the side of the semiconductor layer SC of the first transistor T1 facing the substrate 10, wherein the sidewall inclination angle of the third part 33 is greater than the sidewall inclination angle of the above-mentioned buffer layer and / or the light shielding layer LS.

[0152] Fig. 20 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0153] In a technical solution corresponding to these embodiments, as Fig. 20 As shown, the thickness H3 of the portion of the first insulating layer 40 between the conductive pad 30 and the lead wire 20 is less than the thickness H4 of the portion of the first insulating layer 40 between the gate G1 of the first transistor T1 and the semiconductor layer SC. That is, the insulating layer between the conductive pad 30 and the lead wire 20 is the first insulating portion 41 of the same layer as the second insulating portion 42 between the gate G1 of the first transistor T1 and the semiconductor layer SC, and the thickness H3 of the first insulating portion 41 is less than the thickness H4 of the second insulating portion 42.

[0154] In the present technical solution, at least part of the process steps for preparing the first insulating part 41 and at least part of the process steps for preparing the second insulating part 42 are the same process steps, which reduces the difficulty of preparing the first insulating part 41; and the thickness H3 of the first insulating part 41 is smaller than the thickness H4 of the second insulating part 42, which makes it easier to obtain the weak point P1 for electrostatic release.

[0155] Fig.21 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0156] In some embodiments of the present application, Fig.21As shown, the display substrate 01 includes not only the first transistor T1, but also the capacitor C. If the display substrate 01 includes a pixel circuit, the pixel circuit may include the first transistor T1 and the capacitor CC. The first transistor T1 includes a gate G1, and the capacitor C includes a first electrode plate E1 and a second electrode plate E2, wherein the first electrode plate E1 and the gate G1 are located in the same film layer. At least a portion of the conductive pad 30 is located in the same film layer as the first electrode plate E1, and at least a portion of the lead wire 20 is located in the same film layer as the second electrode plate E2, then at least a portion of the conductive pad 30 is prepared simultaneously with the gate G1 of the first transistor T1 and the first electrode plate E1 of the capacitor C, and at least a portion of the lead wire 20 is prepared simultaneously with the second electrode plate E2 of the capacitor C. For example, as Fig.21 As shown, the conducting pad 30 includes a first portion 31 , and the first portion 31 , the gate G1 , and the first electrode plate E1 are located in the same conducting film layer, and the lead wire 20 and the second electrode plate E2 are located in the same conducting film layer.

[0157] In order to ensure the capacitance of the capacitor C, generally only one inorganic material film layer is included between the first plate E1 and the second plate E2 of the capacitor C as an insulating layer, and the thickness of the insulating layer is relatively thin. Therefore, at least part of the conductive pad 30 in these embodiments is located in the same film layer as the first plate E1 of the capacitor C, the first insulating layer 40 is located in the same film layer as the insulating layer between the first plate E1 and the second plate E2, and at least part of the lead wire 20 is located in the same film layer as the second plate E2 of the capacitor C. In this case, it is easy to obtain a weak point P1 for electrostatic discharge between the lead wire 20 and the conductive pad 30 without increasing the process difficulty.

[0158] Fig. 22 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0159] In a technical solution corresponding to these embodiments, as Fig. 22 As shown, the conductive pad 30 includes a first portion 31 and a second portion 32 , wherein the first portion 31 is a conductor and is located in the same film layer as the first electrode E1 of the capacitor C, and the second portion 32 is a semiconductor and is located in the same film layer as the semiconductor layer SC of the first transistor T1 .

[0160] In one implementation, when the first transistor T1 includes a top gate G11 located on a side of its semiconductor layer SC away from the substrate 10 and a bottom gate G12 located on a side close to the substrate 10, the conductive pad 30 may include a first portion 31 located in the same film layer as the top gate G11, a second portion 32 located in the same film layer as the semiconductor layer SC of the first transistor T1, and other portions located in the same film layer as the bottom gate G12.

[0161] Fig.23 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0162] In a technical solution corresponding to these embodiments, as Fig.23 As shown, the conductive pad 30 includes a first portion 31 and a third portion 33, wherein the first portion 31 is a conductor and is located in the same film layer as the first electrode E1 of the capacitor C, and the third portion 33 is an insulator and is located in the same film layer as the insulating layer located between the semiconductor layer SC and the gate G1.

[0163] In one implementation, when the first transistor T1 includes a top gate G11 located on a side of its semiconductor layer SC away from the substrate 10 and a bottom gate G12 located on a side close to the substrate 10, the conductive pad 30 may include a first portion 31 located in the same film layer as the top gate G11, a second portion 32 located in the same film layer as the bottom gate G12, and a third portion 33 located in the same film layer as the insulating layer between the semiconductor layer SC and the gate G1.

[0164] In one implementation, when the insulating layer between the film layer where the semiconductor layer SC of the first transistor T1 is located and the substrate 10 may include a buffer layer and / or a light shielding layer, the conductive pad 30 may include a first portion 31 located in the same film layer as the top gate G11, a third portion 33 located in the same film layer as the insulating layer between the semiconductor layer SC and the gate G1, and other portions located in the same film layer as the buffer layer and / or the light shielding layer.

[0165] In addition, when the first portion 31 is a conductor and is located in the same film layer as the first electrode E1 of the capacitor C, the third portion 33 of the conductive pad 30 can be located in the same film layer as the buffer layer and / or the light shielding layer; or, when the first transistor T1 includes a top and bottom double gate, the third portion 33 of the conductive pad 30 can be located in the same film layer as the insulating layer between the bottom gate of the first transistor T1 and the semiconductor layer SC. No further details will be given here.

[0166] Fig.24 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0167] In a technical solution corresponding to these embodiments, as Fig.24 As shown, the first portion 31 of the conductive pad 30 and the first electrode plate E1 of the capacitor C are located in the same film layer, and the thickness of the first portion 31 in a direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the first electrode plate E1 of the first capacitor C in a direction perpendicular to the plane where the display substrate 01 is located. That is, the first electrode plate E1 of the capacitor C is a first structure 30' located in the same film layer as the first portion 31, and the thickness H1 of the first portion 31 in a direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness H2 of the first structure 30' in a direction perpendicular to the plane where the display substrate 01 is located.

[0168] In the present technical solution, at least part of the process steps for preparing the first part 31 are the same process steps as at least part of the process steps for preparing the first electrode plate E1 of the capacitor C, thereby reducing the difficulty of preparing the first part 31; and the thickness H1 of the first part 31 is greater than the thickness H2 of the first electrode plate E1 of the capacitor C, so that a thicker conductive pad 30 can be obtained, which makes it easier to obtain the weak point P1 for electrostatic discharge.

[0169] In one implementation, the conductive pad 30 includes at least two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located, and the thickness of the two parts can be greater than the thickness of the structure in the second region R2 that is located in the same film layer. For example, in addition to the first part 31 that is in the same layer as the first plate E1 of the capacitor C, the conductive pad 30 also includes a second part 32 that is in the same layer as the semiconductor layer SC of the first transistor T1, wherein the thickness of the second part 32 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the semiconductor layer SC of the first transistor T1 in the direction perpendicular to the plane where the display substrate 01 is located. For example, in addition to the first part 31 that is in the first plate E1 of the capacitor C, the conductive pad 30 also includes a third part 33 that is in the same layer as the insulating structure on the side of the semiconductor layer SC of the first transistor T1 facing the substrate 10, wherein the thickness of the third part 33 in the direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the above-mentioned insulating structure in the direction perpendicular to the plane where the display substrate 01 is located.

[0170] Fig.25 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0171] In a technical solution corresponding to these embodiments, as Fig.25 As shown, the first portion 31 of the conductive pad 30 and the first electrode plate E1 of the capacitor C are located in the same film layer, and the sidewall inclination angle of the first portion 31 is greater than the sidewall inclination angle of the first electrode E1 included in the capacitor C. That is, the first electrode plate E1 of the capacitor C is a first structure 30' located in the same film layer as the first portion 31, and the sidewall inclination angle α of the first portion 31 is greater than the sidewall inclination angle β of the first structure 30'.

[0172] In the present technical solution, at least part of the process steps for preparing the first part 31 are the same process steps as at least part of the process steps for preparing the first electrode plate E1 of the capacitor C, thereby reducing the difficulty of preparing the first part 31; and the side wall inclination angle α of the first part 31 is greater than the side wall inclination angle β of the first electrode plate E1 of the capacitor C, so that a conductive pad 30 with a larger inclination angle of at least part of the side wall can be obtained, which makes it easier to obtain the weak point P1 for electrostatic release.

[0173] In one implementation, the conductive pad 30 includes at least two parts stacked in a direction perpendicular to the plane where the display substrate 01 is located, and the sidewall inclination angles of the two parts can be greater than the sidewall inclination angle of the structure located in the same film layer in the second region R2. For example, in addition to the first part 31 on the same layer as the first plate E1 of the capacitor C, the conductive pad 30 also includes a second part 32 on the same layer as the semiconductor layer SC of the first transistor T1, wherein the sidewall inclination angle of the second part 32 is greater than the sidewall inclination angle of the semiconductor layer SC of the first transistor T1. For example, in addition to the first part 31 on the same layer as the first plate E1 of the capacitor C, the conductive pad 30 also includes a third part 33 on the same layer as the insulating structure on the side of the semiconductor layer SC of the first transistor T1 toward the substrate 10, wherein the sidewall inclination angle of the third part 33 is greater than the sidewall inclination angle of the above-mentioned insulating structure.

[0174] Fig.26 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0175] In a technical solution corresponding to these embodiments, as Fig.26 As shown, the thickness of the portion of the first insulating layer 40 between the conductive pad 30 and the lead wire 20 is less than the thickness of the portion of the first insulating layer 40 between the first electrode plate E1 and the second electrode plate E2 of the capacitor C. That is, the insulating layer between the conductive pad 30 and the lead wire 20 is the first insulating portion 41 of the same layer as the second insulating portion 42 between the first electrode plate E1 and the second electrode plate E2 of the capacitor C, and the thickness H3 of the first insulating portion 41 is less than the thickness H4 of the second insulating portion 42.

[0176] In the present technical solution, at least part of the process steps for preparing the first insulating part 41 and at least part of the process steps for preparing the second insulating part 42 are the same process steps, which reduces the difficulty of preparing the first insulating part 41; and the thickness H3 of the first insulating part 41 is smaller than the thickness H4 of the second insulating part 42, which makes it easier to obtain the weak point P1 for electrostatic release.

[0177] In some embodiments of the present application, the display substrate 01 further includes a second insulating layer 50, which is located between different conductive film layers, and the second insulating layer 50 is a different layer from the first insulating layer 40. In a direction perpendicular to the plane where the display substrate 01 is located, the thickness of the first insulating layer 40 is less than the thickness of the second insulating layer 50. In the embodiment of the present application, the thickness of the first insulating layer 40 located between the lead wire 20 and the conductive pad 30 is less than the thickness of all other insulating layers or part of the insulating layers, so it is easier to obtain the weak point P1 for electrostatic discharge.

[0178] like Figures 13 to 20As shown, the first insulating layer 40 is located between the semiconductor layer SC and the gate G1 of the first transistor T1, the second insulating layer 50 is located on the side of the film layer where the gate G1 of the first transistor T1 is located away from the substrate 10, and the thickness of the second insulating layer 50 in a direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the first insulating layer 40 in a direction perpendicular to the plane where the display substrate 01 is located.

[0179] like Figure 21 to Figure 26 As shown, the first insulating layer 40 is located between the first plate E1 and the second plate E2 of the capacitor C, the second insulating layer 50 is located on the side of the film layer where the second plate E2 is located away from the substrate 10, and the thickness of the second insulating layer 50 in a direction perpendicular to the plane where the display substrate 01 is located is greater than the thickness of the first insulating layer 40 in a direction perpendicular to the plane where the display substrate 01 is located.

[0180] Fig. 27 for Figure 3 A schematic cross-sectional view along the B1-B2 direction.

[0181] Combination Figure 3 and Fig. 27 In order to enable the functional signal line 20' to be electrically connected to the IC and / or the flexible circuit board, the display substrate 01 further includes a transfer electrode block 70. The transfer electrode block 70 is located in the first region R1 and serves as a transfer portion between the functional signal line 20' and the IC and / or the flexible circuit board. The transfer electrode block 70 is located in the first region R1 and is connected to the functional signal line 20'.

[0182] like Fig. 27 As shown, the transfer electrode block 70 includes at least two transfer electrodes 700 arranged in a direction perpendicular to the plane where the display substrate 01 is located and located in different conductive film layers. Since the transfer electrode block 70 includes at least two stacked transfer electrodes 700, the stacked multiple transfer electrodes 700 can be in the same layer as at least part of the functional signal lines 20' located in different film layers in the display substrate 01, which facilitates the connection between the functional signal lines 20' and the transfer electrode block 70. For example, the transfer electrode block 70 connected to the data line includes the transfer electrode 700 in the same layer as the data line, and the data line and the transfer electrode 700 in the transfer electrode block 70 remain connected after etching, and no other structure is required for transfer, which reduces the process difficulty and improves the process reliability.

[0183] In addition, the lead wire 20 may also include a portion located in the same conductive film layer as at least one transfer electrode 700 in the transfer electrode block 70, so as to realize electrical connection between the lead wire 20 and the functional signal line 20' through the transfer electrode block 70. Fig. 27As shown, the lead-out wire 20 and the transfer electrode 700 which is at the bottom of the transfer electrode block 70 and is located in the same conductive film layer as the gate of the first transistor T1 are located in the same conductive film layer. The lead-out wire 20 and the transfer electrode 700 in the transfer electrode block 70 remain connected after etching, and there is no need to transfer through other structures, so the process difficulty is reduced and the process reliability is improved.

[0184] Fig.28 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in Fig.29 for Fig.28 A schematic cross-sectional view along the C1-C2 direction.

[0185] Please refer to Fig.28 and Fig.29 , the lead wire 20 is electrically connected to the transfer electrode block 70, and at least a portion of the lead wire 20 and the first transfer electrode 71 are located in the same film layer. Fig.29 As shown, when the lead wire 20 only includes a structure located in one conductive film layer, the lead wire 20 and the first transfer electrode 71 may be located in the same film layer.

[0186] In some embodiments of the present application, Fig. 27 and Fig.29 As shown, the display substrate 01 includes a light emitting surface S1 and a backlight surface S2. The light emitting surface S1 is the side of the display substrate 01 that displays the display image to the user. In order to reduce the frame of the display substrate 01, the IC and / or flexible circuit board bound to the display substrate 01 are bound to the display substrate 01 on the backlight surface S2 side of the display substrate 01. The display substrate 01 also includes a connecting electrode 60 and an external electrode block 80. The transfer electrode block 70 and the external electrode block 80 are located on different sides of the substrate 10, as shown in FIG. Fig. 27 and Fig.29 As shown, the external electrode block 80 is located on the backlight surface S2 side of the display substrate 01, and the connecting electrode 60 is electrically connected to the transfer electrode block 70 and the external electrode block 80, so the external electrode block 80 is electrically connected to the functional signal line 20' through the connecting electrode 60. Specifically, the end 61 of the connecting electrode 60 located on the light-emitting surface S1 side of the display substrate 01 contacts the transfer electrode block 70 on the light-emitting surface S1 side of the display substrate 01, the end 62 of the connecting electrode 60 located on the backlight surface S2 side of the display substrate 01 contacts the external electrode block 80 on the backlight surface S2 side of the display substrate 01 or serves as the external electrode block 80, and the portion of the connecting electrode 60 between the end 61 located on the light-emitting surface S1 side of the display substrate 01 and the end 62 located on the backlight surface S2 side of the display substrate 01 is routed at the side wall of the display substrate 01.

[0187] In addition, the backlight surface S2 side of the display substrate 01 may include an external electrode block 80 prepared by a semiconductor process; the external electrode block 80 may include at least two conductive structures stacked in a direction perpendicular to the plane where the display substrate 01 is located. Alternatively, the end 62 of the connecting electrode 60 located on the backlight surface S2 side of the display substrate 01 serves as the external electrode block 80 combined with the IC and / or the flexible circuit board.

[0188] The transfer electrode block 70 is an electrode block for electrically connecting the external electrode block 80 and the lead wire to the functional signal line 20 ′. The width of the transfer electrode block 70 is usually greater than that of the signal line and the lead wire, which facilitates the contact yield between the connection electrode 60 and the transfer electrode block 70 .

[0189] In some embodiments of the present application, Fig.29 As shown, the transfer electrode block 70 includes a first transfer electrode 71, and the first transfer electrode 71 is located on a side of the other transfer electrodes 700 away from the substrate 10, that is, the first transfer electrode 71 is the transfer electrode 700 farthest from the substrate 10 in the transfer electrode block 70. When the transfer electrode block 70 contacts the connection electrode 60, it is mainly the first transfer electrode 71 in the transfer electrode block 70 that contacts the connection electrode 60. And at least part of the lead-out wire 20 is arranged in the same layer as the first transfer electrode 71, so when the connection electrode 60 contacts the first transfer electrode 71, it can also contact this part of the lead-out wire 20, which can ensure the yield of the electrical connection between the connection electrode 60 and the transfer electrode block 70 and can reduce the impedance between the connection electrode 60 and the transfer electrode block 70. In a technical solution, as Fig.29 As shown, the connection electrode 60 is contact-connected to the lead wire 20 .

[0190] Fig.30 for Fig.28 A schematic cross-sectional view along the C1-C2 direction.

[0191] In a technical solution corresponding to these embodiments, as Fig.30 As shown, the transfer electrode block 70 also includes a second transfer electrode 72 and a third transfer electrode 73. The second transfer electrode 72 and the third transfer electrode 73 are located on the side of the first transfer electrode 71 close to the substrate 10. The preparation steps of the second transfer electrode 72 and the third transfer electrode 73 are performed before the first transfer electrode 71 is prepared.

[0192] The conductive pad 30 includes a portion located in the same film layer as the second transfer electrode 72 and a portion located in the same film layer as the third transfer electrode 73. For example, Fig.31As shown, the first portion 31 of the conductive pad 30 is disposed in the same layer as the second transfer electrode 72 of the transfer electrode block 70, and the second portion 32 of the conductive pad 30 is disposed in the same layer as the third portion 73 of the transfer electrode 70. Since at least a portion of the lead-out wire 20 and the first transfer electrode 71 of the transfer electrode block 70 are located in the same film layer, at least a portion of the conductive pad 30 and at least a portion of the lead-out conductive wire can be obtained when preparing the transfer electrode block 70, thereby saving process flow.

[0193] In some embodiments of the present application, Fig.29 and Fig.30 As shown, the lead wire 20 includes a first lead portion 21 and a second lead portion 22, and the first lead portion 21 is electrically connected to the second lead portion 22. The first lead portion 21 of the lead wire 20 is reused with at least one transfer electrode 700 included in the transfer electrode block 70, for example, Fig.29 and Fig.30 As shown, the first lead portion 21 is reused with the first transfer electrode 71, and the second lead portion 22 does not overlap with the transfer electrode block 70 in a direction perpendicular to the plane where the display substrate 01 is located. Then the lead wire 20 is electrically connected to the transfer electrode block 70 through the first lead portion 21, and the second lead portion 22 can be located on the side of the first lead portion 21 away from the second region R2.

[0194] Fig.31 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0195] In these embodiments, Fig.31 In the embodiment, at least part of the first lead-out portion 21 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, so that at least part of the transfer electrode blocks 70 and the lead-out wires 20 electrically connected to the transfer electrode blocks 70 overlap with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located. Therefore, a weak point P1 for static discharge can be obtained in the area where the transfer electrode blocks 70 of the display substrate 01 are located, and the space of the first area R1 of the display substrate 01 is fully utilized.

[0196] In a technical solution corresponding to these embodiments, at least part of the second lead-out portion 22 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located. Fig.31 As shown, the first lead portion 21 and the second lead portion 22 overlap with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0197] Fig.32 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0198] In a technical solution corresponding to these embodiments, as Fig.32 As shown, the conductive pads 30 overlap with the first lead-out portion 21 in a direction perpendicular to the plane where the display substrate 01 is located, that is, the portion of the lead-out wire 20 that overlaps with the conductive pad in a direction perpendicular to the plane where the display substrate 01 is located only includes the portion of the transfer electrode 700 reused as the transfer electrode block 70. In this way, the extension length of the second lead-out portion 22 in the lead-out wire 20 may not be limited by the conductive pad 30, and therefore, it is beneficial for the width of the first region R1 to be narrower.

[0199] In some embodiments of the present application, Fig. 27 , Fig.29 , Fig.30 and Figure 5 , Figure 6 , at least part of the edge of the lead wire 20 away from the second region R2 overlaps with the edge of the display substrate 01. It should be noted that the overlap of the lead wire 20 with the edge of the display substrate 01 refers to the overlap of the lead wire 20 with the substrate 10 in the display substrate 01 and the edges of multiple stacked film layers prepared by semiconductor technology.

[0200] The connection electrode 60 is manufactured after the stacked film layers are prepared by semiconductor process on the substrate 10. Before manufacturing the connection electrode 60, the display substrate 01 obtained initially needs to be edge-grinded, so that the edges of the substrate 10 and the multiple stacked film layers prepared by semiconductor process form chamfered edges. When manufacturing the connection electrode 60, the continuity and manufacturing yield of the connection electrode 60 at the position of the display substrate 01 can be guaranteed; in addition, the display substrate 01 can have a narrower frame.

[0201] However, during the edge grinding process, the friction between the required grinding rod or grinding wheel and the display substrate 01 will generate static electricity. In addition, the substrate in the display substrate 01 may be a glass substrate, which is more likely to generate static electricity during the edge grinding process. The static electricity will be introduced into the display substrate 01, causing damage to the device of the display substrate 01 and loss of process yield.

[0202] After the edge grinding process, at least part of the edge of the lead wire 20 away from the second region R2 coincides with the edge of the display substrate 01 obtained initially, that is, during the edge grinding process, at least part of the edge of the lead wire 20 is exposed at the edge position of the display substrate 01. During the edge grinding process, the grinding of the lead wire 20 will generate static electricity, and at least part of the static electricity generated by structures such as the glass substrate will also be introduced into the lead wire 20. In the embodiment provided in the present application, the lead wire 20 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, which can effectively release the static electricity on the lead wire 20.

[0203] Fig.33 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0204] In some embodiments of the present application, Fig.33 As shown, at least part of the edge of at least part of the conductive pad 30 away from the second region R2 overlaps with the edge of the display substrate 01. It should be noted that the overlap of the conductive pad 30 with the edge of the display substrate 01 refers to the overlap of the conductive pad 30 with the substrate 10 in the display substrate 01 and the edges of multiple stacked film layers prepared by semiconductor technology. On the one hand, when performing the above-mentioned edge grinding process, the edge grinding cut-off position can be at the position where the conductive pad 30 is set, so that the first region R1 has a smaller width; on the other hand, the conductive pad 30 is as close to the edge of the display substrate 01 as possible, so that the weak point P1 is located at the edge of the display substrate 01 as much as possible, and then at least part of the static electricity on the display substrate 01 can be released at the weak point P1 at the edge of the display substrate 01.

[0205] In some technical solutions, such as Fig.33 As shown, at least a portion of the edge of the conductive pad 20 away from the second region R2 overlaps with the edge of the display substrate 01 , and at least a portion of the edge of the lead wire 20 away from the second region R2 overlaps with the edge of the display substrate 01 .

[0206] Fig.34 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0207] In some embodiments of the present application, Fig.32 and Fig.34 As shown, the lead wire 20 overlaps with at least two conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the position of the lead wire 20 can correspond to at least two weak points P1 for static discharge.

[0208] It should be noted that at least part of the lead wires 20 in the display substrate 01 overlap with at least two conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located. That is, all the lead wires 20 in the display substrate 01 may overlap with multiple conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located; or, part of the lead wires 20 in the display substrate 01 overlap with multiple conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the present application does not limit whether other lead wires 20 overlap with one conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located or not.

[0209] It should also be noted that if Fig.32As shown, among the at least two conductive pads 30 overlapping the same lead wire 20 in a direction perpendicular to the plane where the display substrate 01 is located, at least one of the at least two conductive pads 30 may overlap with the first lead portion 21 and at least one may overlap with the second lead portion 22. Alternatively, as Fig.34 As shown, among the at least two conductive pads 30 overlapping with the same lead-out conductive line 20 in a direction perpendicular to the plane where the display substrate 01 is located, the at least two conductive pads 30 may both overlap with the second lead-out portion 22 .

[0210] In a technical solution corresponding to these embodiments, the distance between two adjacent conductive pads 30 overlapping the same lead-out wire 20 is greater than or equal to 2.5 μm. Fig.34 As shown, among the multiple conductive pads 30 overlapping the same lead wire 20 , the multiple conductive pads 30 are arranged along the extension direction of the lead wire 20 and the distance between adjacent conductive pads 30 is d, d≥2.5 μm.

[0211] When the distance between two adjacent conductive pads 30 overlapping the same lead-out wire 20 is greater than or equal to 2.5 μm, the first insulating layer 40 will form an effective electrostatic release weak point P1 on the adjacent side walls of the two conductive pads 30, thereby avoiding the risk of significant thinning of the thickness of the first insulating layer 40 located between the two conductive pads 30.

[0212] In a technical solution corresponding to these embodiments, as Fig.32 and Fig.34 As shown, at least two conductive pads 30 overlapping and adjacent to the same lead-out wire 20 are separately arranged, that is, there may be no connection relationship between these conductive pads 30 .

[0213] Fig.35 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in Fig.36 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0214] In a technical solution corresponding to these embodiments, at least two conductive pads 30 that overlap and are adjacent to the same lead-out wire 20 are connected. Fig.35 and Fig.36 As shown, adjacent conductive pads 30 among a plurality of conductive pads 30 overlapping the same lead wire 20 are connected. When the conductive pads 30 are connected, they are more likely to become a path for static electricity on the lead wire 20 to be discharged.

[0215] like Fig.35 As shown, the connected conductive pads 30 may be U-shaped; Fig.36As shown, the connected conductive pads 30 may also be S-shaped. In addition, the connected conductive pads 30 may also be other shapes.

[0216] Fig.37 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0217] In one embodiment of the present application, Fig.37 As shown, the lead wire 20 includes branch wires 200 extending in different directions, and in a direction perpendicular to the plane where the display substrate 01 is located, the branch wires 200 overlap with the conductive pad 30. In the embodiment of the present application, the lead wire 20 is a structure including a plurality of branch wires 200 respectively overlapping with the conductive pad 30, wherein each branch wire 200 can become a path for static electricity release in the lead wire 20 and can obtain more weak points P1, which is conducive to the release of static electricity on the lead wire 20.

[0218] It should be noted that the branch wires 200 included in the same lead wire 20 may overlap with different conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located. In addition, the branch wires 200 included in the same lead wire 20 may also overlap with the same conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, for example, Fig.37 As shown, the lead wire 20 includes three branch wires 200 and the three branch wires 200 overlap with the same conducting pad 30 .

[0219] In some embodiments of the present application, at least some of the lead wires 20 may be located in different conductive film layers, which can reduce the pressure of setting too many lead wires 20 in the same conductive film layer and avoid the risk of short circuit between adjacent lead wires 20.

[0220] In one implementation, at least two lead wires transmitting different signals are located in different conductive film layers, for example, the lead wire 20 transmitting the data voltage and the lead wire 20 transmitting the power supply voltage are located in different conductive film layers. When the lead wires 20 transmitting different signals are located in different film layers, signal crosstalk between the lead wires 20 transmitting different signals can be reduced.

[0221] In addition, when the lead wire 20 includes branch wires 200, the space occupied by the lead wires 20 increases, and the distance between adjacent lead wires 20 in the direction parallel to the plane where the display substrate 01 is located decreases. At this time, the adjacent branch wires 200 are arranged in different conductive film layers, which can reduce the risk of short circuit, and also reduce the risk of short circuit of the lead wires 20.

[0222] Fig.38 for Figure 1 and Figure 2A detailed schematic diagram of a local area in the figure.

[0223] In one embodiment of the present application, Fig.38 As shown, the conductive pad 30 includes a first surface in contact with the first insulating layer 40, and the shape of the first surface includes at least one vertex 30a. Fig.38 As shown, the orthographic projection of the first surface on the substrate 10 is a hexagon, and the first surface includes six vertices 30a. In this embodiment, along a direction perpendicular to the plane where the display substrate 01 is located, the lead wire 20 overlaps with at least one vertex 30a.

[0224] When the surface of the conductive pad 30 in contact with the first insulating layer 40 includes a vertex 30a, the thickness of the first insulating layer 40 near the vertex 30a is thinner when climbing near the vertex 30a, forming a weak point P1 that is easier to release static electricity; and when the lead wire 20 overlaps with at least one vertex 30a, the lead wire 20 overlaps with more side wall positions of the conductive pad 30, that is, more weak points P1 can be obtained.

[0225] Fig.39 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in Fig.40 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0226] In a technical solution corresponding to this embodiment, the lead wire 20 covers the conductive pad 30 in a direction perpendicular to the plane of the display substrate 01. In this technical solution, the lead wire 20 overlaps all sidewall positions of the conductive pad 30, that is, a considerable number of weak points P1 can be obtained.

[0227] In addition, when the shape of the first surface of the conductive wire 30 is a polygon, the shape of the first surface may be as follows: Fig.39 The shape of the first surface shown is a hexagon or can also be Fig.40 The figure shows a quadrilateral. In this case, the first surface includes a plurality of vertices 30a and the lead wires 20 cover the conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, so that more weak points P1 that are easier to release static electricity can be obtained.

[0228] Fig.41 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0229] In some embodiments of the present application, Fig.41As shown, the lead wire 20 includes a third lead portion 23 and a fourth lead portion 24, the third lead portion 23 is located on the side of the fourth lead portion 24 close to the edge of the display substrate 01; the width of the third lead portion 23 in a direction perpendicular to the extension direction of the lead wire 20 is smaller than the width of the fourth lead portion 24 in a direction perpendicular to the extension direction of the lead wire 20. The extension direction of the lead wire 20 is substantially parallel to the arrangement direction between the first region R1 where it is located and the connected second region R2. Fig.41 As shown, the width of the third lead-out portion 23 is W1 and the width of the fourth lead-out portion 24 is W2, W1<W2.

[0230] A considerable part of the static electricity in the display substrate 01 diffuses from the edge of the display substrate 01 to the inside. In this embodiment, the width of the third lead-out portion 23 closer to the edge of the display substrate 01 is smaller, which is convenient for the static electricity to be released in the third lead-out portion 23, that is, the static electricity is released at a position closer to the edge of the display substrate 01, thereby effectively protecting the functional components in the display substrate 01. In addition, the width of the fourth lead-out portion 24 farther from the edge of the display substrate 01 is larger, which is convenient for the reliability of the signal on the functional signal line 20' transmitted via the lead-out wire 20. In particular, when it is necessary to grind the display substrate 01, the grinding position is located at the edge of the display substrate 01. Therefore, the static electricity density near the position close to the edge of the display substrate 01 is higher, and the technical solution of this embodiment can effectively release this part of the static electricity.

[0231] In a technical solution corresponding to this embodiment, at least the third lead portion 23 of the lead wire 20 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located. In one implementation, Fig.41 As shown, the third lead portion 23 of the lead wire 20 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the fourth lead portion 24 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located. In one implementation, only the third lead portion 23 of the lead wire 20 overlaps with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the fourth lead portion 24 does not overlap with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0232] Fig.42 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0233] like Fig.42As shown, the first region R1 of the display substrate 01 may include a first sub-region R11 and a second sub-region R12, and the second sub-region R12 is located between the first sub-region R11 and the second region R2, so the first sub-region R11 is closer to the edge of the display substrate 01 than the second sub-region R12. Wherein, under the premise of taking into account the process yield, process difficulty and electrostatic protection effect, the conductive pads 30 in the first sub-region R11 and the second sub-region R12 can be differently arranged.

[0234] In some embodiments, Fig.42 As shown, the density of the conductive pads 30 in the first sub-region R11 is greater than the density of the conductive pads 30 in the second sub-region R12. Then, among the portions of the lead wire 20 located in the first sub-region R11 and the portions located in the second sub-region R12, the number density of the conductive pads 30 overlapped by the portions located in the first sub-region R11 is greater than the number density of the conductive pads 30 overlapped by the portions located in the second sub-region R12. The number density of the conductive pads 30 overlapped by different portions of the lead wire 20 refers to the number of conductive pads 30 overlapped by different portions of the lead wire 20 per unit length in the extension direction of the lead wire 20. For example, Fig.42 As shown, the first sub-region R11 and the second sub-region R12 are arranged along the column direction and the lead-out wire 20 extends along the column direction, wherein the length of the lead-out wire 20 extending along the column direction in the first sub-region R11 is substantially the same as the length of the lead-out wire 20 extending along the column direction in the second sub-region R12, the lead-out wire 20 overlaps with two conductive pads 30 in the first sub-region R11 and overlaps with one conductive pad 30 in the second sub-region R12.

[0235] In this embodiment, by setting the density of the conductive pads 30 in the first sub-region R11 to be greater than the density of the conductive pads 30 in the second sub-region R12, the number of weak points P1 in the first sub-region R11 closer to the edge of the display substrate 01 is greater, which facilitates the release of static electricity in the first sub-region R11, that is, static electricity is released at a position closer to the edge of the display substrate 01, thereby effectively protecting the functional components in the display substrate 01. In particular, when the display substrate 01 needs to be ground, the grinding position is located at the edge of the display substrate 01, so the static electricity density near the position close to the edge of the display substrate 01 is higher, and the technical solution of this embodiment can effectively release this part of static electricity.

[0236] Fig.43 A schematic cross-sectional view of a local area of ​​a display substrate provided in an embodiment of the present application.

[0237] In some embodiments, Fig.43As shown, the sidewall inclination angle α1 of the conductive pad 30 in the first sub-region R11 is greater than the sidewall inclination angle α2 of the conductive pad 30 in the second sub-region R12. Therefore, the weak point P1 formed by the overlap of the first insulating layer 40 and the lead wire 20 with the conductive pad 30 in the first sub-region R11 is more likely to become a sacrificial point for electrostatic discharge than the weak point P1 formed by the overlap of the first insulating layer 40 and the lead wire 20 with the conductive pad 30 in the second sub-region R12.

[0238] In this embodiment, by setting the sidewall inclination angle α1 of the conductive pad 30 in the first sub-region R11 to be greater than the sidewall inclination angle α2 of the conductive pad 30 in the second sub-region R12, the weak point P1 in the first sub-region R11 closer to the edge of the display substrate 01 is more likely to release static electricity, which is convenient for static electricity to be released in the first region R11, that is, static electricity is released at a position closer to the edge of the display substrate 01, thereby effectively protecting the functional components in the display substrate 01. In particular, when the display substrate 01 needs to be ground, the grinding position is located at the edge of the display substrate 01. Therefore, the static electricity density near the position close to the edge of the display substrate 01 is higher, and the technical solution of this embodiment can effectively release this part of static electricity.

[0239] Fig.44 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0240] During the simulation experiment of the present application, the inventor found that in the overlapping area between the lead-out wire 20 and the conductive pad 30, the probability of static electricity being released near the corner of the overlapping area is greater than the probability of static electricity being released at other positions. The weak point P1 near the corner of the overlapping area is called the obvious weak point P10.

[0241] In order to increase the number of obvious weak points P10, in one embodiment of the present application, as Fig.44 As shown, the lead wire 20 includes a hollow portion 20a and a solid portion 20b located outside the hollow portion 20a. In a direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a and part of the solid portion 20b located outside the hollow portion 20a overlap with the same conductive pad 30. The number of solid portions 20b overlapping with the conductive pad 30 in the same lead wire 20 increases, and the number of obvious weak points P10 corresponding to the overlap of the solid portion 20b and the conductive pad 30 increases, which can increase the electrostatic discharge capability of the display substrate 01.

[0242] Fig.45 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0243] In a technical solution corresponding to this embodiment, as Fig.45 As shown, in the direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a overlaps with at least two conductive pads 30, and the solid portions 20b on both sides of the hollow portion 20a also overlap with at least two conductive pads 30 in the direction perpendicular to the plane where the display substrate 01 is located, so as to increase the number of obvious weak points P10. In addition, in the present technical solution, the hollow portion 20a overlaps with at least two conductive pads 30, so the preparation difficulty of the hollow portion 20a is relatively small.

[0244] Fig.46 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0245] In a technical solution corresponding to this embodiment, as Fig.46 As shown, the lead wire 20 includes a third lead portion 23 and a fourth lead portion 24, wherein the third lead portion 23 is located on a side of the fourth lead portion 24 close to the edge of the display substrate 01, wherein the third lead portion 23 and the fourth lead portion 24 both include a hollow portion 20a. In a direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a included in the third lead portion 23 and the hollow portion 20a included in the fourth lead portion 24 overlap with different conductive pads 30 respectively.

[0246] In the present technical solution, the solid parts 20b located on both sides of the at least two hollow parts 20a in the lead wire 20 overlap with the conductive pad 30, so the number of weak points P10 can be significantly reduced. In addition, the hollow parts 20a overlapping with different conductive pads 30 are not connected, so the impedance of the lead wire 20 is small and the process yield is good.

[0247] Fig.47 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0248] In a technical solution corresponding to this embodiment, as Fig.47 As shown, the lead wire 20 includes a third lead portion 23 and a fourth lead portion 24, wherein the third lead portion 23 is located on a side of the fourth lead portion 24 close to the edge of the display substrate 01, wherein the third lead portion 23 includes a hollow portion 20a and the fourth lead portion 24 does not include the hollow portion 20a. In a direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a included in the third lead portion 23 overlaps with the conductive pad 30 and the fourth lead portion 24 overlaps with the conductive pad 30.

[0249] In the present technical solution, only the hollow portion 20b is provided on the third lead-out portion 23, so the preparation difficulty of the hollow portion 20b is relatively small. In addition, the hollow portion 20b on the lead-out wire 20 is located on the third lead-out portion 23 closer to the edge of the display substrate 01. Therefore, more obvious weak points P10 are obtained at the edge position closer to the display substrate 01, which facilitates the release of static electricity at a position closer to the edge of the display substrate 01, thereby effectively protecting the functional components in the display substrate 01. In particular, when the display substrate 01 needs to be ground, the grinding position is located at the edge of the display substrate 01. Therefore, the static electricity density near the position close to the edge of the display substrate 01 is higher, and the technical solution of this embodiment can effectively release the static electricity in this part.

[0250] Fig.48 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0251] In a technical solution corresponding to this embodiment, as Fig.48 As shown, the lead wire 20 includes a third lead portion 23 and a fourth lead portion 24, wherein the third lead portion 23 is located on a side of the fourth lead portion 24 close to the edge of the display substrate 01, wherein the third lead portion 23 and the fourth lead portion 24 both include hollow portions 20a. In the present technical solution, the number of hollow portions 20a included in the third lead portion 23 is greater than the number of hollow portions 20a included in the fourth lead portion 24. For example, Fig.48 As shown, the third lead-out portion 23 includes two hollow portions 20 a and the fourth lead-out portion 24 includes one hollow portion 20 a.

[0252] In the present technical solution, the third lead-out portion 23 at the edge position closer to the display substrate 01 includes more hollow portions 20b, which makes it possible to obtain more obvious weak points P10 at the edge position closer to the display substrate 01, so that static electricity can be released at a position closer to the edge of the display substrate 01, thereby effectively protecting the functional components in the display substrate 01. In particular, when the display substrate 01 needs to be ground, the grinding position is located at the edge of the display substrate 01. Therefore, the static electricity density near the position close to the edge of the display substrate 01 is higher, and the technical solution of this embodiment can effectively release the static electricity of this part. In addition, the fourth lead-out portion 24 at the edge position farther away from the display substrate 01 also includes a hollow portion 20b. On the one hand, there can be more obvious weak points P10 at the position where the lead-out wire 20 overlaps with the conductive pad 30; on the other hand, it is avoided that too many hollow portions 20b on the lead-out wire 20 cause the impedance of the lead-out wire 20 to increase significantly and the yield to decrease.

[0253] Fig.49 for Figure 1 and Figure 2A detailed schematic diagram of a local area in the figure.

[0254] In a technical solution corresponding to this embodiment, as Fig.49 As shown, in a direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a overlaps with the edge of the conductive pad 30 extending along the first direction X, and the hollow portion 20a overlaps with the edge of the conductive pad 30 extending along the second direction Y. The first direction X and the second direction Y are both parallel to the plane where the display substrate 01 is located, and the first direction X intersects with the second direction Y. In addition, since part of the solid portion 20b outside the hollow portion 20a overlaps with the same conductive pad 30, the solid portion 20b outside the hollow portion 20a overlapping with the edges of the conductive pad 30 extending in different directions also overlaps with the edges extending in different directions, so that more obvious weak points P10 can be obtained.

[0255] For example, Fig.49 As shown, when the hollow portion 20a overlaps with the edge of the conductive pad 30 extending along the first direction X, and the solid portion 20b outside the hollow portion 20a also overlaps with the edge of the conductive pad 30 extending along the first direction X, the edge of the hollow portion 20a and the edge of the conductive pad 30 extending along the first direction X intersect near the position where the edge is obvious weak point P10; and when the hollow portion 20a overlaps with the edge of the conductive pad 30 extending along the second direction YY, and the solid portion 20b outside the hollow portion 20a also overlaps with the edge of the conductive pad 30 extending along the second direction YY, the edge of the hollow portion 20a and the edge of the conductive pad 30 extending along the second direction YY intersect near the position where the edge is obvious weak point P10.

[0256] In one implementation, Fig.49 As shown, the hollow portion 20a overlapping the edges of the conductive pad 30 extending in different directions may be a connected structure. For example, the shape of the hollow portion 20a may be a "cross".

[0257] Fig.50 for Figure 1 and Figure 2 A detailed schematic diagram of a local area in the figure.

[0258] In one implementation, Fig.50 As shown, the hollow portion 20a overlapping the edge extending in different directions in the conductive pad 30 is not connected. Fig.50 In the middle, the left and right hollow portions 20a overlap with the edge of the conductive pad 30 extending along the second direction Y, and the upper and lower hollow portions 20a overlap with the edge of the conductive pad 30 extending along the first direction X.

[0259] Fig.51 A schematic diagram of an overlap of lead wires and conductive pads in a display substrate provided in an embodiment of the present application.

[0260] In a technical solution corresponding to this embodiment, as Fig.51 As shown, the lead wire 20 includes a plurality of entity parts 20b arranged along a third direction Z. The plurality of entity parts 20b include a first entity part 20b1 and a second entity part 20b2, the first entity part 20b1 is located on both sides of the second entity part 20b2, and the width of the first entity part 20b1 along the third direction Z is smaller than the width of the second entity part 20b2 along the third direction Z.

[0261] For example, Fig.51 As shown, the lead wire 20 includes two hollow portions 20a arranged along the third direction Z, and the two hollow portions 20a divide three solid portions 20b arranged along the third direction Z. The outer solid portion 20b is referred to as the first solid portion 20b1 and the inner solid portion 20b is referred to as the second solid portion 20b2. The widths of the two outer first solid portions 20b1 along the third direction Z are both smaller than the width of the inner second solid portion 20b2.

[0262] In one implementation, Fig.51 As shown, the third direction Z may be substantially perpendicular to the extending direction of the lead wire 20 .

[0263] In the present technical solution, the width of the outer solid portion 20b is narrower, so that the static electricity on the lead-out conductor 20 can be more easily released at the edge of the lead-out conductor 20; in addition, the width of the inner solid portion 20b is wider, and the design of the inner solid portion 20b with a larger width makes the impedance of the lead-out conductor 20 smaller and the process yield better.

[0264] Fig.52 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0265] In one embodiment of the present application, Fig.52 As shown, the display substrate 01 includes a first signal line L1, a second signal line L2 and a third signal line L2, the first signal line L1 is used to transmit a pulse signal, the second signal line L2 is used to transmit a data voltage and the third signal line L2 is used to transmit a fixed voltage signal. That is, part of the functional signal line 20' is the first signal line L1, part of the functional signal line 20' is the second signal line L2 and part of the functional signal line 20' is the third signal line L3.

[0266] For example, the first signal line L1 is a shift register that transmits a clock signal, and / or the first signal line L1 is a multiplexer that transmits a clock signal, etc. For example, the second signal line L2 is a pixel driving circuit that transmits a data voltage, or a pixel switch transistor that transmits a data voltage, etc. For example, the third signal line L2 is a shift register that transmits a power supply voltage, and / or the third signal line L2 is a pixel circuit that transmits a power supply voltage, a reset voltage, etc.

[0267] Fig.53 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0268] Combination Fig.52 and Fig.53 In order to ensure that the first signal line L1, the second signal line L2, and the third signal line L2 respectively receive the signals transmitted by them during the performance test phase of the display substrate 01, part of the lead-out wires 20 are the first lead-out wires 201, part of the lead-out wires 20 are the second lead-out wires 202, and part of the lead-out wires 20 are the third lead-out wires 203. The first lead-out wire 201 is electrically connected to the first signal line L1, the second lead-out wire 202 is electrically connected to the second signal line L2, and the third lead-out wire 203 is electrically connected to the third signal line L2.

[0269] Along the direction perpendicular to the plane where the display substrate 01 is located, at least one of the first lead wire 201, the second lead wire 202, and the third lead wire 203 overlaps with the conductive pad 30. Fig.52 and Fig.53 As shown, the first lead wire 201 , the second lead wire 202 and the third lead wire 203 all overlap with the conducting pad 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0270] The first signal line L1, the second signal line L2, and the third signal line L3 have different requirements for electrostatic protection. For example, the types of signals transmitted by the first signal line L1, the second signal line L2, and the third signal line L3 are obviously different, and the signals transmitted on these signal lines are different in sensitivity to electrostatic interference; the structural differences between the first signal line L1, the second signal line L2, and the third signal line L3 may also lead to different sensitivities to static electricity, etc. Based on the different requirements for electrostatic protection of the first signal line L1, the second signal line L2, and the third signal line L3, the number and structure of the weak points P1 corresponding to the first lead wire 201, the second lead wire 202, and the third lead wire 203 can be designed differently.

[0271] Fig.54 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0272] In a technical solution corresponding to the present embodiment, along a direction perpendicular to the plane where the display substrate 01 is located, the first lead wire 201 and the second lead wire 202 both overlap with the conductive pads 30, and the number of conductive pads 30 overlapped by the first lead wire 201 is greater than the number of conductive pads 30 overlapped by the second lead wire 202. Therefore, the number of conductive pads 30 overlapped by the lead wire 20 for transmitting a pulse signal for the first signal line L1 is greater than the number of conductive pads 30 overlapped by the lead wire 20 for transmitting a data voltage for the second signal line L2.

[0273] For example, Fig.53 As shown, the first lead wire 201 overlaps with three conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the second lead wire 202 overlaps with two conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0274] In the present technical solution, the accuracy of the pulse signal has a great influence on the display drive of the display substrate 01. Therefore, the requirements for the signal transmitted on the first signal line L1 are high, and static interference should be avoided as much as possible. In addition, the risk of the voltage change of the pulse signal breaking through the insulating layer is relatively large. If static electricity is superimposed, the risk of the first signal line L1 breaking through the insulating layer is further increased. In summary, the first signal line L1 has a higher requirement for electrostatic protection. By setting more conductive pads 30 overlapping with the first lead wire 201, the stability of the signal transmitted by the first signal line L1 can be effectively guaranteed.

[0275] The data voltage is also a changing signal. Although its changing frequency is lower than that of the pulse signal, it is also more susceptible to static electricity and further affects the display driving performance of the display substrate 01. Therefore, the second lead wire 202 can also overlap with the conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located, so as to reduce the influence of static electricity on the signal transmitted on the second signal line L2.

[0276] In addition, the signal transmitted by the third signal line L3 is less seriously affected by static electricity than the signal transmitted by the first signal line L1 and the second signal line L2. For example, when the third signal line L3 is used to transmit the power supply voltage required by the pixel circuit, the third signal line L3 transmitting the power supply voltage is usually electrically connected on the entire surface, that is, the third signal lines L3 at different positions are electrically connected together, and the signal transmitted by it is less affected by static electricity.

[0277] In one implementation, Fig.54 As shown, the third lead wire 203 has no overlap with the conducting pad 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0278] Fig.55 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0279] In one implementation, Fig.55 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the third lead wire 203 also overlaps with the conductive pad 30, and the number of conductive pads 30 overlapped by the second lead wire 202 is greater than the number of conductive pads 30 overlapped by the third lead wire 203. Then, the number of conductive pads 30 overlapped by the third lead wire 203 is less than the number of conductive pads 30 overlapped by the first lead wire 201 and less than the number of conductive pads overlapped by the second lead wire 202.

[0280] For example, Fig.55 As shown, the first lead wire 201 overlaps with three conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, the second lead wire 202 overlaps with two conductive pads 30 in a direction perpendicular to the plane where the display substrate 01 is located, and the third lead wire 203 overlaps with one conductive pad 30 in a direction perpendicular to the plane where the display substrate 01 is located.

[0281] In one implementation, Fig.54 and Fig.55 As shown, the width of the conductive pad 30 overlapping the first lead wire 201 along the extension direction of the first lead wire 201 is smaller than the width of the conductive pad 30 overlapping the second lead wire 202 along the extension direction of the second lead wire 202. Wherein, the conductive pad 301 overlapping the first lead wire 201 is the first conductive pad 301, and the conductive pad 302 overlapping the second lead wire 202 is the second conductive pad 302, then the width of the first conductive pad 301 in the extension direction of the lead wire 20 overlapping with it is smaller than the width of the second conductive pad 301 in the extension direction of the lead wire 20 overlapping with it.

[0282] For example, Fig.54 and Fig.55 As shown, the lead wires 20 all extend along the column direction, and the three first conductive pads 301 overlapping the first lead wires 201 are also arranged along the column direction, and the two second conductive pads 302 overlapping the second lead wires 202 are also arranged along the column direction, wherein the width of the first conductive pads 301 along the column direction is smaller than the width of the second conductive pads 302 along the column direction.

[0283] When the number of conductive pads 30 overlapped by the first lead-out wire 201 is greater than the number of conductive pads 30 overlapped by the second lead-out wire 202, the width of the first conductive pad 301 overlapping with the first lead-out wire 201 along its arrangement direction is smaller than the width of the first conductive pad 301 overlapping with the second lead-out wire 202 along its arrangement direction. In this way, more conductive pads 30 overlapping with the first lead-out wire 201 can be arranged in a smaller space without increasing the number of first lead-out wires 201, so that the first region R1 has a smaller width.

[0284] In addition, if Fig.55 As shown, when the number of conductive pads 30 overlapped by the second lead-out wire 202 is greater than the number of conductive pads 30 overlapped by the third lead-out wire 203, the width of the second conductive pad 302 overlapping with the second lead-out wire 202 in the extension direction of the second lead-out wire 202 may also be smaller than the width of the third conductive pad 302 overlapping with the third lead-out wire 203 in the extension direction of the third lead-out wire 203.

[0285] Fig.56 for Fig.54 A schematic cross-sectional view along the D1-D2 direction.

[0286] In a technical solution corresponding to this embodiment, as Fig.56 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the first lead wire 201 and the second lead wire 202 both overlap with the conductive pad 30, and the side wall inclination angle of the conductive pad 30 overlapping with the first lead wire 201 is greater than the side wall inclination angle of the conductive pad 30 overlapping with the second lead wire 202. Fig.56 As shown, the inclination angle of the sidewall of the first conducting pad 301 is greater than the inclination angle of the sidewall of the second conducting pad 302 .

[0287] When the sidewall inclination angle of the first conductive pad 301 is larger, static electricity on the first lead wire 201 can be released more easily. In addition, when the sidewall inclination angle of the second conductive pad 302 is smaller than the sidewall inclination angle of the first conductive pad 301, the risk of the second lead wire 202 being disconnected at the position where the sidewall of the second conductive pad 302 overlaps can be reduced, which reduces the probability of disconnection of all lead wires 20.

[0288] Fig.57 for Fig.55 A schematic cross-sectional view along the F1-F2 direction.

[0289] In one implementation, Fig.57As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the third lead wire 203 also overlaps with the conductive pad 30, and the side wall inclination angle of the conductive pad 30 overlapping with the second lead wire 202 is greater than the side wall inclination angle of the conductive pad 30 overlapping with the third lead wire 203. Fig.57 As shown, the sidewall inclination angle of the first conducting pad 301 is greater than the sidewall inclination angle of the second conducting pad 302 , and the sidewall inclination angle of the second conducting pad 302 is greater than the sidewall inclination angle of the third conducting pad 303 .

[0290] Fig.58 for Fig.54 Another cross-sectional schematic diagram along the D1-D2 direction.

[0291] In a technical solution corresponding to this embodiment, as Fig.58 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the first lead wire 201 and the second lead wire 202 both overlap with the conductive pad 30, and the height of the conductive pad 30 overlapping with the first lead wire 201 is greater than the height of the conductive pad 30 overlapping with the second lead wire 202. Fig.58 As shown, the height of the first conducting pad 301 is greater than the height of the second conducting pad 302 .

[0292] When the height of the first conductive pad 301 is greater, static electricity on the first lead wire 201 can be released more easily. In addition, when the height of the second conductive pad 302 is smaller than that of the first conductive pad 301, the risk of disconnection at the overlapping position of the second lead wire 202 and the second conductive pad 302 can be reduced, which reduces the probability of disconnection of the lead wire 20 among all the lead wires 20.

[0293] Fig.59 for Fig.55 Another cross-sectional schematic diagram along the F1-F2 direction.

[0294] In one implementation, Fig.59 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the third lead wire 203 also overlaps with the conductive pad 30, and the height of the conductive pad 30 overlapping with the second lead wire 202 is greater than the height of the conductive pad 30 overlapping with the third lead wire 203. Fig.59 As shown, the height of the first conducting pad 301 is greater than the height of the second conducting pad 302 and the inclination angle of the sidewall of the second conducting pad 302 is greater than the inclination angle of the sidewall of the third conducting pad 303 .

[0295] Fig.60 for Fig.54 Another cross-sectional schematic diagram along the D1-D2 direction.

[0296] In a technical solution corresponding to this embodiment, as Fig.60 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the first lead wire 201 and the second lead wire 202 both overlap with the conductive pad 30, and the thickness of the insulating layer between the first lead wire 201 and the overlapping conductive pad 30 is less than the thickness of the insulating layer between the second lead wire 202 and the overlapping conductive pad 30. Fig.60 As shown, the thickness of the first insulating layer 40 between the first lead wire 201 and the first conducting pad 301 is smaller than the thickness of the first insulating layer 40 between the second lead wire 202 and the second conducting pad 302 .

[0297] When the thickness of the insulating layer 40 between the first lead wire 201 and the first conducting pad 301 is smaller, static electricity on the first lead wire 201 can be released more easily.

[0298] Fig.61 for Fig.55 Another cross-sectional schematic diagram along the F1-F2 direction.

[0299] In one implementation, Fig.61 As shown, along the direction perpendicular to the plane where the display substrate 01 is located, the third lead wire 203 also overlaps with the conductive pad 30, and the thickness of the insulating layer between the second lead wire 202 and the overlapping conductive pad 30 is less than the thickness of the insulating layer between the third lead wire 203 and the overlapping conductive pad 30. Fig.59 As shown, the thickness of the first insulating layer 40 between the first lead-out wire 201 and the first conductive pad 301 is less than the thickness of the first insulating layer 40 between the second lead-out wire 202 and the second conductive pad 302, and the thickness of the first insulating layer 40 between the second lead-out wire 202 and the second conductive pad 302 is less than the thickness of the first insulating layer 40 between the third lead-out wire 203 and the third conductive pad 303.

[0300] Fig.62 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0301] In a technical solution corresponding to this embodiment, as Fig.62 As shown, the first lead wire 201 includes a hollow portion 20a and a solid portion 20b located outside the hollow portion 20a, and in a direction perpendicular to the plane where the display substrate 01 is located, the hollow portion 20a and part of the solid portion 20b located outside the hollow portion 20a overlap with the same conductive pad 30. This technical solution can improve the electrostatic discharge efficiency on the first lead wire 201.

[0302] Fig.63 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0303] In one implementation, Fig.63 As shown, the second lead wire 202 includes a hollow portion 20a and a solid portion 20b located outside the hollow portion 20a, and the number of the hollow portions 20a included in the first lead wire 201 is greater than the number of the hollow portions 20a included in the second lead wire 202. Fig.63 As shown, the first lead wire 201 includes three hollow portions 20 a and the second lead wire 202 includes two hollow portions 20 a.

[0304] When more hollow portions 20a are provided on the first lead wire 201, static electricity on the first lead wire 201 can be released more easily. In addition, when the number of hollow portions 20a provided on the first lead wire 201 is greater than the number of hollow portions 20a provided on the second lead wire 202, the risk of disconnection due to too many hollow portions 20a provided on the second lead wire 202 can be reduced, and the probability of disconnection of the lead wire 20 among all the lead wires 20 is reduced.

[0305] In one implementation, Fig.62 As shown, the second lead wire 202 may not include the hollow portion 20a.

[0306] Fig.64 A partial schematic diagram of a display substrate provided in an embodiment of the present application.

[0307] Alternatively, if Fig.64 As shown, the third lead wire 203 includes a hollow portion 20a and a solid portion 20b located outside the hollow portion 20a; the number of hollow portions 20a included in the second lead wire 202 is greater than the number of hollow portions 20a included in the third lead wire 203. Fig.64 As shown, the first lead wire 201 includes three hollow portions 20 a , the second lead wire 202 includes two hollow portions 20 a , and the third lead wire 203 includes one hollow portion 20 a .

[0308] Optionally, the third lead wire 203 may not include the hollow portion 20a.

[0309] Fig.65 A schematic diagram of a display device provided in an embodiment of the present application, Fig.66 A schematic diagram of a display device provided in an embodiment of the present application.

[0310] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.65 As shown, the display device includes the above-mentioned display substrate 01. Of course, Fig.65The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0311] Based on the same inventive concept, an embodiment of the present invention further provides a splicing display device, such as Fig.66 As shown, the display device is a spliced ​​display device including the above-mentioned display substrate 01. At least part of the first region R1 of the display substrate 01 can be its splicing side, and the splicing side is the side of the display substrate 01 spliced ​​with the adjacent display substrate 01. This type of spliced ​​display device can be a spliced ​​large screen, which can be used in public information display (Public Information Display, PID) scenes such as stations and airports. When the spliced ​​display device includes the above-mentioned display substrate 01, the antistatic ability of the device can be effectively improved, thereby improving the display effect of the spliced ​​display device.

[0312] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display substrate, characterized in that: The display substrate comprises a first area and a second area, wherein the first area is located on a side of the second area close to an edge of the display substrate; the second area comprises a plurality of first transistors, and the first transistors are electrically connected to the first electrode; the display substrate comprises: substrate; Leading wires, located in the first area; A conductive pad, the conductive pad is located between the film layer where the lead wire is located and the substrate; along a direction perpendicular to the plane where the display substrate is located, the conductive pad overlaps with the lead wire; A first insulating layer is located between the film layer where the conductive pad is located and the film layer where the lead wire is located, and the conductive pad and the lead wire include the first insulating layer.

2. The display substrate according to claim 1, characterized in that: The display substrate includes a first film layer, and the first film layer includes a first structure in the second area; The conductive pad includes at least a first portion, which is located in the first film layer; the thickness of the first portion in a direction perpendicular to the plane where the display substrate is located is greater than the thickness of the first structure in a direction perpendicular to the plane where the display substrate is located.

3. The display substrate according to claim 1, characterized in that: The display substrate includes a first film layer, and the first film layer includes a first structure in the second area; The conducting pad at least includes a first portion, and the first portion is located in the first film layer; the sidewall inclination angle of the first portion is greater than the sidewall inclination angle of the first structure.

4. The display substrate according to claim 1, characterized in that: The conductive pad includes a first part and a second part stacked in a direction perpendicular to a plane where the display substrate is located, the first part is a conductor or a semiconductor, and the second part is a conductor or a semiconductor.

5. The display substrate according to claim 1, characterized in that: The conductive pad comprises a first portion and a third portion stacked in a direction perpendicular to a plane where the display substrate is located, the first portion is a conductor or a semiconductor and the third portion is an insulator; The first portion is located on a side of the third portion close to the first insulating layer.

6. The display substrate according to claim 1, characterized in that: A surface of the conductive pad away from the substrate includes at least one protrusion.

7. The display substrate according to claim 1, characterized in that: The first insulating layer is an inorganic material film layer.

8. The display substrate according to claim 1, characterized in that: The display substrate further comprises a second insulating layer, wherein the second insulating layer is located between different conductive film layers; Along a direction perpendicular to a plane where the display substrate is located, a thickness of the first insulating layer is smaller than a thickness of the second insulating layer.

9. The display substrate according to claim 1, characterized in that: A thickness of a portion of the first insulating layer located between the conductive pad and the lead wire is smaller than a thickness of a portion of the first insulating layer located in the second region.

10. The display substrate according to claim 1, characterized in that: The display substrate further comprises: A switching electrode block is located in the first area; the switching electrode block includes at least two switching electrodes arranged in a direction perpendicular to the plane where the display substrate is located and located in different conductive film layers; the switching electrode block includes a first switching electrode, and the first switching electrode is located on a side of the other switching electrodes away from the substrate; The lead wire is electrically connected to the switching electrode block, and at least a portion of the lead wire and the first switching electrode are located in the same film layer.

11. The display substrate according to claim 10, characterized in that: The switching electrode block further includes a second switching electrode and a third switching electrode, wherein the second switching electrode and the third switching electrode are located on a side of the first switching electrode close to the substrate; The conducting pad includes a portion located in the same film layer as the second switching electrode and includes a portion located in the same film layer as the third switching electrode.

12. The display substrate according to claim 10, characterized in that: The display substrate further comprises a connecting electrode and an external electrode block, wherein the external electrode block and the transfer electrode block are located on different sides of the substrate; The connecting electrode is electrically connected to the switching electrode block and the external electrode block, and the connecting electrode is in contact with and connected to the lead wire.

13. The display substrate according to claim 10, characterized in that: The lead wire comprises a first lead portion and a second lead portion, the first lead portion is reused with the first switching electrode, and the second lead portion has no overlap with the switching electrode block in a direction perpendicular to the plane where the display substrate is located; At least a portion of the first lead-out portion overlaps the conducting pad in a direction perpendicular to a plane where the display substrate is located.

14. The display substrate according to claim 13, characterized in that: At least a portion of the second lead-out portion overlaps the conducting pad in a direction perpendicular to a plane where the display substrate is located.

15. The display substrate according to claim 1, characterized in that: The first transistor includes a semiconductor layer and a gate, and the first insulating layer is between the semiconductor layer and the gate; At least a portion of the conductive pad and the semiconductor layer are located in the same film layer, and at least a portion of the lead wire and the gate are located in the same film layer.

16. The display substrate according to claim 1, characterized in that: The first transistor includes a gate, the capacitor includes a first plate and a second plate, and the first plate and the gate are located in the same film layer; At least a portion of the conductive pad is located in the same film layer as the first electrode plate, and at least a portion of the lead wire is located in the same film layer as the second electrode plate.

17. The display substrate according to claim 1, characterized in that: The lead wire overlaps with at least two of the conducting pads in a direction perpendicular to the plane where the display substrate is located.

18. The display substrate according to claim 17, characterized in that: The distance between two adjacent conducting pads overlapping the same lead-out wire is greater than or equal to 2.5 μm.

19. The display substrate according to claim 17, characterized in that: At least two of the conductive pads that overlap and are adjacent to the same lead-out wire are connected.

20. The display substrate according to claim 17, characterized in that: The first region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; The inclination angle of the sidewall of the conductive pad in the first sub-region is greater than the inclination angle of the sidewall of the conductive pad in the second sub-region.

21. The display substrate according to claim 17, characterized in that: The first region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; The density of the conductive pads in the first sub-region is greater than the density of the conductive pads in the second sub-region.

22. The display substrate according to claim 1, characterized in that: At least part of the edges of at least part of the conducting pads away from the second region overlap with the edge of the display substrate, and / or at least part of the edges of the lead wires away from the second region overlap with the edge of the display substrate.

23. The display substrate according to claim 1, characterized in that: The lead wires include branch wires extending in different directions; Along a direction perpendicular to the plane where the display substrate is located, the branch wire overlaps the conducting pad.

24. The display substrate according to claim 1, characterized in that: The conductive pad comprises a first surface in contact with the first insulating layer, and the shape of the first surface comprises at least one vertex angle; Along a direction perpendicular to the plane where the display substrate is located, the lead wire overlaps with at least one of the vertex angles.

25. The display substrate according to claim 24, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the lead wire covers the conducting pad.

26. The display substrate according to claim 1, characterized in that: The lead-out wire includes a third lead-out portion and a fourth lead-out portion, the third lead-out portion is located on a side of the fourth lead-out portion close to an edge of the display substrate; the width of the third lead-out portion in a direction perpendicular to an extension direction of the lead-out wire is smaller than the width of the fourth lead-out portion in a direction perpendicular to the extension direction of the lead-out wire.

27. The display substrate according to claim 1, characterized in that: The lead wire includes a hollow portion and a solid portion located outside the hollow portion; in a direction perpendicular to the plane where the display substrate is located, the hollow portion and part of the solid portion located outside the hollow portion overlap with the same conducting pad.

28. The display substrate according to claim 27, characterized in that: In a direction perpendicular to the plane where the display substrate is located, the hollow portion overlaps with at least two of the conducting pads.

29. The display substrate according to claim 27, characterized in that: The lead wire includes a third lead portion and a fourth lead portion, the third lead portion is located on a side of the fourth lead portion close to the edge of the display substrate; the third lead portion includes the hollow portion and the fourth lead portion does not include the hollow portion; In a direction perpendicular to the plane where the display substrate is located, the hollow portion included in the third lead-out portion overlaps with the conductive pad, and the fourth lead-out portion overlaps with the conductive pad.

30. The display substrate according to claim 27, characterized in that The lead wire comprises a third lead portion and a fourth lead portion, wherein the third lead portion is located on a side of the fourth lead portion close to an edge of the display substrate; the third lead portion and the fourth lead portion both comprise a hollow portion; In a direction perpendicular to the plane where the display substrate is located, the hollow portion included in the third lead-out portion and the hollow portion included in the fourth lead-out portion overlap with different conducting pads respectively.

31. The display substrate according to claim 27, characterized in that The lead wire comprises a third lead portion and a fourth lead portion, wherein the third lead portion is located on a side of the fourth lead portion close to an edge of the display substrate; the third lead portion and the fourth lead portion both comprise a hollow portion; The number of the hollow portions included in the third lead-out portion is greater than the number of the hollow portions included in the fourth lead-out portion.

32. The display substrate according to claim 27, characterized in that: In a direction perpendicular to the plane where the display substrate is located, the hollow portion overlaps with an edge of the conductive pad extending along a first direction, and the hollow portion overlaps with an edge of the conductive pad extending along a second direction; the first direction and the second direction are both parallel to the plane where the display substrate is located and the first direction intersects with the second direction.

33. The display substrate according to claim 27, characterized in that: The lead-out wire includes a plurality of solid parts arranged along a third direction; the plurality of solid parts include a first solid part and a second solid part, the first solid part is located on both sides of the second solid part, and the width of the first solid part along the third direction is smaller than the width of the second solid part along the third direction.

34. The display substrate according to claim 1, characterized in that: The display substrate comprises a first signal line, a second signal line and a third signal line, the first signal line is used to transmit a pulse signal, the second signal line is used to transmit a data voltage and the third signal line is used to transmit a fixed voltage signal; Some of the lead wires are first lead wires, some of the lead wires are second lead wires, and some of the lead wires are third lead wires, the first lead wire is electrically connected to the first signal wire, the second lead wire is electrically connected to the second signal wire, and the third lead wire is electrically connected to the third signal wire; Along a direction perpendicular to a plane where the display substrate is located, at least one of the first lead-out wire, the second lead-out wire, and the third lead-out wire overlaps with the conducting pad.

35. The display substrate according to claim 34, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the first lead wire and the second lead wire both overlap with the conducting pad; The number of the conductive pads overlapped by the first lead-out wire is greater than the number of the conductive pads overlapped by the second lead-out wire.

36. The display substrate according to claim 35, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the third lead wire also overlaps with the conducting pad; The number of the conducting pads overlapped by the second lead wire is greater than the number of the conducting pads overlapped by the third lead wire.

37. The display substrate according to claim 35, characterized in that: The width of the conductive pad overlapping the first lead wire in the extending direction of the first lead wire is smaller than the width of the conductive pad overlapping the second lead wire in the extending direction of the second lead wire.

38. The display substrate according to claim 34, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the first lead wire and the second lead wire both overlap with the conducting pad; The inclination angle of the side wall of the conductive pad overlapping the first lead wire is greater than the inclination angle of the side wall of the conductive pad overlapping the second lead wire.

39. The display substrate according to claim 38, characterized in that Along a direction perpendicular to the plane where the display substrate is located, the third lead wire also overlaps with the conducting pad; The inclination angle of the side wall of the conducting pad overlapping the second lead wire is greater than the inclination angle of the side wall of the conducting pad overlapping the third lead wire.

40. The display substrate according to claim 34, characterized in that Along a direction perpendicular to the plane where the display substrate is located, the first lead wire and the second lead wire both overlap with the conducting pad; A height of the conductive pad overlapping the first lead wire is greater than a height of the conductive pad overlapping the second lead wire.

41. The display substrate according to claim 40, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the third lead wire also overlaps with the conducting pad; A height of the conductive pad overlapping the second lead wire is greater than a height of the conductive pad overlapping the third lead wire.

42. The display substrate according to claim 34, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the first lead wire and the second lead wire both overlap with the conducting pad; The thickness of the insulating layer between the first lead wire and the overlapping conductive pad is smaller than the thickness of the insulating layer between the second lead wire and the overlapping conductive pad.

43. The display substrate according to claim 42, characterized in that: Along a direction perpendicular to the plane where the display substrate is located, the third lead wire also overlaps with the conducting pad; The thickness of the insulating layer between the second lead wire and the overlapping conductive pad is smaller than the thickness of the insulating layer between the third lead wire and the overlapping conductive pad.

44. The display substrate according to claim 34, characterized in that The first lead wire includes a hollow portion and a solid portion located outside the hollow portion; in a direction perpendicular to the plane where the display substrate is located, the hollow portion and part of the solid portion located outside the hollow portion overlap with the same conducting pad.

45. The display substrate according to claim 44, characterized in that: The second lead wire includes a hollow portion and a solid portion located outside the hollow portion; the number of the hollow portions included in the first lead wire is greater than the number of the hollow portions included in the second lead wire.

46. ​​The display substrate according to claim 45, characterized in that The third lead wire includes a hollow portion and a solid portion located outside the hollow portion; the number of the hollow portions included in the second lead wire is greater than the number of the hollow portions included in the third lead wire.

47. The display substrate according to claim 1, characterized in that: The first area includes a first type of first area and a second type of first area; along the first arrangement direction, the first type of first area is located on one side of the second area; along the second arrangement direction, the second type of first area is located on one side of the second area; the first arrangement direction intersects with the second arrangement direction; The first-type first region and the second-type first region both include the lead wire and the conducting pad.

48. A display device, characterized in that: Comprising a display substrate as described in any one of claims 1-47.

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