Semiconductor structure, method of manufacturing a semiconductor structure, and electronic device

Abstract

The application relates to a semiconductor structure, a preparation method of the semiconductor structure and an electronic device. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a first circuit on the substrate, and forming a conductive interconnection structure on the first circuit, the conductive interconnection structure being electrically connected with the first circuit; forming a stack layer on the conductive interconnection structure, the stack layer comprising alternately stacked isolation layers and conductive layers, and forming a device through hole penetrating through the isolation layers and the conductive layers in the stack layer; sequentially forming a channel material layer, a gate dielectric material layer and a first word line material layer on the hole wall of the device through hole; forming a through hole penetrating through the first word line material layer, the gate dielectric material layer and the channel material layer at the bottom of the device through hole and extending to the conductive interconnection structure; and forming a second word line layer in the through hole and the device through hole above the through hole. The application can improve the integration degree and ensure the device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a preparation method of the semiconductor structure, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] Therefore, the embodiments of the present application provide a semiconductor structure which can improve the integration and ensure the performance of the devices, a preparation method of the semiconductor structure, and an electronic device.

[0005] A preparation method of a semiconductor structure includes:

[0006] providing a substrate;

[0007] forming a first circuit on the substrate, and forming a conductive interconnection structure on the first circuit, the conductive interconnection structure being electrically connected to the first circuit;

[0008] forming a stack layer on the conductive interconnection structure, the stack layer including alternatingly stacked isolation layers and conductive layers, and forming a device via penetrating the isolation layers and the conductive layers in the stack layer, a normal projection of the device via and the conductive interconnection structure on the substrate having an overlap;

[0009] forming, in sequence, a channel material layer, a gate dielectric material layer, and a first word line material layer on a hole wall of the device via;

[0010] forming the first word line material layer, the gate dielectric material layer, and the channel material layer penetrating the bottom of the device via and extending to a through hole of the conductive interconnection structure, the remaining first word line material layer forming a first word line layer, the remaining gate dielectric material layer forming a gate dielectric layer, and the remaining channel material layer forming a channel layer;

[0011] forming a second word line layer in the through hole and the remaining space in the device via.

[0012] The preparation method of the semiconductor structure can effectively save the chip area and improve the integration density of the device. Meanwhile, before the channel material layer is etched to form the through hole extending to the conductive interconnection structure, the channel material layer, the gate dielectric material layer and the first word line material layer are sequentially formed on the hole wall of the device via. Then, the first word line material layer, the gate dielectric material layer and the channel material layer are sequentially etched. At this time, the first word line layer formed by the first word line material layer remaining after etching can serve as a protective layer to protect the channel material layer from being damaged in the dry etching process. The first word line layer does not need to be removed, so the channel layer will not be damaged when the protective layer is removed, and thus the channel layer and the gate dielectric layer can be effectively protected, thereby ensuring the performance of the device.

[0013] In one of the embodiments, before the first word line material layer, the gate dielectric material layer and the channel material layer are formed to extend to the through hole of the conductive interconnection structure, the method further comprises:

[0014] At least partially etching the first word line material layer on the top of the device via.

[0015] In one of the embodiments, the forming of the stack layer on the conductive interconnection structure comprises:

[0016] forming a stack initial layer on the conductive interconnection structure, the stack initial layer comprising alternately stacked isolation material layers and sacrificial material layers;

[0017] forming a dummy word line hole extending through the stack initial layer, and forming a dummy word line in the dummy word line hole;

[0018] performing a patterning process on the stack initial layer after the dummy word line is formed, to form an isolation trench, the remaining isolation material layers forming the isolation layer, and the remaining sacrificial material layers forming a sacrificial layer;

[0019] etching and removing the sacrificial layer from the isolation trench;

[0020] forming the conductive material layer in the region where the sacrificial layer is removed, and forming a filling dielectric layer in the isolation trench;

[0021] removing the dummy word line, and laterally etching the conductive material layer from the dummy word line hole to form a lateral hole, the lateral hole and the dummy word line hole forming the device via, and the remaining conductive material layer forming the conductive layer.

[0022] In one of the embodiments, after the channel material layer, the gate dielectric material layer and the first word line material layer are sequentially formed on the hole wall of the device via, the lateral hole is filled.

[0023] In one of the embodiments,

[0024] Before forming the stack initial layer on the conductive interconnection structure, further comprising:

[0025] forming an insulating medium layer on the conductive interconnection structure;

[0026] The forming of the pseudo word line hole penetrating through the stack initial layer and the forming of the pseudo word line in the pseudo word line hole, comprising:

[0027] Taking the insulating medium layer as an etching stop layer, etching the stack initial layer to form a pseudo word line hole;

[0028] forming the pseudo word line in the pseudo word line hole.

[0029] In one of the embodiments, after the patterning of the stack initial layer after the forming of the pseudo word line to form an isolation trench, the stack initial layer has a first trunk part extending along a first direction and a first branch part located on at least one side of the first trunk part along a second direction, the pseudo word line penetrates through the first branch part, and the first direction and the second direction are intersected and both are parallel to the substrate.

[0030] In one of the embodiments, before the patterning of the stack initial layer after the forming of the pseudo word line to form an isolation trench, further comprising:

[0031] forming a support layer penetrating through the stack initial layer and extending along the first direction, the support layer being located on the side of the first branch part away from the first trunk part.

[0032] In one of the embodiments, the side of the pseudo word line away from the first trunk part has a capacitor region, the capacitor region being arranged spaced apart from the pseudo word line,

[0033] Before the removing of the pseudo word line and the lateral etching of the conductive material layer from the side of the pseudo word line hole to form the lateral hole, further comprising:

[0034] removing the isolation layer located in the capacitor region to expose the conductive material layer;

[0035] forming a capacitor medium layer and a capacitor outer electrode layer in sequence around the peripheral surface of the conductive material layer located in the capacitor region.

[0036] A semiconductor structure, comprising:

[0037] a substrate;

[0038] a first circuit located on the substrate;

[0039] a stack of layers on a side of the first circuit away from the substrate, the stack of layers comprising alternating layers of an insulating layer and a conductive layer;

[0040] a transistor structure comprising a channel layer, a gate dielectric layer, a first word line layer, and a second word line layer, the second word line layer extending through the stack of layers and electrically connected to the first circuit, the first word line layer being within the stack of layers and at least partially covering a sidewall of the second word line layer, the gate dielectric layer and the channel layer being within the stack of layers, the gate dielectric layer being on a side of the first word line layer away from the second word line layer, the channel layer being on a side of the gate dielectric layer away from the first word line layer and between the gate dielectric layer and the conductive layer.

[0041] The semiconductor structure described above has a first word line layer within the stack of layers, the first word line layer being between the second word line layer 5 and the gate dielectric layer. Thus, in the process of forming the second word line layer electrically connected to the first circuit, the first word line layer can well protect the channel layer and the gate dielectric layer, thereby improving the performance of the device.

[0042] In one embodiment, a bottom of the second word line layer on the substrate is surrounded by a bottom of the first word line layer on the substrate.

[0043] In one embodiment, the semiconductor structure further comprises a conductive interconnect structure between the first circuit and the stack of layers, the conductive interconnect structure electrically connecting the first circuit and the second word line layer.

[0044] In one embodiment, a bottom of the second word line layer on the substrate is within a top of the second word line layer on the substrate.

[0045] In one embodiment, the first word line layer has a protrusion projecting in a direction away from the second word line layer, the protrusion being between adjacent insulating layers and overlapping the conductive layer in a direction perpendicular to the substrate.

[0046] In one embodiment, the semiconductor structure further comprises an insulating dielectric layer on a side of the conductive interconnect structure away from the substrate, the stack of layers being on a side of the insulating dielectric layer away from the substrate, the second word line layer extending through the stack of layers and the insulating dielectric layer.

[0047] In one embodiment, the stack of layers has a second trunk portion extending in a first direction and a second branch portion on at least one side of the second trunk portion in a second direction, the transistor structure extending through the second branch portion, the first direction and the second direction being intersecting and both parallel to the substrate.

[0048] In one embodiment, the semiconductor structure further comprises:

[0049] A support layer is located on the side of the second branch part away from the second trunk part, and extends through the stacked layers and along the first direction.

[0050] In one embodiment, the side of the transistor structure away from the second trunk part has a capacitor region, which is spaced apart from the transistor structure, and which is provided with a capacitor dielectric layer and a capacitor outer electrode layer, the capacitor dielectric layer being located on the outer peripheral surface of the conductive layer, and the capacitor outer electrode layer being located on the outer peripheral surface of the capacitor dielectric layer.

[0051] An electronic device comprising the semiconductor structure described above. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the technical solutions in the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0053] Figure 1 A flow chart of the preparation method of the semiconductor structure provided in an embodiment;

[0054] Figures 2 to 14 A structure diagram of the structure obtained in each step of the preparation method of the semiconductor structure provided in an embodiment, wherein, Figure 11 is an enlarged view of the portion A in the dashed box in Figure 10 Figure 13 is an enlarged view of the portion B in the dashed box in Figure 12

[0055] Figure 15 A structure diagram of the semiconductor structure provided in an embodiment;

[0056] Figure 16 is an enlarged view of the portion C in the dashed box in Figure 15

[0057] Figure 17 is an enlarged view of the portion D in the dashed box in Figure 15

[0058] ​​​​Explanation of reference signs: 100 - substrate, 200 - first circuit, 300 - conductive interconnection structure, 310 - first interconnection structure, 320 - redistribution layer, 330 - second interconnection structure, 400 - stacked layer, 400a - second trunk portion, 400b - second branch portion, 410 - isolation layer, 4101 - isolation material layer, 420 - conductive layer, 4201 - conductive material layer, 4001 - initial layer of stacking, 4001a - first trunk portion, 4001b - first branch portion, 430 - sacrificial layer, 4301 - sacrificial material layer, 500 - transistor structure, 510 - channel layer, 5101 - channel material layer, 520 - gate dielectric layer, 5201 - gate dielectric material layer, 530 - first word line layer, 5301 - first word line material layer, 531 - protrusion, 540 - second word line layer, 550 - dummy word line, 610 - first dielectric layer, 620 - second dielectric layer, 630 - third dielectric layer, 640 - filled dielectric layer, 700 - insulating dielectric layer, 800 - support layer, 900 - capacitor, 910 - capacitor dielectric layer, 920 - capacitor outer electrode layer, 10 - device via, 11 - dummy word line hole, 12 - lateral hole, 13 - through hole, 20 - isolation trench, 30 - first photoresist, 40 - hard mask layer, 50 - third patterned photoresist. DETAILED DESCRIPTION

[0059] For the purpose of facilitating the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. In the drawings, embodiments of the present application are shown. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present application to those skilled in the art.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0061] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0062] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly.

[0063] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0064] In some embodiments, referring to Figure 1 , a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0065] In step S10, a substrate 100 is provided;

[0066] Step S20, forming a first circuit 200 on the substrate 100, and forming a conductive interconnection structure 300 on the first circuit 200, the conductive interconnection structure 300 electrically connecting the first circuit 200;

[0067] Step S30, forming a stack layer 400 on the conductive interconnection structure 300, the stack layer 400 comprising insulating layers 410 and conductive layers 420 alternately stacked, and forming a device via 10 penetrating the insulating layers 410 and the conductive layers 420 in the stack layer 400, a normal projection of the device via 10 and the conductive interconnection structure 300 on the substrate having an overlap;

[0068] Step S40, sequentially forming a channel material layer 5101, a gate dielectric material layer 5201 and a first word line material layer 5301 on a hole wall of the device via 10;

[0069] Step S60, forming the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 penetrating a bottom of the device via 10 and extending to the through hole 13 of the conductive interconnection structure 300, the remaining first word line material layer 5301 forming a first word line layer 530, the remaining gate dielectric material layer 5201 forming a gate dielectric layer 520, and the remaining channel material layer 5101 forming a channel layer 510;

[0070] Step S70, forming a second word line layer 540 in the through hole 13 and the remaining space in the device via 10.

[0071] In step S10, please refer to Figure 2 The substrate 100 can be a single-layer structure or a multi-layer structure. When the substrate 100 is a multi-layer structure, it can comprise a semiconductor substrate and other structures or film layers formed on the semiconductor substrate.

[0072] In step S20, please continue to refer to Figure 2 The first circuit 200 can be, for example, a peripheral logic circuit. The peripheral logic circuit can comprise a complementary metal-oxide-semiconductor (CMOS) circuit.

[0073] The conductive interconnection structure 300 can be formed in one or more layers of medium covering the first circuit 200, for electrically connecting the first circuit 200 and the subsequently formed second word line layer 540. At the same time, while forming the conductive interconnection structure 300 electrically connecting the first circuit 200 and the subsequently formed second word line layer 540, other conductive connection structures connecting the first circuit 200 and the bit lines and the capacitor outer electrode layer 920 of the storage array above it can also be formed.

[0074] As an example, please refer to Figures 2 to 3 Step S20 can comprise:

[0075] Step S21, forming a first circuit 200 on the substrate 100;

[0076] Step S22, forming a first interconnect structure 310 on the first circuit 200;

[0077] Step S23, forming a re-distribution layer 320 on the first interconnect structure 310;

[0078] Step S24, forming a second interconnect structure 330 on the re-distribution layer 320, the second interconnect structure 330, the re-distribution layer 320 and the first interconnect structure 310 form a conductive interconnect structure 300.

[0079] In step S21, the substrate 100 can include a semiconductor substrate and a shallow trench isolation structure, for example. At this time, when forming the first circuit 200 (such as a peripheral logic circuit), the semiconductor substrate can be doped to form a P-well region 110 and an N-well region 120. And a shallow trench isolation structure 130 can be formed in the semiconductor substrate. The shallow trench isolation structure can separate the semiconductor substrate into a plurality of active regions. The transistors in the first circuit 200 (such as the transistors in a CMOS circuit) can be formed based on the active regions.

[0080] In step S22, a first dielectric layer 610 can be first formed to cover the first circuit 200 and the substrate 100. Then a first interconnect structure 310 connected to the first circuit 200 can be formed through the first dielectric layer 610. The first interconnect structure 310 can be connected to one of the drain or source of a transistor in a CMOS circuit, for example.

[0081] In step S23, a second dielectric layer 620 can be first formed on the first dielectric layer 610 and the first interconnect structure 310. Then a trench can be formed through the second dielectric layer, and a conductive material can be filled in the trench to form a re-distribution layer 320 connected to the first interconnect structure 310 by a damascene process.

[0082] In step S24, a third dielectric layer 630 can be first formed on the second dielectric layer 620 and the re-distribution layer 320. Then a second interconnect structure 330 connected to the re-distribution layer 320 can be formed through the third dielectric layer 630. The second interconnect structure 330, the re-distribution layer 320 and the first interconnect structure 310 form a conductive interconnect structure 300, so that the conductive interconnect structure 300 is electrically connected to the first circuit 200.

[0083] Of course, the form of the conductive interconnection structure 300 is not limited herein. For example, the conductive interconnection structure 300 can also only include the first interconnection structure 310. Alternatively, when forming the re-distribution layer 320, the second dielectric layer 620 can not be formed. In this case, the re-distribution layer material layer can be formed first. Then, photolithography or other processes are performed to pattern the re-distribution layer material layer, thereby forming the re-distribution layer 320.

[0084] In step S30, referring to Figure 9 A stack layer 400 can be formed above the conductive interconnection structure 300 and the dielectric layer in which the conductive interconnection structure 300 is located. As an example, the top and bottom film layers of the stack layer 400 can both be the isolation layer 410, and the conductive layer 420 is located between the isolation layers 410.

[0085] The material of the isolation layer 410 can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON), etc.

[0086] The material of the conductive layer 420 can include, but is not limited to, tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc.

[0087] The device via 10 formed in the stack layer 400 can be used to form a transistor structure 500.

[0088] In step S40, referring to Figures 10 to 11 The channel material layer 5101 can be formed first on the hole wall of the device via 10 and the upper surface of the structure obtained in the previous process steps. Then, the gate dielectric material layer 5201 is formed on the surface of the channel material layer 5101. After that, the first word line material layer 5301 is formed on the surface of the gate dielectric material layer 5201.

[0089] In addition, the channel material layer 5101, the gate dielectric material layer 5201, and the first word line material layer 5301 can be formed by a deposition process, but are not limited to this. The deposition process can include, but is not limited to, a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process, etc.

[0090] Meanwhile, the material of the channel material layer 5101 can include, but is not limited to, indium gallium zinc oxide (IGZO), etc. The material of the gate dielectric material layer 5201 can include, but is not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3), etc. The material of the first word line material layer 5301 can include, but is not limited to, indium tin oxide (ITO), etc.

[0091] In step S60, referring to Figure 14 The first word line material layer 5301, the gate dielectric material layer 5201, and the channel material layer 5101 located at the bottom of the device trench can be etched away in sequence by dry etching, and a through hole 13 exposing the conductive interconnection structure 300 is formed. The through hole 13 communicates with the device via hole 10.

[0092] The first word line layer 530 formed by the first word line material layer 5301 remaining after etching can serve as a protective layer to protect the channel material layer 5101 from damage during dry etching. The first word line layer 530 does not need to be removed, so the channel layer 510 will not be damaged when the protective layer is removed.

[0093] In step S70, referring to Figure 15 The second word line material layer can be formed first on the structure upper surface outside the device via hole 10, in the remaining space inside the device via hole 10, and in the through hole 13. Then, the second word line material layer formed outside the device via hole 10 can be removed by chemical mechanical polishing (CMP) to form the second word line layer 540.

[0094] As an example, referring to Figure 16 and Figure 17 Before forming the second word line material layer on the structure upper surface outside the device via hole 10, in the remaining space inside the device via hole 10, and in the through hole 13, the channel layer 510 and the gate dielectric layer 520 opposite to the isolation layer 410 can also be removed, or the channel layer 510 opposite to the isolation layer 410 is removed, so as to prevent the formation of a parasitic transistor between the adjacent layer conductive layers 420.

[0095] The channel layer 510 and the gate dielectric layer 520 on the sidewall of the isolation layer 410 can be removed by first forming a side etch trench in the stack layer 400. Then, the isolation layer 410 is etched from the side etch trench to expose the channel layer 510 opposite to the isolation layer. Then, the channel layer 510 opposite to the isolation layer 410 can be etched to remove the channel layer 510. Optionally, the gate dielectric layer 520 opposite to the isolation layer 410 can also be etched to remove the gate dielectric layer 520. Then, the isolation layer material can be refilled in the etched region of the isolation layer 410, the etched region of the channel layer 510, and the etched region of the gate dielectric layer 520 to form a new isolation layer 410. Then, the second word line layer 540 can be formed in the remaining space in the via 13 and the device via 10.

[0096] At this time, the second word line layer 540 and the first word line layer 530 together form the word line of the transistor. Please refer to Figure 17 The width of the word line of the transistor on the upper portion of the bottom isolation layer 410 is L2, which is the sum of the width of the second word line layer 540 and the width of the first word line layer 530. The width of the word line of the transistor on the lower portion of the bottom isolation layer 410 and the portion of the word line of the transistor below the stack layer 400 (e.g., the portion in the insulating dielectric layer 700) is L1, which is the width of the second word line layer 540. Therefore, L2 is greater than L1.

[0097] The material of the second word line layer 540 and the material of the first word line layer 530 can be the same (e.g., both are ITO) or different.

[0098] As an example, the material of the second word line layer 540 and the material of the first word line layer 530 are the same. At this time, the chemical mechanical polishing (CMP) can remove the second word line material layer formed outside the device via 10, and at the same time, the first word line layer 530 outside the device via 10 can also be removed.

[0099] The second word line layer 540, the first word line layer 530, the gate dielectric layer 520, and the channel layer 510 can together form a transistor structure 500. When the stack layer 400 includes n layers of conductive layers 420, n is a positive integer, the same transistor structure 500 can include n stacked switching transistors in a memory array. Each layer of conductive layers 420 on both sides of the transistor structure 500 is connected to the channel layer 510 of the transistor structure 500 to form the source and drain of each switching transistor.

[0100] In the embodiment, the first circuit 200 (such as a peripheral logic circuit) is made below the memory array, which can effectively save the area of the chip and improve the integration density of the device. Meanwhile, before the through hole 13 extending to the conductive interconnection structure 300 is formed by etching the channel material layer 5101, the channel material layer 5101, the gate dielectric material layer 5201 and the first word line material layer 5301 are sequentially formed on the hole wall of the device via hole 10. Then, the first word line material layer 5301, the gate dielectric material layer 5201 and the channel material layer 5101 are sequentially etched. At this time, the first word line layer 530 formed by the first word line material layer 5301 remaining after etching can serve as a protective layer to protect the channel material layer 5101 from being damaged in the dry etching process. The first word line layer 530 does not need to be removed, so the channel layer 510 will not be damaged when the protective layer is removed. Therefore, the channel layer 510 and the gate dielectric layer 520 can be effectively protected in the embodiment, thereby ensuring the performance of the device.

[0101] In some embodiments, referring to Figures 12 to 13 , before step S60, the method further comprises:

[0102] In step S50, at least part of the first word line material layer 5301 on the top of the device via hole 10 is etched.

[0103] At this time, after the subsequent step forms the second word line layer 540 in the through hole 13, the orthographic projection of the bottom of the second word line layer 540 on the substrate 100 is located within the orthographic projection of the top of the second word line layer 540 on the substrate 100.

[0104] As an example, the first word line material layer 5301 can be formed first, and then the first photoresist 30 is applied on the remaining space of the device via hole 10 and the upper surface of the first word line material layer 5301. Then, the first photoresist 30 is exposed and developed to remove the first photoresist 30 on the top of the device via hole 10, thereby exposing the first word line material layer 5301 on the top of the device via hole 10. Then, the first word line material layer 5301 on the top of the device via hole 10 can be etched by vapor etching. During etching, part of the first word line material layer 5301 on the top can be etched, or the first word line material layer 5301 can be etched completely, as long as the space on the top of the device via hole is increased. At this time, the remaining space of the device via hole 10 is increased on the top, thereby facilitating the etching of the through hole 13 in step S60.

[0105] In some embodiments, step S30 comprises:

[0106] In step S302, referring to Figure 3forming a stack initial layer 4001 on the conductive interconnection structure 300, the stack initial layer 4001 including alternatingly stacked isolation material layers 4101 and sacrificial material layers 4301;

[0107] At step S304, referring to Figure 3 forming a dummy word line hole 11 through the stack initial layer 4001, and forming a dummy word line 550 in the dummy word line hole 11;

[0108] At step S306, referring to Figure 6 performing a patterning process on the stack initial layer 4001 after forming the dummy word line 550, to form an isolation trench 20, the remaining isolation material layers 4101 forming isolation layers 410, and the remaining sacrificial material layers 4301 forming sacrificial layers 430;

[0109] At step S308, etching and removing the sacrificial layers 430 from the isolation trench 20;

[0110] At step S310, referring to Figure 7 forming a conductive material layer 4201 in the region where the sacrificial layers 430 are removed, and forming a filling dielectric layer 640 in the isolation trench 20;

[0111] At step S312, referring to Figure 9 removing the dummy word line 550, and laterally etching the conductive material layer 4201 from the dummy word line hole 11 to form a lateral hole 12, the lateral hole 12 and the dummy word line hole 11 forming a device via 10, and the remaining conductive material layer 4201 forming a conductive layer 420.

[0112] At step S302, referring to Figure 3 When forming the stack initial layer 4001, the isolation material layers 4101 and the sacrificial material layers 4301 can be repeatedly formed by a deposition process.

[0113] The material of the isolation material layers 4101 can include, but is not limited to, silicon oxide (SiO2), and the material of the sacrificial material layers 4301 can include, but is not limited to, silicon nitride (Si3N4).

[0114] At step S304, referring to Figure 3 The dummy word line hole 11 can be first formed in the stack initial layer 4001 by a photolithography process, and then the dummy word line 550 can be filled in the dummy word line hole 11.

[0115] Specifically, a second patterned photoresist can be first formed on the stack initial layer 4001. The second patterned photoresist has a second opening. The second opening can define the size and position of the dummy word line hole 11. Then, based on the second patterned photoresist, the stack initial layer 4001 is subjected to dry etching, etc., to form the dummy word line hole 11. After that, the second patterned photoresist can be removed.

[0116] Then, a dummy word line 550 material (e.g. polysilicon) can be formed on the top surface of the stack initial layer 4001 and inside the dummy word line hole 11 by a deposition process. Afterwards, the dummy word line 550 material on the top surface of the stack initial layer 4001 can be removed by a chemical mechanical polishing (CMP) process, leaving the dummy word line 550 material inside the dummy word line hole 11, thereby forming the dummy word line 550.

[0117] In step S306, referring to Figure 6 The stack initial layer 4001 after the formation of the dummy word line 550 can be patterned by a photolithography process, thereby forming an isolation trench 20 penetrating the stack initial layer 4001. The isolation trench 20 exposes the sidewalls of each layer of the isolation layer 410 and each layer of the sacrificial layer 430 after etching.

[0118] In step S308, the etching liquid of the wet etching can flow to the sacrificial layer 430 through the isolation trench 20, thereby removing the sacrificial layer 430. At this time, the dummy word line 550 can play a supporting role for the structure of each layer of the isolation layer 410 during the removal of the sacrificial layer 430.

[0119] In step S310, referring to Figure 7 First, a conductive material layer 4201 can be formed on the surface of the structure after the removal of the sacrificial layer 430 by an atomic layer deposition process or the like. Then, the surface of the conductive material layer 4201 on the top layer of the isolation layer 410 can be planarized by a chemical mechanical polishing (CMP) process. Afterwards, the conductive material layer 4201 inside the isolation trench 20 can be removed by a dry etching process. Then, a filling material layer can be formed to fill the isolation trench 20, and the filling material layer outside the isolation trench 20 can be removed by a chemical mechanical polishing (CMP) process, thereby forming a filling medium layer 640 inside the isolation trench 20.

[0120] The material of the filling medium layer 640 can include, but is not limited to, silicon oxide (SiO2). For example, the material of the filling medium layer 640 can also be silicon nitride (Si3N4) or silicon oxynitride (SiON) or the like.

[0121] It can be understood that the same material of the filling medium layer 640 and the isolation layer 410 is taken as an example for illustration in the drawings of the specification. However, the material of the filling medium layer 640 and the isolation layer 410 is not limited to be the same, and they can also be different.

[0122] In step S312, referring to Figure 9The dummy word line 550 can be removed by dry etching. At this time, the conductive material layer 4201 on the sidewall of the dummy word line hole 11 is exposed. Then, the conductive material layer 4201 can be subjected to wet lateral etching from the dummy word line hole 11, so as to form a lateral hole 12. The lateral hole 12 is in communication with the dummy word line hole 11, and the two form the device via hole 10. Moreover, the conductive material layer 4201 remaining after etching forms the conductive layer 420.

[0123] In the embodiment, first, a stack initial layer 4001 including alternately stacked isolation material layers 4101 and sacrificial material layers 4301 is formed. Then, the sacrificial layers 430 are removed by the isolation trenches 20. Then, the conductive layer 420 is formed in the region where the sacrificial layers 430 are removed. Before the sacrificial layers 430 are removed by forming the isolation trenches 20, the dummy word line 550 is formed through the stack initial layer 4001, so that the structure of each layer isolation layer 410 can be supported during the removal of the sacrificial layers 430. After the conductive layer 420 is formed, the dummy word line 550 is removed, i.e., the device via hole 10 can be formed based on the dummy word line hole 11, which facilitates the formation of the device via hole 10.

[0124] In other embodiments, the formation of the stack layer 400 can also be different from this. For example, the isolation layer 410 and the conductive layer 420 can be directly formed in an alternating stack, and after the isolation layer 410 and the conductive layer 420 are formed in an alternating stack, etching is performed to form the device via hole 10 through the isolation layer 410 and the conductive layer 420.

[0125] In some embodiments, referring to Figures 10 to 11 After step S40, the lateral hole 12 is filled. At this time, the first word line layer 530 has a raised portion 531 away from the second word line portion, so as to ensure that the first word line layer 530 (especially the first word line layer 530 at the position opposite to the conductive layer 420) has sufficient thickness.

[0126] At this time, in the process of etching the gate dielectric material layer 5201 and the channel material layer 5101, the first word line layer 530 on the sidewall of the gate dielectric material layer 5201 will not be etched through, so as to well protect the gate dielectric layer 520 and the channel layer 510, and prevent the gate dielectric layer 520 and the channel layer 510 from being damaged in the process of forming the through hole 13.

[0127] Of course, in other embodiments, after the first word line material layer 5301 is formed, the lateral hole 12 can also not be filled. At this time, the first word line material layer 5301 can be formed to have a preset thickness, so as to ensure that it will not be etched through in the process of forming the through hole 13, thereby well protecting the gate dielectric layer 520 and the channel layer 510. The preset thickness can be greater than 30 nm, for example.

[0128] In some embodiments, referring to Figure 3 , step S302 is preceded by:

[0129] Step S301, forming an insulating dielectric layer 700 on the conductive interconnection structure 300.

[0130] At this point, step S302 involves forming a stack initial layer 4001 on the insulating dielectric layer 700.

[0131] Meanwhile, step S304 involves:

[0132] Step S3041, etching the stack initial layer 4001 with the insulating dielectric layer 700 as an etching stop layer, to form a dummy word line hole 11.

[0133] Step S3042, forming a dummy word line 550 in the dummy word line hole 11.

[0134] The material of the insulating dielectric layer 700 can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON), etc. Meanwhile, the material of the insulating dielectric layer 700 is different from that of the isolation layer 410, so that it can serve as an etching stop layer when etching the stack initial layer 4001. For example, when the material of the isolation layer 410 includes silicon oxide (SiO2), the material of the insulating dielectric layer 700 can include silicon carbon nitride (SiCN).

[0135] Through the provision of the insulating dielectric layer 700, damage to the underlying structure (such as the conductive interconnection structure 300) can be effectively prevented when etching the stack initial layer 4001.

[0136] It can be understood that at this point, when the through hole 13 is formed in step S60, the through hole 13 can be formed through the first word line material layer 5301, the gate dielectric material layer 5201, the channel material layer 5101, and the insulating dielectric layer 700 at the bottom of the through device via 10, so that the through hole 13 extends to the conductive interconnection structure 300.

[0137] In some embodiments, referring to Figure 6After the isolation trench 20 is formed in step S306, the stack initial layer 4001 can have a first trunk portion 4001a and a first branch portion 4001b. The first trunk portion 4001a extends along a first direction. The first branch portion 4001b is located at least one side of the first trunk portion 4001a along a second direction. The first direction intersects the second direction and both are parallel to the substrate. As an example, the first branch portion 4001b can be located at opposite sides of the first trunk portion 4001a along the second direction. There can be multiple first branch portions 4001b at the same side of the first trunk portion 4001a along the second direction. The first branch portions 4001b located at opposite sides of the first trunk portion 4001a along the second direction are symmetrically arranged.

[0138] Meanwhile, the dummy word line 550 formed in step S304 penetrates the first branch portion 4001b. There can be one dummy word line 550 in each first branch portion 4001b.

[0139] At this time, please refer to Figure 7 After the sacrificial layer 430 is removed in subsequent steps and the stack layer 400 is formed by replacing the sacrificial layer 430 with the conductive layer 420, the first trunk portion 4001a can be converted into a second trunk portion 400a and the first branch portion 4001b can be converted into a second branch portion 400b. That is, the stack layer 400 has the second trunk portion 400a and the second branch portion 400b. The second trunk portion 400a extends along the first direction. The second branch portion 400b is located at least one side of the second trunk portion 400a along the second direction. As an example, the second branch portion 400b can be located at opposite sides of the second trunk portion 400a along the second direction. There can be multiple second branch portions 400b at the same side of the second trunk portion 400a along the second direction. The second branch portions 400b located at opposite sides of the second trunk portion 400a along the second direction are symmetrically arranged.

[0140] Meanwhile, after the dummy word line 550 is removed in subsequent steps and the transistor structure 500 is formed in the device via 10, there is one transistor structure 500 including multiple switching transistors in each second branch portion 400b.

[0141] The conductive layer 420 in the second trunk portion 400a can serve as a bit line, and the conductive layer 420 located at both sides of the switching transistor in the second branch portion 400b can serve as the source and the drain of the switching transistor, so that the bit line is connected to the switching transistor. When the second branch portion 400b is located at opposite sides of the second trunk portion 400a along the second direction, the same bit line can supply power to the switching transistors of the memory cells located at both sides thereof.

[0142] In some embodiments, please refer to Figure 5 Before step S306, the method further includes:

[0143] At step S305, a support layer 800 is formed to penetrate the stacked initial layer 4001 and extend along the first direction, and the support layer 800 is located at the side of the first branch part 4001b away from the first trunk part 4001a.

[0144] Specifically, referring to Figure 4 After the pseudo word line 550 is formed in the stacked initial layer 4001 at step S304, a hard mask layer 40 can be deposited on the stacked initial layer 4001. The hard mask layer 40 can include one or more film layers. Then, a third patterned photoresist 50 can be formed on the hard mask layer 40. The third patterned photoresist 50 has a third opening. The third opening can define the size and position of the support layer 800, etc.

[0145] Then, based on the third patterned photoresist 50, dry etching or the like is performed on the stacked initial layer 4001, thereby forming a support hole. When the stacked initial layer 4001 is formed on the insulating medium layer 700, the insulating medium layer 700 can be used as an etching stop layer. After that, the third patterned photoresist 50 can be removed.

[0146] As an example, referring to Figure 5 After the support hole is formed, the isolation material layer 4101 in the stacked initial layer 4001 can also be laterally etched back from the support hole to form a support side hole. Then, the support layer 800 can be formed in the support hole and the support side hole.

[0147] The support layer 800 can play a supporting role together with the pseudo word line 550 in the process of removing the sacrificial layer 430 in the subsequent step and replacing the sacrificial layer 430 with the conductive layer 420.

[0148] The material of the support layer 800 can include, but is not limited to, silicon oxynitride (SiON). For example, it can also include silicon oxide (SiO2) or silicon nitride (Si3N4), etc.

[0149] In some embodiments, the side of the pseudo word line 550 away from the first trunk part 4001a has a capacitor region, and the capacitor region is arranged spaced apart from the pseudo word line 550.

[0150] Before step S312, referring to Figure 8 Further comprising:

[0151] At step S3111, the isolation layer 410 located at the capacitor region is removed to expose the conductive material layer 4201;

[0152] At step S3112, a capacitor dielectric layer 910 and a capacitor outer electrode layer 920 are sequentially formed around the peripheral surface of the conductive material layer 4201 located at the capacitor region.

[0153] In step S3111, a fourth photoresist can be formed on the surface of the structure after the filling medium layer is formed. The fourth photoresist has a fourth opening. The fourth opening can define the size and position of the capacitor region, etc.

[0154] Then, based on the fourth photoresist, dry etching is performed on the isolation layer 410 in the capacitor region to remove the isolation layer 410 between the conductive material layers 4201 adjacent in the first direction. After that, wet lateral etching is performed on the isolation layer 410 between the conductive material layers 4201 adjacent in the stacking direction, so as to completely remove the isolation layer 410 in the capacitor region. At this time, the conductive material layer 4201 in the capacitor region is exposed. The exposed conductive material layer 4201 can serve as an inner electrode layer of the capacitor. Therefore, the inner electrode layer of the capacitor and the bit line can be connected on the two sides of the switching transistor, respectively.

[0155] In step S3112, a capacitor dielectric layer 910 can be formed on the outer peripheral surface of the exposed conductive material layer 4201 in the capacitor region. After that, a capacitor outer electrode layer 920 can be formed on the outer peripheral surface of the capacitor dielectric layer 910. The capacitor outer electrode layer 920, the capacitor dielectric layer 910, and the inner electrode layer of the capacitor (the conductive material layer 4201 in the capacitor region) together form a capacitor 900. The capacitor 900 and the switching transistor together form a memory cell.

[0156] As an example, the material of the capacitor dielectric layer 910 can include, but is not limited to, a high dielectric constant layer such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the capacitor outer electrode layer 920 can include, but is not limited to, polysilicon, etc.

[0157] It should be understood that, although Figure 1 The steps in the flowchart of FIG. 11 are shown in sequence according to the direction of the arrows, but these steps are not necessarily executed in sequence according to the direction of the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 At least part of the steps in FIG. 11 can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0158] In some embodiments, please refer to Figure 15 and Figure 16A semiconductor structure is also provided, which includes a substrate 100, a first circuit 200, a conductive interconnect structure 300, a stack layer 400, and a transistor structure 500.

[0159] The substrate 100 can be a single-layer structure or a multi-layer structure. When the substrate 100 is a multi-layer structure, it can include a semiconductor substrate and other structures or film layers formed on the semiconductor substrate.

[0160] The first circuit 200 is located on the substrate 100. The first circuit 200 can be, for example, a peripheral logic circuit. The peripheral logic circuit can include a complementary metal-oxide-semiconductor (CMOS) circuit and can be formed based on the substrate 100.

[0161] As an example, the substrate 100 can include a semiconductor substrate. The semiconductor substrate can include P-well and N-well regions. A shallow trench isolation (STI) structure can be provided in the semiconductor substrate. The STI structure can separate the semiconductor substrate into a plurality of active regions. Transistors in the first circuit 200, such as transistors in the CMOS circuit, can be formed based on the active regions.

[0162] The conductive interconnect structure 300 is located on a side of the first circuit 200 away from the substrate 100 and electrically connects the first circuit 200.

[0163] As an example, the conductive interconnect structure 300 can include a first interconnect structure 310, a redistribution layer 320, and a second interconnect structure 330. Meanwhile, the semiconductor structure can also include a first dielectric layer 610, a second dielectric layer 620, and a third dielectric layer 630.

[0164] The first dielectric layer 610 can cover the first circuit 200 and the substrate 100. The first interconnect structure 310 can pass through the first dielectric layer 610 and connect to the first circuit 200. For example, the first interconnect structure 310 can connect to one of the drain or source of a transistor in the CMOS circuit.

[0165] The second dielectric layer 620 can cover the first dielectric layer 610 and the first interconnect structure 310. The redistribution layer 320 is located in the second dielectric layer 620 and connects the first interconnect structure 310.

[0166] The third dielectric layer 630 can cover the second dielectric layer 620 and the redistribution layer 320. The second interconnect structure 330 can pass through the third dielectric layer 630 and connect to the redistribution layer 320. The second interconnect structure 330, the redistribution layer 320, and the first interconnect structure 310 form the conductive interconnect structure 300, so that the conductive interconnect structure 300 electrically connects the first circuit 200.

[0167] The stack layer 400 is located on the side of the conductive interconnection structure 300 away from the substrate 100.

[0168] Meanwhile, the stack layer 400 comprises alternatingly stacked isolation layers 410 and conductive layers 420. As an example, the top and bottom film layers of the stack layer 400 can both be isolation layers 410, and the conductive layers 420 are located between the isolation layers 410.

[0169] The material of the isolation layer 410 can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON), etc.

[0170] The material of the conductive layer 420 can include, but is not limited to, tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc.

[0171] The transistor structure 500 comprises a channel layer 510, a gate dielectric layer 520, a first word line layer 530, and a second word line layer 540.

[0172] The second word line layer 540 extends through the stack layer 400 and reaches the conductive interconnection structure 300, so that the conductive interconnection structure 300 electrically connects the second word line layer 540 and the first circuit 200.

[0173] Of course, in other embodiments, the conductive interconnection structure 300 can not be provided, and the second word line layer 540 is directly connected to the first circuit 200, and the stack layer 400 is located on the side of the first circuit 200 away from the substrate 100. At this time, in the preparation process of the semiconductor structure, in step S20, after the first circuit is formed on the substrate 100, an isolation medium layer covering the first circuit can be directly formed. In step S30, the stack layer is formed on the isolation medium layer, and the device via hole penetrating through the isolation layer and the conductive layer 420 is formed in the stack layer. Then in step S60, the first word line material layer 5301, the gate dielectric material layer 5201, and the channel material layer 5101 penetrating through the bottom of the device via hole 10 and extending to the through hole 13 of the first circuit 200 are formed.

[0174] The first word line layer 530 is located in the stack layer 400 and at least partially covers the sidewall of the second word line layer 540.

[0175] The gate dielectric layer 520 and the channel layer 510 are located in the stack layer 400. The gate dielectric layer 520 is located on the side of the first word line layer 530 away from the second word line layer 540, the channel layer 510 is located on the side of the gate dielectric layer 520 away from the first word line layer 530, and is located between the gate dielectric layer 520 and the conductive layer 420.

[0176] As an example, the first word line layer 530 can entirely surround the second word line layer 540. At this time, the gate dielectric layer 520 entirely surrounds the first word line layer 530, and the channel layer 510 entirely surrounds the gate dielectric layer 520.

[0177] As another example, the first word line layer 530 can also partially surround the second word line layer 540. At this time, the gate dielectric layer 520 partially surrounds the first word line layer 530, and the channel layer 510 partially surrounds the gate dielectric layer 520.

[0178] Alternatively, the first word line layer 530 can also be in other forms.

[0179] As yet another example, the second word line layer 540 is in a cubic columnar structure, and the first word line layer 530 is in a columnar structure between the gate dielectric layer 520 and one side of the second word line layer 540. Accordingly, the gate dielectric layer 520 is in a columnar structure between the channel layer 510 and the first word line layer 530, and the channel layer 510 is in a columnar structure between the stack layer 400 and the gate dielectric layer 520.

[0180] At this time, in the preparation process of the semiconductor structure, for example, the device via hole 10 can be a square hole; and when the through hole is formed in step 60, the first word line material layer 5301, the gate dielectric material layer 5201, and the channel material layer 5101 on one side wall of the device via hole 10 are retained, and the first word line material layer 5301, the gate dielectric material layer 5201, and the channel material layer 5101 on the remaining side walls of the device via hole and the bottom of the device via hole 10 are removed.

[0181] The material of the second word line layer 540 can be the same as that of the first word line layer 530 (for example, both are ITO). Of course, the two can also be different. For example, the material of the second word line layer 540 includes tungsten or copper, and the material of the first word line layer includes ITO or IZO.

[0182] The material of the channel layer 510 can include, but is not limited to, indium gallium zinc oxide (IGZO) and the like. The material of the gate dielectric layer 520 can include, but is not limited to, high dielectric constant layers such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxide nitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0183] The second word line layer 540, the first word line layer 530, the gate dielectric layer 520 and the channel layer 510 can collectively form the transistor structure 500. When the stack layer 400 includes n conductive layers 420, the same transistor structure 500 can include n stacked switching transistors in a memory array, n being a positive integer. The conductive layers 420 on both sides of the transistor structure 500 are connected to the channel layer 510 of the transistor structure 500, thereby forming the source and drain of each switching transistor.

[0184] In the present embodiment, the first word line layer 530 is provided in the stack layer 400, and is located between the second word line layer 540 and the gate dielectric layer 520. Therefore, in the process of forming the second word line layer 540 electrically connected to the first circuit, such as the process of forming the second word line layer 540 connected to the conductive interconnection structure 300, the first word line layer 530 can well protect the channel layer 510 and the gate dielectric layer 520, thereby improving the performance of the device.

[0185] In some embodiments, the bottom of the second word line layer 540 on the substrate 100 is surrounded by the bottom of the first word line layer 530 on the substrate 100.

[0186] At this time, the first word line layer 530 formed earlier is used to protect the channel layer 510, and the second word line layer 540 is formed inside the first word line layer 530, so it has the above structural characteristics, which can improve the stability of the channel layer.

[0187] In some embodiments, the bottom of the second word line layer 540 on the substrate 100 is located within the top of the second word line layer 540 on the substrate 100.

[0188] At this time, the top of the second word line layer 540 has a large size, thereby facilitating the formation of the second word line layer 540.

[0189] As an example, at this time, the top of the second word line layer 540 can directly contact the sidewall of the gate dielectric layer 520.

[0190] In some embodiments, the first word line layer 530 has a protruding portion 531 protruding in a direction away from the second word line layer, the protruding portion 531 is located between adjacent isolation layers 410, and has an overlap with the conductive layer in a direction perpendicular to the substrate.

[0191] At this time, the first word line layer 530 can better protect the channel layer 510 and the gate dielectric layer 520 in the process of forming the second word line layer 540, thereby improving the performance of the device.

[0192] In some embodiments, the semiconductor structure further comprises an insulating dielectric layer 700 on the side of the conductive interconnect structure 300 away from the substrate 100. The stack layer 400 is on the side of the insulating dielectric layer 700 away from the substrate 100. The second word line layer 540 extends through the stack layer 400 and the insulating dielectric layer 700.

[0193] As an example, the insulating dielectric layer 700 can be on the upper surface of the second interconnect structure 330 and the upper surface of the third dielectric layer 630. In this case, the stack layer 400 can be on the upper surface of the insulating dielectric layer 700.

[0194] The material of the insulating dielectric layer 700 can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON), etc. Meanwhile, the material of the insulating dielectric layer 700 is different from the material of the isolation layer 410. For example, when the material of the isolation layer 410 includes silicon oxide (SiO2), the material of the insulating dielectric layer 700 can include silicon carbon nitride (SiCN). In this case, during the preparation of the semiconductor structure, the insulating dielectric layer 700 can act as an etching stop layer during the etching of the stack layer 400.

[0195] In some embodiments, the stack layer 400 has a second trunk portion 400a extending along a first direction and a second branch portion 400b on at least one side of the second trunk portion 400a along a second direction, the transistor structure 500 extending through the second branch portion 400b, the first direction and the second direction being perpendicular to each other and both parallel to the substrate.

[0196] As an example, the second branch portion 400b can be on opposite sides of the second trunk portion 400a along the second direction. On the same side of the second trunk portion 400a along the second direction, there can be multiple second branch portions 400b. The second branch portions 400b on opposite sides of the second trunk portion 400a along the second direction can be symmetrically arranged.

[0197] Each second branch portion 400b has one transistor structure 500 including multiple switching transistors.

[0198] The conductive layer 420 in the second trunk portion 400a can act as a bit line. The conductive layer 420 in the second branch portion 400b on both sides of the switching transistor can act as the source and the drain of the switching transistor, thereby connecting the bit line to the switching transistor. When the second branch portion 400b is on opposite sides of the second trunk portion 400a along the second direction, the same bit line can supply power to the switching transistors of the memory cells on both sides thereof.

[0199] In some embodiments, the semiconductor structure further comprises a support layer 800. The support layer 800 is located on the side of the second branch 400b away from the second stem 400a. Meanwhile, the support layer 800 extends through the stack 400 and along the first direction.

[0200] The material of the support layer 800 can include, but is not limited to, silicon oxynitride (SiON). For example, it can also include silicon oxide (SiO2) or silicon nitride (Si3N4), etc.

[0201] In some embodiments, the side of the transistor structure 500 away from the second stem 400a has a capacitor region, which is spaced apart from the transistor structure 500, and is provided with a capacitor dielectric layer 910 and a capacitor outer electrode layer 920. The capacitor dielectric layer 910 is located on the outer peripheral surface of the conductive layer 420, and the capacitor outer electrode layer 920 is located on the outer peripheral surface of the capacitor dielectric layer 910.

[0202] For example, the material of the capacitor dielectric layer 910 can include, but is not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3), etc. The material of the capacitor outer electrode layer 920 can include, but is not limited to, polycrystalline silicon, etc.

[0203] At this time, the conductive layer 420 located in the capacitor region can serve as a capacitor inner electrode layer. Therefore, the capacitor inner electrode layer and the bit line can be connected on both sides of the switching transistor, respectively.

[0204] The capacitor outer electrode layer 920, the capacitor dielectric layer 910, and the capacitor inner electrode layer (the conductive layer 420 located in the capacitor region) collectively form a capacitor 900. The capacitor 900 and the switching transistor collectively form a memory cell.

[0205] In some embodiments, an electronic device comprising the semiconductor structure in the above embodiments is also provided. The electronic device can include, but is not limited to, a storage device, a computer, a mobile phone, a television, a display, a notebook, etc.

[0206] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0207] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the application encompasses all possible combinations of the technical features unless such a combination exists only in the prior art.

[0208] The above-described embodiments only express several implementation manners of the application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the application, and these all belong to the protection scope of the application. Therefore, the patent protection scope of the application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a first circuit on the substrate, and forming a conductive interconnection structure on the first circuit, the conductive interconnection structure electrically connecting the first circuit; forming a stack layer on the conductive interconnection structure, the stack layer comprising alternatingly stacked isolation layers and conductive layers, and forming a device via through the isolation layers and the conductive layers in the stack layer, a normal projection of the device via on the substrate and the conductive interconnection structure having an overlap; forming, in sequence, a channel material layer, a gate dielectric material layer, and a first word line material layer on a hole wall of the device via; forming a through hole through the first word line material layer, the gate dielectric material layer, and the channel material layer at a bottom of the device via and extending to the conductive interconnection structure, the remaining first word line material layer forming a first word line layer, the remaining gate dielectric material layer forming a gate dielectric layer, and the remaining channel material layer forming a channel layer; forming a second word line layer in the through hole and the remaining space in the device via.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before the forming of the through hole through the first word line material layer, the gate dielectric material layer, and the channel material layer at the bottom of the device via and extending to the conductive interconnection structure, the method further comprises: at least partially etching the first word line material layer at the top of the device via.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The forming of the stack layer on the conductive interconnection structure comprises: forming a stack initial layer on the conductive interconnection structure, the stack initial layer comprising alternatingly stacked isolation material layers and sacrificial material layers; forming a pseudo word line hole through the stack initial layer, and forming a pseudo word line in the pseudo word line hole; performing a patterning process on the stack initial layer after the formation of the pseudo word line, to form an isolation trench, the remaining isolation material layers forming the isolation layers, and the remaining sacrificial material layers forming sacrificial layers; etching and removing the sacrificial layers from the isolation trench; forming a conductive material layer in the sacrificial layer removal area, and forming a filling dielectric layer in the isolation trench; removing the pseudo word line, and laterally etching the conductive material layer from the pseudo word line hole to form a lateral hole, the lateral hole and the pseudo word line hole forming the device via, and the remaining conductive material layer forming the conductive layers.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: After the formation of the channel material layer, the gate dielectric material layer, and the first word line material layer in sequence on the hole wall of the device via, the lateral hole is filled.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein, before the forming of the stack initial layer on the conductive interconnection structure, the method further comprises: forming an insulating dielectric layer on the conductive interconnection structure; the forming of the pseudo word line hole through the stack initial layer, and the forming of the pseudo word line in the pseudo word line hole, comprises: using the insulating dielectric layer as an etching stop layer, etching the stack initial layer to form the pseudo word line hole; forming the pseudo word line in the pseudo word line hole.

6. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The stack initial layer after forming the dummy word line is subjected to a patterning process to form an isolation trench, and the stack initial layer has a first stem portion extending along a first direction and a first branch portion located on at least one side of the first stem portion along a second direction, the dummy word line penetrates the first branch portion, and the first direction and the second direction are perpendicular to the substrate.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: Before the stack initial layer after forming the dummy word line is subjected to a patterning process to form an isolation trench, the method further comprises: forming a support layer penetrating the stack initial layer and extending along the first direction, the support layer being located on the side of the first branch portion away from the first stem portion.

8. The method of claim 6, wherein the step of forming the semiconductor structure is performed by a method comprising: The side of the dummy word line away from the first stem portion has a capacitor region, and the capacitor region is spaced apart from the dummy word line, Before the dummy word line is removed and the conductive material layer is laterally etched from the dummy word line hole to form the lateral hole, the method further comprises: removing the isolation layer located in the capacitor region to expose the conductive material layer; forming a capacitor dielectric layer and a capacitor outer electrode layer in sequence around the peripheral surface of the conductive material layer located in the capacitor region.

9. A semiconductor structure, characterized by Comprise: a substrate; a first circuit located on the substrate; a stack layer located on the side of the first circuit away from the substrate, comprising alternately stacked isolation layers and conductive layers; a transistor structure comprising a channel layer, a gate dielectric layer, a first word line layer, and a second word line layer, the second word line layer penetrating the stack layer and electrically connected to the first circuit, the first word line layer being located in the stack layer and at least partially covering the sidewall of the second word line layer, the gate dielectric layer and the channel layer being located in the stack layer, and the gate dielectric layer being located on the side of the first word line layer away from the second word line layer, the channel layer being located on the side of the gate dielectric layer away from the first word line layer, and between the gate dielectric layer and the conductive layer.

10. The semiconductor structure of claim 9, wherein, The bottom of the second word line layer on the substrate is surrounded by the bottom of the first word line layer on the substrate.

11. The semiconductor structure of claim 9, wherein, The semiconductor structure further comprises a conductive interconnection structure between the first circuit and the stack layer, and electrically connected to the first circuit and the second word line layer.

12. The semiconductor structure of claim 9, wherein, The bottom of the second word line layer on the substrate is located within the top of the second word line layer on the substrate.

13. The semiconductor structure of claim 9, wherein, The first word line layer has a protruding portion protruding in a direction away from the second word line layer, the protruding portion being located between adjacent isolation layers and overlapping with the conductive layer in a direction perpendicular to the substrate.

14. The semiconductor structure of claim 11, wherein, The semiconductor structure further comprises an insulating dielectric layer located on the side of the conductive interconnection structure away from the substrate, and the stack layer is located on the side of the insulating dielectric layer away from the substrate, and the second word line layer penetrates the stack layer and the insulating dielectric layer.

15. The semiconductor structure of claim 9, wherein, The stack layer has a second stem portion extending along a first direction and a second branch portion located on at least one side of the second stem portion along a second direction, and the transistor structure penetrates the second branch portion, and the first direction and the second direction are perpendicular to the substrate.

16. The semiconductor structure of claim 15, wherein, The semiconductor structure further comprises: A support layer is provided on the side of the second branch portion away from the second stem portion, extending through the stacked layers and in the first direction.

17. The semiconductor structure of claim 15, wherein, The side of the transistor structure away from the second stem portion has a capacitor region, which is spaced apart from the transistor structure, and which is provided with a capacitor dielectric layer on the outer circumferential surface of the conductive layer and a capacitor outer electrode layer on the outer circumferential surface of the capacitor dielectric layer.

18. An electronic device, comprising: A semiconductor structure according to any one of claims 9 to 17.

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