Anti-fuse OTP memory and manufacturing method thereof

Abstract

The invention discloses an anti-fuse OTP (One Time Programmable) memory, which comprises a first gate structure of a control tube and a second gate structure of an anti-fuse tube, and a first interval is formed between the two gate structures; the first spacing is smaller than the minimum spacing of the layout design rule and is greater than or equal to the minimum spacing which can be manufactured by the gate process. A first side wall and a second side wall are formed on each side face of each gate structure. A first lightly doped drain region, a second lightly doped drain region and a third lightly doped drain region are formed in the surface region of the well region on the side surface of each gate structure; a source-drain injection region is not formed between the two gate structures; and the first source-drain region and the second source-drain region are respectively formed on the surface region of the well region at the second side wall on the outer sides of the two gate structures in a self-aligned manner. And the second lightly doped drain region is used as a series node of the control tube and the anti-fuse tube. The invention further discloses a manufacturing method of the anti-fuse OTP memory. According to the invention, the cell size can be reduced, the storage density can be improved, the manufacturing cost can be reduced, and the leakage current can be reduced, thereby improving the programming success rate and reducing the reading power consumption.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an anti-fuse one-time programmable (OTP) memory. The present invention also relates to a manufacturing method of the anti-fuse OTP memory. Background Art

[0002] Single-time programmable memory is a commonly used embedded memory. Its storage principle is to break down the gate dielectric layer of MOSFET through high voltage and form a current path between the gate and the lightly doped drain (LDD). The capacitor device becomes a smaller resistor device to realize data writing, so it is called an anti-fuse device.

[0003] In order to ensure compatibility with the existing traditional CMOS logic process and higher storage density, the CMOS logic process includes core devices and input-output (IO) devices, and the anti-fuse devices used for storage cells often use the core devices of the process platform. Patents CN104347637B and CN106981313B both describe methods for manufacturing anti-fuse storage cells using core MOS tubes.

[0004] like Figure 1 , which is a schematic diagram of the cross-sectional structure of an anti-fuse storage unit of an existing anti-fuse OTP memory; taking an N-type device as an example, the existing anti-fuse OTP memory includes: an anti-fuse storage unit formed in an active area.

[0005] The anti-fuse memory cell comprises: a P-type well region 102 formed in a semiconductor substrate 101 , a first gate structure of a control tube and a second gate structure of an anti-fuse tube formed on the surface of the well region 102 . The active region is defined by a field oxide layer 203 surrounding it.

[0006] The first gate structure includes a first gate dielectric layer 106 and a first gate conductive material layer 107 stacked in sequence.

[0007] The second gate structure includes a second gate dielectric layer 108 and a second gate conductive material layer 109 stacked in sequence.

[0008] A lightly doped drain region 105 is formed on the surface of the well region 102 on each side of the first gate structure and the second gate structure, and is self-aligned with the side of the corresponding first spacer;

[0009] A source / drain region 104 is formed on the surface of the well region 102 at each side of the first gate structure and the second gate structure, and is self-aligned with the side of the corresponding second spacer.

[0010] The lightly doped drain region 105 and the source-drain region 104 between the first gate structure and the second gate structure are shared by the control tube and the anti-fuse tube and are the series nodes of the control tube and the anti-fuse tube.

[0011] When a higher programming voltage is applied to the second gate conductive material layer 109, the second gate dielectric layer 108 will be broken down to realize programming, and the breakdown is shown by the lightning line.

[0012] In the existing anti-fuse OTP memory, although the gate spacing of the core MOS tube is often the minimum spacing allowed by the layout design rules of the process platform, the process can actually manufacture gates with smaller spacing. Considering the processes such as source through holes (CT) between the gates and ion implantation in the source and drain regions, the minimum spacing of the gates is limited to a larger value, otherwise it will violate the layout design rules and manufacturing process rules.

[0013] For a continuous active area, the mask for ion implantation of the source and drain regions is also a whole piece, and the implantation area between gates is determined by the spacing between the adjacent gate sidewalls. For the series intermediate nodes of the anti-fuse memory cells, the ion implantation of the source and drain regions will reduce the equivalent series resistance, resulting in an increase in the gate induced leakage current (GIDL) of the unselected memory cells and a larger programming inhibition current. For large-capacity memory cells, the programming power supply voltage may drop, resulting in the failure of some anti-fuse programming. The long-term exposure of the unselected cells to the programming inhibition current will also cause device degradation or even failure. Summary of the invention

[0014] The technical problem to be solved by the present invention is to provide an anti-fuse OTP memory, which can reduce the unit size, improve the storage density, reduce the manufacturing cost, and reduce the leakage current to improve the programming success rate and reduce the reading power consumption. To this end, the present invention also provides a manufacturing method of the anti-fuse OTP memory.

[0015] In order to solve the above technical problem, the anti-fuse OTP memory provided by the present invention comprises: an anti-fuse storage unit formed in an active area.

[0016] The anti-fuse memory cell comprises: a well region of a second conductivity type formed in a semiconductor substrate, and a first gate structure and a second gate structure formed on a surface of the well region.

[0017] There is a first spacing between the second side of the first gate structure and the first side of the second gate structure; the first spacing is smaller than the minimum spacing of the layout design rule and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0018] A first spacer and a second spacer are sequentially formed in a self-aligned manner on the first side surface and the second side surface of the first gate structure and the first side surface and the second side surface of the second gate structure.

[0019] A first lightly doped drain region of a first conductivity type is formed in a self-aligned manner on a surface region of the well region at the first sidewall of the first gate structure.

[0020] A first source and drain region heavily doped with a first conductivity type is formed in a self-aligned manner on a surface area of ​​the well region at the second sidewall of the first side of the first gate structure.

[0021] Twice the thickness of the first side wall is less than the first spacing, a first spacer region is provided between the first side wall at the second side of the first gate structure and the first side wall at the first side of the second gate structure, and a second lightly doped drain region is self-aligned to form a surface region of the well region at the bottom of the first spacer region.

[0022] The second sidewall spacer completely fills the first spacing region and forms a source-drain injection blocking structure. There is no source-drain injection region heavily doped with the first conductivity type in the surface area of ​​the well region at the bottom of the first spacing region.

[0023] A third lightly doped drain region of the first conductivity type is formed in a self-aligned manner on a surface region of the well region at the first sidewall of the second side of the second gate structure.

[0024] The second source and drain regions heavily doped with the first conductivity type are formed in a self-aligned manner on the surface area of ​​the well region at the second sidewall of the second gate structure.

[0025] The first gate structure is used as the gate structure of the control tube, the second gate structure is used as the gate structure of the anti-fuse tube, and the second lightly doped drain region is used as the series node of the control tube and the anti-fuse tube.

[0026] A further improvement is that the first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked in sequence.

[0027] The second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

[0028] A further improvement is that the first gate dielectric layer and the second gate dielectric layer are made of the same material and are formed simultaneously.

[0029] The first gate conductive material layer and the second gate conductive material layer are made of the same material and are formed at the same time.

[0030] A further improvement is that it includes a storage array formed by arranging a plurality of the anti-fuse storage units.

[0031] In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row.

[0032] The first source and drain regions in the same column are connected to the bit lines in the same column.

[0033] The second source and drain regions of each of the anti-fuse memory cells are both floating.

[0034] The second gate conductive material layer of each of the anti-fuse memory cells is connected to a first voltage source.

[0035] The well region of each of the anti-fuse memory cells is connected to a fixed point.

[0036] A further improvement is that the control tube and the anti-fuse tube are both NMOS, the first conductivity type is N type, and the second conductivity type is P type; or, the control tube and the anti-fuse tube are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

[0037] A further improvement is that both the control tube and the anti-fuse tube are NMOS.

[0038] The well region of each of the anti-fuse memory cells is grounded.

[0039] During the programming operation, the voltage of the first voltage source is a programming voltage that is greater than the breakdown voltage of the second gate dielectric layer; the bit line connected to the selected anti-fuse memory cell is connected to a low voltage and the word line connected to the selected anti-fuse memory cell is connected to a first positive voltage, and the first positive voltage turns on the control tube; the bit lines not connected to the selected anti-fuse memory cell are all connected to a second positive voltage and the word lines not connected to the selected anti-fuse memory cell are all connected to a low voltage.

[0040] During a read operation, the voltage of the first voltage source is reduced to a third positive voltage, the bit line connected to the selected anti-fuse memory cell is connected to a sensitive discharger, and the word line connected to the bit line is connected to a first positive voltage; the bit line not connected to the selected anti-fuse memory cell is disconnected from the sensitive discharger, and the word lines not connected to the selected anti-fuse memory cell are connected to a low voltage; the first positive voltage, the second positive voltage and the third positive voltage are all greater than or equal to the operating voltage of the NMOS tube, and the minimum value of the low voltage is 0V.

[0041] A further improvement is that, in the storage array, in the anti-fuse storage cells in the same column, every two anti-fuse storage cells form an anti-fuse storage cell combination.

[0042] In the anti-fuse memory cell combination, the active regions of two anti-fuse memory cells are connected to form an integral structure and share the same first source and drain region and are connected to the bit lines corresponding to the same column through the same contact holes; the active regions of each anti-fuse memory cell combination are isolated by a field oxide layer.

[0043] A further improvement is that the first voltage source supplies power to the entire storage array through a power grid.

[0044] Alternatively, the first voltage source is divided into a plurality of first voltage source sub-blocks, each of the first voltage source sub-blocks corresponds to a storage array sub-block of the storage array, and when the storage array sub-block is operating, the corresponding first voltage source sub-block is selected for power supply.

[0045] In order to solve the above technical problems, in the method for manufacturing an anti-fuse OTP memory provided by the present invention, the step of forming an anti-fuse storage unit includes:

[0046] Step 1: providing a semiconductor substrate, forming a well region doped with a second conductivity type in the semiconductor substrate, forming a field oxide layer in the well region and defining an active region of the anti-fuse memory cell.

[0047] Step 2: forming a gate structure, including:

[0048] A first dielectric layer and a second conductive material layer are formed in sequence.

[0049] A first photomask is used to define formation regions of the first gate structure and the second gate structure.

[0050] The second conductive material layer and the first dielectric layer are sequentially etched to form a first gate structure and a second gate structure on the surface of the well region.

[0051] The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked in sequence; the second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence; the first gate dielectric layer and the second gate dielectric layer are both composed of the first dielectric layer after etching; the first gate conductive material layer and the second gate conductive material layer are both composed of the second conductive material layer after etching; there is a first spacing between the second side of the first gate structure and the first side of the second gate structure; the first spacing is smaller than the minimum spacing of the layout design rules and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0052] Step three: self-align and form first spacers on the first side surface and the second side surface of the first gate structure and the first side surface and the second side surface of the second gate structure.

[0053] Twice the thickness of the first spacer is smaller than the first spacing, and a first spacing region is provided between the first spacer at the second side of the first gate structure and the first spacer at the first side of the second gate structure.

[0054] Step 4: Performing a lightly doped drain implantation of the first conductivity type to form a first lightly doped drain region, a second lightly doped drain region and a third lightly doped drain region.

[0055] The first lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the first side wall of the first side of the first gate structure; the second lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the bottom of the first spacer region; the third lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the first side wall of the second side of the second gate structure.

[0056] Step 5: Form a second spacer by self-aligning the side surfaces of the first side surface and the second side surface of the first gate structure and the first side surface and the second side surface of the second gate structure with the side surfaces of the first spacer.

[0057] The second spacer completely fills the first spacer and forms a source-drain injection blocking structure.

[0058] Step 6: Perform source-drain implantation with heavy doping of the first conductivity type to form a first source-drain region and a second source-drain region.

[0059] The first source and drain regions are formed in a self-aligned manner on a surface area of ​​the well region at the second sidewall of the first side of the first gate structure.

[0060] The second source and drain regions are formed in a self-aligned manner on a surface region of the well region at the second sidewall of the second gate structure.

[0061] The source-drain injection blocking structure ensures that there is no source-drain injection region heavily doped with the first conductivity type in the surface area of ​​the well region at the bottom of the first spacer region.

[0062] The first gate structure is used as the gate structure of the control tube, the second gate structure is used as the gate structure of the anti-fuse tube, and the second lightly doped drain region is used as the series node of the control tube and the anti-fuse tube.

[0063] A further improvement is that the method further comprises the steps of:

[0064] An interlayer film, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a word line, a bit line and a first voltage source connection line.

[0065] A memory array is formed by arranging a plurality of the anti-fuse memory cells.

[0066] In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row.

[0067] Each of the first source and drain regions in the same column is connected to the bit line in the same column through the corresponding contact hole.

[0068] The second source and drain regions of each of the anti-fuse memory cells are both floating.

[0069] The second gate conductive material layer of each of the anti-fuse memory cells is connected to the first voltage source line through the corresponding contact hole and is connected to the first voltage source through the first voltage source line.

[0070] The well region of each of the anti-fuse memory cells is connected to a fixed point.

[0071] A further improvement is that the control tube and the anti-fuse tube are both NMOS, the first conductivity type is N type, and the second conductivity type is P type; or, the control tube and the anti-fuse tube are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

[0072] A further improvement is that, in the storage array, in the anti-fuse storage cells in the same column, every two anti-fuse storage cells form an anti-fuse storage cell combination.

[0073] In the anti-fuse memory cell combination, the active areas of two anti-fuse memory cells are connected to form an integral structure and share the same first source and drain area and are connected to the bit line corresponding to the same column through the same contact hole; the active areas of each anti-fuse memory cell combination are isolated by the field oxide layer.

[0074] A further improvement is that the first voltage source supplies power to the entire storage array through a power grid.

[0075] Alternatively, the first voltage source is divided into a plurality of first voltage source sub-blocks, each of the first voltage source sub-blocks corresponds to a storage array sub-block of the storage array, and when the storage array sub-block is operating, the corresponding first voltage source sub-block is selected for power supply.

[0076] A further improvement is that a first identification layer is used in the layout design of the first mask, and the coverage area of ​​the first identification layer is larger than the formation area of ​​the first gate structure and the second gate structure, so as to avoid the violation of the design rule of the first spacing.

[0077] The present invention makes a special arrangement for the first spacing between the first gate structure and the second gate structure of the anti-fuse storage unit, so that the first spacing is smaller than the minimum spacing of the layout design rules and is greater than or equal to the minimum spacing that can be manufactured by the gate process. In this way, the first spacing can be reduced as much as possible under the condition of ensuring the realization of manufacturing the gate structure, breaking through the limitation of the minimum spacing of the layout design rules on the first spacing, so that the unit size can be reduced and the storage density can be improved. The improvement of storage density can reduce manufacturing costs.

[0078] In addition, the present invention sets the first spacing to be smaller than the minimum spacing of the layout design rules. During the layout design process, violation detection of the design rules for the first spacing can be avoided by setting an identification layer, and no mask operation is required. Therefore, the present invention sets the first spacing to be smaller than the minimum spacing of the layout design rules and does not require the addition of additional masks, thereby not causing an increase in manufacturing costs.

[0079] The present invention can ensure that only a lightly doped drain region, i.e., a second lightly doped drain region, which is self-aligned with the first side wall, is formed on the surface of the well region between the first gate structure and the second gate structure by setting a first spacing and combining the setting of a first side wall and a second side wall. The characteristic of the second side wall completely filling the first spacing region between the first gate structure and the second gate structure is utilized to realize a source-drain injection blocking structure and prevent the formation of a source-drain injection region on the surface of the well region between the first gate structure and the second gate structure. Firstly, the process of only forming the second lightly doped drain region and not forming the source-drain injection region in the region between the gate structures is completely realized by self-alignment, which has the advantages of simple process and low cost.

[0080] Secondly, the region between the gate structures only forms the second lightly doped drain region and does not form the source-drain injection region, so that the series node of the control tube and the anti-fuse tube is realized by the second lightly doped drain region. Compared with the existing structure in which the series node of the control tube and the anti-fuse tube adopts the heavily doped source-drain injection region, the resistance of the series node is increased, which can reduce the leakage current such as the GIDL leakage current. During the programming process, the reduction of the leakage current can reduce the reduction of the programming voltage, thereby improving the programming success rate; the reduction of the leakage current can also reduce the reading power consumption. Therefore, the present invention can also reduce the leakage current and thereby improve the programming success rate and reduce the reading power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0082] Figure 1 It is a schematic cross-sectional structure diagram of an anti-fuse storage unit of an existing anti-fuse OTP memory;

[0083] Figure 2 It is a schematic cross-sectional structure diagram of an anti-fuse storage unit of an anti-fuse OTP memory according to an embodiment of the present invention;

[0084] Figure 3 It is a layout of an anti-fuse storage unit of an anti-fuse OTP memory according to an embodiment of the present invention;

[0085] Figure 4A It is a layout of a storage array of an anti-fuse OTP memory according to an embodiment of the present invention;

[0086] Figure 4B yes Figure 4A A circuit diagram of a storage array;

[0087] Figure 5 It is a structural diagram of another storage array of the anti-fuse OTP memory according to an embodiment of the present invention;

[0088] Figure 6 It is a structural diagram of another storage array of the anti-fuse OTP memory according to an embodiment of the present invention;

[0089] Figure 7A-7F It is a schematic cross-sectional structure diagram of an anti-fuse storage unit in each step of a method for manufacturing an anti-fuse OTP memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0090] In the embodiment of the present invention, the anti-fuse OTP memory includes a storage array formed by arranging a plurality of the anti-fuse storage units 301. Figure 4A , which is a layout of a storage array of an anti-fuse OTP memory according to an embodiment of the present invention; Figure 4B yes Figure 4A A circuit diagram of a storage array; Figure 4A The storage array 501a in is a 4*4 array. Figure 4A and Figure 4B The storage array is described in detail:

[0091] In the memory array, the first gate conductive material layers 205 a in the same row are all connected to the word lines WL in the same row. Figure 4A The vertical direction is the row direction, and the horizontal direction is the column direction. Figure 4A 4 rows are shown in the figure, and the 4 word lines are respectively WL0, WL1, WL2 and WL3, and the number after WL represents the row number. Usually, the first gate conductive material layers 205a in the same row are connected to form a row, and the end of the row of the first gate conductive material layers 205a is connected to the corresponding word line WL through the contact hole 306.

[0092] The first source and drain regions 209 a in the same column are connected to the bit line BL in the same column. Figure 4A Four columns are shown in the figure, and the bit lines of the four columns are BL0, BL1, BL2 and BL3 respectively, and the number after BL represents the column number.

[0093] The second source and drain regions 209 b of each of the anti-fuse memory cells 301 are both floating.

[0094] The second gate conductive material layer 205b of each anti-fuse memory cell 301 is connected to the first voltage source VPP. Usually, the second gate conductive material layers 205b in the same row are connected to form a row, and the ends of the row of the second gate conductive material layers 205b are connected to the corresponding first voltage source connection line 308 through the contact hole 306 and connected to the first voltage source VPP through the first voltage source connection line 308.

[0095] The well region 202 of each of the anti-fuse memory cells 301 is connected to a fixed point.

[0096] In the embodiment of the present invention, the control transistor 304 and the anti-fuse transistor 305 are both NMOS, the first conductivity type is N type, and the second conductivity type is P type. In other embodiments, the control transistor 304 and the anti-fuse transistor 305 are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

[0097] In the embodiment of the present invention, the control transistor 304 and the anti-fuse transistor 305 are both NMOS, such as core NMOS. The voltage applied to the anti-fuse storage unit 301 during operation includes:

[0098] The well region 202 of each of the anti-fuse memory cells 301 is grounded.

[0099] During the programming operation, the voltage of the first voltage source VPP is a programming voltage greater than the breakdown voltage of the second gate dielectric layer 204b; the bit line BL connected to the selected anti-fuse memory cell 301 is connected to a low voltage and the word line WL connected to it is connected to a first positive voltage, and the first positive voltage turns on the control tube 304; the bit lines BL not connected to the selected anti-fuse memory cell 301 are all connected to a second positive voltage and the word lines WL not connected to the selected anti-fuse memory cell 301 are all connected to a low voltage.

[0100] Combine the following Figure 4B The bit line BL not connected to the selected anti-fuse memory cell 301 and the word line WL not connected to the selected anti-fuse memory cell 301 are further described as follows:

[0101] like Figure 4BAs shown, the 4 rows are represented by A, B, C and D respectively, and the 4 columns are represented by 0, 1, 2 and 4 respectively. If the selected anti-fuse memory cell 301 is A0, that is, the cell with row number A and column number 0, that is, the cell where the word line WL0 and the bit line BL0 intersect. The bit line connected to the cell A0 is the bit line BL0, which is connected to a low voltage. The bit lines not connected to the cell A0 are the bit lines BL1, BL2 and BL3, which are connected to a second positive voltage. The word line connected to the cell A0 is the word line WL0, which is connected to a first positive voltage. The word lines not connected to the cell A0 are the word lines WL1, WL2 and WL3, which are connected to a low voltage.

[0102] During the reading operation, the voltage of the first voltage source VPP is reduced to the third positive voltage, the bit line BL connected to the selected anti-fuse memory cell 301 is connected to the sensitive discharger and the word line WL connected to the first positive voltage; the bit line BL not connected to the selected anti-fuse memory cell 301 is disconnected from the bit line BL connected to the sensitive discharger, and the word lines WL not connected to the selected anti-fuse memory cell 301 are all connected to a low voltage; the first positive voltage, the second positive voltage and the third positive voltage are all greater than or equal to the working voltage of the NMOS tube, and the minimum value of the low voltage is 0V. In the embodiment of the present invention, the first positive voltage, the second positive voltage and the third positive voltage are all equal to the working voltage of the core NMOS tube or slightly greater than the working voltage of the core NMOS tube.

[0103] like Figure 4A As shown, in the storage array, in the anti-fuse storage units 301 in the same column, every two anti-fuse storage units 301 form an anti-fuse storage unit 301 combination.

[0104] In the anti-fuse memory unit 301 combination, the active areas 401 of the two anti-fuse memory units 301 are connected to form an integral structure and share the same first source and drain area 209a and are connected to the bit line BL corresponding to the same column through the same contact hole 306. The structure in which two adjacent active areas 401 are connected together at the end of the first source and drain area 209a is arranged in a "head-to-head" manner.

[0105] The active regions 401 of each anti-fuse memory cell 301 are isolated from each other by a field oxide layer 203. The structure where two adjacent active regions 401 are isolated from each other at the second source / drain region 209b is connected together in a "back-to-back" arrangement.

[0106] In the embodiment of the present invention, the number of the anti-fuse storage units 301 in the storage array can be set as required. Figure 4AThe structure can be expanded and will not be described in detail here.

[0107] like Figure 5 , which is a structural diagram of another storage array of the anti-fuse OTP memory according to an embodiment of the present invention; the storage array 501b is an m*n array, Figure 5 In the example, an m*n array is also represented by array m*n, where m and n are both positive integers greater than 1.

[0108] The first voltage source VPP supplies power to the entire memory array through a power mesh 502. That is, the same first voltage source VPP supplies power to all the anti-fuse memory cells 301 at the same time, which is more suitable for the memory array with medium capacity.

[0109] Depend on Figure 5 As shown, the anti-fuse memory cell 301 in the memory array 501b is selected by the bit line BL and the word line WL. The bit line BL is selected by the column address signal and the bit line multiplexer 503 (BL MUX). The word line WL is selected by the row address signal and decoded by the word line decoder 504 (WL decoder).

[0110] like Figure 6 , which is a structural diagram of another storage array of the anti-fuse OTP memory according to an embodiment of the present invention; and Figure 5 The difference is that the capacity of the storage array 501b is large, that is, the values ​​of m and n are larger. At this time, if the same first voltage source VPP is used to power all the anti-fuse storage units 301 at the same time, the leakage of the large-capacity anti-fuse storage units 301 will be relatively large, which is likely to cause a large drop in the voltage of the first voltage source VPP and increase power consumption.

[0111] The first voltage source VPP is divided into a plurality of first voltage source VPP sub-blocks, each of which corresponds to a storage array sub-block of the storage array. When the storage array sub-block is working, the corresponding first voltage source VPP sub-block is selected for power supply. Figure 6 , VPP[0], VPP[1] to VPP[i] are voltages output by i first voltage source VPP sub-blocks, and each voltage is selected by a first voltage source multiplexer 505 (VPP MUX). During operation, only the corresponding first voltage source VPP is added to the selected memory array sub-block, and the corresponding first voltage source VPP is not added to the unselected memory array sub-block, so the voltage drop of the first voltage source VPP and the power consumption can be reduced.

[0112] The embodiment of the present invention makes a special arrangement for the first spacing between the first gate structure 302 and the second gate structure 303 of the anti-fuse storage unit 301, so that the first spacing is smaller than the minimum spacing of the layout design rules and is greater than or equal to the minimum spacing that can be manufactured by the gate process. In this way, the first spacing can be reduced as much as possible under the condition of ensuring the realization of manufacturing the gate structure, breaking through the limitation of the minimum spacing of the layout design rules on the first spacing, so that the unit size can be reduced and the storage density can be improved. The improvement of storage density can reduce manufacturing costs.

[0113] In addition, the embodiment of the present invention sets the first spacing to be smaller than the minimum spacing of the layout design rules. During the layout design process, violation detection of the design rules for the first spacing can be avoided by setting an identification layer, and no mask operation is required. Therefore, the embodiment of the present invention sets the first spacing to be smaller than the minimum spacing of the layout design rules, and does not require the addition of additional masks, thereby not causing an increase in manufacturing costs.

[0114] The embodiment of the present invention can ensure that only a lightly doped drain region 208b that is self-aligned with the first side wall 206 is formed on the surface of the well region 202 between the first gate structure 302 and the second gate structure 303 by setting a first spacing, combined with the setting of the first side wall 206 and the second side wall 207. The second side wall 207 completely fills the first spacing region between the first gate structure 302 and the second gate structure 303 to realize a source-drain injection blocking structure and prevent the formation of a source-drain injection region on the surface of the well region 202 between the first gate structure 302 and the second gate structure 303. Firstly, the process of only forming the second lightly doped drain region 208b in the area between the gate structures and not forming a source-drain injection region is completely implemented by self-alignment, which has the advantages of simple process and low cost.

[0115] Secondly, the region between the gate structures only forms the second lightly doped drain region 208b and does not form the source-drain injection region, so that the series node of the control tube 304 and the anti-fuse tube 305 is realized by the second lightly doped drain region 208b. Compared with the existing structure in which the series node of the control tube 304 and the anti-fuse tube 305 adopts the heavily doped source-drain injection region, the resistance of the series node is increased, which can reduce the leakage current such as the GIDL leakage current. During the programming process, the reduction of the leakage current can reduce the reduction of the programming voltage, thereby improving the programming success rate; the reduction of the leakage current can also reduce the reading power consumption. Therefore, the embodiment of the present invention can also reduce the leakage current and thereby improve the programming success rate and reduce the reading power consumption.

[0116] like 7A to 7F , which is a schematic diagram of the cross-sectional structure of the anti-fuse memory unit in each step of the method for manufacturing the anti-fuse OTP memory according to the embodiment of the present invention; in the method for manufacturing the anti-fuse OTP memory according to the embodiment of the present invention, the step of forming the anti-fuse memory unit 301 includes:

[0117] Step 1: Fig. 7A As shown, a semiconductor substrate 201 is provided, a well region 202 doped with a second conductivity type is formed in the semiconductor substrate 201 , a field oxide layer 203 is formed in the well region 202 and defines an active region 401 of the anti-fuse memory cell 301 .

[0118] Step 2: forming a gate structure, including:

[0119] like Fig. 7A As shown, a first dielectric layer 204 and a second conductive material layer 205 are formed in sequence.

[0120] like Figure 7B As shown, a first photomask is used to define the formation regions of the first gate structure 302 and the second gate structure 303 .

[0121] The second conductive material layer 205 and the first dielectric layer 204 are etched in sequence to form a first gate structure 302 and a second gate structure 303 on the surface of the well region 202 .

[0122] The first gate structure 302 includes a first gate dielectric layer 204a and a first gate conductive material layer 205a stacked in sequence; the second gate structure 303 includes a second gate dielectric layer 204b and a second gate conductive material layer 205b stacked in sequence; the first gate dielectric layer 204a and the second gate dielectric layer 204b are both composed of the first dielectric layer 204 after etching; the first gate conductive material layer 205a and the second gate conductive material layer 205b are both composed of the second conductive material layer 205 after etching; there is a first spacing between the second side of the first gate structure 302 and the first side of the second gate structure 303; the first spacing is less than the minimum spacing of the layout design rule and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process.

[0123] In some embodiments, the first dielectric layer 204 is a silicon dioxide layer, and the second conductive material layer 205 is polysilicon. In other embodiments, the first dielectric layer 204 can be a high dielectric constant (HK) gate oxide layer, and the second conductive material layer 205 can be a metal gate.

[0124] Please refer to the layout corresponding to the first mask Figure 3 As shown, Figure 3 A first gate conductive material layer 205 a and a second gate conductive material layer 205 b are respectively formed in the formation regions of the first gate structure 302 and the second gate structure 303 .

[0125] like Figure 3As shown, the first spacing is smaller than the minimum spacing of the layout design rule, so the layout design of the first mask defining the gate structure cannot pass the layout design rule check. In the method of the embodiment of the present invention, it is also necessary to set an identification layer 402 to avoid the violation of the design rule of the first spacing. This identification layer 402 will not be used for special calculations of the mask, and no additional mask will be added to increase the manufacturing cost.

[0126] Step 3: Figure 7C As shown, the first spacer 206 is formed on the first side surface and the second side surface of the first gate structure 302 and the first side surface and the second side surface of the second gate structure 303 in a self-aligned manner.

[0127] Two times of the thickness of the first spacer 206 is smaller than the first interval, and a first spacing region is provided between the first spacer 206 at the second side of the first gate structure 302 and the first spacer 206 at the first side of the second gate structure 303 .

[0128] Step 4: Fig.7D As shown, a first conductive type lightly doped drain implantation is performed to form a first lightly doped drain region 208a, a second lightly doped drain region 208b and a third lightly doped drain region 208c.

[0129] The first lightly doped drain region 208a is self-aligned to form a surface area of ​​the well region 202 at the first side wall 206 on the first side of the first gate structure 302; the second lightly doped drain region 208b is self-aligned to form a surface area of ​​the well region 202 at the bottom of the first spacer region; the third lightly doped drain region 208c is self-aligned to form a surface area of ​​the well region 202 at the first side wall 206 on the second side of the second gate structure 303.

[0130] Step 5: Fig. 7E As shown, the second spacer 207 is formed by self-alignment on the side surfaces of the first spacer 206 at the first side surface and the second side surface of the first gate structure 302 and the first side surface and the second side surface of the second gate structure 303 .

[0131] The second spacer 207 completely fills the first spacer region and forms a source-drain injection blocking structure.

[0132] Step 6: Figure 7F As shown, a first conductive type heavily doped source / drain implantation is performed to form a first source / drain region 209 a and a second source / drain region 209 b .

[0133] The first source and drain regions 209 a are formed in a self-aligned manner on a surface region of the well region 202 at the second spacer 207 on a first side surface of the first gate structure 302 .

[0134] The second source and drain regions 209 b are formed in a self-aligned manner on a surface region of the well region 202 at the second sidewall spacer 207 of the second side surface of the second gate structure 303 .

[0135] The source-drain injection blocking structure ensures that there is no source-drain injection region heavily doped with the first conductivity type in the surface area of ​​the well region 202 at the bottom of the first spacer region.

[0136] The first gate structure 302 is used as the gate structure of the control tube 304 , the second gate structure 303 is used as the gate structure of the anti-fuse tube 305 , and the second lightly doped drain region 208 b is used as the series node between the control tube 304 and the anti-fuse tube 305 .

[0137] Also includes the steps:

[0138] An interlayer film, a contact hole 306 and a front metal layer are formed, and the front metal layer is patterned to form word lines WL, bit lines BL and first voltage source VPP connections. Figure 4A shown.

[0139] like Figure 4A As shown, a storage array is formed by arranging a plurality of anti-fuse storage units 301 .

[0140] In the memory array, the first gate conductive material layers 205 a in the same row are all connected to the word lines WL in the same row.

[0141] Each of the first source and drain regions 209 a in the same column is connected to the bit line BL in the same column through the corresponding contact hole 306 .

[0142] The second source and drain regions 209 b of each of the anti-fuse memory cells 301 are both floating.

[0143] The second gate conductive material layer 205 b of each of the anti-fuse memory cells 301 is connected to the first voltage source VPP connection line through the corresponding contact hole 306 and is connected to the first voltage source VPP through the first voltage source VPP connection line.

[0144] The well region 202 of each of the anti-fuse memory cells 301 is connected to a fixed point.

[0145] In the embodiment of the present invention, the control transistor 304 and the anti-fuse transistor 305 are both NMOS, the first conductivity type is N type, and the second conductivity type is P type. In other embodiments, the control transistor 304 and the anti-fuse transistor 305 are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

[0146] In the storage array, in the anti-fuse storage units 301 in the same column, every two anti-fuse storage units 301 form an anti-fuse storage unit 301 combination.

[0147] In the anti-fuse memory unit 301 combination, the active areas 401 of two anti-fuse memory units 301 are connected to form an integral structure and share the same first source and drain area 209a and are connected to the bit line BL corresponding to the same column through the same contact hole 306; the active areas 401 of each anti-fuse memory unit 301 combination are isolated by the field oxide layer 203.

[0148] In some examples, such as Figure 5 As shown, the first voltage source VPP supplies power to the entire storage array through the power grid 502 .

[0149] In some examples, such as Figure 6 As shown, the first voltage source VPP is divided into a plurality of first voltage source VPP sub-blocks, each of the first voltage source VPP sub-blocks corresponds to a storage array sub-block of the storage array, and when the storage array sub-block is working, the corresponding first voltage source VPP sub-block is selected for power supply.

[0150] The anti-fuse OTP memory of the embodiment of the present invention can further reduce the distance between the gate of the gate control tube 302 and the gate of the anti-fuse tube 303 based on the existing device structure, and the second side walls of the two gates are in a superimposed interconnected form, and the ion implantation of the source and drain region between the two gates is removed, leaving only the lightly doped drain region (LDD). Figure 3 In the layout shown, the embodiment of the present invention needs to additionally add an identification layer 402 of the anti-fuse storage unit 301 to avoid violations of the design rules and manufacturing rules of the minimum gate spacing. This identification layer 402 will not be used for special calculations of the mask, and no additional masks will be added to increase manufacturing costs.

[0151] In the embodiment of the present invention, since the spacing between the gate control tube 302 and the anti-fuse device, that is, the anti-fuse tube 303, is significantly reduced, the area of ​​a single anti-fuse storage unit 301 is also significantly reduced, and can be reduced by 15% to 35% according to the process implementation, thereby reducing the manufacturing cost of the chip. In addition, since the source-drain injection between the gate control tube 302 and the anti-fuse device is removed, only the LDD provides a series path, and its series resistance is significantly increased. For unselected storage cells, the drain leakage current (GIDL) of the gate control tube 302 caused by the high-voltage gate of the adjacent anti-fuse device is significantly suppressed. For a large-capacity storage array, there will be a large number of unselected storage cells in a single programming process. A smaller GIDL can avoid local programming failures caused by the high-voltage programming power supply voltage being pulled down.

[0152] Since the gate spacing of the anti-fuse memory cell 301 of the embodiment of the present invention is smaller than the gate spacing of the existing anti-fuse memory cell, the embodiment of the present invention has a higher storage density, lower manufacturing cost, smaller leakage current, higher programming success rate, and lower reading power consumption.

[0153] In the embodiment of the present invention, Figure 4B As shown, during programming operation:

[0154] The voltage of VPP is the voltage that can break down the anti-fuse dielectric layer, namely the second gate dielectric layer 204b. The high voltage of WL / BL is the core MOS voltage or slightly higher than this voltage. VPP is the first voltage source VPP. WL is the word line and BL is the bit line.

[0155] There are 4 different states of storage cells, for example:

[0156] The A0 storage cell is selected for programming, its WL0 is high, BL0 is low, and the programming operation can be performed. A0 indicates that the row number is A and the column number is 0, and A corresponds to the row number 0 in WL0. The numbers after A in A1, A2, and A3 are also the corresponding column numbers; B, C, and D in B0, C0, and D0 are also the corresponding row numbers, and B, C, and D correspond to the row numbers 1, 2, and 3 in WL1, WL2, and WL3, respectively.

[0157] At this time, in the A1, A2, A3 cells in the same row, WL0 is high, BL1, BL2, BL3 are high, the LDD potential under the antifuse is also high, and the voltage difference of the gate dielectric layer is not enough to break down, so programming is impossible.

[0158] At this time, in the B0, C0, D0 cells in the same column, WL1, WL2, WL3 are low, BL0 is low, and after the LDD under the anti-fuse is charged to high by the gate leakage current, the gate dielectric layer voltage difference is not enough to break through, and programming is also impossible; in other cells in different rows and columns, WL1, WL2, WL3 are low, BL1, BL2, BL3 are high, and similarly the anti-fuse gate dielectric layer cannot be broken through. Therefore, this array can realize the programming operation of a specific address.

[0159] During the reading process:

[0160] The VPP voltage is reduced to a voltage slightly higher than the core MOS voltage but can ensure the reliability of the gate dielectric layer, i.e., the second gate dielectric layer 204b. The high voltage of WL is the core MOS voltage or slightly higher. BL transmits the voltage to the sensitive amplifier and sampling module through the column selection module to realize data reading.

[0161] For example, when a data reading operation is performed on the A0 unit, if this unit is programmed, the VPP voltage of the anti-fuse gate, i.e., the second gate conductive material layer 205b, is connected in series to the selection control tube 302 through a smaller equivalent resistor. At this time, BL0 will generate a larger read current, and the resistance voltage division of BL0 to ground in the sampling module is higher, so the programmed data is read out.

[0162] If the cell is not programmed, the VPP voltage of the anti-fuse gate has negligible effect on the leakage current of LDD, ie, the second lightly doped drain region 208b, and there is almost no read current on BL0. The voltage division of the sampling module is approximately 0, and the unprogrammed data is read.

[0163] For the memory cells in the same row, although VPP and WL0 are both turned on, BL1, BL2, and BL3 are not selected to the sampling module and can be approximately in a floating state, so BL1, BL2, and BL3 will not generate a read current.

[0164] For storage cells in different rows, WL1, WL2, and WL3 are low, and VPP will not supply power to BL through these cells, and will not affect the data reading of the selected cells.

[0165] In the embodiment of the present invention, in order to increase the density of the storage array, the selection control tubes 302 in adjacent rows are arranged "head to head" to share the source and drain region, namely the first source and drain region 209a, and are connected to the BL potential through punching, and the anti-fuse devices in adjacent rows are arranged "back to back". However, since the anti-fuse gates in the same column are connected to the same high voltage, the active areas of the "back-to-back" anti-fuse devices need to be isolated to avoid mutual conduction that leads to programming and reading failures.

[0166] The storage array of the embodiment of the present invention can be Figure 4A The 2*2 is replicated and expanded to a larger capacity, and WL and BL are selected through row and column decoding.

[0167] In some examples, such as Figure 5 As shown, VPP can interconnect the entire array through a power grid.

[0168] In some examples, such as Figure 6 As shown, according to the leakage of the actual memory cell, the VPP of some columns can be connected together, and the entire array is divided into multiple blocks of VPP, namely the first voltage source VPP sub-blocks, and through certain column decoding address selection, only the VPP power supply of the selected block is turned on, thereby reducing the leakage of the entire array. Similarly, when the word line gate WL is overloaded, or the long line metal resistance of the bit line BL causes a voltage drop, if it affects the overall speed or read-write characteristics of the memory, more array blocks can be divided for design.

[0169] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An anti-fuse OTP memory, characterized in that: include: an anti-fuse memory cell formed in the active region; The anti-fuse memory cell comprises: a well region of a second conductivity type formed in a semiconductor substrate, a first gate structure and a second gate structure formed on a surface of the well region; There is a first spacing between the second side of the first gate structure and the first side of the second gate structure; the first spacing is smaller than the minimum spacing of the layout design rule and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process; A first side wall and a second side wall are sequentially formed on the first side wall and the second side wall of the first gate structure and the first side wall and the second side wall of the second gate structure in a self-aligned manner; A first lightly doped drain region of a first conductivity type is formed in a self-aligned manner in a surface area of ​​the well region at the first sidewall of the first gate structure; A first source and drain region heavily doped with a first conductivity type is self-aligned and formed in a surface area of ​​the well region at the second sidewall of the first side of the first gate structure; The thickness of the first sidewall is twice less than the first spacing, a first spacing region is provided between the first sidewall at the second side of the first gate structure and the first sidewall at the first side of the second gate structure, and the second lightly doped drain region is self-aligned to form a surface region of the well region at the bottom of the first spacing region; The second sidewall completely fills the first spacer and forms a source-drain injection blocking structure, and there is no source-drain injection region heavily doped with the first conductivity type in the surface area of ​​the well region at the bottom of the first spacer; A third lightly doped drain region of the first conductivity type is formed in a self-aligned manner in a surface area of ​​the well region at the first sidewall of the second side surface of the second gate structure; A second source and drain region heavily doped with a first conductivity type is self-aligned and formed in a surface area of ​​the well region at the second sidewall of the second gate structure; The first gate structure is used as the gate structure of the control tube, the second gate structure is used as the gate structure of the anti-fuse tube, and the second lightly doped drain region is used as the series node of the control tube and the anti-fuse tube.

2. The anti-fuse OTP memory according to claim 1, characterized in that: The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked in sequence; The second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

3. The anti-fuse OTP memory according to claim 2, characterized in that: The first gate dielectric layer and the second gate dielectric layer are made of the same material and are formed at the same time; The first gate conductive material layer and the second gate conductive material layer are made of the same material and are formed at the same time.

4. The anti-fuse OTP memory according to claim 2, characterized in that: A storage array comprising a plurality of anti-fuse storage cells arranged to form a storage array; In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row; The first source and drain regions in the same column are connected to the bit line in the same column; The second source and drain regions of each of the anti-fuse memory cells are both floatingly arranged; The second gate conductive material layer of each of the anti-fuse memory cells is connected to a first voltage source; The well region of each of the anti-fuse memory cells is connected to a fixed point.

5. The anti-fuse OTP memory according to claim 4, characterized in that: The control tube and the anti-fuse tube are both NMOS, the first conductivity type is N type, and the second conductivity type is P type; or, the control tube and the anti-fuse tube are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

6. The anti-fuse OTP memory according to claim 5, characterized in that: The control tube and the anti-fuse tube are both NMOS; The well region of each of the anti-fuse memory cells is grounded; During a programming operation, the voltage of the first voltage source is a programming voltage greater than a breakdown voltage of the second gate dielectric layer; The bit line connected to the selected anti-fuse memory cell is connected to a low voltage and the word line connected to the selected anti-fuse memory cell is connected to a first positive voltage, and the first positive voltage turns on the control tube; the bit lines not connected to the selected anti-fuse memory cell are all connected to a second positive voltage and the word lines not connected to the selected anti-fuse memory cell are all connected to a low voltage; During a read operation, the voltage of the first voltage source is reduced to a third positive voltage, the bit line connected to the selected anti-fuse memory cell is connected to a sensitive discharger, and the word line connected to the bit line is connected to a first positive voltage; the bit line not connected to the selected anti-fuse memory cell is disconnected from the sensitive discharger, and the word lines not connected to the selected anti-fuse memory cell are connected to a low voltage; the first positive voltage, the second positive voltage and the third positive voltage are all greater than or equal to the operating voltage of the NMOS tube, and the minimum value of the low voltage is 0V.

7. The anti-fuse OTP memory according to claim 4, characterized in that: In the storage array, in the anti-fuse storage cells in the same column, every two anti-fuse storage cells form an anti-fuse storage cell combination; In the anti-fuse memory cell combination, the active regions of two anti-fuse memory cells are connected to form an integral structure and share the same first source and drain region and are connected to the bit line corresponding to the same column through the same contact hole; The active regions of each anti-fuse memory unit combination are isolated by a field oxide layer.

8. The anti-fuse OTP memory according to claim 4, characterized in that: The first voltage source supplies power to the entire storage array through a power mesh; Alternatively, the first voltage source is divided into a plurality of first voltage source sub-blocks, each of the first voltage source sub-blocks corresponds to a storage array sub-block of the storage array, and when the storage array sub-block is operating, the corresponding first voltage source sub-block is selected for power supply.

9. A method for manufacturing an anti-fuse OTP memory, characterized in that: The steps of forming an anti-fuse memory cell include: Step 1, providing a semiconductor substrate, forming a well region doped with a second conductivity type in the semiconductor substrate, forming a field oxide layer in the well region and defining an active region of the anti-fuse memory cell; Step 2: forming a gate structure, including: forming a first dielectric layer and a second conductive material layer in sequence; Using a first photomask to define a formation area of ​​a first gate structure and a second gate structure; Sequentially etching the second conductive material layer and the first dielectric layer to form a first gate structure and a second gate structure on the surface of the well region; The first gate structure comprises a first gate dielectric layer and a first gate conductive material layer stacked in sequence; the second gate structure comprises a second gate dielectric layer and a second gate conductive material layer stacked in sequence; the first gate dielectric layer and the second gate dielectric layer are both composed of the first dielectric layer after etching; the first gate conductive material layer and the second gate conductive material layer are both composed of the second conductive material layer after etching; there is a first spacing between the second side surface of the first gate structure and the first side surface of the second gate structure; the first spacing is less than the minimum spacing of the layout design rule and the first spacing is greater than or equal to the minimum spacing that can be manufactured by the gate process; Step 3: forming a first spacer by self-alignment on the first side surface and the second side surface of the first gate structure and the first side surface and the second side surface of the second gate structure; Two times of the thickness of the first spacer is smaller than the first spacing, and a first spacing region is provided between the first spacer at the second side of the first gate structure and the first spacer at the first side of the second gate structure; Step 4: performing a lightly doped drain implantation of the first conductivity type to form a first lightly doped drain region, a second lightly doped drain region and a third lightly doped drain region; The first lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the first sidewall of the first side of the first gate structure; the second lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the bottom of the first spacer; the third lightly doped drain region is self-aligned and formed in the surface area of ​​the well region at the first sidewall of the second side of the second gate structure; Step 5, forming a second spacer by self-aligning the first side surface and the second side surface of the first gate structure and the first side surface and the second side surface of the second gate structure on the side surface of the first spacer; The second sidewall spacer completely fills the first spacer and forms a source-drain injection blocking structure; Step 6: Performing source-drain implantation with heavy doping of the first conductivity type to form a first source-drain region and a second source-drain region; The first source and drain regions are self-aligned and formed in a surface area of ​​the well region at the second sidewall of the first side of the first gate structure; The second source and drain regions are self-aligned and formed in a surface area of ​​the well region at the second sidewall of the second side of the second gate structure; The source-drain injection blocking structure ensures that there is no source-drain injection region heavily doped with the first conductivity type in the surface area of ​​the well region at the bottom of the first spacer region; The first gate structure is used as the gate structure of the control tube, the second gate structure is used as the gate structure of the anti-fuse tube, and the second lightly doped drain region is used as the series node of the control tube and the anti-fuse tube.

10. The method for manufacturing an anti-fuse OTP memory according to claim 9, wherein: Also includes the steps: Forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a word line, a bit line and a first voltage source connection line; A storage array formed by arranging a plurality of said anti-fuse storage units; In the memory array, the first gate conductive material layers in the same row are all connected to the word lines in the same row; Each of the first source and drain regions in the same column is connected to the bit line in the same column through the corresponding contact hole; The second source and drain regions of each of the anti-fuse memory cells are both floatingly arranged; The second gate conductive material layer of each of the anti-fuse memory cells is connected to the first voltage source connection line through the corresponding contact hole and is connected to the first voltage source through the first voltage source connection line; The well region of each of the anti-fuse memory cells is connected to a fixed point.

11. The method for manufacturing an anti-fuse OTP memory according to claim 10, wherein: The control tube and the anti-fuse tube are both NMOS, the first conductivity type is N type, and the second conductivity type is P type; or, the control tube and the anti-fuse tube are both PMOS, the first conductivity type is P type, and the second conductivity type is N type.

12. The method for manufacturing an anti-fuse OTP memory according to claim 10, wherein: In the storage array, in the anti-fuse storage cells in the same column, every two anti-fuse storage cells form an anti-fuse storage cell combination; In the anti-fuse memory cell combination, the active regions of two anti-fuse memory cells are connected to form an integral structure and share the same first source and drain region and are connected to the bit line corresponding to the same column through the same contact hole; The active regions of each anti-fuse memory cell combination are isolated by the field oxide layer.

13. The method for manufacturing an anti-fuse OTP memory according to claim 10, wherein: The first voltage source supplies power to the entire storage array through a power mesh; Alternatively, the first voltage source is divided into a plurality of first voltage source sub-blocks, each of the first voltage source sub-blocks corresponds to a storage array sub-block of the storage array, and when the storage array sub-block is operating, the corresponding first voltage source sub-block is selected for power supply.

14. The method for manufacturing an anti-fuse OTP memory according to claim 9, wherein: A first identification layer is used in the layout design of the first mask. The coverage area of ​​the first identification layer is larger than the formation area of ​​the first gate structure and the second gate structure, so as to avoid the violation of the design rule of the first spacing.

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