Flash memory structure and flash memory

Abstract

The invention provides a flash memory structure and a flash memory, the flash memory structure comprises a plurality of groups of active array regions and end regions located between the adjacent active array regions, in the horizontal direction, a source line layer in each end region is of a U-shaped structure, an opening of each U-shaped structure faces a word line contact hole, and the opening of each U-shaped structure faces the corresponding word line contact hole. Through the design of the U-shaped structure, the area of the word line layer connected with the word line contact hole is far away from the source line layer, and enough process windows are ensured to prevent short circuit of the word line contact hole and the source line layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory structure and a flash memory. Background Art

[0002] There are two types of flash memory: stack gate flash memory and split gate flash memory. Stack gate flash memory has a floating gate and a control gate located above the floating gate. Stack gate flash memory has the problem of crossing the source line. Unlike stack gate flash memory, split gate flash memory forms a word line as a source line gate on one side of the floating gate, and split gate flash memory can effectively avoid the crossing source line effect.

[0003] In the split-gate flash memory structure design, a strap area is formed between every several I / Os, such as Figure 1 In the Strap region, the word line contact hole (Word Line CT) and the source line contact hole (Source line CT) are separated according to their special structure, as shown in FIG. Figure 2 and Figure 5 As shown, the function of controlling the word line and the source line respectively is realized.

[0004] In the structure of Flash cell design, if the floating gate etching process window (FGPL CD) is too large, the source polysilicon size (SPL CD) will be too large, and the distance between the insulating layer (SPL) and the word line (WL) isolated by the sidewall isolation process (FGSP) will be shortened. Figure 4 As shown, when the overlay (CT OVL) of the contact window is too large, it will cause a potential risk of short-circuiting (Bridge) between the contact hole of the word line and the source line, thereby causing IM fail. Summary of the invention

[0005] The object of the present invention is to provide a flash memory structure and a flash memory, comprising a plurality of groups of active array areas and terminal areas located between adjacent active array areas, and by changing the structural design of the terminal areas, the area where the word line layer connects the word line contact hole is moved away from the source line layer, ensuring that there is sufficient process window to prevent the word line contact hole from short-circuiting with the source line layer.

[0006] To achieve the above object, the present invention provides a flash memory structure, which solves the problem of IM failure caused by the connection between the word line contact hole area and the source line layer. The flash memory structure includes a plurality of groups of active array areas and terminal areas located between adjacent active array areas, and the terminal areas include:

[0007] A semiconductor substrate including a source line floating gate region and a word line bit line region adjacent to each other;

[0008] A floating gate structure, located in the source line floating gate region, comprising a floating gate layer, a first sidewall spacer located in the floating gate layer, a source line layer located between the floating gate layer and the first sidewall spacer, and a source line contact hole located on the source line layer and connected to the source line layer;

[0009] A word line structure, located in the word line and bit line region, comprising a word line layer and a word line contact hole located on the word line layer and connected to the word line layer, wherein the word line layer covers the floating gate layer and the sidewall of the first spacer;

[0010] Among them, in the horizontal direction, the source line layer is in a U-shaped structure, and the U-shaped structure opens toward the word line contact hole. The U-shaped structure design is used to keep the area where the word line layer connects to the word line contact hole away from the source line layer, ensuring that there is enough process window to prevent the word line contact hole from short-circuiting with the source line layer.

[0011] In some optional embodiments, the floating gate structure further includes a source region located in the semiconductor substrate at the bottom of the source line layer.

[0012] In some optional embodiments, the word line structure also includes a second sidewall located on the sidewall of the word line layer, a bit line located in the semiconductor substrate in the word line bit line region, and a drain region located in the semiconductor substrate at the bottom of the bit line and the bottom of the second sidewall.

[0013] In some optional embodiments, a gate oxide layer is disposed between the semiconductor substrate and the floating gate layer.

[0014] In some optional embodiments, within the end region, the U-shaped structure includes a first U-shaped structure and a second U-shaped structure, and in the horizontal direction, the first U-shaped structure is nested within the periphery of the second U-shaped structure, the opening directions of the first U-shaped structure and the second U-shaped structure are opposite, and the opening directions of the first U-shaped structure and the second U-shaped structure are both toward the word line contact hole.

[0015] In some of the optional embodiments, in a horizontal direction, the first U-shaped structure and the second U-shaped structure are not in contact.

[0016] In some optional embodiments, the end head region includes two sets of the U-shaped structures, and the two sets of the U-shaped structures are symmetrical about the center of the end head region.

[0017] In a second aspect, based on the same inventive concept, the present invention further provides a flash memory, wherein the flash memory comprises the flash memory structure as described in any one of the above items.

[0018] In summary, the present invention provides a flash memory structure and a flash memory, comprising a plurality of groups of active array areas and terminal areas located between adjacent active array areas. In the horizontal direction, the source line layer in the terminal area is in a U-shaped structure, and the opening of the U-shaped structure faces the word line contact hole. The U-shaped structure is designed to keep the area where the word line layer connects the word line contact hole away from the source line layer, thereby ensuring that there is enough process window to prevent the word line contact hole from short-circuiting with the source line layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a flash memory device including a plurality of active array regions and terminal regions located between adjacent active array regions;

[0020] Figure 2 It is a SEM image of the horizontal direction of the terminal area in the flash memory structure;

[0021] Figure 3 It is a SEM image of the terminal area in the vertical direction of the flash memory structure;

[0022] Figure 4 It is a schematic diagram of the structure of a storage unit in a flash memory structure;

[0023] Figure 5 A schematic diagram of the header area layout in the flash memory structure;

[0024] Figure 6 A layout of a header region of a flash memory structure provided by an embodiment of the present invention.

[0025] Wherein, the accompanying drawings are marked as follows:

[0026] 100-semiconductor substrate; 101-source region; 102-drain region;

[0027] 110-floating gate structure; 111-gate oxide layer; 112-floating gate; 113-first sidewall spacer; 114-source line layer; 115-source line contact control;

[0028] 120 - word line structure; 121 - word line layer; 122 - word line contact hole; 123 - second sidewall; 124 - bit line layer. DETAILED DESCRIPTION

[0029] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0030] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0031] For ease of description, some embodiments of the present invention may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" the other elements or components. The terms "first", "second", etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0032] Figure 4 is a schematic diagram of the structure of a storage unit in a flash memory structure, Figure 6 A schematic diagram of a flash memory structure provided by an embodiment of the present invention, referring to Figure 4 and Figure 6 As shown, the present invention provides a flash memory structure, comprising: a plurality of active array areas and terminal areas located between adjacent active array areas, wherein the terminal areas include:

[0033] The semiconductor substrate 100 includes a source line floating gate region I and a word line bit line region II adjacent to each other;

[0034] A floating gate structure 110, located in the source line floating gate region I, includes a floating gate layer 112, a first spacer 113 located on the floating gate structure, a source line 114 layer located between the floating gate layer 112 and the first spacer 113, and a source line contact hole 115 located on the source line layer 114 and connected to the source line layer;

[0035] A word line structure 120, located in the word line and bit line region II, includes a word line layer 121 and a word line contact hole 122 located on the word line layer 121 and connected to the word line layer 121, wherein the word line layer 121 covers the floating gate layer 112 and the sidewalls of the first spacer 113;

[0036] Among them, in the horizontal direction (parallel to the direction of the semiconductor substrate), the source line layer 114 is in a U-shaped structure, and the U-shaped structure opens toward the word line contact hole 122. The U-shaped structure is designed to keep the area where the word line layer 121 connects to the word line contact hole 122 away from the source line layer 114, ensuring that there is enough process window to prevent the word line contact hole 122 from short-circuiting with the source line layer 114.

[0037] Specifically, the floating gate structure 110 further includes a gate oxide layer 111 located between the semiconductor substrate 100 and the floating gate layer 112. Furthermore, the floating gate structure 110 further includes a source region 101 located in the semiconductor substrate 100 at the bottom of the source line layer 114.

[0038] The word line structure 120 further includes a second sidewall spacer 123 located on the sidewall of the word line layer 121 , a bit line layer 124 located in the semiconductor substrate in the word line bit line region, and a drain region 102 located in the semiconductor substrate at the bottom of the bit line layer 124 and the bottom of the second sidewall spacer 123 .

[0039] Continue to refer Figure 6 As shown, in the end region, the source line layer 114 is in a U-shaped structure, and the U-shaped structure includes a first U-shaped structure U1 and a second U-shaped structure U2. In the horizontal direction, the first U-shaped structure U1 and the second U-shaped structure U2 are not in contact, and the first U-shaped structure U1 is nested in the periphery of the second U-shaped structure U2. The opening directions of the first U-shaped structure U1 and the second U-shaped structure U2 are opposite, and the opening directions of the first U-shaped structure U1 and the second U-shaped structure U2 are both toward the word line contact hole 122.

[0040] Furthermore, the terminal region includes at least two sets of the U-shaped structures, and the two sets of the U-shaped structures are symmetrical about the center of the terminal region. The first U-shaped structures U1 in the two sets of U-shaped structures are connected, and the second U-shaped structures U2 in the two sets of U-shaped structures are separated by the connected first U-shaped structures U1. The word line contact hole 122 is located in the first U-shaped structure U1, and the area where the word line layer 121 connects the word line contact hole 122 is far away from the source line layer 114, ensuring that there is enough process window to prevent the word line contact hole 122 from short-circuiting with the source line layer 114.

[0041] Figure 3 This is a SEM image of the vertical direction of the terminal area in the flash memory structure. Figure 5 FIG. 1 is a schematic diagram of the terminal area layout in the flash memory structure. Figure 3 and Figure 5 As shown, in the original design, in order to connect the word line (WL) in the terminal area of ​​the flash memory structure, an arc-shaped source line (SL) structure is designed, and the area of ​​the word line layer is along the side wall of the first sidewall (FGSP). This arc-shaped design will fill the word line layer connected to the word line contact hole (Contact), but because the source line layer and the word line layer are separated only by FGSP, OVL deviation occurs when connecting the word line contact hole. Figure 3 and Figure 5As shown, a physical verification analysis (PFA) is performed on the abnormal point P where the word line contact hole and the source line are shorted. The PFA result shows that a short circuit (Bridge) occurs between the word line contact hole and the source line (SL), resulting in IM failure.

[0042] In this embodiment, in the terminal region of the flash memory structure, the U-shaped structure of the source line layer is used to separate the area where the word line layer is connected to the word line contact hole from the source line layer. For example, the word line layer can be grown along the sidewall of the floating gate layer, and the position of the U-shaped structure and the cell will be filled with word line layer polysilicon (World line poly), which is subsequently used to connect the word line contact hole, so that the area of ​​the word line contact hole is separated from the source line layer.

[0043] In other embodiments of the present invention, the present invention further provides a flash memory, wherein the storage unit includes the above-mentioned flash memory structure.

[0044] In summary, the present invention provides a flash memory structure and a flash memory, comprising a plurality of groups of active array areas and terminal areas located between adjacent active array areas. In the horizontal direction, the source line layer in the terminal area is in a U-shaped structure, and the opening of the U-shaped structure faces the word line contact hole. The U-shaped structure is designed to keep the area where the word line layer connects the word line contact hole away from the source line layer, thereby ensuring that there is enough process window to prevent the word line contact hole from short-circuiting with the source line layer.

[0045] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A flash memory structure, characterized in that: It comprises a plurality of groups of active array areas and terminal areas located between adjacent active array areas, wherein the terminal areas include: A semiconductor substrate including a source line floating gate region and a word line bit line region adjacent to each other; A floating gate structure, located in the source line floating gate region, comprising a floating gate layer, a first spacer located in the floating gate layer, a source line layer located between the floating gate layer and the first spacer, and a source line contact hole located on the source line layer and connected to the source line layer; A word line structure, located in the word line and bit line region, comprising a word line layer and a word line contact hole located on the word line layer and connected to the word line layer, wherein the word line layer covers the floating gate layer and the sidewall of the first spacer; Among them, in the horizontal direction, the source line layer is in a U-shaped structure, and the U-shaped structure opens toward the word line contact hole. The U-shaped structure design is used to keep the area where the word line layer connects to the word line contact hole away from the source line layer, ensuring that there is enough process window to prevent the word line contact hole from short-circuiting with the source line layer.

2. The flash memory structure according to claim 1, characterized in that: The floating gate structure further includes a source region located in the semiconductor substrate at the bottom of the source line layer.

3. The flash memory structure according to claim 1, characterized in that: The word line structure further includes a second spacer located at the sidewall of the word line layer, a bit line located in the semiconductor substrate in the word line bit line region, and a drain region located in the semiconductor substrate at the bottom of the bit line and the bottom of the second spacer.

4. The flash memory structure according to claim 1, characterized in that: A gate oxide layer is arranged between the semiconductor substrate and the floating gate layer.

5. The flash memory structure according to claim 1, characterized in that: In the end region, the U-shaped structure includes a first U-shaped structure and a second U-shaped structure. In the horizontal direction, the first U-shaped structure is nested in the periphery of the second U-shaped structure. The opening directions of the first U-shaped structure and the second U-shaped structure are opposite, and the opening directions of the first U-shaped structure and the second U-shaped structure are both toward the word line contact hole.

6. The flash memory structure according to claim 5, characterized in that: In the horizontal direction, the first U-shaped structure and the second U-shaped structure are not in contact.

7. The flash memory structure according to claim 6, characterized in that: The end head area includes two sets of U-shaped structures, and the two sets of U-shaped structures are symmetrical about the center of the end head area.

8. A flash memory, characterized in that: The flash memory comprises a flash memory structure as claimed in any one of claims 1 to 7.

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