Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present application provides a semiconductor structure and a method for manufacturing the same. In the method for manufacturing the semiconductor structure provided in the embodiment of the present application, after forming a first channel between the semiconductor pillar and the substrate, the first channel is processed using an oxidation reaction process and an etching process to remove the protrusions at the connection of the cavity, thereby achieving a flattening effect. This allows the formed bit line channel to have a greater degree of flattening than the first channel, facilitating the subsequent formation of a relatively flat bit line in the bit line channel. This helps reduce the probability of voids in the bit line and helps ensure the quality of the bit line. Furthermore, it helps ensure the uniformity of the radial dimensions of the bit line along the extension direction, helping to ensure the electrical performance of the bit line.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, memory represented by three-dimensional stacked memory has become a key research and development direction. In three-dimensional stacked memory, the bit line is often located between the substrate and the transistor.

[0003] Currently, the manufacturing process for 3D stacked memory typically involves lateral etching of the bottom of a semiconductor pillar to create a cavity, and then forming a bit line within the cavity. However, the bottom and top walls of the cavity are often poorly flat, making the formed bit line prone to voids, which can reduce memory performance. Summary of the Invention

[0004] In view of the shortcomings of the existing methods, this application proposes a semiconductor structure and a manufacturing method thereof, which at least improves the deficiencies in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] A plurality of first spacers and first trenches for separating the first spacers are formed on one side of the substrate; the first spacers include a plurality of semiconductor pillars and a plurality of sacrificial pillars, the semiconductor pillars and the sacrificial pillars are alternately arranged along a first direction parallel to the substrate; and the first trenches extend along the first direction;

[0007] forming a first protective structure covering the first side wall;

[0008] Using the first protection structure as a mask, etching is performed to expose the substrate at the bottom of the first trench and the substrate below the semiconductor pillar, so that a first channel is formed between the semiconductor pillar and the substrate; the first channel includes a plurality of cavities arranged and connected along a second direction parallel to the substrate and perpendicular to the first direction, and a convex portion is formed at the connection between any two adjacent cavities;

[0009] The first channel is processed based on an oxidation reaction process and an etching process to obtain a bit line channel with the protrusion removed.

[0010] In a second aspect, an embodiment of the present application provides a semiconductor structure formed by the method for manufacturing the semiconductor structure provided in the first aspect, the semiconductor structure comprising: a plurality of transistors arranged in an array, a plurality of word lines, and a plurality of bit lines, the bit lines being filled in a bit line channel having flat circumferential sidewalls, the word lines extending in a direction perpendicular to the direction of the bit lines extending, wherein the bit line channel is formed based on an oxidation reaction and an etching process;

[0011] The semiconductor column of the transistor includes a bottom, a middle and a top stacked along a third direction perpendicular to the substrate, and the peripheral wall of the middle portion is surrounded by a gate dielectric layer and a gate; each bit line is connected to the bottom of a column of transistors arranged along the second direction, and each word line is connected to the gate of a row of transistors arranged along the first direction; the first direction and the second direction are both parallel to the substrate, and the first direction is perpendicular to the second direction.

[0012] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0013] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, after forming a first channel between a semiconductor pillar and a substrate, the first channel is processed using an oxidation reaction process and an etching process to remove the protrusions at the connection points of the cavities, thereby achieving a flattening effect. This ensures that the flattening degree of the formed bit line channel is greater than that of the first channel, facilitating the subsequent formation of relatively flat bit lines in the bit line channel. This helps reduce the probability of voids in the bit lines and helps ensure the quality of the bit lines.

[0014] At the same time, it helps to ensure the uniformity of the radial dimension of the bit line along the extension direction, and helps to ensure the electrical performance of the bit line.

[0015] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic flow chart of a semiconductor structure manufacturing method provided in an embodiment of the present application;

[0018] Figure 2 A schematic top view of a film layer structure after a first hard mask structure is formed on one side of an initial substrate in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0019] Figure 3 for Figure 2 Schematic diagram of the cross-section of the membrane layer at point aa in the membrane layer structure shown;

[0020] Figure 4 for Figure 2 The schematic diagram of the cross-section of the membrane layer at point bb in the membrane layer structure shown;

[0021] Figure 5 for Figure 2 Schematic diagram of the cross-section of the membrane layer at position cc in the membrane layer structure shown;

[0022] Figure 6 for Figure 2 Schematic diagram of the cross-section of the membrane layer at point dd in the membrane layer structure shown;

[0023] Figure 7 A schematic diagram of a cross-sectional film layer at point aa after forming a semiconductor wall in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of a cross-sectional film layer at point bb after forming a semiconductor wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0025] Figure 9 A schematic diagram of a cross-sectional film layer at position cc after forming a semiconductor wall in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0026] Figure 10 A schematic diagram of a cross-sectional film layer at point bb after forming a second barrier layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0027] Figure 11 A schematic diagram of a cross-sectional film layer at point cc after forming a second barrier layer in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0028] Figure 12 A schematic diagram of a cross-sectional film layer at point bb after forming a second hard mask structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0029] Figure 13 A schematic diagram of a cross-sectional film layer at position cc after forming a second hard mask structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0030] Figure 14 A schematic diagram of a cross-sectional film layer at point aa after forming a first trench in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0031] Figure 15 A schematic diagram of a cross-sectional film layer at point bb after forming a first trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0032] Figure 16 A schematic diagram of a cross-sectional film layer at point cc after forming a first trench in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0033] Figure 17 A schematic diagram of a cross-sectional film layer at point dd after forming a first trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0034] Figure 18A schematic diagram of a cross-sectional film layer at point aa after forming a first channel in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0035] Figure 19 A schematic diagram of a cross-sectional film layer at point bb after forming a first channel in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0036] Figure 20 A schematic diagram of a cross-sectional film layer at position cc after forming a first channel in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 21 A schematic diagram of a cross-sectional film layer at point dd after forming a first channel in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0038] Figure 22 A schematic diagram of a cross-sectional film layer at point aa after forming a bit line channel in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 23 A schematic diagram of a cross-sectional film layer at position cc after forming a bit line channel in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0040] Figure 24 A schematic diagram of a cross-sectional film layer at point aa after forming a bit line in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0041] Figure 25 A schematic diagram of a cross-sectional film layer at position cc after forming a bit line in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0042] Figure 26 A schematic diagram of a cross-sectional film layer at point aa after forming a first isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0043] Figure 27 A schematic diagram of a cross-sectional film layer at point bb after forming a first isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0044] Figure 28 A schematic diagram of a cross-sectional film layer at point dd after forming a first isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0045] Figure 29 A schematic diagram of a cross-sectional film layer at point bb after forming a second isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0046] Figure 30A schematic diagram of a cross-sectional film layer at position cc after forming a second isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0047] Figure 31 A schematic diagram of a cross-sectional film layer at point dd after forming a second isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0048] Figure 32 A schematic diagram of a cross-sectional film layer at point bb after forming a third isolation wall in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0049] Figure 33 A schematic diagram of a cross-sectional film layer at point aa after etching back the first sub-protection structure and the second isolation structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 34 A schematic diagram of a cross-sectional film layer at point bb after etching back the first sub-protection structure and the second isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0051] Figure 35 A schematic diagram of a cross-sectional film layer at point cc after etching back the first sub-protection structure and the second isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0052] Figure 36 A schematic diagram of a cross-sectional film layer at point aa after forming a support structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0053] Figure 37 A schematic diagram of a cross-sectional film layer at point bb after forming a support structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0054] Figure 38 A schematic diagram of a cross-sectional film layer at point cc after forming a support structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0055] Figure 39 A schematic diagram of a cross-sectional film layer at point aa after etching back the second protection structure and the second sub-isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0056] Figure 40 A schematic diagram of a cross-sectional film layer at point bb after etching back the second protection structure and the second sub-isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0057] Figure 41A schematic diagram of a cross-sectional film layer at point cc after etching back the second protection structure and the second sub-isolation structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0058] Figure 42 A schematic diagram of a cross-sectional film layer at point aa after forming a word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0059] Figure 43 A schematic diagram of a cross-sectional film layer at point bb after forming a word line in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0060] Figure 44 A schematic diagram of a cross-sectional film layer at position cc after forming a word line in a method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0061] Description of reference numerals:

[0062] 100 - initial substrate; 101 - first barrier layer; 102 - first hard mask structure; 1021 - first sub-mask structure; 1022 - second sub-mask structure;

[0063] 103 - substrate; 104 - semiconductor wall; 1041 - first semiconductor structure; 1042 - second semiconductor structure; 105 - first spacing trench; 106 - sacrificial wall; 1061 - sacrificial structure; 107 - second barrier layer; 1071 - second barrier structure;

[0064] 108 - second hard mask structure; 1081 - third sub-mask structure; 1082 - fourth sub-mask structure; 109 - first spacer; 1091 - semiconductor pillar; 1092 - sacrificial pillar;

[0065] 110 - first groove; 111 - first protection structure; 1111 - first protection substructure; 1112 - second protection substructure; 1113 - second protection structure; 1114 - third protection structure;

[0066] 112 - first channel; 1121 - cavity; 1122 - convex portion; 1123 - top wall sacrificial layer; 1124 - bottom wall sacrificial layer; 1125 - top wall; 1126 - bottom wall;

[0067] 113 - bit line channel; 114 - bit line; 115 - first isolation wall; 1151 - first isolation structure;

[0068] 116 - second isolation wall; 1161 - second isolation structure; 1162 - second sub-isolation structure; 1163 - third sub-isolation structure;

[0069] 117 - third isolation wall; 118 - support structure; 119 - gate dielectric layer; 120 - gate; 121 - word line; 122 - transistor; 123 - gap. DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0071] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" to another element, the element may be directly connected to the other element, or it may refer to a connection relationship between the element and the other element through an intermediate element. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0072] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0073] In the manufacturing process of three-dimensional stacked memory, a cavity is formed between the bottom of a semiconductor pillar and the substrate. Multiple interconnected cavities arranged in the same direction form a bitline channel. However, during the etching process to form the cavity, due to limitations in the etching process, the top and bottom walls of the resulting bitline channel have significant protrusions and depressions, resulting in poor flatness of the top and bottom walls. During the subsequent bitline formation process, the resulting bitline is susceptible to voids due to the influence of the protrusions, resulting in poor density and uniformity of the bitline. Sharp protrusions can also exacerbate the Schottky barrier at the contact point between the bitline and the protrusion, affecting the read and write speed of the memory and reducing memory performance.

[0074] Moreover, due to the poor flatness of the top and bottom walls, the thickness of the formed bit lines in the extension direction is significantly inconsistent, resulting in significant resistance variation of the bit lines along the extension direction, further reducing the performance of the memory.

[0075] The semiconductor structure and manufacturing method thereof provided in this application are intended to solve the above technical problems of the prior art.

[0076] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0077] The present invention provides a method for manufacturing a semiconductor structure. The flowchart of the method is as follows: Figure 1 As shown, the method includes steps S101 to S104.

[0078] S101, forming a plurality of first sidewalls and a first trench for spacing the first sidewalls on one side of a substrate; the first sidewalls include a plurality of semiconductor pillars and a plurality of sacrificial pillars, and the semiconductor pillars and the sacrificial pillars are alternately arranged along a first direction parallel to the substrate; and the first trench extends along the first direction.

[0079] S102 , forming a first protection structure covering the first sidewall.

[0080] S103, using the first protective structure as a mask, etching to expose the substrate at the bottom of the first trench and the substrate below the semiconductor pillar, so that a first channel is formed between the semiconductor pillar and the substrate; the first channel includes a plurality of cavities arranged and connected along a second direction parallel to the substrate and perpendicular to the first direction, and a convex portion is formed at the connection between any two adjacent cavities.

[0081] S104 , processing the first channel based on an oxidation reaction process and an etching process to obtain a bit line channel with the protrusion removed.

[0082] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, after forming a first channel between a semiconductor pillar and a substrate, the first channel is processed using an oxidation reaction process and an etching process to remove the protrusions at the connection points of the cavities, thereby achieving a flattening effect. This ensures that the flattening degree of the formed bit line channel is greater than that of the first channel, facilitating the subsequent formation of relatively flat bit lines in the bit line channel. This helps reduce the probability of voids in the bit lines and helps ensure the quality of the bit lines.

[0083] At the same time, it helps to ensure the uniformity of the radial dimension of the bit line along the extension direction, and helps to ensure the electrical performance of the bit line.

[0084] In the manufacturing method of the semiconductor structure provided in the embodiment of the present application, in the process of processing the first channel based on the oxidation reaction process, since the thickness of the protrusion is larger than that of other parts of the first channel, the protrusion protrudes from the other parts of the first channel, and the protrusion has a larger surface area than other parts of the first channel, so that the contact area between the protrusion and the reactant (such as oxygen, nitrogen, etc.) is larger, and the reaction rate of the protrusion is greater than the reaction rate of other parts, so that the protrusion can be completely reacted before other parts to form a substance different from the substrate and the semiconductor column material, so that the reacted protrusion can be removed by an etching process, so that the formed bit line channel has a relatively flat top wall and bottom.

[0085] In order to facilitate readers to intuitively understand the semiconductor structure manufacturing method provided by the embodiment of the present application and the advantages of the manufacturing method, the following will be combined with Figure 2-Figure 44 A method for manufacturing a semiconductor structure is described in detail.

[0086] Optionally, in one embodiment of the present application, in the above step S101, a plurality of first spacers 109 and first trenches 110 for separating the first spacers are formed on one side of the substrate 103, comprising: forming a first hard mask structure 102 on one side of the initial substrate 100, wherein the extension direction of the first hard mask structure 102 is parallel to the second direction; patterning the initial substrate 100 based on the first hard mask structure 102 to form a substrate 103 and a plurality of semiconductor walls 104 located on one side of the substrate 103, wherein any two adjacent semiconductor walls 104 are formed on the same side of the substrate 103; A first spacing trench 105 is provided between the semiconductor walls 104; a sacrificial wall 106 is formed to fill the first spacing trench 105, and a second barrier layer 107 is formed to cover the semiconductor walls 104 and the sacrificial wall 106; a second hard mask structure 108 is formed on one side of the second barrier layer 107, and the extension direction of the second hard mask structure 108 is parallel to the first direction; the semiconductor walls 104 and the sacrificial wall 106 are patterned based on the second hard mask structure 108 to form a plurality of first sidewalls 109 and a plurality of first trenches 110.

[0087] Optionally, in one embodiment of the present application, a first hard mask structure 102 is formed on one side of the initial substrate 100 in the above steps, including: depositing a first barrier layer 101, a first mask layer, and a second mask layer in sequence on one side of the initial substrate 100; forming a photoresist layer on a side of the second mask layer away from the original substrate 100; exposing and developing the photoresist layer to form a photoresist mask structure; patterning the first mask layer and the second mask layer based on the photoresist mask structure, and using the first barrier layer 101 as a stop layer, the patterned first mask layer forms a first sub-mask structure 1021, and the patterned second mask layer forms a second sub-mask structure 1022, and the first hard mask structure 102 includes the first sub-mask structure 1021 and the second sub-mask structure 1022.

[0088] Alternatively, as Figure 2 、 Figure 3 、 Figure 4 as well as Figure 5 As shown, a plurality of first hard mask structures 102 spaced apart along a first direction are provided on a side of the first barrier layer 101 away from the original substrate 100 , and the first hard mask structures 102 extend along a second direction.

[0089] It should be noted that, in order to facilitate readers to intuitively understand the various intermediate structures and the structure of the final semiconductor structure formed in the semiconductor structure manufacturing method provided in the embodiment of the present application, as shown in FIG. Figure 2 As shown, a portion of the semiconductor pillar 1091 to be formed subsequently is exemplarily identified by a dotted frame.

[0090] Optionally, in an embodiment of the present application, the material of the original substrate 100 includes single crystal silicon, the material of the first barrier layer 101 includes silicon oxide, the material of the first sub-mask structure 1021 includes polycrystalline silicon, and the material of the second sub-mask structure 1022 includes silicon oxynitride.

[0091] Optionally, in one embodiment of the present application, the above steps include patterning the initial substrate 100 based on the first hard mask structure 102 to form a substrate 103 and a plurality of semiconductor walls 104 located on one side of the substrate 103, including: using the first hard mask structure 102 as a mask, etching the first barrier layer 101 and the initial substrate 100 until a plurality of first spacing trenches 105 of a preset depth are formed, and the original substrate 100 after etching forms the substrate 103 and a plurality of semiconductor walls 104 located on one side of the substrate 103; and removing the first hard mask structure 102.

[0092] Alternatively, as Figure 7 、 Figure 8 and Figure 9 As shown, a first spacing trench 105 is provided between any two adjacent semiconductor walls 104 , that is, along the first direction, the semiconductor walls 104 and the first spacing trenches 105 are alternately arranged in sequence.

[0093] It should be noted that, in order to facilitate readers to intuitively understand the relationship between the substrate 103, the semiconductor wall 104 and the first spacing trench 105, as shown in FIG. Figure 7 and Figure 9 As shown, the dividing line between the substrate 103 and the semiconductor wall 104 is represented by a dotted line. In actual products, the substrate 103 and the semiconductor wall 104 are an integrated structure and do not exist. Figure 7 and Figure 9 The dashed line is shown.

[0094] Optionally, in one embodiment of the present application, the above steps form a sacrificial wall 106 filling the first spacing trench 105 and form a second barrier layer 107 covering the semiconductor wall 104 and the sacrificial wall 106, including: forming the sacrificial wall 106 filling the first spacing trench 105 based on a deposition process, and forming the second barrier layer 107 based on a deposition process.

[0095] Alternatively, as Figure 10 and Figure 11 As shown, each first spacing trench 105 is filled with a sacrificial wall 106. Optionally, during the formation of the sacrificial wall 106, a CMP (Chemical Mechanical Polishing) process may be used to make the top surface of the sacrificial wall 106 and the semiconductor wall 104 coplanar.

[0096] Alternatively, as Figure 11 As shown, along the first direction, the semiconductor walls 104 and the sacrificial walls 106 are alternately arranged.

[0097] Optionally, in an embodiment of the present application, the material of the sacrificial wall 106 includes silicon nitride, and the material of the second barrier layer 107 includes silicon oxide.

[0098] Optionally, in the embodiment of the present application, the specific process steps for forming the second hard mask structure 108 may refer to the process steps for forming the first hard mask structure 102 , which will not be repeated here.

[0099] Optionally, in the embodiment of the present application, Figure 12 and Figure 13 As shown, the second hard mask structure 108 includes a stacked third sub-mask structure 1081 and a fourth sub-mask structure 1082. Figure 12 As shown, a plurality of second hard mask structures 108 are arranged at intervals along the second direction; Figure 13 As shown, the extension direction of the second hard mask structure 108 is parallel to the first direction.

[0100] Optionally, during the process of forming the second hard mask structure 108 , the second barrier layer 107 acts as a barrier, thereby preventing the semiconductor wall 104 and the sacrificial wall 106 from being etched in this step.

[0101] Optionally, in an embodiment of the present application, the material of the third sub-mask structure 1081 includes silicon carbide, and the material of the fourth sub-mask structure 1082 includes silicon oxynitride.

[0102] Optionally, in one embodiment of the present application, the above steps of patterning the semiconductor wall 104 and the sacrificial wall 106 based on the second hard mask structure 108 to form a plurality of first sidewalls 109 and a plurality of first trenches 110 include: using the second hard mask structure 108 as a mask, etching the semiconductor wall 104 and the sacrificial wall 106 until a plurality of first trenches 110 and a plurality of first sidewalls 109 of a preset depth are formed.

[0103] Optionally, in the embodiment of the present application, Figure 14 and Figure 16 As shown, the patterned semiconductor wall 104 forms a semiconductor pillar 1091 and a first semiconductor structure 1041 . The semiconductor pillar 1091 is disposed on a side of the first semiconductor structure 1041 away from the substrate 103 .

[0104] Alternatively, as Figure 15 and Figure 16 As shown, the patterned sacrificial wall 106 forms a plurality of sacrificial pillars 1092 and a sacrificial structure 1061 . The sacrificial pillars 1092 are disposed on a side of the sacrificial structure 1061 away from the substrate 103 . The patterned second barrier layer 107 forms a second barrier structure 1071 .

[0105] Alternatively, as Figure 14 、 Figure 15 、 Figure 16 as well as Figure 17 As shown, the first spacer 109 includes a plurality of semiconductor pillars 1091 and a plurality of sacrificial pillars 1092. The semiconductor pillars 1091 and the sacrificial pillars 1092 are alternately arranged along a first direction parallel to the substrate 103. The first spacers 109 and the first trenches 110 both extend along the first direction; along the second direction, the first spacers 109 and the first trenches 110 are alternately arranged.

[0106] Optionally, in one embodiment of the present application, the first protective structure 111 covering the first side wall is formed in the above-mentioned step S102, including: sequentially forming a first protective layer and a second protective layer covering the first side wall 109 and the bottom of the first trench 110; the material of the second protective layer is different from the semiconductor compound formed after the convex portion is reacted; etching the first protective layer and the second protective layer to form a first protective substructure 1111 and a second protective substructure 1112 of the first protective structure 111, respectively, so that the bottom of the first trench 110 is exposed.

[0107] Optionally, in an embodiment of the present application, a first protective layer and a second protective layer are sequentially formed based on a deposition process; the first protective layer and the second protective layer are patterned to form a first protective structure 111 so that the bottom of the first trench 110 is exposed.

[0108] Optionally, in the embodiment of the present application, the material of the first protection substructure 1111 includes silicon oxide, and the material of the second protection substructure 1112 includes silicon nitride.

[0109] Optionally, in one embodiment of the present application, in the above-mentioned step S103, the first protective structure 111 is used as a mask to etch and expose the substrate 103 in the first trench 110 and the substrate 103 located below the semiconductor pillar 1091, so that a first channel 112 is formed between the semiconductor pillar 1091 and the substrate 103, including: based on an etching process, using the first protective structure 111 as a mask, etching the portion of the first semiconductor structure 1041 exposed in the first trench 110 until the first channel 112 located between the substrate 103 and the semiconductor pillar 1091 is formed.

[0110] Alternatively, as Figure 18 、 Figure 19 、 Figure 20 as well as Figure 21 Figure 1 shows a schematic cross-sectional structure diagram along the aa, bb, cc, and dd directions after forming the first channel 112. The first semiconductor structure 1041 is etched to form the second semiconductor structure 1042. The first channel 112 is located between the second semiconductor structure 1042 and the array formed by the plurality of semiconductor pillars 1091. The first channel 112 extends along the second direction.

[0111] Alternatively, as Figure 18 As shown, the first channel 112 includes a plurality of cavities 1121 , and a convex portion 1122 is formed at the connection between any two adjacent cavities 1121 .

[0112] Those skilled in the art understand that, in the process of forming the first channel 112 through an etching process, due to limitations of process conditions, the first semiconductor structure 1041 is difficult to be etched along a specific direction, resulting in the formation of a convex portion 1122 at the connection between any two adjacent cavities 1121, causing the top and bottom walls of the first channel 112 to be uneven and have poor flatness, thereby affecting the density and uniformity of the bit lines subsequently formed in the first channel 112. Moreover, the sharp convex portion 1122 will aggravate the Schottky barrier and affect the read and write speeds of the semiconductor structure.

[0113] Optionally, in one embodiment of the present application, the above step is to process the first channel 112 based on the oxidation reaction process and the etching process in step 104 to obtain the bit line channel 113 with the protrusion 1122 removed, including: processing the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 of the first channel 112 including the protrusion 1122 based on the oxidation reaction whose reaction rate increases with the increase of the film thickness; the top wall sacrificial layer 1123 is located on the top wall 1125 of the first channel 112 away from the semiconductor pillar 1091 On one side, the bottom wall sacrificial layer 1124 is located on the side of the bottom wall 1126 of the first channel 112 facing the semiconductor column 1091; the surface undulations of the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 away from the central axis of the first channel 112 are greater than the surface undulations of the top wall 1125 and the bottom wall 1126; the reacted top wall sacrificial layer 1123 and the reacted bottom wall sacrificial layer 1124 are etched away, so that the top wall 1125 and the bottom wall 1126 are exposed to form the bit line channel 113.

[0114] Optionally, in the embodiment of the present application, Figure 18 and Figure 20 As shown, for the first channel 112 , the top wall sacrificial layer 1123 is located on the side of the top wall 1125 away from the semiconductor column 1091 , and the bottom wall sacrificial layer 1124 is located on the side of the bottom wall 1126 facing the semiconductor column 1091 . Both the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1123 include a protrusion 1122 .

[0115] It should be noted that, in order to facilitate readers to intuitively understand the top wall sacrificial layer 1123, the bottom wall sacrificial layer 1124, the top wall 1125 and the bottom wall 1126 in the first channel 112, as shown in FIG. Figure 18 and Figure 20 As shown, the top wall 1125 and the bottom wall 1126 are represented by dotted lines, but in the actual product, there are no dotted lines.

[0116] Optionally, in the embodiment of the present application, Figure 18 and Figure 20 As shown, the surface undulation of the top wall sacrificial layer 1123 away from the central axis of the first channel 112 is greater than the surface undulation of the top wall 1125, and the surface undulation of the bottom wall sacrificial layer 1124 away from the central axis of the first channel 112 is greater than the surface undulation of the bottom wall 1126. Therefore, after removing the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124, the flatness of the top wall 1125 and the bottom wall 1126 in the first channel 112 can be improved.

[0117] Alternatively, as Figure 22 and Figure 23As shown, the reacted top wall sacrificial layer 1123 and the reacted bottom wall sacrificial layer 1124 are removed, so that the top wall 1125 and the bottom wall 1126 are exposed, forming a bit line channel 113, and the bit line channel 113 has a flat circumferential sidewall. Figure 18 and Figure 22 It can be seen that the flatness of the bit line channel 113 is much greater than that of the first channel 112 , which helps to ensure the quality of the bit lines formed in the bit line channel 113 in subsequent processes.

[0118] Optionally, in one embodiment of the present application, the above-mentioned step is to process the first channel 112 based on the oxidation reaction process and the etching process in 104 to obtain the bit line channel 113 with the protrusion 1122 removed, and further includes: based on the oxygen atmosphere, so that the semiconductor element in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 forms a semiconductor oxide; or, based on the nitrogen atmosphere, so that the semiconductor element in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 forms a semiconductor nitride.

[0119] Optionally, the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 of the first channel 112 can be treated based on an oxidation reaction so that the semiconductor element in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 forms a semiconductor oxide, and the formed semiconductor oxide is removed by etching to expose the top wall 1125 and the bottom wall 1126.

[0120] In an embodiment of the present application, during the process of treating the first channel 112 through an oxidation reaction, for the convex portion 1122 in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124, since the convex portion 1122 is thicker than other parts, the convex portion 1122 protrudes from other parts, so that the convex portion 1122 has a larger surface area than other parts, thereby making the contact area between the convex portion 1122 and oxygen larger, and the oxidation rate of the convex portion 1122 is greater than the oxidation rate of other parts, so that the convex portion 1122 can be completely reacted before other parts, and finally the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 are both oxidized to form silicon oxide, so that the oxidized top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 can be removed through an etching process.

[0121] Optionally, the semiconductor element in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 may be formed into a semiconductor nitride based on a nitridation reaction, or the semiconductor element in the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 may be formed into a semiconductor carbide.

[0122] It should be noted that in the embodiment of the present application, during the reaction between the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124, the first protective structure 111 plays a role in protecting the semiconductor column 1091, preventing the side walls of the semiconductor column 1091 from reacting with oxygen, nitrogen, etc.; in the process of etching and removing the reacted top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124, the first protective structure 111 plays a role in stopping the etching, preventing the etching gas or etching gas from contacting the semiconductor column 1091.

[0123] Therefore, in the embodiment of the present application, the material of the second protective substructure 1112 in the first protective structure 111 should be different from the semiconductor compound generated by the top wall sacrificial layer 1123 and the bottom wall sacrificial layer 1124 after the reaction, so that the semiconductor compound has a larger etching rate ratio with the material of the second protective substructure 1112.

[0124] Optionally, the reacted top wall sacrificial layer 1123 and the reacted bottom wall sacrificial layer 1124 generate silicon oxide, and the material of the second protection substructure 1112 should be silicon nitride.

[0125] Optionally, in an embodiment of the present application, after the first channel 112 is processed based on the oxidation reaction process and the etching process in the above step 104 to obtain the bit line channel 113 with the protrusion 1122 removed, the method further includes: removing the second protection substructure 1112 .

[0126] Optionally, in the embodiment of the present application, in order to facilitate subsequent processes, after the bit line channel 113 is formed, the second protection substructure 1112 needs to be removed by an etching process to facilitate the subsequent formation of the bit line.

[0127] Optionally, in one embodiment of the present application, after the first channel 112 is processed based on the oxidation reaction process and the etching process in the above step 104 to obtain the bit line channel 113 with the protrusion 1122 removed, the step further includes: filling the bit line channel 113 with a conductive material to form a bit line 114 extending along the second direction.

[0128] Optionally, in the embodiment of the present application, after removing the second protection substructure 1112, a conductive material is filled into the bit line channel 113 based on a deposition process until the conductive material fills the bit line channel 113, thereby forming a bit line 114 extending along the second direction. Figure 24 and Figure 25 shown.

[0129] Optionally, in an embodiment of the present application, the deposition process includes an ALD (Atomic Layer Deposition) process.

[0130] Optionally, in one embodiment of the present application, after the above steps fill the bit line channel 113 with conductive material to form the bit line 114 extending along the second direction, the steps further include: etching the sacrificial column 1092 and the first protection structure 111 to remove the sacrificial column 1092, and forming the second protection structure 1113 from the etched first protection structure 111, so that the top peripheral wall of the semiconductor column 1061 is exposed; forming a support structure 118 surrounding the top peripheral wall; etching the second protection structure 1113 to expose the peripheral wall of the middle portion of the semiconductor column 1092 located below the top; forming a gate dielectric layer 119 surrounding the middle peripheral wall; forming a gate 120 surrounding the gate dielectric layer 119, and a word line 121 connected to the gate 120.

[0131] Optionally, in an embodiment of the present application, after forming the bit line 114, a gate dielectric layer 119 and a gate 120 surrounding the semiconductor pillar 1092 are formed in sequence to form an array of transistors, and then a word line 121 connected to the same row of transistors is formed to form a semiconductor structure.

[0132] Optionally, in one embodiment of the present application, before the sacrificial column 1092 and the first protective structure 111 are etched in the above steps to remove the sacrificial column 1092 and the etched first protective structure 111 forms a second protective structure 1113, so that the peripheral wall of the top of the semiconductor column 1091 is exposed, it also includes: forming a first isolation wall 115 filling the first trench 110; etching the sacrificial column 1092 and the first isolation wall 115 located between any two adjacent sacrificial columns 1092 until the sacrificial column 1092 is removed to form a plurality of second trenches extending along the second direction; the etched first isolation wall forms a first isolation structure; and forming a second isolation wall 116 filling the second trench.

[0133] Optionally, in the embodiment of the present application, forming the first isolation wall 115 filling the first trench 110 includes: depositing a dielectric material, such as silicon nitride, into the first trench 110 based on a deposition process to form the first isolation wall 115, such as Figure 26 、 Figure 27 as well as Figure 28 As shown, the first isolation wall 115 extends along a first direction.

[0134] Optionally, during the process of forming the first isolation wall 115 , a CMP process may be used to expose the surface of the first protection substructure 1111 .

[0135] Optionally, in the embodiment of the present application, the first isolation wall 115 , the sacrificial pillar 1092 , and the sacrificial structure 1061 are made of the same material.

[0136] Optionally, in an embodiment of the present application, etching the sacrificial pillars 1092 and the first isolation wall 115 located between any two adjacent sacrificial pillars 1092 until the sacrificial pillars 1092 are removed, thereby forming a plurality of second trenches extending along the second direction, includes: simultaneously etching the sacrificial pillars 109, the portion of the first isolation wall 115 located between any two adjacent sacrificial pillars 1092, and a portion of the first sub-protection structure 1111, until the sacrificial pillars 1092 and the sacrificial structure 1061 are removed, thereby forming a plurality of second trenches extending along the second direction. The etched first isolation wall 115 forms a first isolation structure 1151.

[0137] Optionally, in the embodiment of the present application, forming the second isolation wall 116 filling the second trench includes: depositing a dielectric material, such as silicon oxide, in the second trench based on a deposition process to form the second isolation wall 116. Figure 29 、 Figure 30 as well as Figure 31 As shown, the second isolation wall 116 extends along the second direction.

[0138] Optionally, in one embodiment of the present application, the above steps etch the sacrificial column 1092 and the first protective structure 111 to remove the sacrificial column 1092, and the etched first protective structure 111 forms a second protective structure 1113, so that the top peripheral wall of the semiconductor column 1091 is exposed, including: etching the portion of the second isolation wall 116 located between two adjacent semiconductor columns 1091 along the second direction to form a third trench; the etched second isolation wall 116 forms a second isolation structure 1161; forming a third isolation wall 117 that fills the third trench and exposes the top wall of the semiconductor column 1091; and etching back the first protective structure 111 and the second isolation structure 1161 to expose the top peripheral wall of the semiconductor column 1091.

[0139] Optionally, in an embodiment of the present application, etching a portion of the second isolation wall 116 located between two adjacent semiconductor pillars 1091 along the second direction to form a third trench includes: removing a portion of the second isolation wall 116 located between two adjacent semiconductor pillars 1091 along the second direction based on an etching process to form a third trench.

[0140] Optionally, in the embodiment of the present application, the bottom of the third trench is not lower than the upper surface of the bit line 114 , thereby preventing the bit line 114 from being short-circuited with a subsequently formed conductive component.

[0141] Optionally, in the embodiment of the present application, during the etching of the second isolation wall 116 , a portion of the first isolation structure 1151 will also be etched.

[0142] Optionally, in an embodiment of the present application, a third isolation wall 117 is formed to fill the third trench, and the top wall of the semiconductor column 1091 is exposed, including: depositing a dielectric material, such as silicon nitride, into the third trench based on a deposition process to form a third isolation wall 117 that fills the third trench; and processing the third isolation wall 117 and the first sub-protection structure 1111 of the first protection structure 111 based on a CMP process to expose the top wall of the semiconductor column 1091.

[0143] Optionally, in the embodiment of the present application, the first protection structure 111 and the second isolation structure 1161 are etched back to expose the peripheral wall of the top of the semiconductor column 1091, including: etching back a portion of the first sub-protection structure 1111 of the first protection structure 111 and a portion of the second isolation structure 1161 to expose the top of the semiconductor column 1091.

[0144] Alternatively, as Figure 33 、 Figure 34 and with Figure 35 As shown, after etching back part of the first sub-protection structure 1111 and part of the second isolation structure 1161, a gap is formed between the tops of any two adjacent semiconductor pillars 1091 along the first direction and the second direction, so that the peripheral walls of the tops are exposed.

[0145] Optionally, in the embodiment of the present application, since the first sub-protection structure 1111 and the second isolation structure 1161 are made of the same material, the first sub-protection structure 1111 and the second isolation structure 1161 can be etched back to the same depth based on the same etching process.

[0146] Optionally, the first sub-protection structure 1111 after etching back forms a second protection structure 1113 , and the second isolation structure 1161 after etching back forms a second sub-isolation structure 1162 .

[0147] Optionally, in one embodiment of the present application, the above steps form a supporting structure arranged around the top peripheral wall, including: forming a supporting structure 118 connected to both the top and the third isolation wall 117 .

[0148] Optionally, in an embodiment of the present application, forming a support structure 118 connected to both the top and the third isolation wall 117 includes: depositing a dielectric material on the peripheral wall of the top of the semiconductor column 1091 based on a deposition process to form a support structure 118 surrounding the top of the semiconductor column 1091, the support structure 118 being connected to the third isolation wall 117, the first isolation structure 1151, and the top of the semiconductor column 1091, as shown in FIG. Figure 36 、 Figure 37 as well as Figure 38 shown.

[0149] Optionally, the material of the support structure 118 , the material of the third isolation wall 117 , and the material of the first isolation structure 1151 are all the same.

[0150] Optionally, in one embodiment of the present application, the second protective structure 1113 is etched in the above step to expose the peripheral wall of the middle part below the top of the semiconductor column 1092, including: etching back the first protective structure 111 and the second isolation structure 1161 after etching, so that the peripheral wall of the middle part of the semiconductor column 1091 is exposed.

[0151] Optionally, in the embodiment of the present application, the first sub-protection structure 1111 is etched back to form the second protection structure 1113 and the second isolation structure 1161 is etched back to form the second sub-isolation structure 1162, and the etching is performed to a set depth so that the peripheral wall of the middle portion of the semiconductor pillar 1091 is exposed, as shown in FIG. Figure 39 、 Figure 40 as well as Figure 41 shown.

[0152] Alternatively, as Figure 39 As shown, a gap 123 is formed between two adjacent semiconductor pillars 1091 .

[0153] Optionally, the second protection structure 1113 after etching back forms a third protection structure 1114 , and the second sub-isolation structure 1162 after etching back forms a third sub-isolation structure 1163 .

[0154] Optionally, in one embodiment of the present application, the gate dielectric layer 119 surrounding the central peripheral wall is formed in the above steps, including: processing the exposed peripheral wall in the middle of the semiconductor column 1091 based on an oxidation process to form the gate dielectric layer 119 surrounding the central portion.

[0155] Optionally, in the embodiment of the present application, Figure 39 and Figure 41 As shown, since the peripheral wall of the middle portion of the semiconductor pillar 1091 is exposed, the semiconductor pillar 1091 can be treated based on an oxidation process. For example, in an oxidizing atmosphere, the silicon exposed in the semiconductor pillar 1091 undergoes an oxidation reaction to form silicon oxide, so that the peripheral wall exposed in the middle portion of the semiconductor pillar 1091 is formed into silicon oxide, forming a gate dielectric layer 119 surrounding the semiconductor pillar 1091, as shown in FIG. Figure 42 and Figure 44 shown.

[0156] Compared with forming the gate dielectric layer 119 based on a deposition process, in the embodiment of the present application, the distribution concentration of the oxidizing atmosphere is controlled through an oxidation process, so that the silicon exposed in the semiconductor column 1091 can undergo an oxidation reaction with a consistent oxidation rate, so that the formed silicon oxide is evenly distributed on the exposed peripheral wall of the semiconductor column 1091, and the film thickness of the formed silicon oxide can be kept consistent, thereby improving the formation quality of the gate dielectric layer 119, which is beneficial to ensuring the performance of the subsequently formed semiconductor devices.

[0157] Optionally, in one embodiment of the present application, the above steps form a gate 120 surrounding the gate dielectric layer 119 and a word line 121 connected to the gate 120, including: based on a deposition process, forming the gate 120 and the word line 121 at the same time, the gate 120 is arranged on the outer wall of the gate dielectric layer 119, and the word line 121 is connected to the gate 120.

[0158] Optionally, in the embodiment of the present application, Figure 42 As shown, the gate 120 is disposed on the outer peripheral wall of the gate dielectric layer 119. Figure 43 and Figure 44 As shown, the word line 121 extends along a first direction.

[0159] Based on the same inventive concept, an embodiment of the present application provides a semiconductor structure, including: a plurality of transistors 122 arranged in an array, a plurality of word lines 121, and a plurality of bit lines 114, the bit lines 114 filling a bit line channel 113 having a flat circumferential sidewall, the extension direction of the word lines 121 being perpendicular to the extension direction of the bit lines 114, wherein the bit line channel is formed based on an oxidation reaction and an etching process; a semiconductor pillar 1092 of the transistor 122 includes a bottom, a middle, and a top stacked along a third direction perpendicular to the substrate 103, the peripheral wall of the middle portion being surrounded by a gate dielectric layer 119 and a gate 120; each bit line 114 is connected to the bottom of a column of transistors 121 arranged along a second direction, and each word line 121 is connected to the gate 120 of a row of transistors 121 arranged along a first direction; the first direction and the second direction are both parallel to the substrate 103, and the first direction is perpendicular to the second direction.

[0160] In the embodiments of the present application, since the semiconductor structure is formed using any of the semiconductor structure manufacturing methods provided in the aforementioned embodiments, the top and bottom surfaces of the bit line 114 in the semiconductor structure have high flatness, which helps to ensure the electrical performance of the bit line 114 and also helps to reduce the Schottky barrier between the semiconductor pillars 1091 of the bit line 114. For any unfinished technical effects of the semiconductor structure provided in the embodiments of the present application, please refer to the aforementioned embodiments and will not be repeated here.

[0161] Optionally, in the embodiment of the present application, Figure 42 、 Figure 43 as well as Figure 44 As shown in FIG, it is a schematic diagram of the structure of the semiconductor structure. The semiconductor structure includes a plurality of transistors 122 arranged in an array. In order to facilitate readers to intuitively understand the schematic diagram of the structure of the semiconductor structure, as shown in FIG. Figure 42 as well as Figure 44 As shown, the transistor 122 is represented by a dotted line frame, but there is no dotted line in the actual product.

[0162] Optionally, in the embodiment of the present application, the bottom and top of the semiconductor column 1092 are the source and drain of the transistor 122 , and the middle of the semiconductor column 1092 is the channel portion of the transistor 122 .

[0163] Based on the same inventive concept, an embodiment of the present application provides a memory, which includes: any semiconductor structure provided by the above embodiments.

[0164] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: a memory provided by the above embodiments.

[0165] In the embodiments of the present application, since the electronic device adopts any one of the semiconductor structures provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be repeated here.

[0166] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0167] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor structure provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0168] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices have any semiconductor structure provided in the above embodiments.

[0169] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0170] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, after forming a first channel between a semiconductor pillar and a substrate, the first channel is processed using an oxidation reaction process and an etching process to remove the protrusions at the connection points of the cavities, thereby achieving a flattening effect. This ensures that the flattening degree of the formed bit line channel is greater than that of the first channel, facilitating the subsequent formation of relatively flat bit lines in the bit line channel. This helps reduce the probability of voids in the bit lines and helps ensure the quality of the bit lines.

[0171] At the same time, it helps to ensure the uniformity of the radial dimension of the bit line along the extension direction, and helps to ensure the electrical performance of the bit line.

[0172] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0173] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0174] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0175] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0176] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0177] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of first spacers and first trenches for separating the first spacers on one side of the substrate; The first sidewall spacer includes a plurality of semiconductor pillars and a plurality of sacrificial pillars, and the semiconductor pillars and the sacrificial pillars are alternately arranged along a first direction parallel to the substrate; the first trench extends along the first direction; forming a first protective structure covering the first side wall; Using the first protection structure as a mask, etching is performed to expose the substrate at the bottom of the first trench and the substrate below the semiconductor pillar, so that a first channel is formed between the semiconductor pillar and the substrate; the first channel includes a plurality of cavities arranged and connected along a second direction parallel to the substrate and perpendicular to the first direction, and a convex portion is formed at the connection between any two adjacent cavities; The top wall sacrificial layer and the bottom wall sacrificial layer including the protrusion in the first channel are processed based on an oxidation reaction process and an etching process or based on a nitridation reaction process and an etching process to obtain a bit line channel with the protrusion removed.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Processing the top wall sacrificial layer and the bottom wall sacrificial layer including the protrusion in the first channel based on an oxidation reaction process and an etching process or a nitridation reaction process and an etching process to obtain a bit line channel with the protrusion removed includes: Based on an oxidation reaction or a nitridation reaction whose reaction rate increases with increasing film thickness, a top wall sacrificial layer and a bottom wall sacrificial layer including the protrusion in the first channel are processed; the top wall sacrificial layer is located on a side of the top wall of the first channel away from the semiconductor pillar, and the bottom wall sacrificial layer is located on a side of the bottom wall of the first channel facing the semiconductor pillar; and a surface undulation of each of the top wall sacrificial layer and the bottom wall sacrificial layer away from the central axis of the first channel is greater than a surface undulation of the top wall and the bottom wall; The reacted top wall sacrificial layer and the reacted bottom wall sacrificial layer are removed by etching, so that the top wall and the bottom wall are exposed, thereby forming the bit line channel.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: Based on an oxidation reaction or a nitridation reaction whose reaction rate increases with increasing thickness of the film layer, processing the top wall sacrificial layer and the bottom wall sacrificial layer including the protrusion in the first channel, comprising: Based on the oxygen atmosphere, the semiconductor element in the top wall sacrificial layer and the bottom wall sacrificial layer forms a semiconductor oxide; Alternatively, based on a nitrogen atmosphere, the semiconductor element in the top wall sacrificial layer and the bottom wall sacrificial layer forms a semiconductor nitride.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: After processing the top wall sacrificial layer and the bottom wall sacrificial layer including the protrusion in the first channel based on an oxidation reaction process and an etching process or based on a nitridation reaction process and an etching process to obtain a bit line channel with the protrusion removed, the method further includes: filling a conductive material in the bit line channel to form a bit line extending along the second direction.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: After filling the bit line channel with a conductive material to form a bit line extending along the second direction, the method further includes: Etching the sacrificial column and the first protective structure to remove the sacrificial column, and forming a second protective structure from the etched first protective structure, so that the peripheral wall of the top of the semiconductor column is exposed; forming a supporting structure disposed around the top peripheral wall; Etching the second protection structure to expose a peripheral wall of a middle portion below the top portion of the semiconductor column; forming a gate dielectric layer surrounding the central peripheral wall; A gate surrounding the gate dielectric layer and a word line connected to the gate are formed.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: Before etching the sacrificial column and the first protective structure to remove the sacrificial column and forming a second protective structure from the etched first protective structure so that the peripheral wall of the top of the semiconductor column is exposed, the method further includes: forming a first isolation wall filling the first trench; etching the sacrificial pillars and the first isolation walls between any two adjacent sacrificial pillars until the sacrificial pillars are removed, thereby forming a plurality of second trenches extending along the second direction; the etched first isolation walls form a first isolation structure; A second isolation wall is formed to fill the second trench.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: Etching the sacrificial column and the first protective structure to remove the sacrificial column, and forming a second protective structure from the etched first protective structure so that the peripheral wall of the top of the semiconductor column is exposed, comprising: Etching a portion of the second isolation wall located between two adjacent semiconductor pillars along the second direction to form a third trench; the etched second isolation wall forms the second isolation structure; forming a third isolation wall filling the third trench and exposing a top wall of the semiconductor column; etching back the first protection structure and the second isolation structure so that the peripheral wall of the top of the semiconductor column is exposed; And, forming a supporting structure surrounding the peripheral wall of the top, including: forming the supporting structure connected to both the top and the third isolation wall.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: Etching the second protection structure to expose a peripheral wall of a middle portion below the top portion of the semiconductor column, comprising: The first protection structure and the second isolation structure after the etching are etched back, so that the peripheral wall of the middle portion of the semiconductor column is exposed.

9. The method for manufacturing a semiconductor structure according to claim 2, wherein: forming a first protective structure covering the first sidewall, comprising: forming a first protective layer and a second protective layer covering the first sidewall and the bottom of the first trench in sequence; the material of the second protective layer is different from the semiconductor compound formed after the protrusion is reacted; Etching the first protective layer and the second protective layer to respectively form a first protective substructure and a second protective substructure of the first protective structure, so that the bottom of the first trench is exposed; Furthermore, after processing the top wall sacrificial layer and the bottom wall sacrificial layer including the protrusion in the first channel based on an oxidation reaction process and an etching process or based on a nitridation reaction process and an etching process to obtain a bit line channel with the protrusion removed, it also includes: removing the second protective substructure.

10. A semiconductor structure, characterized in that The semiconductor structure is formed based on the manufacturing method according to any one of claims 1 to 9, characterized in that it comprises: a plurality of transistors arranged in an array, a plurality of word lines, and a plurality of bit lines, wherein the bit lines are filled in a bit line channel having a flat circumferential sidewall, the word lines extending in a direction perpendicular to the bit line extending direction, wherein the bit line channel is formed based on an oxidation reaction and etching process or based on a nitridation reaction process and etching process; The semiconductor column of the transistor includes a bottom, a middle and a top stacked along a third direction perpendicular to the substrate, and the peripheral wall of the middle portion is surrounded by a gate dielectric layer and a gate; each of the bit lines is connected to the bottom of a column of the transistors arranged along the second direction, and each of the word lines is connected to the gates of a row of the transistors arranged along the first direction; the first direction and the second direction are both parallel to the substrate, and the first direction is perpendicular to the second direction.

Images