Memory, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a memory, a manufacturing method thereof and electronic equipment. The memory comprises a substrate and a plurality of memory cells, each memory cell comprises a transistor, and each transistor comprises a gate electrode, a gate insulating layer, a channel region and two first protection structures. The gate insulating layer and the channel region are sequentially arranged on the periphery of the gate electrode; the gate insulating layer and the gate electrode extend along a first direction perpendicular to the substrate; the first protection structure is arranged on at least one side of the channel region along a second direction, and the second direction is parallel to the substrate; the etching rate of the material of the channel region is greater than that of the material of the first protection structure. According to the embodiment of the invention, the channel region and the first protection structure can form a relatively obvious etching selection ratio, and the first protection structure can protect the channel region when the parasitic channel region is etched, thereby facilitating the improvement of the performance stability of the memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory device and a method for manufacturing the memory device and an electronic device. Background Art

[0002] In current memories, the requirements for memory density are constantly increasing. In order to improve integration capabilities, reduce unit area, and manufacture more memory cells in the same chip area, the memory cell size needs to be continuously miniaturized as technology develops. As the memory density increases and the size of a single memory cell decreases, more problems are prone to occur. Summary of the invention

[0003] The present application provides a memory and a manufacturing method thereof, and an electronic device.

[0004] In a first aspect, some embodiments of the present application provide a memory, comprising: a substrate and a plurality of memory cells, wherein the memory cells include transistors, and the transistors include:

[0005] A gate electrode, a gate insulating layer and a channel region, wherein the gate insulating layer and the channel region are sequentially arranged at the periphery of the gate electrode; the gate insulating layer and the gate electrode both extend along a first direction perpendicular to the substrate;

[0006] A first protection structure is provided on at least one side of the channel region along a second direction, wherein the second direction is parallel to the substrate; an etching rate of a material of the channel region is greater than an etching rate of a material of the first protection structure.

[0007] In a second aspect, some embodiments of the present application provide an electronic device, comprising: the memory of the first aspect.

[0008] In a third aspect, some embodiments of the present application provide a method for manufacturing a memory, comprising:

[0009] A plurality of first storage structures arranged in an array and insulated from each other are manufactured on one side of a substrate, wherein the first storage structure comprises a plurality of first grooves arranged in an array in a plane parallel to the substrate, a plurality of first sacrificial layers arranged around the periphery of the first grooves and spaced along a first direction perpendicular to the substrate, and a first protection structure arranged on at least one side of the first grooves along a second direction parallel to the substrate;

[0010] performing side etching on the first sacrificial structure through the first groove to remove part of the first sacrificial structure to form a second sacrificial structure, and forming a second groove from the first groove;

[0011] Conformally manufacturing a semiconductor layer, a gate insulating layer and a word line in the second trench, wherein the word line fills the second trench;

[0012] The second sacrificial structure is removed to expose part of the semiconductor layer; the exposed semiconductor layer is removed using the first protective structure as a mask, and the remaining semiconductor layer forms a channel region, wherein the etching rate of the material of the channel region is greater than the etching rate of the material of the first protective structure.

[0013] The beneficial technical effects brought about by the technical solutions provided by some embodiments of the present application include:

[0014] If the etching rate of the material of the first protection structure outside the channel region is lower than the etching rate of the material of the channel region, the channel region and the first protection structure can form a more obvious etching selectivity, which is beneficial to protecting the channel region when removing the semiconductor layer connected to the channel region.

[0015] For the manufacture of stacked memories, since the first protective structure protects the channel region, it is possible to avoid damage to the channel region due to the difference in etching rates between the top and the bottom caused by the decrease in etchant concentration from top to bottom; that is, even if the etchant concentration at the bottom of the trench is lower than the etchant concentration at the top, when the etchant at the bottom etches away the parasitic channel region of the parasitic transistor at the bottom, the channel regions of (non-parasitic) transistors at other locations are still covered by the first protective structure and are not damaged by the etching of the etchant, which is beneficial to improving the structural integrity of the transistor and the structural stability of the stacked memory; moreover, the removal rate of the channel region of the parasitic transistor can be improved, the influence of the parasitic transistor can be reduced, and the performance of the transistor can be guaranteed or improved.

[0016] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic cross-sectional view perpendicular to a substrate and parallel to both a first direction and a third direction of a memory provided in some embodiments of the present application;

[0018] Figure 2 A schematic cross-sectional view perpendicular to a substrate and parallel to both a first direction and a second direction of a memory provided in some embodiments of the present application;

[0019] Figure 3 A schematic top view of a memory provided in some embodiments of the present application;

[0020] Figure 4 for Figure 3 Schematic diagram of the cross section perpendicular to the substrate at AA in the middle;

[0021] Figure 5 for Figure 3 Schematic diagram of the cross section perpendicular to the substrate at BB in the middle;

[0022] Figure 6 for Figure 3 Schematic diagram of the cross section perpendicular to the substrate at CC in the middle;

[0023] Figure 7 for Figure 3 Schematic diagram of the cross section perpendicular to the substrate at DD in the middle;

[0024] Figure 8 A schematic flow chart of a method for manufacturing a memory provided in some embodiments of the present application;

[0025] Fig. 9 A schematic diagram of a process of manufacturing a plurality of first memory structures arranged in an array and insulated from each other on one side of a substrate in a memory manufacturing method provided in some embodiments of the present application;

[0026] Figures 10 to 75 A schematic cross-sectional view perpendicular to a substrate obtained in each step of a method for manufacturing a memory provided in some embodiments of the present application.

[0027] Description of reference numerals:

[0028] 1-substrate; 11-gate electrode; 12-gate insulating layer; 13-channel region; 14-first protection structure; 15-source; 16-drain; 17-third insulating layer;

[0029] 2-storage structure; 21-word line; 211-connection line; 22-bit line;

[0030] 31-first groove; 32-second groove; 33-first sacrificial layer; 34-second sacrificial structure; 35-semiconductor layer; 36-blank area; 37-fourth groove; 38-fifth groove; 39-sixth groove;

[0031] 41-first insulating layer; 42-replacement layer; 43-first word line groove; 44-second word line groove; 45-sacrificial word line; 451-first sacrificial layer; 46-first dielectric layer; 47-second dielectric layer; 48-third dielectric layer;

[0032] 51 - first isolation trench; 52 - second isolation trench; 53 - first isolation layer;

[0033] 61-replacement groove; 62-initial metal layer; 63-transition metal layer / first capacitor electrode; 64-metal layer; 65-third groove; 66-second isolation layer; 67-second insulating layer; 68-third word line groove; 69-fourth word line groove;

[0034] 71- third isolation layer;

[0035] 81-capacitor groove;

[0036] 91 - capacitor insulation layer; 92 - first electrode layer; 93 - series structure. DETAILED DESCRIPTION

[0037] Some embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of some embodiments of the present application, and do not constitute a limitation on the technical solutions of some embodiments of the present application.

[0038] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with some specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0041] Some embodiments of the present application provide a memory, which includes a substrate 1 and a plurality of memory cells, wherein the memory cells include transistors, and the structure diagram of the transistors is shown in FIG. Figure 1 and Figure 2 The transistor includes: a gate electrode 11 , a gate insulating layer 12 , a channel region 13 and two first protection structures 14 .

[0042] The gate insulating layer 12 and the channel region 13 are sequentially arranged at the periphery of the gate electrode 11 ; the gate insulating layer 12 and the gate electrode 11 both extend along a first direction perpendicular to the substrate 1 .

[0043] The first protection structure 14 is disposed on at least one side of the channel region 13 along a second direction, and the second direction is parallel to the substrate 1 ; the etching rate of the material of the channel region 13 is greater than the etching rate of the material of the first protection structure 14 .

[0044] In some embodiments of the present application, the etching rate of the material of the first protection structure 14 outside the channel region 13 is lower than the etching rate of the material of the channel region 13, and the channel region 13 can be protected when the semiconductor layer 53 connected to the channel region 13 (parasitic channel region) is removed.

[0045] For manufacturing a stacked memory, the first protection structure 14 protects the channel region 13, which can avoid damage to the channel region 13 due to the different etching rates at the top and bottom caused by the decrease in the etchant concentration from the top to the bottom. In other words, even if the etchant concentration at the bottom of the trench is lower than the etchant concentration at the top, when the etchant at the bottom etches away the parasitic channel region of the parasitic transistor at the bottom, the channel region of the (non-parasitic) transistor at other positions is still covered by the first protection structure and is not damaged by the etching of the etchant, which is beneficial to improving the structural integrity of the transistor and the structural stability of the stacked memory; moreover, it can improve the removal rate of the channel region of the parasitic transistor, reduce the influence of the parasitic transistor, and ensure or improve the performance of the transistor.

[0046] It should be noted that the first protection structure 14 may be disposed only on one side of the channel region 13 along the second direction; or, the first protection structure 14 may be disposed on both sides of the channel region 13 along the second direction.

[0047] Optionally, the material of the channel region 13 includes metal oxide, and the material of the first protection structure 14 includes nitride.

[0048] In some embodiments of the present application, a first protection structure 14 comprising nitride and a channel region 13 comprising metal oxide form a more obvious etching selectivity ratio, thereby avoiding damage to the top channel region 13 when etching the parasitic channel region at the bottom, thereby improving the stability and process stability of the memory including the stack of transistors.

[0049] Specifically, the material of the channel region 13 may be IGZO (Indium Gallium Zinc Oxide), and the material of the first protection structure 14 may be silicon nitride.

[0050] In some embodiments, the material of the metal oxide semiconductor layer or the channel region may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0051] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the dynamic memory.

[0052] The material of the metal oxide semiconductor layer or the channel region only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0053] Optionally, refer to Figure 1 The transistor further includes a source 15 and a drain 16, which are respectively arranged on opposite sides of the channel region 13 along a third direction; the third direction is parallel to the substrate 1 and intersects with the second direction.

[0054] In some embodiments of the present application, the channel region 13 is arranged along a first direction perpendicular to the substrate 1 , and the source 15 and the drain 16 are arranged along a third direction parallel to the substrate 1 .

[0055] Optionally, refer to Figure 2 In a cross section parallel to both the first direction and the second direction, at least one side of the channel region 13 along the second direction contacts the first protection structure 14 .

[0056] and / or, reference Figure 1 In a cross section parallel to both the first direction and the third direction, two sides of the channel region 13 along the third direction are in contact with the source 15 and the drain 16 respectively.

[0057] In some embodiments of the present application, since the first protection structure 14, the source 15 and the drain 16 protect the channel region 13, the channel region 13 will not be damaged when etching the semiconductor layer 53 connected to the channel region 13. Moreover, since the channel region 13 is closer to the inside than the semiconductor layer 53 connected to the channel region 13, the channel region 13 is protected to a greater extent during the process of removing the semiconductor layer 53 connected to the channel region 13.

[0058] Optionally, refer to Figure 2 The first protection structure 14 has a bottom surface close to the substrate 1 , a top surface far from the substrate 1 , and side surfaces between the top surface and the bottom surface; the channel region 13 is in contact with the top surface, the bottom surface and the side surfaces of the first protection structure 14 .

[0059] In some embodiments of the present application, the channel region 14 is in contact with the top surface, the bottom surface and the side surface of the first protection structure 14 , and the first protection structure 14 can further protect the channel region 14 .

[0060] Optionally, refer to Figure 3 and Figure 4 , multiple transistors are stacked along a first direction perpendicular to the substrate 1 and arranged in an array in a plane parallel to the substrate 1 .

[0061] The drain 16 has a bottom surface close to the substrate 1 , a top surface far from the substrate 1 , and side surfaces between the top surface and the bottom surface. The channel region 13 is in contact with the top surface, the bottom surface, and the side surfaces of the drain 16 .

[0062] In some embodiments of the present application, the channel region 13 is in contact with the top surface, the bottom surface and the side surface of the drain 16 , and the drain 16 can further protect the channel region 14 .

[0063] Optionally, the source electrode 15 has a bottom surface close to the substrate 1 , a top surface far from the substrate 1 , and side surfaces between the top surface and the bottom surface. The channel region 13 is in contact with the top surface, the bottom surface, and the side surfaces of the source electrode 15 .

[0064] In some embodiments of the present application, the channel region 13 is in contact with the top surface, the bottom surface and the side surface of the source electrode 15 , and the source electrode 15 can further protect the channel region 14 .

[0065] Optionally, refer to Figure 4 Along the first direction, the gate electrodes 11 of two adjacent transistors are connected through a connecting line 211 to form a word line 21.

[0066] Optionally, along the second direction, the width of the connection line 211 is greater than the width of the gate electrode 11 .

[0067] In some embodiments of the present application, along the second direction, the width of the connection line 211 is greater than the width of the gate electrode 11, so that the parasitic channel region is located further outward than the channel region 13, which is beneficial for protecting the channel region 13 when removing the parasitic channel region.

[0068] Optionally, refer to Figure 3 Along the third direction, a bit line 22 is set between the drain 16 of one transistor and the drain 16 of another transistor in the same row, and the bit line 22 extends along the second direction.

[0069] In some embodiments of the present application, two transistors share one bit line 22, which can make the memory more integrated and help reduce the unit area.

[0070] Optionally, the memory further includes a capacitor structure, which is arranged on a side of the source 15 away from the drain 16 .

[0071] Optionally, the capacitor structure includes a second electrode layer sequentially arranged on one side of the source electrode 15, and a capacitor insulating layer 91, a first electrode layer 92 and a series structure 93 on the periphery of the second electrode layer. The second electrode layer can be a phase-separated structure having a different material from the source electrode 15, or can be an integrally formed structure having the same material as the source electrode 15.

[0072] Based on the same inventive concept, some embodiments of the present application provide an electronic device, which includes the memory provided by some of the above embodiments.

[0073] In some embodiments of the present application, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0074] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0075] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain electronic devices provided in some embodiments of the present application.

[0076] Based on the same inventive concept, some embodiments of the present application provide a method for manufacturing a memory, the flow chart of the method is as follows: Figure 8 As shown, the method comprises steps S1 to S4:

[0077] S1: A plurality of first storage structures arranged in an insulated array are manufactured on one side of a substrate 1, the first storage structure comprising a plurality of first grooves 31 arranged in an array in a plane parallel to the substrate 1, a plurality of first sacrificial layers 33 arranged around the periphery of the first grooves 31 and spaced apart along a first direction perpendicular to the substrate 1, and a first protective structure 14 arranged on at least one side of the first groove 31 along a second direction; the second direction is parallel to the substrate 1.

[0078] In some embodiments of the present application, Fig.64 It is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after a plurality of first storage structures arranged in an array and insulated from each other are manufactured on one side of the substrate 1; Fig.65 It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after a plurality of first storage structures arranged in an insulated array are manufactured on one side of the substrate 1.

[0079] S2 : performing side etching on the first sacrificial structure 33 through the first trench 31 to remove a portion of the first sacrificial structure 33 to form a second sacrificial structure 34 , and forming a second trench 32 from the first trench 31 .

[0080] In some embodiments of the present application, Fig.66 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained by performing side etching on the first sacrificial structure 33 through the first trench 31 to remove part of the first sacrificial structure 33 and form a second sacrificial structure 34, and a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after the second trench 32 is formed from the first trench 31; Fig.67 The first sacrificial structure 33 is laterally etched through the first trench 31 to remove part of the first sacrificial structure 33 to form a second sacrificial structure 34 , and a cross-sectional schematic diagram perpendicular to the substrate 1 at CC obtained after the second trench 32 is formed from the first trench 31 .

[0081] S3 : forming a semiconductor layer 35 , a gate insulating layer 12 and a word line 21 in sequence in the second trench 32 .

[0082] In some embodiments of the present application, Fig.68 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after the word line 21 fills the second trench 32 to sequentially form a semiconductor layer 35, a gate insulating layer 12 and a word line 21 in the second trench 32; Fig.69 To sequentially conformally manufacture the semiconductor layer 35 , the gate insulating layer 12 and the word line 21 in the second trench 32 , a schematic cross-sectional view perpendicular to the substrate 1 at CC is obtained after the word line 21 fills the second trench 32 .

[0083] Optionally, after step S3 and before step S4 , the manufacturing method further includes: removing structures between two adjacent columns of second sacrificial structures 34 along the second direction to form fourth trenches 37 .

[0084] In some embodiments of the present application, Fig.70 A schematic cross-sectional view of a section perpendicular to the substrate 1 at a point BB obtained after removing the structure between two adjacent columns of second sacrificial structures 34 along the second direction to form a fourth trench 37; Fig.71 This is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after removing the structure between two adjacent rows of second sacrificial structures 34 along the second direction to form a fourth trench 37. Fig.70 and Fig.71 The purpose of removing the structure between two adjacent columns of the second sacrificial structures 34 along the second direction is to expose the second sacrificial structures 34 to facilitate the subsequent removal of the second sacrificial structures 34 .

[0085] S4: remove the second sacrificial structure 34 to expose part of the semiconductor layer 35 ; use the first protective structure 14 as a mask to remove the exposed semiconductor layer 35 , and the remaining semiconductor layer 35 forms a channel region 13 , and the etching rate of the material of the channel region 13 is greater than the etching rate of the material of the first protective structure 14 .

[0086] In some embodiments of the present application, Fig.72 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after removing the second sacrificial structure 34 and exposing a portion of the semiconductor layer 35; Fig.73 A schematic cross-sectional view of a section CC perpendicular to the substrate 1 obtained after removing the second sacrificial structure 34 and exposing a portion of the semiconductor layer 35 is shown. Fig.74 The schematic cross-sectional view of the portion AA perpendicular to the substrate 1 obtained after the exposed semiconductor layer 35 is removed by using the first protection structure 14 as a mask and the remaining semiconductor layer 35 forms the channel region 13; Fig.75 A schematic cross-sectional view of the CC perpendicular to the substrate 1 obtained after the exposed semiconductor layer 35 is removed using the first protective structure 14 as a mask and the remaining semiconductor layer 35 forms a channel region 13. In the present application, the etching rate of the material of the first protective structure 14 outside the channel region 13 is lower than the etching rate of the material of the channel region 13, and the channel region 13 can be protected when the semiconductor layer 53 connected to the channel region 13 is removed. For manufacturing a stacked memory, since the first protective structure 14 protects the channel region 13, it can avoid damage to the channel region 13 due to different etching rates at the top and bottom caused by the reduction of the etchant concentration from the top to the bottom, which is beneficial to improving the structural stability of the stacked memory.

[0087] refer to Fig.73 After removing the second sacrificial structure 34, the fourth trench 37 forms a fifth trench 38. Fig.75 After removing the exposed semiconductor layer 35 , the fifth trench 38 forms a sixth trench 39 .

[0088] Optionally, after step S4 , the manufacturing method further includes: manufacturing a third insulating layer 17 in the sixth trench 39 .

[0089] In some embodiments of the present application, the structural schematic diagram obtained after manufacturing the third insulating layer 17 in the sixth trench 39 is shown in FIG. Figures 4 to 7 .

[0090] Optionally, before step S1, the manufacturing method further includes:

[0091] On one side of the substrate 1, first insulating layers 41 and replacement layers 42 are alternately arranged.

[0092] Each first insulating layer 41 and each replacement layer 42 is patterned to form a plurality of first word line grooves 43 arranged in an array in a plane parallel to the substrate 1 ; each first insulating layer 41 is laterally etched through the first word line grooves 43 to obtain second word line grooves 44 formed by the first word line grooves 43 .

[0093] A sacrificial word line 45 is fabricated in the second word line trench 44 .

[0094] In some embodiments of the present application, the width of the first word line groove 44 along the second direction is the third width, and the width of the first word line groove 44 along the third direction is the first width. The third width is less than the width of the gate electrode 11 manufactured subsequently along the second direction, specifically, the third width is 50% to 80% (including the two end values) of the width of the gate electrode 11 along the second direction; the first width is less than the width of the gate electrode 11 manufactured subsequently along the third direction, specifically, the first width is 50% to 80% (including the two end values) of the width of the gate electrode 11 along the third direction. After the first insulating layers 41 are lateral-etched, the width along the second direction between two adjacent first insulating layers 41 in the same layer in the second word line groove 44 is the fourth width, and the width along the third direction between two adjacent first insulating layers 41 in the same layer in the second word line groove 44 is the fifth width. The fourth width is greater than the width of the gate electrode 11 manufactured subsequently along the second direction, and the fifth width is greater than the width of the gate electrode 11 manufactured subsequently along the third direction. Specifically, the fourth width may be 120% to 140% (including both end points) of the width of the gate electrode 11 along the second direction, and the fifth width may be 120% to 140% (including both end points) of the width of the gate electrode 11 along the third direction.

[0095] Specifically, Fig.10 It is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the first insulating layer 41 and the replacement layer 42 arranged alternately on one side of the substrate 1; Fig.11 It is a schematic cross-sectional view perpendicular to the substrate 1 at a point BB obtained after manufacturing the first insulating layer 41 and the replacement layer 42 arranged alternately on one side of the substrate 1; Fig.12It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing the first insulating layer 41 and the replacement layer 42 arranged alternately on one side of the substrate 1; Fig.13 It is a schematic cross-sectional view perpendicular to the substrate 1 at DD obtained after manufacturing the first insulating layer 41 and the replacement layer 42 arranged alternately on one side of the substrate 1.

[0096] Fig.14 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after patterning each first insulating layer 41 and each replacement layer 42 to form a plurality of first word line grooves 43 arranged in an array in a plane parallel to the substrate 1; Fig.15 A schematic cross-sectional view perpendicular to the substrate 1 at a point BB is obtained after patterning each first insulating layer 41 and each replacement layer 42 to form a plurality of first word line grooves 43 arranged in an array in a plane parallel to the substrate 1 .

[0097] Fig.16 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after the first insulating layers 41 are laterally etched through the first word line grooves 43 to obtain the second word line grooves 44 formed by the first word line grooves 43; Fig.17 The schematic cross-sectional view of the CC perpendicular to the substrate 1 is obtained after the first insulating layers 41 are laterally etched through the first word line grooves 43 to obtain the second word line grooves 44 formed by the first word line grooves 43 .

[0098] Fig.18 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing a sacrificial word line 45 in the second word line groove 44; Fig.19 FIG. 4 is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing a sacrificial word line 45 in the second word line groove 44 .

[0099] Optionally, after manufacturing the sacrificial word line 45 in the second word line groove 44 and before manufacturing a plurality of first storage structures arranged in an array and insulated from each other on one side of the substrate 1 in step S1, the manufacturing method further includes:

[0100] The first insulating layer 41 and the replacement layer 42 are patterned to form first storage structure regions arranged in an array, thereby obtaining first isolation trenches 51 between adjacent first storage structure regions.

[0101] The first insulating layers 41 are laterally etched through the first isolation trenches 51 to form second isolation trenches 52 ; first isolation layers 53 are manufactured in the second isolation trenches 52 to obtain an initial first storage structure with an insulated array arrangement.

[0102] In some embodiments of the present application, the first isolation layer 53 can isolate two adjacent initial first storage structures to avoid signal crosstalk.

[0103] Fig. 22A schematic cross-sectional view perpendicular to the substrate 1 at AA is obtained after patterning the entire substrate 1 to form array-arranged first storage structure regions and obtaining first isolation trenches 51 between adjacent first storage structure regions; Fig.23 The entire substrate 1 is patterned to form array-arranged first storage structure regions, and a cross-sectional schematic diagram of a section BB perpendicular to the substrate 1 is obtained after first isolation trenches 51 between adjacent first storage structure regions are obtained.

[0104] Fig.24 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after the first isolation trenches 51 are laterally etched to form the second isolation trenches 52; Fig.25 The schematic cross-sectional view of the section BB perpendicular to the substrate 1 obtained after the second isolation grooves 52 are formed by side-etching each first insulation layer 41 through the first isolation grooves 51 .

[0105] Fig.26 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the first isolation layer 53 in the second isolation trench 52 to obtain an initial first storage structure arranged in an insulated array; Fig. 27 A schematic cross-sectional view perpendicular to the substrate 1 at point BB is obtained after manufacturing the first isolation layer 53 in the second isolation trench 52 to obtain an initial first storage structure arranged in an insulated array.

[0106] Optionally, before patterning the entire substrate 1 to form the first storage structure region arranged in an array, the method further includes: manufacturing a first dielectric layer 46 on the upper surface of the entire substrate, so that the first dielectric layer 46 covers the first insulating layer 41 and the sacrificial word line 45 .

[0107] In some embodiments of the present application, Fig. 20 It is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the first dielectric layer 46 on the upper surface of the entire substrate; Fig.21 It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing the first dielectric layer 46 on the upper surface of the entire substrate.

[0108] Optionally, in step S1, a plurality of first storage structures arranged in an array and insulated from each other are manufactured on one side of the substrate 1, including the following steps S11 to S18. The flowchart of the manufacturing process is shown in FIG. Fig. 9 shown.

[0109] S11 : removing the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction to form a replacement groove 61 ; the third direction is parallel to the substrate 1 and intersects with the second direction.

[0110] In some embodiments of the present application, the replacement layer 42 can be replaced with metal by replacing the groove 61. Specifically, the replacement layer 42 is silicon nitride. Fig.28 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after forming a replacement groove 61 to remove the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction; Fig.29 A schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after forming a replacement groove 61 to remove the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction; Fig.30 A schematic cross-sectional view perpendicular to the substrate 1 at DD is obtained after a replacement groove 61 is formed to remove the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction.

[0111] S12 : The replacement layer 42 is laterally removed through the replacement groove 61 to produce an initial metal layer 62 that fills the replacement layer 42 and the replacement groove 61 .

[0112] In some embodiments of the present application, the material of the first dielectric layer 46 is the same as that of the replacement layer 42, both of which can be silicon nitride. When the replacement layer 42 is removed, the first dielectric layer 46 is removed, and an initial metal layer 62 is also manufactured in the area where the first dielectric layer 46 is located.

[0113] Fig.31 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the region filled with the replacement layer 42 and the initial metal layer 62 of the replacement groove 61 in order to laterally remove the replacement layer 42 through the replacement groove 61; Fig.32 A schematic cross-sectional view perpendicular to the substrate 1 at BB obtained after manufacturing the region filled with the replacement layer 42 and the initial metal layer 62 of the replacement groove 61 in order to laterally remove the replacement layer 42 through the replacement groove 61; Fig.33 A schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing the region filled with the replacement layer 42 and the initial metal layer 62 of the replacement groove 61 in order to laterally remove the replacement layer 42 through the replacement groove 61; Fig.34 A schematic cross-sectional view perpendicular to the substrate 1 at DD obtained after manufacturing an initial metal layer 62 that fills the replacement layer 42 and the replacement groove 61 in order to laterally remove the replacement layer 42 through the replacement groove 61 .

[0114] S13 : removing a portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction, to form a transition metal layer 63 and a third trench 65 .

[0115] In some embodiments of the present application, Fig.35A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after removing a portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction and forming a transition metal layer 63 and a third trench 65;

[0116] Fig.36 A schematic cross-sectional view perpendicular to the substrate 1 at the BB obtained after removing a portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction and forming a transition metal layer 63 and a third trench 65; Fig.37 A schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after removing a portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction and forming a transition metal layer 63 and a third trench 65; Fig.38 A schematic cross-sectional view perpendicular to the substrate 1 at DD is obtained after a transition metal layer 63 and a third trench 65 are formed to remove a portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 in the same column along the second direction.

[0117] S14 : forming a second isolation layer 66 conformally along the third trench 65 ; forming a second insulating layer 67 in the third trench 65 .

[0118] In some embodiments of the present application, the second isolation layer 66 can prevent the oxygen used to manufacture the second insulating layer 67 from affecting the sacrificial word line 45 . Fig.39 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after conformally manufacturing the second isolation layer 66 along the third trench 65; Fig.40 is a schematic cross-sectional view perpendicular to the substrate 1 at point BB obtained after conformally manufacturing the second isolation layer 66 along the third trench 65; Fig.41 is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after conformally manufacturing the second isolation layer 66 along the third trench 65; Fig.42 It is a schematic cross-sectional view perpendicular to the substrate 1 at DD obtained by conformally manufacturing the second isolation layer 66 along the third trench 65 .

[0119] Fig.43 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the second insulating layer 67 in the third trench 65; Fig.44 is a schematic cross-sectional view perpendicular to the substrate 1 at point BB obtained after manufacturing the second insulating layer 67 in the third trench 65; Fig.45 is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing the second insulating layer 67 in the third trench 65; Fig.46 It is a schematic cross-sectional view perpendicular to the substrate 1 at DD obtained after manufacturing the second insulating layer 67 in the third trench 65 .

[0120] Optionally, after step S14 and before step S15, the manufacturing method further includes:

[0121] The second insulating layer 67 , the second isolation layer 66 and the first insulating layer 41 in the capacitor region are removed in sequence to expose the first capacitor electrode 63 in the capacitor region, thereby forming a capacitor trench 81 .

[0122] A capacitor insulating layer 91 , a first electrode layer 92 and a series structure 93 are sequentially manufactured on the periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81 .

[0123] The series structure 93 in the transistor region is removed.

[0124] In some embodiments of the present application, Fig.47 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 in the capacitor region and forming the capacitor trench 81; Fig.48 A schematic cross-sectional view of the portion BB perpendicular to the substrate 1 obtained after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 in the capacitor region and forming the capacitor trench 81; Fig.49 A schematic cross-sectional view of the part CC perpendicular to the substrate 1 obtained after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 in the capacitor region and forming the capacitor trench 81; Fig.50 A schematic cross-sectional view perpendicular to the substrate 1 at DD is obtained after the capacitor trench 81 is formed to remove the first insulating layer 41 , the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 in the capacitor region.

[0125] Fig.51 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after sequentially manufacturing a capacitor insulating layer 91, a first electrode layer 92 and a series structure 93 on the periphery of the exposed first capacitor electrode 63 and along the capacitor groove 81; Fig.52 is a schematic cross-sectional view perpendicular to the substrate 1 at a point BB obtained after sequentially manufacturing a capacitor insulating layer 91, a first electrode layer 92 and a series structure 93 on the periphery of the exposed first capacitor electrode 63 and along the capacitor groove 81; Fig.53 is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after sequentially manufacturing a capacitor insulating layer 91, a first electrode layer 92 and a series structure 93 on the periphery of the exposed first capacitor electrode 63 and along the capacitor groove 81; Fig.54It is a schematic cross-sectional view perpendicular to the substrate 1 at DD obtained after sequentially manufacturing a capacitor insulating layer 91 , a first electrode layer 92 and a series structure 93 on the periphery of the exposed first capacitor electrode 63 and along the capacitor groove 81 .

[0126] Optionally, after removing the series structure 93 in the transistor region and before step S15 , the manufacturing method further includes: manufacturing a third dielectric layer 48 in the region of the removed series structure 93 .

[0127] In some embodiments of the present application, the series structure 93 in the transistor region is replaced with the third dielectric layer 48 , so that the series structure 93 in the capacitor region will not be affected when the sacrificial word line 45 is subsequently patterned.

[0128] In some embodiments of the present application, Fig.55 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the third dielectric layer 48 in the removed series structure 93 region; Fig.56 is a schematic cross-sectional view perpendicular to the substrate 1 at BB obtained after manufacturing the third dielectric layer 48 in the removed series structure 93 region; Fig.57 It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after the third dielectric layer 48 is manufactured in the removed series structure 93 region.

[0129] S15 : patterning the sacrificial word line 45 to obtain a third word line groove 68 having the same size as the first word line groove 43 .

[0130] In some embodiments of the present application, along the second direction, the width of the third word line groove 68 is equal to the third width of the first word line groove 43 ; along the third direction, the width of the third word line groove 68 is equal to the first width of the first word line groove 43 . Fig.58 A schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after patterning the sacrificial word line 45 to obtain a third word line groove 68 having the same size as the first word line groove 43; Fig.59 A schematic cross-sectional view perpendicular to the substrate 1 at CC is obtained after patterning the sacrificial word line 45 to obtain a third word line groove 68 having the same size as the first word line groove 43 .

[0131] S16: Laterally etching the transition metal layer 63 through the third word line groove 68 to remove the transition metal layer 63 located on both sides of the third word line groove 68 along the second direction, thereby obtaining a fourth word line groove 69 formed by the third word line groove 68, and a metal layer 64 obtained from the transition metal layer 63; the metal layer 64 includes a bit line 22 located between two adjacent columns of sacrificial word lines 45 along the third direction and extending along the second direction, a drain 16 arranged on one side of the sacrificial word line 45 and connected to the bit line 22, and a source 15 located on the other side of the sacrificial word line 45.

[0132] In some embodiments of the present application, Fig.60 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after the transition metal layer 63 is laterally etched through the third word line groove 68; Fig.61 It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after the transition metal layer 63 is laterally etched through the third word line groove 68 .

[0133] Optionally, in step S16, the transition metal layer 63 is laterally etched through the third word line groove 68 to remove the transition metal layer 63 located on both sides of the third word line groove 68 along the second direction, thereby obtaining a fourth word line groove 69 formed by the third word line groove 68, including: removing part of the transition metal layer 63 located on both sides of the third word line groove 68 along the third direction, so that the width between two adjacent transition metal layers 63 along the third direction is changed from the first width to the second width.

[0134] In some embodiments of the present application, the width of the third word line groove along the third direction is the first width. The second width is the width of the gate electrode 11 manufactured subsequently.

[0135] S17 : manufacturing a third isolation layer 71 in the fourth word line trench 69 .

[0136] In some embodiments of the present application, Fig.62 is a schematic cross-sectional view perpendicular to the substrate 1 at AA obtained after manufacturing the third isolation layer 71 in the fourth word line trench 69; Fig.63 It is a schematic cross-sectional view perpendicular to the substrate 1 at CC obtained after manufacturing the third isolation layer 71 in the fourth word line trench 69 .

[0137] S18 : patterning the third isolation layer 71 to obtain a first trench 31 and a first protection structure 14 whose width along the second direction is equal to the width of the third word line trench 68 .

[0138] In some embodiments of the present application, Fig.65 The width of the first trench 31 along the second direction is smaller than the width of the gate electrode 11 along the second direction. Specifically, the width of the first trench 31 along the second direction is 50% to 80% (including both end points) of the width of the gate electrode along the second direction.

[0139] Optionally, in step S18, patterning the third isolation layer 71 to obtain a first trench 31 having a width along the second direction equal to the width of the third word line trench 68 includes: patterning the third isolation layer 71 to obtain a first trench 31 having a width along the third direction equal to the second width.

[0140] In some embodiments of the present application, Fig.64 The width of the first trench 31 along the third direction is the second width, that is, the width of the gate electrode 11 .

[0141] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0142] 1. In some embodiments of the present application, the etching rate of the material of the first protection structure outside the channel region is lower than the etching rate of the material of the channel region. Then, the channel region and the first protection structure can form a more obvious etching selectivity ratio, which is beneficial to protecting the channel region when removing the semiconductor layer connected to the channel region.

[0143] 2. In some embodiments of the present application, for manufacturing a stacked memory, since the first protection structure protects the channel region, it is possible to avoid damage to the channel region due to the difference in etching rates between the top and the bottom due to the decrease in etchant concentration from the top to the bottom, which is beneficial to improving the structural stability of the stacked memory.

[0144] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0145] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0146] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0147] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0148] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0149] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0150] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A memory, characterized in that: include: A substrate and a plurality of memory cells, wherein the memory cells include transistors, wherein the transistors include: A gate electrode, a gate insulating layer and a channel region, wherein the gate insulating layer and the channel region are sequentially arranged at the periphery of the gate electrode; the gate insulating layer and the gate electrode both extend along a first direction perpendicular to the substrate; A first protection structure is provided on at least one side of the channel region along a second direction, wherein the second direction is parallel to the substrate; an etching rate of a material of the channel region is greater than an etching rate of a material of the first protection structure.

2. The memory according to claim 1, characterized in that: The material of the channel region includes metal oxide, and the material of the first protection structure includes nitride.

3. The memory according to claim 1, characterized in that: The transistor further includes a source and a drain, wherein the source and the drain are respectively arranged at two opposite sides of the channel region along a third direction; the third direction is parallel to the substrate and intersects with the second direction.

4. The memory according to claim 3, characterized in that: In a cross section parallel to both the first direction and the second direction, at least one side of the channel region along the second direction is in contact with the first protection structure; And / or, in a cross section parallel to both the first direction and the third direction, two sides of the channel region along the third direction are in contact with the source and the drain respectively.

5. The memory according to claim 4, characterized in that: The first protection structure has a bottom surface close to the substrate, a top surface far from the substrate, and side surfaces between the top surface and the bottom surface; the channel region is in contact with the top surface, the bottom surface and the side surfaces of the first protection structure.

6. The memory according to claim 3, characterized in that: The plurality of transistors are stacked along a first direction perpendicular to the substrate and arranged in an array in a plane parallel to the substrate; The drain of the transistor has a bottom surface close to the substrate, a top surface far from the substrate, and side surfaces between the top surface and the bottom surface, and the channel region is in contact with the top surface, the bottom surface and the side surfaces of the drain.

7. The memory according to claim 6, characterized in that: Along the first direction, gate electrodes of two adjacent transistors are connected via a connecting line to form a word line.

8. The memory according to claim 7, characterized in that: Along the second direction, the width of the connection line is greater than the width of the gate electrode.

9. The memory according to claim 6, characterized in that: Along the third direction, a bit line is provided between a drain of one of the transistors and a drain of another of the transistors, and the bit line extends along the second direction.

10. An electronic device, characterized in that: Comprising a memory as claimed in any one of claims 1-9.

11. A method for manufacturing a memory, characterized in that: include: A plurality of first storage structures arranged in an array and insulated from each other are manufactured on one side of a substrate, wherein the first storage structure comprises a plurality of first grooves arranged in an array in a plane parallel to the substrate, a plurality of first sacrificial layers arranged around the periphery of the first grooves and spaced apart in a first direction perpendicular to the substrate, and a first protection structure arranged on at least one side of the first grooves along a second direction; The second direction is parallel to the substrate; performing side etching on the first sacrificial structure through the first groove to remove part of the first sacrificial structure to form a second sacrificial structure, and forming a second groove from the first groove; sequentially forming a semiconductor layer, a gate insulating layer and a word line in the second trench; removing the second sacrificial structure to expose a portion of the semiconductor layer; The exposed semiconductor layer is removed by using the first protective structure as a mask, and the remaining semiconductor layer forms a channel region, wherein the etching rate of the material of the channel region is greater than the etching rate of the material of the first protective structure.

12. The manufacturing method according to claim 11, characterized in that: Before manufacturing a plurality of first storage structures arranged in an array and insulated from each other on one side of the substrate, the method further includes: Fabricating an alternating arrangement of first insulating layers and replacement layers on one side of the substrate; Patterning each of the first insulating layers and each of the replacement layers to form a plurality of first word line grooves arranged in an array in a plane parallel to the substrate; performing side etching on each of the first insulating layers through the first word line grooves to obtain second word line grooves formed by the first word line grooves; A sacrificial word line is fabricated in the second word line trench.

13. The manufacturing method according to claim 12, characterized in that: After manufacturing a sacrificial word line in the second word line groove and before manufacturing a plurality of first storage structures arranged in an array and insulated from each other on one side of the substrate, the method further includes: Patterning the first insulating layer and the replacement layer to form first storage structure regions arranged in an array, and obtaining first isolation grooves between adjacent first storage structure regions; The first insulating layers are laterally etched through the first isolation grooves to form second isolation grooves; first isolation layers are manufactured in the second isolation grooves to obtain an initial first storage structure arranged in an insulated array.

14. The manufacturing method according to claim 13, characterized in that: A plurality of first storage structures arranged in an array and insulated from each other are manufactured on one side of a substrate, comprising: Removing the first insulating layer and the replacement layer extending along a third direction between any two adjacent sacrificial word lines in the same column along the second direction to form a replacement groove; the third direction is parallel to the substrate and intersects with the second direction; Laterally removing the replacement layer through the replacement groove to produce an initial metal layer that fills the replacement layer area and the replacement groove; removing a portion of the initial metal layer extending along the third direction between any two adjacent sacrificial word lines in the same column along the second direction to form a transition metal layer and a third trench; Conformally manufacturing a second isolation layer along the third trench; and manufacturing a second insulating layer in the third trench; Patterning the sacrificial word line to obtain a third word line groove having the same size as the first word line groove; The transition metal layer is laterally etched through the third word line groove to remove the transition metal layer located on both sides of the third word line groove along the second direction, thereby obtaining a fourth word line groove formed by the third word line groove and a metal layer obtained from the transition metal layer; the metal layer comprises a bit line located between two adjacent columns of sacrificial word lines along the third direction and extending along the second direction, a drain electrode arranged at one side of the sacrificial word line and connected to the bit line, and a source electrode located at the other side of the sacrificial word line; manufacturing a third isolation layer in the fourth word line trench; The third isolation layer is patterned to obtain the first trench and the first protection structure, the width of which along the second direction is equal to the width of the third word line trench.

15. The manufacturing method according to claim 14, characterized in that: Laterally etching the transition metal layer through the third word line groove to remove the transition metal layer located on both sides of the third word line groove along the second direction to obtain a fourth word line groove formed by the third word line groove, comprising: removing a portion of the transition metal layer located at both sides of the third word line groove along the third direction, so that the width between two adjacent transition metal layers along the third direction changes from the first width to the second width; The third isolation layer is patterned to obtain the first trench and the first protection structure whose width along the second direction is equal to the width of the third word line trench, comprising: The third isolation layer is patterned to obtain the first groove having a second width along the third direction.

16. The manufacturing method according to claim 14, characterized in that: After manufacturing the second insulating layer in the third trench and before patterning the sacrificial word line, the method further includes: removing the first insulating layer, the second insulating layer and the second isolation layer in the capacitor region to expose the transition metal layer in the capacitor region and form a capacitor trench; A capacitor insulating layer, a first electrode layer and a series structure are sequentially manufactured on the periphery of the exposed transition metal layer and along the capacitor groove; Remove the series structure in the transistor area.

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