An insulated gate bipolar transistor and its fabrication method

Abstract

This invention discloses an insulated-gate bipolar transistor (IGBT) and its fabrication method in the field of semiconductor device technology. The transistor includes: a substrate comprising, from bottom to top, a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer; an active region comprising, from bottom to top, a P-well, a gate insulating layer, a polysilicon gate, an insulating leveling layer, and an emitter electrode, with an N-well disposed within the P-well; a termination region comprising, from bottom to top, a field limiting ring, a polysilicon field plate, an insulating leveling layer, and a metal field plate; and a cutoff region comprising, from bottom to top, a cutoff ring, a polysilicon field plate, and an insulating leveling layer; wherein an oxide masking layer is disposed on the N- epitaxial layer, between adjacent field limiting rings and between the field limiting ring and the cutoff ring. This IGBT is a soft-punch-through type, exhibiting strong noise immunity, low power consumption, and eliminating the need for back-side implantation and annealing, simplifying the production process, reducing costs, and improving device reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an insulated gate bipolar transistor and its fabrication method. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are fully controllable power semiconductor devices that combine the gate voltage control characteristics of MOSFETs with the low on-resistance characteristics of BJTs. They are core components in power control and energy conversion, capable of adjusting voltage, current, frequency, and phase in circuits according to signal commands, and are often referred to as the "CPU of the power electronics industry" and the "heart of the industrial internet." In recent years, the rapid development of industries such as new energy vehicles, clean energy power generation, and the low-altitude economy has led to increasingly widespread IGBT applications, and the performance requirements for IGBTs are gradually increasing.

[0003] There are two main technical solutions for manufacturing IGBTs: one is to manufacture punch-through IGBTs through epitaxial processes; the other is to manufacture non-punch-through and field-stop IGBTs through back-side implantation and thermal annealing. Punch-through IGBTs suffer from poor dynamic characteristics because the epitaxial thickness and doping concentration are difficult to control precisely during epitaxial growth. Furthermore, over-diffusion occurs during the wafer fabrication process due to high-temperature operations such as thermal oxidation and annealing, making carrier injection efficiency difficult to control. Non-punch-through and field-stop IGBTs, on the other hand, have limited back-side implantation depth, typically resulting in hard breakdown. This leads to weaker electromagnetic interference resistance, noise suppression, and reliability. Additionally, back-side annealing can affect the front-side MOS structure, posing a certain reliability risk.

[0004] Therefore, there is an urgent need for a high-performance, high-reliability insulated-gate bipolar transistor device to be put on the market. Summary of the Invention

[0005] This application provides an insulated gate bipolar transistor and its fabrication method, which solves the problems of poor electrical characteristics and weak reliability of current insulated gate bipolar transistors, and improves the performance and reliability of insulated gate bipolar transistors.

[0006] This application provides an insulated-gate bipolar transistor, including:

[0007] The substrate comprises, from bottom to top, a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer; wherein the P+ silicon substrate is the collector region, the N+ epitaxial layer is the buffer region, and the N- epitaxial layer is the drift region;

[0008] A source region, a terminal region, and a cutoff region are provided on the N-epitaxial layer;

[0009] The active region is provided with a P-well, a gate insulating layer, a polysilicon gate, an insulating leveling layer and an emitter electrode in sequence from bottom to top. An N-well is provided in the P-well. The P-well is connected to the emitter electrode through a contact hole in the insulating leveling layer.

[0010] The terminal area is provided with a P-injection field limiting ring, a polysilicon field plate, an insulating leveling layer and a metal field plate in sequence from bottom to top. The P-injection field limiting ring is connected to the polysilicon field plate, and the polysilicon field plate is connected to the metal field plate through contact holes in the insulating leveling layer.

[0011] The cutoff region is provided with an N-injection cutoff ring, the polycrystalline silicon field plate and the insulating flow leveling layer in sequence from bottom to top, and the N-injection field limiting ring is connected to the polycrystalline silicon field plate;

[0012] An oxide masking layer is disposed on the N-epitaxial layer, and the oxide masking layer is disposed between adjacent P-implantation field limiting rings and between the P-implantation field limiting rings and the N-implantation cutoff rings. The polysilicon field plate and the insulating leveling layer are located above the oxide masking layer.

[0013] The beneficial effects of the above embodiments are as follows: This insulated-gate bipolar transistor (IGBT) is a soft-punch-through type. The N+ epitaxial layer can buffer the built-in electric field, reduce the thickness of the depletion region (i.e., the N- epitaxial layer drift region), decrease the forward conduction voltage, reduce power consumption, and slow down the expansion speed of the depletion layer boundary, resulting in very soft turn-off transient electrical characteristics. When the polysilicon gate receives an electrical signal, the P-well forms an inversion layer as a conductive channel, the N-well provides electrons, the insulating leveling layer covers the front structure to isolate moisture, and the oxide masking layer and polysilicon field plate optimize the electric field line distribution within the device, reducing surface collision ionization. After structural optimization, this IGBT has strong noise immunity, low power consumption, and eliminates the need for back-side implantation and annealing, simplifying the production process and reducing costs. It also avoids the impact of back-side annealing on front-side impurities, improving device reliability.

[0014] Based on the above embodiments, this application can be further improved as follows:

[0015] In one embodiment of this application, a collector electrode is provided on the back side of the substrate.

[0016] In one embodiment of this application, the N+ epitaxial layer is doped with arsenic. Arsenic has a larger relative atomic mass and a smaller diffusion coefficient, which helps to avoid excessive diffusion of impurities.

[0017] In one embodiment of this application, the doping concentration of the N-epitaxial layer is 1e 12 -1e 15 cm-3 Within the range, the thickness is 30μm-260μm; the doping concentration of the N+ epitaxial layer is 1e 14 ~9e 17 cm -3 Within the range of 3μm to 20μm, the thickness of the P+ silicon substrate is 1e. 16 ~9e 19 cm -3 Within the range, the thickness is 0.5μm~5μm.

[0018] In one embodiment of this application, on the P+ silicon substrate, the boron ion doping concentration is 1-3 orders of magnitude higher than the arsenic or phosphorus ion doping concentration; on the N+ epitaxial layer, the arsenic ion doping concentration is higher than the boron or phosphorus ion doping concentration, and under the same depth conditions, the arsenic ion doping concentration is 1-3 orders of magnitude higher than the boron ion doping concentration, and under the same doping concentration conditions, the arsenic ion doping depth is 2-5 μm deeper than the boron ion doping depth; on the N- epitaxial layer, the phosphorus ion doping concentration is 1-3 orders of magnitude higher than the boron or arsenic ion doping concentration. This overall thermal budget control allows the soft-punch-through insulated-gate bipolar transistor to adjust the collector carrier injection efficiency in forward conduction mode, reducing the forward conduction voltage and further reducing power consumption; simultaneously, it slows down the expansion rate of the depletion layer boundary, effectively suppressing higher dv / dt and di / dt electromagnetic interference noise.

[0019] In one embodiment of this application, the width of the field limiting ring is 5~20μm, and the doping concentration is 1e. 13 ~1e 16 cm -3 After annealing, the junction depth is 5~15μm; the width of the stop ring is 20~60μm, and the doping concentration is 1e. 14 ~1e 19 cm -3 After annealing, the junction depth is 5~15μm.

[0020] In one embodiment of this application, the injection dose of the P-trap is 1e 13 -5e 14 cm -3 The push-in depth is 3-6 μm; the N-well injection dose is 5e 14 -9e 15 cm -3 The push-bonding depth is 0.1-1.5μm.

[0021] This application also provides a method for fabricating the above-mentioned insulated gate bipolar transistor, including the following steps:

[0022] S1: Select the substrate with three N- / N+ / P+ doped layers, the substrate comprising, from bottom to top, a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer;

[0023] S2: An oxide masking layer with a thickness of 10,000~25,000 Å is formed on the top of the N-epitaxial layer by thermal oxidation process, and windows are opened by photolithography etching process to form the implantation region of active region, field limiting ring and cut-off ring. The oxide masking layer between the field limiting ring is retained, and the field limiting ring and cut-off ring are formed by implantation and annealing process.

[0024] S3: A gate insulating layer with a thickness of approximately 500-1500 Å is grown on the N-epitaxial layer and oxide masking layer by dry oxidation, a 5000-15000 Å polysilicon layer is deposited as the gate, and the P-well implantation region is opened by photolithography etching process to simultaneously form the polysilicon gate and polysilicon field plate pattern; wherein, the gate insulating layer is grown in two stages to cover the polysilicon gate;

[0025] S4: P-wells and N-wells are formed in the P-well injection region through injection and annealing processes;

[0026] S5: Deposit 10000-20000Å BPSG as an insulating leveling layer and reflow it. Open contact holes through photolithography etching process. Deposit 3~5μm thick Al on the insulating leveling layer as emitter electrode and metal field plate through vacuum evaporation. The metal field plate is connected to the polysilicon field plate through contact holes. The emitter metal electrode is connected to the P-well through contact holes.

[0027] S6: Grind the P+ silicon substrate, perform back-side thinning, retain a substrate thickness of 0.5-5μm as the collector region, and vacuum deposit 1-3μm Al as the collector electrode. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0029] Figure 1 This is a schematic diagram of the structure of an insulated gate bipolar transistor in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the fabrication process of an insulated gate bipolar transistor according to an embodiment of this application. Figure 1 ;

[0031] Figure 3 This is a schematic diagram of the fabrication process of an insulated gate bipolar transistor according to an embodiment of this application. Figure 2 ;

[0032] Figure 4 This is a schematic diagram of the fabrication process of an insulated gate bipolar transistor according to an embodiment of this application. Figure 3 ;

[0033] Figure 5 This is a schematic diagram of the fabrication process of an insulated gate bipolar transistor according to an embodiment of this application. Figure 4 ;

[0034] Figure 6 This is a schematic diagram of the fabrication process of an insulated gate bipolar transistor according to an embodiment of this application. Figure 5 ;

[0035] Figure 7 This is a schematic diagram comparing the impurity diffusion depth of the drift region, buffer zone, and collector region in the substrate in the embodiments of this application.

[0036] Among them, 11. N- epitaxial layer, 12. N+ epitaxial layer, 13. P+ silicon substrate, 21. oxide masking layer, 22. field limiting ring, 23. cut-off ring, 31. polysilicon gate, 32. gate insulating layer, 33. polysilicon field plate, 41. P-well, 42. N-well, 51. insulating leveling layer, 52. emitter electrode, 53. metal field plate, 61. collector electrode. Detailed Implementation

[0037] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of this invention, it should be noted that the terms "above," "back," etc., indicating orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. It should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] In the description of this invention, the illustrative expressions of the terms used above do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this invention, as well as the features of those different embodiments or examples, without contradiction.

[0041] This application provides an insulated gate bipolar transistor (IGBT) and its fabrication method, which solves the problems of poor electrical characteristics and weak reliability of current IGBTs, and improves the performance and reliability of IGBTs.

[0042] The technical solution in this application is to solve the above problems, and the overall approach is as follows:

[0043] Example:

[0044] like Figure 1 As shown, an insulated gate bipolar transistor includes:

[0045] The substrate includes, from bottom to top, a P+ silicon substrate 13, an N+ epitaxial layer 12, and an N- epitaxial layer 11; wherein the P+ silicon substrate 13 is the collector region, the N+ epitaxial layer 12 is the buffer region, and the N- epitaxial layer 11 is the drift region; a collector electrode 61 is disposed on the back side of the substrate.

[0046] An active region, a terminal region, and a cutoff region are provided on the N-epipolar layer 11;

[0047] The active region is provided with a P-well 41, a gate insulating layer 32, a polysilicon gate 31, an insulating leveling layer 51 and an emitter electrode 52 in sequence from bottom to top. An N-well 42 is provided in the P-well 41. The P-well 41 is connected to the emitter electrode 52 through a contact hole in the insulating leveling layer 51.

[0048] The terminal area is provided with a P-injection field limiting ring 22, a polysilicon field plate 33, an insulating leveling layer 51 and a metal field plate 53 from bottom to top. The P-injection field limiting ring 22 is connected to the polysilicon field plate 33, and the polysilicon field plate 33 is connected to the metal field plate 53 through the contact holes in the insulating leveling layer 51.

[0049] The cutoff area is provided with an N-injection cutoff ring 23, a polysilicon field plate 33 and an insulating flow leveling layer 51 from bottom to top. The N-injection field limiting ring 22 is connected to the polysilicon field plate 33.

[0050] Among them, an oxide masking layer 21 is provided on the N-epitaxial layer 11, and the oxide masking layer 21 is provided between adjacent P-implantation field limiting rings 22 and between P-implantation field limiting rings 22 and N-implantation cutoff rings 23. The polysilicon field plate 33 and the insulating leveling layer 51 are located above the oxide masking layer 21.

[0051] Furthermore, in the substrate, the doping concentration of the N-epitaxial layer 11 is 1e 12 -1e 15 cm -3 Within the range, the thickness is 30μm-260μm; the N+ epitaxial layer 12 doping concentration is 1e 14 ~9e 17 cm -3 Within the range of thickness, the thickness is 3μm~20μm; the doping concentration of the P+ silicon substrate is 1e 16 ~9e 19 cm -3 Within this range, the original P+ silicon substrate thickness is generally 50μm~150μm, and the thickness of the thinned P+ silicon substrate is generally 0.5~5μm.

[0052] The resistivity and thickness of the N-epipolar layer 11 (drift region) in the N- / N+ / P+ triple-doped epitaxial wafer depend on the IGBT operating voltage. At an operating voltage of 600V, the resistivity of the N-epipolar layer 11 (drift region) ranges from 18Ω·cm to 32Ω·cm, and the thickness ranges from 30μm to 100μm. At an operating voltage of 1200V, the resistivity of the N-epipolar layer 11 (drift region) ranges from 35Ω·cm to 100Ω·cm, and the thickness ranges from 100μm to 200μm. At an operating voltage of 1700V, the resistivity of the N-epipolar layer 11 (drift region) ranges from 80Ω·cm to 160Ω·cm, and the thickness ranges from 160μm to 260μm.

[0053] like Figure 1-6 As shown, the fabrication method of this insulated gate bipolar transistor includes the following steps:

[0054] S1: As Figure 2 As shown, a substrate with three doped layers of N- / N+ / P+ is selected. The substrate includes, from bottom to top, a P+ silicon substrate 13, an N+ epitaxial layer 12, and an N- epitaxial layer 11.

[0055] S2: As Figure 3 As shown, an oxide masking layer 21 with a thickness of 10000~25000 Å is formed on the top of the N-epitaxial layer 11 by thermal oxidation. Windows are then created by photolithography etching to form the implantation region containing the active region, field confinement ring 22, and stop ring 23. The oxide masking layer 21 between the field confinement rings 22 is retained. The field confinement rings 22 and 23 are formed by implantation and annealing processes. The width of the field confinement ring 22 is 5~20 μm, and the doping concentration is 1e. 13 ~1e 16 cm -3 After annealing, the junction depth is 5~15μm, the width of the stop ring 23 is 20~60μm, and the doping concentration is 1e. 14 ~1e 19 cm -3 After annealing, the junction depth is 5~15μm;

[0056] S3: As Figure 4 As shown, a gate insulating layer 32 with a thickness of approximately 500-1500 Å is grown on the N-epitaxy layer 11 and the oxide masking layer 21 by dry oxidation, and a 5000-15000 Å polysilicon layer is deposited as the gate. The P-well implantation region is opened by photolithography etching process to simultaneously form the polysilicon gate 31 and the polysilicon field plate 33 pattern. The gate insulating layer 32 is grown in two stages to cover the polysilicon gate 31.

[0057] S4: As Figure 5 As shown, P-well 41 and N-well 42 are formed in the P-well injection region through an injection and annealing process. The injection dose of P-well 41 is 1e. 13 -5e 14 cm -3 The push-in depth is 3-6 μm, and the N-well 42 injection dose is 5e. 14 -9e 15 cm -3 The push-bonding depth is 0.1-1.5μm;

[0058] S5: As Figure 6As shown, 10,000-20,000 Å of BPSG is deposited as an insulating leveling layer 51 and reflowed. Contact holes are formed by photolithography etching. Al with a thickness of 3-5 μm is deposited on the insulating leveling layer 51 by vacuum evaporation as the emitter electrode 52 and the metal field plate 53. The metal field plate 53 is connected to the polysilicon field plate 33 through contact holes. The emitter metal electrode is connected to the P-well 41 through contact holes.

[0059] S6: As Figure 1 As shown, the P+ silicon substrate 13 is ground and the back side is thinned to retain a substrate thickness of 0.5-5μm as the collector region, and 1-3μm Al is vacuum-deposited as the collector electrode 61.

[0060] Furthermore, the high-temperature operations such as oxidation, annealing, and reflow in steps S2 / 3 / 4 / 5 require an overall thermal budget to control the impurity diffusion depth in the drift region, buffer region, and collector region of the N- / N+ / P+ three-layer epitaxial wafer, such as... Figure 7 As shown, the impurity diffusion depths in the drift region, buffer region, and collector region of the N- / N+ / P+ three-layer epitaxial wafer, after overall thermal budgeting, satisfy the following conditions: In the collector region of the P+ silicon substrate, the boron ion doping concentration is 1-3 orders of magnitude higher than the arsenic or phosphorus ion doping concentration; in the buffer region of the N+ epitaxial layer, the arsenic ion doping concentration is higher than the boron or phosphorus ion doping concentration, and under the same depth conditions, the arsenic ion doping concentration is 1-3 orders of magnitude higher than the boron ion doping concentration, and under the same doping concentration conditions, the arsenic ion doping depth is 2-5 μm deeper than the boron ion doping depth; in the drift region of the N- epitaxial layer, the phosphorus ion doping concentration is 1-3 orders of magnitude higher than the boron or arsenic ion doping concentration.

[0061] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0062] 1. Compared to the traditional punch-through insulated gate bipolar transistor manufacturing process, this invention reduces the thickness of the N+ buffer layer and P+ collector region through thermal budgeting and back-side thinning methods, controls the impurity diffusion depth, thereby adjusting the back-side carrier injection efficiency and conductivity modulation effect, and optimizing the dynamic electrical characteristics of the device; the N+ buffer layer is doped with arsenic, which has a larger relative atomic mass and a smaller diffusion coefficient, which helps to avoid excessive impurity diffusion; epitaxial wafers that meet the design parameters are purchased through supply chain cooperation to avoid the cost pressure of epitaxial equipment.

[0063] 2. Compared with non-punch-through and field-stop insulated gate bipolar transistors, the present invention does not require back-side implantation and annealing, which simplifies the production process and reduces costs. At the same time, it avoids the impact of back-side annealing on front-side impurities and improves device reliability.

[0064] 3. The N+ buffer of the soft-punch-through insulated gate bipolar transistor of the present invention can buffer the built-in electric field, reduce the thickness of the depletion region, i.e., the N- epitaxial layer drift region, and adjust the carrier injection efficiency of the collector in the forward conduction mode, thereby reducing the forward conduction voltage and greatly reducing power consumption. At the same time, it slows down the expansion speed of the depletion layer boundary, making the turn-off transient electrical characteristics very soft, which has advantages in suppressing high dv / dt and di / dt electromagnetic interference noise.

[0065] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An insulated gate bipolar transistor, characterized by, The application relates to a vertical double diffused MOS (VDMOS) transistor, which comprises the following steps: A substrate comprises from bottom to top a P+ silicon substrate, an N+ epitaxial layer, an N- epitaxial layer; the N- epitaxial layer has a doping concentration in the range of 1e 12 -1e 15 cm -3 , a thickness of 30 μm-260 μm; the N+ epitaxial layer has a doping concentration in the range of 1e 14 ~9e 17 cm -3 , a thickness of 3 μm-20 μm; the P+ silicon substrate has a doping concentration in the range of 1e 16 ~9e 19 cm -3 , a thickness of 0.5 μm-5 μm; in the P+ silicon substrate, the doping concentration of boron ions is 1-3 orders of magnitude higher than that of arsenic ions or phosphorus ions; in the N+ epitaxial layer, the doping concentration of arsenic ions is higher than that of boron ions or phosphorus ions, and under the condition of the same depth, the order of magnitude of the doping concentration of arsenic ions is 1-3 orders of magnitude higher than that of boron ions, and under the condition of the same doping concentration, the doping depth of arsenic ions is 2-5 μm deeper than that of boron ions; in the N- epitaxial layer, the doping concentration of phosphorus ions is 1-3 orders of magnitude higher than that of boron ions or arsenic ions. An active region, a terminal region and a cutoff region are arranged on the N-epitaxial layer; The active region is sequentially provided with a P-well, a gate insulating layer, a polysilicon gate, an insulating flow leveling layer and an emitter electrode from bottom to top, an N-well is arranged in the P-well, and the P-well is connected with the emitter electrode through a contact hole in the insulating flow leveling layer; The terminal region is sequentially provided with a field limiting ring, a polysilicon field plate, the insulating flow leveling layer and a metal field plate from bottom to top, the field limiting ring is connected with the polysilicon field plate, and the polysilicon field plate is connected with the metal field plate through a contact hole in the insulating flow leveling layer; The cutoff region is sequentially provided with a cutoff ring, the polysilicon field plate and the insulating flow leveling layer from bottom to top, and the field limiting ring is connected with the polysilicon field plate; An oxidation masking layer is arranged on the N-epitaxial layer, the oxidation masking layer is arranged between adjacent field limiting rings and between the field limiting ring and the cutoff ring.

2. The insulated gate bipolar transistor of claim 1, wherein: A collector electrode is arranged on the back of the substrate.

3. The insulated gate bipolar transistor of claim 1, wherein: The doping element of the N+epitaxial layer is arsenic.

4. The insulated gate bipolar transistor of claim 1, wherein: The width of the field limiting ring is 5-20 μm, the doping concentration is 1e 13 ~1e 16 cm -3 , and the junction depth after annealing is 5-15 μm; the width of the cutoff ring is 20-60 μm, the doping concentration is 1e 14 ~1e 19 cm -3 , and the junction depth after annealing is 5-15 μm.

5. The insulated gate bipolar transistor of claim 1, wherein: The P-well has an implant dose of 1e 13 -5e 14 cm -3 with a push junction depth of 3-6 μm; the N-well has an implant dose of 5e 14 -9e 15 cm -3 with a push junction depth of 0.1-1.5 μm.

6. A method of manufacturing an insulated gate bipolar transistor as claimed in any one of claims 1-5, characterized in that The application further relates to a preparation method of the vertical double diffused MOS (VDMOS) transistor, which comprises the following steps: S1: selecting the substrate, wherein the substrate comprises the P+silicon substrate, the N+epitaxial layer and the N-epitaxial layer; S2: forming an oxidation masking layer on the top of the N-epitaxial layer through a thermal oxidation process, opening a window through a photoetching and etching process to form an injection area of the active region, the field limiting ring and the cutoff ring, retaining the oxidation masking layer between the field limiting rings, and forming the field limiting ring and the cutoff ring through an injection and annealing process; S3: growing a gate insulating layer on the N-epitaxial layer and the oxidation masking layer through dry oxygen oxidation, depositing a polysilicon layer as a gate, and opening a P-well injection area through a photoetching and etching process to simultaneously form the polysilicon gate and the polysilicon field plate; S4: forming the P-well and the N-well in the P-well injection area through an injection and annealing process; S5: depositing BPSG as the insulating flow leveling layer and reflowing, opening a contact hole through a photoetching and etching process, depositing metal on the insulating flow leveling layer as the emitter electrode and the metal field plate through vacuum evaporation, the metal field plate being connected with the polysilicon field plate through the contact hole, and the emitter electrode being connected with the P-well through the contact hole; S6: grinding the P+silicon substrate, performing back thinning, and vacuum evaporating metal as the collector electrode.

Images