Nanostructured field effect transistor devices and methods of forming same

Abstract

Nanostructured field effect transistor devices and methods of forming the same are provided. A method of forming a semiconductor device includes forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer around the gate structure over the fin; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, where the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a section of the gate structure between the first dielectric plug and the second dielectric plug; etching a section of the gate structure using an isotropic etching process using the patterned mask layer as an etch mask to form a recess in the gate structure; extending the recess into the fin, where extending the recess includes performing an anisotropic etch process; and after extending the recess, filling the recess with a dielectric material.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a nanostructure field effect transistor device and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material on a semiconductor substrate and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0004] In one aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising: forming a first fin, a second fin, and a third fin, the first fin, the second fin, and the third fin protruding above a substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure on the first fin, the second fin, and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer on the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug separating the gate structure into a plurality of segments, wherein the first dielectric plug is formed on the first fin; and a third fin, and a second dielectric plug is formed between the third fin and the second fin; forming a patterned mask layer over the ILD layer, wherein a first opening of the patterned mask layer exposes a first segment of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing an isotropic etching process using the patterned mask layer as an etching mask, wherein the isotropic etching process removes the first segment of the gate structure and forms a recess between the gate spacers; after performing the isotropic etching process, performing an anisotropic etching process to deepen the recess, wherein after the anisotropic etching process, the recess extends through the third fin; and after performing the anisotropic etching process, filling the recess with a dielectric material.

[0005] In another aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure between the first dielectric plug and the second dielectric plug; using the patterned mask layer as an etching mask, etching a segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material.

[0006] In another aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising: forming a gate structure on a fin protruding above a substrate; forming an interlayer dielectric (ILD) layer around the gate structure on the fin; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug separate the gate structure into a plurality of segments; forming a patterned mask layer on the ILD layer, wherein an opening of the patterned mask layer exposes a first segment of the gate structure between the first dielectric plug and the second dielectric plug, wherein the opening of the patterned mask layer is formed to be laterally shifted a predetermined distance relative to the first segment of the gate structure, wherein, in a top view, there is a lateral offset between a longitudinal axis of the gate structure and a central axis of the opening; using the patterned mask layer as an etching mask, etching the first segment of the gate structure using an isotropic etching process to form a recess in the gate structure; after etching, deepening the recess by performing an anisotropic etching process; and after deepening the recess, filling the recess with a dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a nanostructure field effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Figures 13A-13C , Figures 14A-14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Figures 19A-19C , Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B are various views of a nanostructure field effect transistor (NSFET) device at various stages of fabrication in accordance with an embodiment.

[0010] Figures 22A-22C The photoresist stripping problem during patterning of the mask layer is shown.

[0011] Fig.23A and Fig. 23B Patterning of a mask layer in some embodiments is shown.

[0012] Fig.24A and Fig. 24B The etching effect of non-scattered and scattered ions / radicals in a plasma etching process is shown.

[0013] Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Figures 32A-32C , Fig.33A and Fig.33B are various views of a nanostructure field effect transistor (NSFET) device at various stages of fabrication according to another embodiment.

[0014] Fig.34An example of a fin field effect transistor (FinFET) device according to some embodiments is shown in a three-dimensional view.

[0015] Figures 35A-35C , Figures 36A-36D , Figures 37A-37C , Fig.38A , Fig.38B , Fig.39A , Fig.39B , Figures 40A-40C , Fig.41A , Fig.41B , Fig.42A , Fig.42B , Fig.43A , Fig.43B , Fig.44A , Fig.44B , Fig.45A and Fig.45B are various views of a fin field effect transistor (FinFET) device at various stages of fabrication according to yet another embodiment.

[0016] Fig.46A and Fig.46B Together, flowcharts of methods of forming a semiconductor device in some embodiments are shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0018] Additionally, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature as shown in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same or similar figure numbers in different figures refer to the same or similar components formed by the same or similar formation process using the same or similar material(s). Additionally, figures having the same numbers but different letters (e.g., Figures 5A-5C ) show different views of the device at the same processing stage.

[0019] Embodiments of the present disclosure are discussed in the context of forming nanostructure field effect transistor (NSFET) devices (eg, nanosheet devices, nanowire devices). The principles of the present disclosure may also be applied to other types of devices, such as fin field effect transistor (FinFET) devices.

[0020] According to some embodiments, in order to avoid photoresist stripping problems in a continuous metal on diffusion edge (CMODE) process or a continuous polysilicon on diffusion edge (CPODE) process, the position of a cutting pattern in a photoresist layer is intentionally shifted away from the central axis of the gate structure. However, shifting the position of the cutting pattern may cause the opening formed between the gate spacers of the gate structure under the cutting pattern to have an asymmetric sidewall profile. The opening with an asymmetric sidewall profile may interfere with the formation of a back via subsequently formed in a back power rail application. The present disclosure avoids the above-mentioned problems and achieves a symmetrical sidewall profile of the opening by using an isotropic etching process to completely remove the section of the gate structure under the cutting pattern, and then performing an anisotropic etching process to form the opening.

[0021] Figure 1 An example of a nanostructure field effect transistor (NSFET) device 30 according to some embodiments is illustrated in a three-dimensional view. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed over the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed over the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is over and around the gate dielectric layer 120.

[0022] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 122 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 112 of the NSFET device 30. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 90 and in a direction of current flow, for example, between the source / drain regions 112 of the NSFET device. Cross section CC is parallel to cross section BB and between two adjacent fins 90. Cross section DD is parallel to cross section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, subsequent figures may refer to these reference cross sections.

[0023] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Figures 13A-13C , Figures 14A-14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Figures 19A-19C , Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B are various views (eg, cross-sectional views, top views) of a nanostructure field effect transistor (NSFET) device 100 at various stages of fabrication in accordance with an embodiment.

[0024] exist Figure 2 In the embodiment, a substrate 50 is provided. Figure 2 In the example of , substrate 50 includes a lower substrate 49A and an upper substrate 49B, and an etch stop layer 51 is sandwiched between the lower substrate 49A and the upper substrate 49B. In some embodiments, the lower substrate 49A and the upper substrate 49B are formed of the same or similar materials, and therefore, they may be collectively referred to as substrate 49 in the discussion herein. Substrate 49 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 49 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 49 includes: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0025] In some embodiments, the etch stop layer 51 is used to control the stop point in the subsequent backside chemical mechanical planarization (CMP) process for thinning the substrate 50, and therefore, it may also be referred to as a CMP stop layer 51. The etch stop layer 51 is formed of a material different from the substrate 49 to provide etching selectivity. For example, the substrate 49 (e.g., 49A and 49B) may be formed of silicon, and the etch stop layer 51 may be formed of silicon oxide, silicon nitride, etc. For example, the etch stop layer 51 may be formed by, for example, ion implantation into the substrate 49. As another example, the substrate 49A may be formed by a suitable formation method (e.g., chemical vapor deposition (CVD), physical vapor deposition, etc.), and then the etch stop layer 51 may be formed on the substrate 49A (e.g., using CVD, PVD, etc.). After the etch stop layer 51 is formed, the upper substrate 49B is formed on the etch stop layer using any suitable formation method. In other embodiments, the etch stop layer 51 is omitted.

[0026] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 , the layers formed of the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, and 54C. Figure 2 The number of layers formed of the first semiconductor material and the second semiconductor material shown in is merely a non-limiting example. Other numbers of layers are possible and are fully intended to be included within the scope of the present disclosure.

[0027] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming a channel region of a p-type FET, such as silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming an n-type FET channel region, such as silicon. The multilayer stack 64 (which may also be referred to as an epitaxial material stack) will be patterned to form a channel region of the NSFET in subsequent processing. Specifically, the multilayer stack 64 will be patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), wherein the resulting channel region of the NSFET includes a plurality of horizontal nanostructures.

[0028] The multilayer stack 64 can be formed by an epitaxial growth process, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is cyclically: exposed to a first set of precursors to selectively grow the first semiconductor material 52, and then exposed to a second set of precursors to selectively grow the second semiconductor material 54. The first set of precursors includes precursors for a first semiconductor material (e.g., silicon germanium), and the second set of precursors includes precursors for a second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanium), and the second set of precursors includes a silicon precursor but omits a germanium precursor. Thus, the epitaxial growth process can include continuously enabling a silicon precursor to flow to the growth chamber, and then cyclically: (1) enabling a germanium precursor to flow to the growth chamber when growing the first semiconductor material 52; and (2) prohibiting a germanium precursor from flowing to the growth chamber when growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed. Although semiconductor materials (e.g., silicon, silicon germanium) are used in the above examples to form the layer stack 64, the above examples are illustrative and not limiting. For example, in embodiments where the layer labeled 52 is subsequently removed to release the second semiconductor material 54 to form a nanostructure (e.g., a nanosheet or a nanowire), the layer labeled 52 may be referred to as an interposer and may be formed of a suitable material, such as silicon oxide.

[0029] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , 12B , Figures 13A-13C , Figures 14A-14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Figures 19A-19C , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B are various views (eg, cross-sectional views, top views) of NSFET device 100 at subsequent fabrication stages, depending on implementation. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A It is along Figure 1 Cross-sectional view of section BB in FIG. Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figure 7C , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B It is along Figure 1 Cross-sectional view of section AA in FIG. Figure 5B , Figure 6B and Figure 7B It is along Figure 1 Cross-sectional view of section DD in FIG. Fig. 13C , Fig. 14C and Fig.19C is a top view (eg, plan view) of the NSFET device 100. The number of fins and the number of gate structures shown in the figures are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0030] exist Figure 3A and Figure 3B In the embodiment, the fin structure 91 is formed to protrude higher than the substrate 50. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 overlying the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0031] The fin structure 91 may be patterned by any suitable method. For example, the fin structure 91 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing a pattern to be created with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern, for example, the fin structure 91.

[0032] In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. Mask 94 may be a single-layer mask, or may be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B may each be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, and may be deposited or thermally grown according to a suitable technique. The first mask layer 94A and the second mask layer 94B are different materials with high etching selectivity. For example, the first mask layer 94A may be silicon oxide, and the second mask layer 94B may be silicon nitride. Mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. Mask 94 may then be used as an etching mask to etch the substrate 50 and the multilayer stack 64. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multilayer stack 64 forms a layer stack 92, and the patterned portion of the substrate 50 forms a fin 90, such as Figure 3A and Figure 3B As shown. Figure 3A and Figure 3B 5 and subsequent figures, the remaining portion of the substrate 50 (e.g., unpatterned) is referred to as the substrate 50. Thus, in the illustrated embodiment, the layer stack 92 also includes alternating layers of the first semiconductor material 52 and the second semiconductor material 54. The fin 90 is formed of the same material(s) as the substrate 50. Figure 2 In the illustrated embodiment, fin 90 includes etch stop layer 51, upper substrate 49B, and lower substrate 49A material. For simplicity, etch stop layer 51 may not be shown in all subsequent figures, but it is understood that etch stop layer 52 may be formed in fin 90.

[0033] Next, in Figure 4A and Figure 4BIn the embodiment, a shallow trench isolation (STI) region 96 is formed on the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed on the substrate 50. The insulating material can be an oxide such as silicon oxide, a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, CVD-based material deposition in a remote plasma system and post-curing to convert it into another material such as oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process can be performed after the insulating material is formed.

[0034] In some embodiments, the insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structure 91, and a fill material such as those discussed above is formed over the liner. In some embodiments, the liner is omitted.

[0035] Next, a removal process is applied to the insulating material to remove excess insulating material above the fin structure 91. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. The planarization process exposes the layer stack 92 so that the top surface of the layer stack 92 and the insulating material are flush after the planarization process is completed. Next, the insulating material is recessed to form an STI region 96. The insulating material is recessed so that the layer stack 92 protrudes from between adjacent STI regions 96. The top portion of the semiconductor fin 90 may also protrude from between adjacent STI regions 96. In addition, the top surface of the STI region 96 may have a flat surface, a convex surface, a concave surface (e.g., a dish) or a combination thereof as shown. The top surface of the STI region 96 may be formed to be flat, convex and / or concave by appropriate etching. The STI region 96 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 90 and the layer stack 92). For example, chemical oxide removal with a suitable etchant such as dilute hydrofluoric acid (dHF) may be used.

[0036] Still reference Figure 4A and Figure 4B, a dummy dielectric layer 97 is formed on the layer stack 92 and on the STI region 96. The dummy dielectric layer 97 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. In one embodiment, a silicon layer is conformally formed on the layer stack 92 and on the upper surface of the STI region 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the dummy dielectric layer 97.

[0037] Next, in Figures 5A-5C In the embodiment of the present invention, a dummy gate 102 is formed on the fin structure 91. In order to form the dummy gate 102, a dummy gate layer can be formed on the dummy dielectric layer 97. The dummy gate layer can be deposited on the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials with high etching selectivity relative to the STI region 96.

[0038] A mask 104 is then formed over the dummy gate layer. The mask 104 may be formed of silicon nitride, silicon oxynitride, combinations thereof, and the like, and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer by an acceptable etching technique to form a dummy gate 102, and then transferred to the dummy dielectric layer by an acceptable etching technique to form a dummy gate dielectric 97. The dummy gate 102 covers each channel region of the layer stack 92. The pattern of the mask 104 may be used to physically separate each dummy gate 102 from an adjacent dummy gate. The dummy gate 102 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the fin structure 91. In some embodiments, the dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as a dummy gate structure.

[0039] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108 includes a plurality of sub-layers. For example, a first sub-layer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sub-layer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sub-layer.

[0040] Figure 5Band Figure 5C They are shown respectively Figure 5A The NSFET device 100 is arranged along Figure 5A The cross-sectional view of sections EE and FF in FIG. Sections EE and FF correspond to Figure 1 Sections DD and AA in.

[0041] Next, in Figures 6A-6C , the gate spacer layer 108 is etched by an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove horizontal portions of the gate spacer layer 108 (e.g., portions above the STI region 96 and the dummy gate 102), wherein the remaining vertical portions of the gate spacer layer 108 (e.g., portions along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) form the gate spacer 108.

[0042] After forming the gate spacers 108, implantation of lightly doped source / drain (LDD) regions (not shown) may be performed. Appropriate type (e.g., p-type or n-type) impurities may be implanted into the exposed layer stack 92 and / or semiconductor fins 90. The n-type impurities may be any suitable n-type impurities, such as phosphorus, arsenic, antimony, etc., and the p-type impurities may be any suitable p-type impurities, such as boron, BF2, indium, etc. The lightly doped source / drain regions may have a density from about 10 15 cm -3 To about 10 16 cm -3 An annealing process may be used to activate the implanted impurities.

[0043] Next, an opening 110 (which may also be referred to as a recess) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the fin 90. The opening 110 may be formed by an anisotropic etching process using, for example, the dummy gate 102 and the gate spacer 108 as an etching mask.

[0044] After the opening 110 is formed, a selective etching process is performed to recess the end of the first semiconductor material 52 exposed by the opening 110 without substantially attacking the second semiconductor material 54. After the selective etching process, a recess (also referred to as a sidewall recess) is formed in the first semiconductor material 52 where the removed end was located.

[0045] Next, an internal spacer layer is formed (e.g., conformally) in the opening 110. The internal spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), etc., which is formed by a suitable deposition method (e.g., PVD, CVD, atomic layer deposition (ALD), etc.). Next, an etching process such as an anisotropic etching process is performed to remove the portion of the internal spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the sidewall recesses of the first semiconductor material 52) forms an internal spacer 55. As shown in FIG. Fig. 6A As shown, the opening 110 exposes the sidewalls of the second semiconductor material 54 and exposes the upper surface 90U of the fin 90 .

[0046] Figure 6B and Figure 6C They are shown respectively Fig. 6A FIG. 1 is a cross-sectional view of the NSFET device 100 along sections EE and FF. Figure 6B , portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between the adjacent fins 90 are completely removed by the anisotropic etching process for forming the gate spacer layer 108. In some embodiments, portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between the adjacent fins 90 are left (e.g., retained). Those portions of the gate spacer layer 108 may be left because the above-mentioned anisotropic etching process may not completely remove the gate spacer layer 108 disposed between the adjacent fins 90 due to the small distance between the adjacent fins 90 reducing the efficiency of the anisotropic etching process.

[0047] Next, in Figures 7A-7CIn the discussion herein, source / drain regions 112 are formed in the openings 110. In the discussion herein, (one or more) source / drain regions may refer to the source or drain, singularly or collectively, depending on the context. In the illustrated embodiment, the source / drain regions 112 are formed of (one or more) epitaxial materials and, therefore, may also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the openings 110 to apply stress in various channel regions of the formed NSFET device to improve performance. In some embodiments, the epitaxial source / drain regions 112 are formed so that the dummy gate 102 is disposed between the corresponding pairs of epitaxial source / drain regions 112. In some embodiments, the gate spacer 108 is used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance so that the epitaxial source / drain regions 112 do not short-circuit the gate of the subsequently formed NSFET device.

[0048] Epitaxial source / drain regions 112 are epitaxially grown in openings 110. Epitaxial source / drain regions 112 may include any acceptable material, such as suitable for n-type or p-type devices. For example, when forming an n-type device, epitaxial source / drain regions 112 may include a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, epitaxial source / drain regions 112 may include a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 112 may have a surface that protrudes from a corresponding surface of the fin 90 and may have a small facet.

[0049] The epitaxial source / drain regions 112 and / or the fins 90 may be implanted with dopants to form source / source regions similar to the process for forming lightly doped source / drain regions discussed previously, followed by annealing. The source / drain regions may have a thickness between about 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 112 may be doped in situ during growth.

[0050] Due to the epitaxial process used to form the epitaxial source / drain regions 112, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 90. In the illustrated embodiment, adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed (see FIG. Figure 7B). In other embodiments, these facets result in merging of adjacent epitaxial source / drain regions 112 of the same NSFET.

[0051] Next, a contact etch stop layer (CESL) 116 is formed (e.g., conformally) over the source / drain regions 112 and the dummy gate 102, and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and may be formed of silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, and the like, as well as alternative techniques for forming the CESL 116 such as low pressure CVD (LPCVD), PVD, and the like may be used instead.

[0052] The first ILD 114 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material for the first ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, undoped silicate glass, etc. Other insulating materials formed by any acceptable process may be used. Figure 7B and Figure 7C They are shown respectively Fig. 7A A cross-sectional view of the NSFET device 100, but along Fig. 7A Sections EE and FF.

[0053] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B A replacement gate process is shown in which the dummy gate structures (eg, 102 and 97 ) are removed and replaced by a replacement gate structure 123 (eg, a metal gate structure).

[0054] Next, in Fig. 8A and Figure 8B In order to remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and the CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process can also remove the mask 104 on the dummy gate 102 (see Fig. 7A) and portions of the gate spacers 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gate 102, the gate spacers 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0055] Next, the dummy gate 102 is removed in (one or more) etching steps, thereby forming the recess 103. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases, which selectively etches the dummy gate 102 without etching the first ILD 114 or the gate spacer 108. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer when etching the dummy gate 102. The dummy gate dielectric 97 may then be removed after the dummy gate 102 is removed. Figure 8B Shows Fig. 8A A cross-sectional view of the NSFET device 100 along section FF.

[0056] Next, in Fig.9A and Fig. 9B In the embodiment, the dummy gate dielectric 97 in the recess 103 is removed. An etching process, such as an isotropic etching process, may be performed to remove the dummy gate dielectric 97. In one embodiment, the isotropic etching process is performed using an etching gas including HF and NH3 to remove the dummy gate dielectric 97. Fig.9A and Fig. 9B As shown, each recess 103 exposes a channel region of the NSFET. Each channel region is disposed between a pair of adjacent epitaxial source / drain regions 112.

[0057] Next, in Fig. 10A and Fig. 10B In the embodiment of the present invention, the first semiconductor material 52 (e.g., the portion exposed by the recess 103) is removed to release the second semiconductor material 54. After the first semiconductor material 52 is removed, the second semiconductor material 54 (e.g., the portion located under the dummy gate 102 before the dummy gate 102 is removed) forms a plurality of nanostructures 54 extending horizontally (e.g., parallel to the main upper surface of the substrate 50). The nanostructures 54 may be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Fig. 10A As shown, by removing the first semiconductor material 52, gaps 53 (eg, empty spaces) are formed between the nanostructures 54. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending on, for example, the dimensions of the nanostructures 54 (eg, size and / or aspect ratio).

[0058] In some embodiments, the first semiconductor material is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate), so that the first semiconductor material 52 is removed without substantially attacking the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process is performed using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and in some embodiments, the carrier gas can be an inert gas, such as Ar, He, N2, a combination thereof, and the like.

[0059] Fig. 10A A cross-sectional view of the NSFET device 100 along the longitudinal axis of the fin (eg, along the direction of current flow in the fin), and Fig. 10B A cross-sectional view of NSFET device 100 is shown along section FF, which is a section along a direction perpendicular to the longitudinal axis of the fin and through a middle portion of nanostructure 54 .

[0060] like Fig. 10A As shown, each nanostructure 54 has a rectangular cross-section along the longitudinal axis of the fin. Fig. 10B In FIG. 5 , each nanostructure 54 has a rectangular cross-section in a cross section along a direction perpendicular to the longitudinal axis of the fin and passing through a middle portion of the nanostructure 54 .

[0061] Next, in Fig.11A and Fig. 11B In some embodiments, the nanostructure 54 is reshaped by a nanostructure reshaping process (e.g., an isotropic etching process). In some embodiments, the nanostructure 54 is reshaped by a selective etching process using an etchant that is selective to the material of the nanostructure 54 (e.g., the second semiconductor material 54), so that the nanostructure 54 is etched without substantially attacking other materials in the NSFET device 100, such as oxides, silicon nitrides, and low-K dielectric materials.

[0062] In some embodiments, an isotropic etching process (eg, a selective etching process) is performed using an etching gas and an optional carrier gas to reshape the nanostructure 54, wherein the etching gas includes F2 and NH3, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, and the like.

[0063] In addition to using the mixture of F2 and NH3 as the etching gas, other suitable etching gases (e.g., ClF3 or a mixture of NF3 and NH3) may also be used as etching gases to reshape the nanostructure 54. For example, an isotropic etching process (e.g., an isotropic plasma etching process) using an etching gas including NF3 and NH3 may be performed to reshape the nanostructure 54.

[0064] The nanostructure remodeling process makes the middle portion of each nanostructure 54 thinner, while the ends of the nanostructure 54 remain substantially unchanged, thereby generating a Fig.11A In addition, the nanostructure remodeling process removes the sharp edges of the nanostructure 54 (see, for example, Fig. 10B 90 degree angle of the nanostructures 54 in the embodiment of the present invention), thereby producing a rounded edge for each nanostructure 54 (see Fig. 11B ), as described in more detail below.

[0065] like Fig.11A As shown, after the nanostructure reshaping process, in a cross section along the longitudinal axis of the fin, each nanostructure 54 has a dumbbell shape, wherein the thickness (along the cross section) of the end portion (eg, the portion that physically contacts the source / drain region 112) of the nanostructure 54 is Fig.11A In some embodiments, the difference between the thickness of the ends of nanostructure 54 and the thickness of the middle portion of nanostructure 54 is between about 0 nm and about 3 nm. Fig.11A In the example of FIG. 5 , the upper and lower surfaces of the middle portion of each nanostructure 54 are illustrated as horizontal surfaces (e.g., flat surfaces). Of course, this is merely a non-limiting example. In some embodiments, the upper and lower surfaces of the middle portion of each nanostructure 54 are curved, for example, curved toward the horizontal center axis of the nanostructure 54. In addition, Fig. 11B In the cross section of , each nanostructure 54 has a stadium shape (which may also be referred to as a racetrack shape, a disc-shaped rectangular shape, a circular shape, or a sausage shape). Specifically, in Fig. 11B In a cross section of , the corners of each nanostructure 54 are rounded (e.g., curved). In some embodiments, the thickness T (also referred to as the sheet thickness) of the nanostructure 54 (e.g., nanosheet) is between about 6.3 nm and about 8.2 nm, and its average value (e.g., mean value) is about 7.1 nm. In some embodiments, the spacing C (also referred to as the intersheet distance) between adjacent nanostructures 54 is between about 4.5 nm and about 5.9 nm, and its average value is about 5.2 nm. In some embodiments, the width O (also referred to as the sheet width) of the nanostructure 54 is between about 94.9 nm and about 97.5 nm, and its average value is about 96.2 nm.

[0066] As feature sizes continue to shrink in advanced process nodes, the distance between adjacent nanostructures 54 may become so small that it may be difficult to form a layer (e.g., a gate dielectric layer, a work function layer) around the nanostructure 54 in subsequent processing. By reshaping the nanostructure 54, such as thinning the middle portion of the nanostructure 54, the distance between adjacent nanostructures 54 is increased, thereby making it easier to form, for example, a gate dielectric layer 120 around the nanostructure 54 (see Fig. 12A and Fig. 12B ). In addition, since the thickness T of the nanostructure 54 forming the channel region 93 of the NSFET device 100 is reduced by the nanostructure reshaping process, it is easier to control (e.g., turn on or off) the NSFET device 100 by applying a gate control voltage on a metal gate formed in a subsequent process.

[0067] In some embodiments, the Fig.11A and Fig. 11B In the subsequent figures, the channel region 93 of the NSFET device 100 is illustrated as having Fig.11A and Fig. 11B It should be understood that the channel region 93 may have Fig. 10A and Fig. 10B cross section (e.g., when the nanostructure remodeling process is omitted).

[0068] Next, in Fig. 12A and Fig. 12B , a gate dielectric layer 120 and a gate electrode 122 are formed to form a replacement gate. The gate dielectric layer 120 is conformally deposited in the recess 103, for example, on the top surface and sidewalls of the semiconductor fin 90 and on the sidewalls of the gate spacer 108. The gate dielectric layer 120 may also be formed on the top surface of the first ILD 114. It is noteworthy that the gate dielectric layer 120 is formed to surround the nanostructure 54. According to some embodiments, the gate dielectric layer 120 includes silicon oxide, silicon nitride or a multilayer thereof. In some embodiments, the gate dielectric layer 120 is formed of a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a k value of about 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti or Pb or a combination thereof. The formation method of the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0069] Next, a gate electrode 122 is deposited over and around the gate dielectric layer 120 and fills the remaining portion of the recess 103. The gate electrode 122 may include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single layer gate electrode 122 is shown, the gate electrode 122 may include any number of liner layers (e.g., barrier layers), any number of work function tuning layers, and fill metal materials. After filling the gate electrode 122, a planarization process (e.g., CMP) may be performed to remove excess portions of the gate dielectric layer 120 and the gate electrode 122 material that are above the top surface of the first ILD 114. Thus, the gate electrode 122 and the remaining portions of the gate dielectric layer 120 material form the replacement gate of the resulting NSFET device 100. Each gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as a gate stack 123 , a replacement gate structure 123 , a metal gate structure 123 , or a gate structure 123 . Each gate structure 123 extends around a corresponding nanostructure 54 .

[0070] Next, the formation process proceeds to cutting the gate structure 123 and cutting (e.g., removing) some of the nanostructures 54 to form isolated transistors. The cutting of the gate structure 123 is referred to as a cut metal gate (CMG) process. The cutting of the nanostructures 54 (and portions of the fins 90 below them, respectively) is referred to as a continuous metal on diffusion edge (CMODE) process, or sometimes referred to as a cut metal on diffusion edge (CMODE) process. Note that in the illustrated CMODE process, the cutting of the nanostructures 54 and their respective underlying fins 90 is performed after the replacement gate stack 123 is formed. In the illustrated CMG process and CMODE process, some examples of cutting locations are shown, such as Fig. 13C and Fig. 22C It can be understood that the cutting process can be performed at different locations and in different sizes according to the design of the transistor.

[0071] exist Fig. 12A and Fig. 12B , two fins 90 and two gate structures 123 are shown. Of course, this is a non-limiting example. The number of fins 90 and the number of gate structures 123 in the NSFET device 100 can be any suitable number. Figures 13A-26B ), in order to facilitate the discussion of the CMG process and the CMODE process, three fins 90 (labeled as 90A, 90B and 90C) and four gate structures 123 (labeled as 123A, 123B, 123C and 123D) are shown.

[0072] Next reference Figures 13A-13C, a dielectric plug 125 is formed to cut the gate structure 123B into a plurality of separate segments. Fig. 13C 1 shows a top view (eg, plan view) of the NSFET device 100 after the dielectric plug 125 is formed. For simplicity, Fig. 13C Not all features of NSFET device 100 are shown. For example, Fig. 13C Only the fins 90A, 90B, 90C (collectively referred to as fins 90 ), gate structures 123A, 123B, 123C, and 123D (collectively referred to as gate structures 123 ), gate spacers 108 surrounding sidewalls of the gate structures 123 , and dielectric plugs 125 are shown.

[0073] In some embodiments, the dielectric plug 125 is formed by forming an opening in the gate structure 123B and the first ILD 114 (e.g., using photolithography and etching techniques), and filling the opening with a dielectric material (e.g., silicon nitride, silicon oxide, a combination thereof, etc.). Next, a planarization process (e.g., CMP) may be performed to remove excess portions of the dielectric material from the upper surface of the first ILD 114, and the remaining portion of the dielectric material in the opening forms the dielectric plug 125.

[0074] In the example shown, dielectric plugs 125 are formed on opposite sides of fin 90B. Fig. 13C In the embodiment shown, one dielectric plug 125 is formed between fins 90A and 90B, and another dielectric plug 125 is formed between fins 90B and 90C. In the embodiment shown, the dimension WDP of the dielectric plug 125 measured along the direction of the cross section BB is greater than the dimension WMG of the gate structure 123B to ensure that the dielectric plug 125 cuts the gate structure 123B into separate sections that are electrically isolated from each other. Fig. 13B As shown, dielectric plug 125 extends through gate structure 123 and into STI region 96 to ensure separation of different sections of gate structure 123B. Note that dielectric plug 125 is not Fig. 13C In the cross section BB, therefore Fig.13A Not visible in.

[0075] Next, in Fig.14A and Fig. 14B In the embodiment of the present invention, a hard mask layer 131 (also referred to as a mask layer) is formed over the first ILD 114 and the gate structure 123. The hard mask layer 131 may be a single-layer hard mask formed of, for example, silicon nitride, silicon oxynitride, etc. using a suitable formation method such as CVD. In some embodiments, the hard mask layer 131 has a multi-layer structure. For example, the hard mask layer 131 may include a silicon layer sandwiched between two silicon nitride layers.

[0076] Next, an etching mask 136 is formed over the hard mask layer 131. The etching mask 136 may have a single-layer structure, which may be a photoresist layer, or a double-layer structure including a bottom anti-reflective coating (BARC) layer and a photoresist layer. Fig.14A and Fig. 14B In the example of , the etching mask 136 has a three-layer structure including a bottom layer 135 (eg, a carbon-based BARC layer), an intermediate layer 137 (eg, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer), and a photoresist layer 139.

[0077] Next, openings 138 are formed in the photoresist layer 139 of the etch mask 136. As described below, the openings 138 are transferred to the hard mask layer 131, thereby defining the openings 132 (see Fig.15A and Fig. 15B ) in the hard mask layer 131. The opening 132 in the hard mask layer 131 exposes the gate structure 123B disposed at Fig. 13C The section 123BM between the dielectric plugs 125 in Fig. 13C ). Although it seems intuitive that the best position of the opening 138 should be located directly above and overlapping with the segment 123BM of the gate structure 123B (e.g., completely overlapping in a top view), the opening 138 in the present disclosure is purposefully (e.g., intentionally) formed to deviate from this seemingly optimal position. Fig.14A In the example of FIG. 1 , the opening 138 has a lateral offset OVS between the central axis 138X of the opening 138 and the central axis 123BX of the gate structure 123B (also as shown in FIG. 1 ). Fig. 14C shown). Fig. 14C A top view of a NSFET device 100 in one embodiment is shown. For clarity, Fig. 14C Only the boundary of the opening 138 (shown as a rectangle), the central axis 138X of the opening 138, the boundary of the segment 123BM of the gate structure 123B (shown as a dashed rectangle), and the central axis 123BX of the gate structure 123B are shown. Note that the central axis 123BX is the longitudinal central axis of the gate structure 123B. In addition to the lateral shift, Fig. 14C The dotted rectangle and the rectangle in FIG. 1 are identical. The lateral offset OVS between the center axis 138X and the center axis 123BX is shown in FIG. Fig. 14C In some embodiments, since the opening 138 is transferred to the hard mask layer 131 as the opening 132, the rectangle of the opening 138 also shows the opening 132 in the hard mask 131. Fig. 14CAs shown, the opening 138 (or the opening 132 ) is formed to be laterally shifted by a predetermined distance (eg, laterally offset OVS) relative to the segment 123BM of the gate structure 123B. As described below, the laterally offset OVS is used to reduce or avoid the photoresist stripping problem.

[0078] refer to Figures 14A-14C , denoting the width of the opening 138 as WO, in some embodiments, the lateral offset OVS is between about 5% and about 33% of the width WO of the opening 138, such as between about 15% and about 30%. Fig.14A Also shown is a width WG of the gate structure 123B, which is measured between the gate spacers 108 on opposite sides of the gate structure 123B. In some embodiments, the width WO of the opening 138 is the same as or similar to the width WG of the gate structure 123B.

[0079] In some embodiments, the opening 138 is purposely formed with a lateral offset OVS to avoid photoresist stripping issues, as described below with reference to Figures 22A-22C and Figures 23A-23B described.

[0080] Temporary reference Fig.22A and Fig. 22B , which respectively show a top view and a cross-sectional view of the three-layer etching mask 136 and the hard mask layer 131, which respectively correspond to Fig.14A and Fig. 14B The etching mask 136 and the hard mask layer 131 in. Fig. 22B Shown along Fig.22A A cross-sectional view of section GG in FIG. Notice that Fig.22A Three openings 138A, 138B, and 138C (collectively referred to as openings 138) in photoresist layer 139 are shown to illustrate the reasons and advantages of having a laterally offset OVS. Fig.14A and Fig. 14B In other related figures of the illustrated embodiment, for simplicity, only one opening 138 is shown. It should be understood that a plurality of openings 138 may be formed in the photoresist layer 139, such as Fig.22A The openings shown in FIG. 1 may be the same or similar to the openings 138. For example, Fig.22A The opening 138A in may correspond to Fig.14A The opening 138 in the.

[0081] exist Fig. 22B In the example of FIG. 1 , the photoresist layer 139 includes two thin fin-shaped sheets 139A and 139B disposed between the openings 138A and 138C. Fig. 22BIn the figure, the width of the fins 139A and 139B is represented as the width S (also referred to as the spacing of the openings), the width of the opening 138 is represented as the width W (also referred to as the critical dimension (CD) of adjacent openings), and the spacing between adjacent openings 138 is represented as the pitch P. In the semiconductor manufacturing process, the feature size continues to shrink. Currently, in advanced process nodes, the feature size is on the order of nanometers. Due to their size (e.g., small width S and / or high aspect ratio), the fins 139A and 139B may collapse. Fig. 22C FIG. 1 shows an example of the fin 139B of the photoresist layer 139 collapsing, which is called the photoresist stripping problem. When the width W is much larger than the width S (e.g., W>>S), the photoresist stripping problem is likely to occur. Therefore, if the opening 138A is Fig. 22B The opening 138C is shifted to the left side. Fig. 22B , while the position of opening 138B remains unchanged, the width S of fins 139A and 139B increases, and the likelihood of photoresist stripping problems is reduced. Generally, if the width W is less than or equal to half of the pitch size P (e.g., W≤1 / 2P), photoresist stripping problems can be avoided. This condition can be met by shifting the positions of openings 138A and 138C as discussed above.

[0082] Fig.23A and Fig. 23B The effect of shifting the positions of openings 138A and 138C as discussed above is shown. Fig.23A , the position of opening 138B remains the same as Fig.22A The same position as Fig.22A Compared with the positions of opening 138A and opening 138C in FIG. 1 , the positions of opening 138A and opening 138C have been shifted to the left and right, respectively. For comparison, Fig.22A The positions of the openings 138A and 138C in Fig.23A As shown by the dashed lines in (e.g., dashed rectangle).

[0083] like Fig.23A As shown, in Fig.23A The central axis 138AX2 of the opening 138A and Fig.22A The opening 138A in Fig.23A There is a lateral offset OVS between the central axis 138AX1 (shown as the dashed rectangle in FIG. 1 ). In some embodiments, Fig.23A The dashed rectangle in Fig.22A The opening 138A in Fig. 13C The central axis 138AX1 corresponds to the boundary of the segment 123BM of the gate structure 123B in (eg, completely overlaps with) Fig. 13CThe longitudinal center axis of the gate structure 123B is shown in FIG. Fig. 13C The lines of the middle section AA are the same. Fig. 23B The width S' of the fins 139A and 139B and the pitch P' of the openings 138 are shown. Note that the width W of the openings 138 remains the same as Fig. 22B The width is the same as in. Fig. 23B As shown, due to the lateral displacement of the openings 138A and 138C, the width S' of the fins 139A and 139B is greater than Fig. 22B The width S in the opening 138 is greater than the pitch P' of the opening 138. Fig. 22B As a result, the photoresist stripping problem is avoided or reduced.

[0084] Next, refer to Fig.15A and Fig. 15B , using a suitable method, such as one or more anisotropic etching processes, the opening 138 of the photoresist layer 139 is extended through the intermediate layer 137 and the bottom layer 135, and is transferred to the hard mask layer 131 as the opening 132. For simplicity, it is assumed that after the (one or more) anisotropic etching processes for transferring the opening 138 of the photoresist layer 139 to the hard mask layer 131, the openings 138 and 132 overlap (e.g., are the same) in a top view. Next, the etching mask 136 is removed by a suitable process (e.g., etching, grinding, a combination thereof, etc.).

[0085] Fig.15A and Fig. 15B NSFET device 100 is shown after removal of etch mask 136. Fig.15A and Fig. 15B As shown, the opening 138 is transferred to the hard mask layer 131 as an opening 132 in the hard mask 131. The opening 132 exposes the section 123BM of the gate structure 123B disposed between the dielectric plugs 125 (see Fig. 13C ), so that the exposed segment 123CM can be removed and replaced with the isolation structure 141 in a subsequent process, the details of which will be discussed below. In a top view, the shape of the opening 132 (e.g., rectangular) is the same as the shape defined by the boundary (e.g., sidewall) of the segment 123BM of the gate structure 123B, but there is a lateral offset OVS between the central axis 132X of the opening 132 and the central axis 123BX of the gate structure 123B, as shown in FIG. Fig.23A and Fig.15AAs shown. In some embodiments, the lateral offset OVS is controlled within a certain range so that the sidewall 132S of the opening 132 does not extend beyond the corresponding sidewall of the CESL 116 facing the back gate structure 123B. In other words, the opening 132 does not expose the first ILD 114 to avoid damaging the first ILD 114 in a subsequent etching process. Note that the lateral offset OVS means that a portion of the segment 123BM of the gate structure is exposed by the opening 132, while another portion of the segment 123BM is covered by the hard mask layer 131. As described below, despite the lateral offset OVS, an isotropic etching process is used to completely remove the segment 123BM of the gate structure 123B.

[0086] Next, in Fig.16A and Fig. 16B In some embodiments, the isotropic etching process is a wet etching process performed using an etching chemical (e.g., an etching fluid), such as a piranha solution (e.g., a mixture of sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and water (H2O), also referred to as an SPM solution) to selectively remove the exposed section of the gate structure 123B without substantially attacking other layers / materials of the NSFET device 100. The wet etching process can be performed at an elevated temperature, such as about 140 degrees Celsius. In some embodiments, the isotropic etching process is a dry etching process (e.g., a plasma etching process) performed using an etching gas including Cl2, BCl3, combinations thereof, and the like. The hard mask layer 131, the gate spacers 108, and the dielectric plugs 125 can help protect (e.g., shield) other areas of the NSFET device 100 from the isotropic etching process and limit the effects of the isotropic etching process to the area defined by the opening 132. Note that due to the isotropy of the wet etching process or the dry etching process, although a portion of the segment 123BM of the gate structure 123B is covered by the hard mask layer 121, the portion of the segment 123BM is also removed. After the isotropic etching process, the gate electrode 122 and the gate dielectric layer 120 in the exposed segment 123BM of the gate structure 123B are removed (e.g., completely removed), and the opening 132 extends downward through the gate structure 123B to expose the upper surface of the STI region 96. The nanostructure 54 that was previously surrounded by the segment 123BM of the gate structure 123B is now exposed to the opening 132. Advantages of using an isotropic etching process to remove the segment 123BM of the gate structure 123 will be discussed below.

[0087] Next, in Fig.17A and Fig. 17BIn the embodiment of the present invention, an anisotropic etching process 143 is performed to remove the nanostructure 54 in the opening 132. In some embodiments, the anisotropic etching process 143 is a plasma dry etching process and may be referred to as a plasma dry etching process 143 or an anisotropic plasma etching process 143 hereinafter. The plasma dry etching process 143 may be performed using a gas source including HBr, Cl2, or a combination thereof. In some embodiments, during the plasma dry etching process 143, other gases such as O2, CO2, or a combination thereof may be added to the gas source to adjust various aspects of the plasma dry etching process, such as etching rate, etching selectivity, and / or etching profile.

[0088] During the plasma dry etching process 143, the gas source is ignited into plasma by the plasma etching tool. The plasma etching tool can use an inductively coupled dipole antenna coil to generate plasma. In some embodiments, the radio frequency (RF) power generator of the plasma etching tool generates a 13.6MHz RF power source (e.g., RF signal). The plasma etching tool chamber can operate at a pressure between about 3mTorr and about 150mTorr and at a temperature between about 20 degrees Celsius and about 150 degrees Celsius. The power of the RF power source can be between about 100W and about 2500W. In some embodiments, the plasma dry etching process uses pulsed plasma etching, wherein the duty cycle of the RF power source is in the range of about 10% to 100%. In some embodiments, an RF bias power between about 10W and about 1200W of the base of the plasma etching tool is used for the plasma dry etching process. The plasma dry etching process 143 can be performed continuously until the opening 132 extends to the target depth (e.g., extending through the nanostructure 54 and into the substrate 50).

[0089] In some embodiments, in order to protect the hard mask layer 131 and maintain the size of the opening 132 during the plasma dry etching process 143, a passivation layer is formed on the upper surface of the hard mask 131 and along the sidewalls and bottom of the opening 132 (e.g., conformally). The passivation layer may also be formed on the surface of the nanostructure 54. The passivation layer may be a carbon-based passivation layer formed by injecting CH4 into a plasma etching tool during the plasma dry etching process. A carrier gas (e.g., Ar or N2) may be used to carry CH4 into the plasma etching tool. In some embodiments, the passivation layer may be a SiO-based passivation layer formed by injecting SiCl4 and O2 gases into a plasma etching tool during the plasma dry etching process. A carrier gas (e.g., Ar or N2) may be used to carry SiCl4 and O2 into the plasma etching tool. The SiO-based passivation layer may be formed by the following chemical reaction:

[0090] SiCl4+O2->SiO2+Cl2

[0091] In some embodiments, (one or more) additive chemicals such as HBr are injected into the plasma etching tool chamber together with SiCl4 to promote the dissociation of SiCl4 in the SiO-based passivation layer formation process. The chemical reaction is, for example:

[0092] SiCl4+HBr->SiCl3+HCl+Br

[0093] This may occur to accelerate the dissociation of SiCl4 and the formation of the SiO-based passivation layer. Bromine (Br) produced by the above chemical reaction may further react with SiO2 to form SiBrO. Therefore, the composition of the SiO-based passivation layer may include SiBrO.

[0094] After forming the passivation layer, a break-through etching step is performed to remove the passivation layer from the etching front side (e.g., remove the passivation layer from the surface of the nanostructure 54 and the bottom of the opening 132), so that a plasma dry etching process 143 can be performed next to remove the nanostructure 54 and / or deepen the opening 132. In some embodiments, the break-through etching step is an anisotropic etching process (e.g., a plasma etching process) performed using a gas source including CF4, CHF3, C4F6, or a combination thereof. After the break-through etching step, the passivation layer at the bottom of the opening 132 is removed, while the sidewalls of the opening 132 remain covered by the passivation layer.

[0095] Therefore, the etching process for removing the nanostructure 54 below the opening 132 and deepening the opening 132 may include multiple etching cycles, wherein each of the multiple etching cycles includes the following three sequential processing steps: 1) a deposition step for forming a passivation layer (e.g., a carbon-based or SiO-based passivation layer) on the hard mask layer 131 and along the sidewalls and bottom of the opening 132; 2) a penetration etching step for removing the passivation layer from the etching front side; and 3) an anisotropic etching step, wherein a plasma dry etching process 143 is performed to remove the nanostructure 54 and deepen the opening 132. The three-step etching process discussed above is optional. In some embodiments, the deposition step and the penetration step are omitted, and the plasma dry etching process 143 is used alone to remove the nanostructure 54 and deepen the opening 132.

[0096] like Fig.17A and Fig. 17B As shown, the section 123BM of the gate structure 123B exposed by the opening 132 is completely removed. The portion of the nanostructure 54 below (eg, directly below) the opening 132 is also removed. The portion of the nanostructure 54 below (eg, directly below) the gate spacer 108 may remain, as shown in FIG. Fig.17A In addition, the fin 90B below the opening 132 is also removed. Fig. 17B As shown, the opening 132 extends through the STI region 96 and into the substrate 50. As a result, the upper surface 50U1 of the portion of the substrate 50 below the opening 132 is lower (e.g., more recessed) than the upper surface 50U2 of other (unetched) portions of the substrate 50. In the illustrated embodiment, the plasma dry etching process 143 is selective (e.g., has a much higher etching rate) to the material of the nanostructure 54 (e.g., silicon) and has little etching effect on the STI region 96.

[0097] like Fig.17A and Fig. 17B As shown in FIG. 1 , after the nanostructure 54 is removed, the opening 132 (also referred to as the recess 132) exposes the sidewall of the dielectric plug 125 facing the nanostructure 54, and exposes the inner sidewall of the gate spacer 108 facing the opening 132. In other words, in a top view, the opening 132 is formed along a first direction (e.g., along Fig.19C The direction of the cross section AA in FIG. 1 is defined by the opposite sidewalls of the dielectric plug 125, and along the second direction (eg, along Fig.19C The direction of the cross section BB in FIG. 1 is defined by the opposite sidewalls of the gate spacer 108. Since the opening 132 is subsequently filled with a dielectric material to form the isolation structure 141, Fig.19C The position of the isolation structure 141 in the top view of FIG. 1 also illustrates the position of the opening 132 before being filled.

[0098] Advantages are achieved by using an isotropic etching process to remove the segment 123BM of the gate structure 123. For example, the presently disclosed method allows Fig.17A The opening 132 in the substrate 50 is formed to have a symmetrical sidewall profile, so that the opening 132 extends straight down toward the substrate 50. In the absence of the disclosed method, the opening 132 may have an asymmetrical sidewall profile (e.g., see Fig. 24B ), wherein one sidewall of the opening 132 protrudes to a position below the corresponding source / drain region 112. The opening 132 is then filled with (one or more) dielectric materials to form the isolation structure 141. In subsequent processing, a backside via 165 is formed on the backside of the substrate 50 (see, for example, Fig.21A ) to connect the back power rail 169 to the source / drain region 112. If the subsequently formed isolation structure 141 has a protrusion protruding toward the path of the back via 165, the isolation structure 141 may hinder the formation of the back via 165, thereby causing device failure. The method disclosed in the present invention prevents the occurrence of an asymmetric sidewall condition, thereby improving the reliability and production yield of the device.

[0099] To understand the advantages of the presently disclosed method, consider a comparative method in which an anisotropic etching process is used to remove the segment 123BM of the gate structure 123 using the hard mask layer 131 as an etching mask. Fig.24A and Fig. 24B , which shows that when the segment 123M of the gate structure 123 is removed using an anisotropic etching process and then the opening 132 is deepened using an anisotropic plasma etching process (eg, 143), the opening 132 is formed with an asymmetric sidewall profile. Fig.24A and Fig. 24B In the embodiment, the sidewall of the gate spacer 108 on the left side of the opening 132 is exposed to the opening 132, and the sidewall of the gate spacer 108 on the right side of the opening 132 is covered by the remaining portion 123R of the segment 123BM of the gate structure 123 (as in the embodiment method for forming the NSFET device 100), or by the portion 102R (e.g., polysilicon) of the dummy gate 102 (as in the embodiment for forming the NSFET device 100A discussed below). The remaining portion 123R or 102R is caused by the lateral offset OVS of the opening 132 to avoid the photoresist stripping problem, as described above.

[0100] Still reference Fig.24A and Fig. 24B After removing the gate structure segment 123BM, an anisotropic plasma etching process (same or similar to the anisotropic plasma etching process 143) is performed to remove the underlying nanostructure 54 and deepen the opening 132. Fig.24A and Fig. 24B , ions and / or radicals of the plasma used in the anisotropic etching process are labeled as ions / radicals 142 . Fig.24A and Fig. 24B The dashed arrow line in shows the trajectory of ions / radicals 142.

[0101] Fig.24A Etching caused by non-scattered ions / radicals 142 (which refers to ions / radicals 142 that hit various material surfaces and stop in these materials) is shown. In other words, the non-scattered ions / radicals 142 do not bounce off (e.g., are not reflected) from the surface (e.g., the sidewalls of the gate spacer 108) and do not continue to travel toward the bottom of the opening 132. Due to the etching selectivity of the anisotropic etching process, the non-scattered ions / radicals 142 react with and remove certain materials (e.g., Si of the nanostructure 54) without reacting with other materials (e.g., SiN) such as the gate spacer 108, the internal spacer 55, etc. Fig.24AThe "x" marks in the figure show the areas / regions that the non-scattered ions / radicals 142 hit but did not react with (thus removing almost no material). The etching effect of the non-scattered ions / radicals 142 on the lower portion of the opening 132 (e.g., the portion below the nanostructure 54) is symmetrical, so it is not believed that the non-scattered ions / radicals 142 are the cause of the asymmetric sidewall profile of the opening 132.

[0102] Fig. 24B Etching caused by scattered ions / radicals 142 (which refers to ions / radicals 142 that strike the surfaces of various materials and bounce off the surfaces and continue to travel (e.g., toward the bottom of the opening 132)) is shown. For example, the ions / radicals 142 may react with the material of the nanostructures 54 (e.g., Si), but not with the material of the gate spacers 108 (e.g., SiN). Thus, the ions / radicals 142 may bounce off the sidewalls of the gate spacers 108 disposed on the left side of the opening 132 and travel to the lower portion of the opening 132 and react with the material of the fin 90B (or substrate 50) disposed on the right side of the opening 132 (e.g., Si) to remove those materials. Note that the sidewalls of the gate spacers 108 located on the right side of the opening 132 are not exposed, but are covered by a portion 123R of the gate structure 123B, or by a portion 102R of the dummy gate 102 (e.g., polysilicon). The ions / radicals 142 that strike the portion 123R or 102R may react with the material(s) of the portions 123R and 102R (and therefore not be reflected by the portions 123R or 102R), or may be reflected less than the ions / radicals 142 that strike the sidewall of the gate spacer 108 that is located to the left of the opening 132. As a result, fewer scattered ions / radicals 142 may travel to the lower portion of the opening 132 to etch the material of the fin 90B (or substrate 50) that is disposed to the left of the opening 132. Therefore, the etching effect of the scattered ions / radicals 142 on the lower portion of the opening 132 is asymmetric, which causes one side of the lower portion of the opening 132 to bulge out, thereby causing the sidewall profile of the opening 132 to be asymmetric. Fig. 24B In the example of , a lower segment of the opening 132 has a width W1, which is greater than a width W2 of an adjacent segment of the opening 132. This can be referred to as a "bend condition" of the opening 132. In the illustrated example, the cross-section of the opening 132 having the bend condition is asymmetric. Specifically, one side (e.g., the right side) of the opening 132 protrudes more than the other side and extends below the source / drain region 112 (e.g., extends to directly below the source / drain region 112). Note that the side of the opening 132 having the protrusion is on the same side as the gate spacer 108 (whose sidewalls are covered by portions 123R or 102R).

[0103] The present disclosure ensures that the sidewalls of the gate spacer 108 are exposed and not covered by the remaining portion 123R or 102R of the gate structure by using an isotropic etching process to completely remove the segment 123BM of the gate structure 123. This ensures that the etching effect from the scattered ions / radicals 142 is symmetrical, thereby avoiding an asymmetric sidewall profile of the opening 132, which in turn avoids hindering the formation of the backside via 165 in subsequent processing. As a result, device failure is avoided and production yield is improved. Fig.17A In the example shown in FIG. 1 , due to the etching effect of the scattered ions / radicals 142 , a rounded bottom surface of the opening 132 is formed.

[0104] Reference now Fig.18A and Fig.18B , which shows that in Fig.17A and Fig. 17B After the processing of. Fig.18A and Fig.18B As shown, dielectric material 141 is formed in opening 132 and on hard mask layer 131. Dielectric material 141 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or multiple layers thereof. Dielectric material 141 may be formed using a suitable formation method, such as CVD, PECVD, ALD, etc. In some embodiments, dielectric material 141 includes multiple layers of different dielectric materials. In some embodiments, dielectric material 141 includes multiple layers of the same dielectric material (e.g., SiO or SiN) formed by different formation methods. For example, a layer of dielectric material may be formed by ALD, and then another layer of the same dielectric material may be formed by, for example, CVD to fill opening 132. Dielectric materials formed by ALD may be dense and have improved etching resistance, while dielectric materials formed by CVD may be formed quickly to reduce production time and cost.

[0105] Next, in Fig.19A and Fig.19B In the process, a planarization process, such as CMP, is performed to remove the dielectric material 141 and the hard mask layer 131 from the upper surface of the first ILD 114. The remaining portion of the dielectric material 141 in the opening 132 forms the isolation structure 141. Fig.19C A top view (eg, plan view) of NSFET device 100 is shown. Fig. 13C , for simplicity, Fig.19C Not all features of NSFET device 100 are shown. Fig.19C In the example shown, the isolation structure 141 is disposed between the dielectric plugs 125 along the direction of the cross section AA, and is disposed between the gate spacers 108 of the gate structure 123B along the direction of the cross section BB. Fig.19A and Fig.19B In the illustrated embodiment, the isolation structure 141 and the dielectric plug 125 separate the gate structure 123B into two separate gate structures 123B1 and 123B2 . The isolation structure 141 also reduces leakage current through the source / drain region 112 , the transistor, and the substrate 50 . Fig.19A and Fig.19B An etch stop layer 51 embedded in the substrate 50 is further shown.

[0106] Next, in Fig. 20A and Fig. 20B , a second ILD 145 is formed over the first ILD 114. A source / drain contact 148S is formed to extend through the first ILD 114 and the second ILD 145 to be electrically coupled to the corresponding source / drain region 112. A gate contact 148G is formed to extend through the second ILD 145 to be electrically coupled to the corresponding gate structure 123. The source / drain contact 148S and the gate contact 148G are collectively referred to as a contact 148. In addition, an interconnect structure 158 (also referred to as a front-side interconnect structure 158) is formed over the second ILD 145, which includes a dielectric layer 153 and conductive features (e.g., conductive lines 155 and vias 157) formed in the dielectric layer 153 to interconnect electrical components formed in / on the substrate 50 to form a functional circuit.

[0107] The second ILD 145 may be formed of the same dielectric material as the first ILD 114 using the same formation method. The contact 148 may include a barrier layer 147 (e.g., TiN, TaN, etc.), a seed layer 149 (e.g., Cu), and a fill metal 151 (e.g., copper, tungsten, cobalt, etc.). In some embodiments, the source / drain contacts 148S are formed by: forming a patterned mask layer over the second ILD 145, wherein openings of the patterned mask layer overlie corresponding source / drain regions 112; removing a portion of the second ILD 145 and a portion of the first ILD 114 located below the openings; conformally forming a barrier layer 147 and a seed layer 149 in the openings; and filling the openings with a fill metal 151. The patterned mask layer is then removed, for example, by a CMP process. Note that in Fig. 20AIn the example of FIG. 1 , a portion of the first ILD 114 disposed between the respective sidewalls of the CESL 116 is completely removed so that the barrier layer 147 of the source / drain contact 148S contacts (e.g., physically contacts) the sidewalls of the CESL 116. The illustrated source / drain contact 148S achieves an increased volume and reduced resistance, which improves the electrical performance of the formed device. The dielectric layer 153 of the interconnect structure 158 may be formed of a suitable dielectric material, such as SiO or a low-k dielectric material. The conductive line 155 and the via 157 of the interconnect structure 158 may be formed of a suitable conductive material (e.g., Cu).

[0108] Next, in Fig.21A and Fig. 21B , the interconnect structure 158 is attached to a carrier 161 (e.g., a glass carrier, a ceramic carrier, a wafer, etc.) by, for example, an adhesive layer. Next, a backside thinning process, such as CMP, a grinding process, etc., is performed to thin the NSFET device 100 from the backside of the substrate 50. The backside thinning process may use the etch stop layer 51 to determine when to stop. In the example shown, after the backside thinning process is completed, the substrate 50, the etch stop layer 51, and some portions of the fin 90 are removed. Fig.21A and Fig. 21B , the isolation structure 141 , (the remaining portion of) the fin 90 , and the first ILD 114 have coplanar upper surfaces.

[0109] Next, backside vias 165 are formed to extend through the fins 90B to connect with the corresponding source / drain regions 112. The backside vias 165 may be formed by patterning the fins 90B to form openings, lining the sidewalls of the openings with a barrier layer (e.g., TiN, TaN, etc.), and then filling the openings with a conductive material (e.g., Cu, W, Co, etc.). In some embodiments, the backside vias 165 are formed to connect with the corresponding source regions 112 but not with the drain regions 112, or to connect with the corresponding drain regions 112 but not with the source regions 112. In some embodiments, the backside vias 165 are formed to connect with both the source regions 112 and the drain regions 112.

[0110] Next, a backside interconnect structure 168 is formed over the fin 90B and electrically coupled to the backside via 165. The backside interconnect structure 168 includes a dielectric layer 167 and conductive features, such as conductive lines 169 and vias 163 formed in the dielectric layer 167. As will be readily appreciated by those skilled in the art, Fig.21A and Fig. 21B The number of dielectric layers and conductive features of the front side interconnect structure 158 and the back side interconnect structure 168 shown in are illustrative and not limiting.

[0111] In some embodiments, the conductive line 169 of the backside interconnect structure 168 is configured to provide a reference voltage, a supply voltage (e.g., +3V, +5V, etc.), etc. to the source / drain region 112, and may be referred to as a power rail 169. Advantages may be achieved by placing the power rail on the back side of the resulting semiconductor die rather than on the front side of the semiconductor die. For example, the gate density of the NSFET device and / or the interconnect density of the frontside interconnect structure 158 may be increased. In addition, the back side of the semiconductor die may accommodate a wider power rail, thereby reducing resistance and improving the efficiency of power transmission to the NSFET device. For example, the width of the conductive line 169 may be twice or more the width of the conductive line of the frontside interconnect structure 158. In addition, capacitors such as metal-insulator-metal (MIM) capacitors may be integrated in the backside interconnect structure 168 to form a power circuit and / or stabilize the reference voltage and / or supply voltage in the backside power distribution network, thereby achieving improved performance of the formed device.

[0112] As will be readily appreciated by those skilled in the art, additional processing may be performed to complete the fabrication of the NSFET device. For example, external connectors (e.g., copper pillars, conductive bumps) may be formed to electrically couple to the front interconnect structure 158 and / or the back interconnect structure 168. Slicing may be performed to separate the plurality of NSFET devices into separate devices. The details are not discussed herein.

[0113] The cutting of the gate structure 123 and the nanostructure 54 of the NSFET device 100 is performed after the dummy gate structure is replaced by the replacement gate structure and is referred to as a continuous metal on diffusion edge (CMODE) process (also referred to as a cut metal on diffusion edge (CMODE) process). The continuous polysilicon on diffusion edge (CPODE) process (also referred to as a cut polysilicon on diffusion edge (CPODE) process) will be discussed below for the NSFET device 100A, in which the cutting of the gate structure and the nanostructure is performed on the dummy gate structure before the replacement gate structure is formed.

[0114] Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Figures 32A-32C , Fig.33A and Fig.33B1 is a diagram of a nanostructured field effect transistor (NSFET) device 100A at various stages of fabrication according to another embodiment. The formation process of the NSFET device 100A has many similarities to the formation process of the NSFET device 100. For simplicity, the discussion below focuses on the differences, and the details of the composition and formation methods of some materials (or features) discussed above in the context of the NSFET device 100 may not be repeated.

[0115] Fig.25A and Fig.25B The processing in Figures 7A-7C After the processing, the CESL 116 and the first ILD 114 are formed. Fig.25A and Fig.25B In the process, a planarization process, such as CMP, is performed to make the top surfaces of the first ILD 114 and the CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process may also remove the mask 104 on the dummy gate 102 (see Fig. 7A ) and portions of the gate spacers 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gates 102, the gate spacers 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surfaces of the dummy gates 102A, 102B, 102C, and 102D (collectively referred to as the dummy gates 102) are exposed through the first ILD 114.

[0116] Next, if Fig.25B As shown, use the same Fig. 13B The dielectric plug 125 is formed in the dummy gate 102B by the same or similar formation method as discussed above for the dielectric plug 125 in FIG. 1 . A top view of the dielectric plug 125 is shown in FIG. Fig.32C shown. Fig.25B The dielectric plugs 125 in the dummy gate 102B separate into a plurality of separate segments.

[0117] Next, in Fig.26A and Fig.26B In the embodiment of the present invention, a hard mask layer 131 is formed over the first ILD 114. A three-layer etch mask 136 is formed over the hard mask layer 131. An opening 138 is formed in a top photoresist layer 139 of the etch mask 136. Fig.14A similar, Fig.26A The opening 138 in is purposefully formed to have a lateral offset OVS between the central axis 138X of the opening 138 and the central axis 102BX of the dummy gate 102B. In some embodiments, the amount of the lateral offset OVS is the same or similar to that discussed above for the NSFET device 100, so the details are not repeated.

[0118] Next, in Fig.27A and Fig.27B In the embodiment, the opening 138 in the etch mask 136 is transferred to the hard mask layer 131 as the opening 132 in the hard mask layer 132. There is a lateral offset OVS between the central axis 132X of the opening 132 and the central axis 102BX of the dummy gate 102B.

[0119] Next, in Fig.28A and Fig.28B In some embodiments, the isotropic etching process is a wet etching process performed using an etching chemical (e.g., an etching fluid). For example, the etching fluid may include potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethylammonium hydroxide (TMAH), combinations thereof, and the like. As another example, the etching fluid may include hydrogen fluoride (HF), nitric acid (HNO3), combinations thereof, and the like. In some embodiments, the isotropic etching process is a dry etching process (e.g., a plasma etching process) performed using an etching gas including H2, NF3, combinations thereof, and the like. Note that due to the isotropy of the isotropic etching process, the dummy gate 102 below the opening 132 is completely removed, and the sidewalls of the gate spacer 108 are exposed to the opening 132. The isotropic etching process also removes the dummy gate dielectric 97 below the opening 132, such as Fig.28A and Fig.28B shown.

[0120] Next, in Fig.29A and Fig.29B , an anisotropic plasma etching process 143 is performed to remove a portion of the layer stack 92 (including the first semiconductor material 52 (e.g., silicon germanium) and the second semiconductor material 54 (e.g., silicon)) below the opening 132. The details of the anisotropic plasma etching process 143 are the same or similar to those described above and are not repeated here. Note that since the isotropic etching process completely removes the dummy gate, the scattered ions / radicals of the anisotropic plasma etching process 143 have a symmetrical etching effect for deepening the opening 132. Therefore, the opening 132 has a symmetrical sidewall profile.

[0121] Next, in Fig. 30A and Fig. 30B In the embodiment of the present invention, a dielectric material 141 is formed to fill the opening 132. The dielectric material 141 may also be formed on an upper surface of the hard mask layer 131.

[0122] Next, in Fig.31A and Fig.31BIn the process, a planarization process, such as CMP, is performed to remove the dielectric material 141 and the hard mask layer 131 from the upper surface of the first ILD 114. The remaining portion of the dielectric material 141 forms the isolation structure 141.

[0123] Next, in Fig.32A and Fig.32B In the embodiment, the dummy gate 102 and the dummy gate dielectric 97 are replaced with a gate structure 123 using the replacement gate process as described above. The gate structure 123 includes a gate dielectric layer 120 and a gate electrode 122. Fig.32C A top view of NSFET device 100A is shown.

[0124] Next, in Fig.33A and Fig.33B , a second ILD 145 is formed on the first ILD 114. A gate contact 148G is formed to extend through the second ILD 145 to be electrically coupled to the corresponding gate structure 123. A source / drain contact 148S is formed to extend through the first ILD 114 and the second ILD 145 to be electrically coupled to the corresponding source / drain region 112. Next, a front interconnect structure 158 is formed on the second ILD 145 and is electrically coupled to the contacts 148 (e.g., 148G and 148S). Next, the front interconnect structure 158 is attached to the carrier 161. Next, a backside thinning process is performed to thin the NSFET device 100A from the back side of the substrate 50. The backside thinning process may remove portions of the substrate 50 and the fin 90. Next, a backside via 165 is formed to extend through the fin 90B to connect with the corresponding source / drain region 112. Next, backside interconnect structure 168 is formed over fin 90B and electrically coupled to backside via 165. Power rail 169 is formed in backside interconnect structure 168. Additional processing may be performed to complete the fabrication of NSFET device 100A, as will be readily appreciated by those skilled in the art, and the details are not discussed here.

[0125] Fig.34 An example of a fin field effect transistor (FinFET) device 31 according to some embodiments is shown in a three-dimensional view. The FinFET device 31 includes a substrate 50 and a fin 90 protruding above the substrate 50. An isolation region 96 is formed on opposite sides of the fin 90, wherein the fin 90 protrudes above the isolation region 96. A gate dielectric 120 is along the sidewalls of the fin 90 and on the top surface of the fin 90, and a gate 122 is on the gate dielectric 120. Source / drain regions 112 are in the fin 90 and on opposite sides of the gate dielectric 120 and the gate 122. Fig.34Reference cross sections used in the following figures are further shown. Cross section AA extends along the longitudinal axis of the gate 122 of the FinFET 31. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 90 and in the direction of current flow, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and between two adjacent fins 90. Cross section DD is parallel to cross section AA and crosses the source / drain region 112. For clarity, the following figures refer to these reference cross sections.

[0126] Figures 35A-35C , Figures 36A-36D , Figures 37A-37C , Fig.38A , Fig.38B , Fig.39A , Fig.39B , Figures 40A-40C , Fig.41A , Fig.41B , Fig.42A , Fig.42B , Fig.43A , Fig.43B , Fig.44A , Fig.44B , Fig.45A and Fig.45B 1 is a diagram of a fin field effect transistor (FinFET) device 100B at various stages of fabrication according to another embodiment. The method for forming the FinFET device 100B illustrates a CMODE process for a FinFET device. The process for forming the FinFET device 100B has many similarities to the process for forming the NSFET device 100. For simplicity, the discussion below focuses on the differences, and details regarding the composition and formation methods of some materials (or features) discussed above in the context of the NSFET device 100 may not be repeated.

[0127] Fig.35A , Fig.36A , Fig.37A , Fig.38A , Fig.39A , Fig.40A , Fig.41A , Fig.42A , Fig.43A , Fig.44A and Fig.45A Shown along Fig.34 Cross-sectional view of section BB.

[0128] Fig.35B and Fig.36B Shown along Fig.34 Cross-sectional view of section CC. Fig.35C , Fig.36C , Fig.37B , Fig.38B , Fig.39B , Fig.40B , Fig.41B , Fig.42B , Fig.43B , Fig.44B and Fig.45B Shown along Fig.34 Cross-sectional view of section AA. Fig.36D , Fig.37C and Fig.40C A top view of the FinFET device 100B is shown.

[0129] exist Figures 35A-35C In the embodiment of the present invention, a semiconductor fin 90 is formed that protrudes higher than the substrate 50. An STI region 96 is formed on the substrate 50 and on opposite sides of the semiconductor fin 90 (also referred to as the fin 90). A gate structure 123 (e.g., 123A-123D) is formed on the fin 90, the gate structure 123 including a gate dielectric layer 120 (e.g., a high-K dielectric material) and a gate electrode material 122. The gate electrode material 122 is a conductive material such as a metal material or a metal-containing material. In some embodiments, the gate electrode material is or includes a work function metal. Before forming the gate structure 123, an interface layer 119 may be formed on the sidewalls and upper surface of the fin 90, and the interface layer 119 may be, for example, silicon oxide. A gate spacer 108 is formed along opposite sidewalls of the gate structure 123. A source / drain region 112 is formed on the fin 90 and on opposite sides of the gate structure 123. A contact etch stop layer (CESL) 116 is formed over the source / drain regions 112 and along the sidewalls of the gate structure 123. A first ILD 114 (e.g., silicon oxide) is formed over the CELS 116 and around the gate structure 123. The top portion of the first ILD 114 is replaced by a dielectric cap layer 115 (e.g., SiN), which can protect the first ILD 114 from subsequent etching processes.

[0130] like Fig.35B and Fig.35C As shown, dummy fins 95 are formed on STI regions 96 between fins 90. Dummy fins 95 are electrically isolated and may be formed of a suitable dielectric material, such as silicon oxide, silicon nitride, etc. Figures 35A-35B1 , the CESL 116, the gate spacers 108, and the gate structure 123 are recessed relative to the upper surface of the dielectric capping layer 115. (One or more) etching processes may be performed to recess the CESL 116, the gate spacers 108, and the gate structure 123. Notably, the gate structure 123 is recessed more than the CESL 116 and the gate spacers 108, and thus has a lower upper surface than the CESL 116 and the gate spacers 108. A sacrificial layer 171, which is amorphous silicon (A-Si) in the illustrated embodiment, is formed over the gate structure 123 and fills the recess created by the recessing of the CESL 116, the gate spacers 108, and the gate structure 123. The sacrificial layer 171 is also formed over the upper surface of the dielectric capping layer 115. Next, a hard mask layer 173 (e.g., SiN) is formed over the sacrificial layer 171.

[0131] Fig.36D A top view (eg, plan view) of the FinFET device 100B is shown. Fig.35A , Fig.35B and Fig.35C They are shown respectively Fig.36D A cross-sectional view along sections BB, CC and AA in FIG. Figures 35A-35C The process steps for the various structures shown in FIG. 1 (eg, fin 90, STI region 96, gate structure 123) are known in the art. A person skilled in the art will be able to readily adjust the process steps for NSFET device 100 to form a device having the same Figures 35A-35C In addition or alternatively, the same or similar processing steps as those in U.S. Pat. No. 10,504,782 may be used to form Figures 35A-35C Various structures shown. U.S. Patent No. 10,504,782 is incorporated herein by reference.

[0132] Next, in Figures 36A-36C In the embodiment of the present invention, a dielectric plug 125 is formed to cut each of the gate structures 123B and 123C into a plurality of separated segments. The dielectric plug 125 is formed above (e.g., directly above) the dummy fins 95A and 95B. Each dielectric plug 125 extends continuously from the gate structure 123B to the gate structure 123C. The dielectric plug 125 is formed by etching the hard mask layer 173 to form an opening at the location of the dielectric plug, and then filling the opening with a dielectric material (e.g., SiN). In some embodiments, the material of the dielectric plug 125 (e.g., SiN) and the material of the hard mask layer 173 are the same material. Therefore, the material of the dielectric plug 125 disposed above the upper surface of the hard mask layer 173 and the hard mask layer 173 are collectively referred to as the hard mask layer 175.

[0133] Fig.36DFIG. 1 shows a top view (eg, plan view) of the FinFET device 100B after forming the dielectric plug 125. For simplicity, not all features of the FinFET device 100B are shown. Fig.36D For example, Fig.36D Only fins 90A, 90B, 90C and 90D (collectively referred to as fins 90), dummy fins 95A, 95B and 95C (collectively referred to as dummy fins 95), gate structures 123A, 123B, 123C and 123D (collectively referred to as gate structures 123), gate spacers 108 surrounding the sidewalls of the gate structures 123, and dielectric plugs 125 are shown.

[0134] Next, in Fig.37A and Fig.37B In the embodiment of the present invention, a three-layer etch mask 136 is formed on the hard mask layer 175. An opening 138 is formed in the etch mask 136. As described below, the opening 138 is transferred to the hard mask layer 175, thereby defining the opening 132 (see Fig.38A and Fig.38B ) in the hard mask layer 175. The opening 132 in the hard mask layer 175 exposes the gate structure 123B at Fig.36D The section 123BM (see Fig.36D ).exist Fig.37A In the example of FIG. 1 , the opening 138 has a lateral offset OVS between the central axis 138X of the opening 138 and the central axis 123BX of the gate structure 123B (also as shown in FIG. 1 ). Fig.37C shown). Fig.37C FIG. 1 shows a top view of a FinFET device 100B in one embodiment. For clarity, Fig.37C Only the boundary of the opening 138 (shown as a rectangle), the central axis 138X of the opening 138, the boundary of the segment 123BM of the gate structure 123B (shown as a dashed rectangle), and the central axis 123BX of the gate structure 123B are shown. Note that the central axis 123BX is the longitudinal central axis of the gate structure 123B. In addition to the lateral offset, Fig.37C The dotted rectangle and the rectangle in FIG. 1 are identical. The lateral offset OVS between the center axis 138X and the center axis 123BX is shown in FIG. Fig.37C In some embodiments, since the opening 138 is transferred to the hard mask layer 175 as the opening 132, the rectangle of the opening 138 also shows the opening 132 in the hard mask 175. Fig.37C As shown, the opening 138 (or the opening 132 ) is formed to be laterally shifted by a predetermined distance (eg, laterally offset OVS) relative to the segment 123BM of the gate structure 123B. As described above, the laterally offset OVS is used to reduce or avoid the photoresist stripping problem.

[0135] refer to Figures 37A-37C , denoting the width of the opening 138 as WO, in some embodiments, the lateral offset OVS is between about 5% and about 33% of the width WO of the opening 138, such as between about 15% and about 30%. Fig.37A Also shown is a width WG of the gate structure 123B, which is measured between the gate spacers 108 on opposite sides of the gate structure 123B. In some embodiments, the width WO of the opening 138 is the same as or similar to the width WG of the gate structure 123B.

[0136] Next, in Fig.38A and Fig.38B In the embodiment of the present invention, an anisotropic etching process is used to transfer the opening 138 of the etching mask 136 to the hard mask layer 175 as the opening 132. Next, a suitable etching process (e.g., a dry etching process using an etching gas selective to the material (a-Si) of the sacrificial layer 171) is performed to remove the sacrificial layer 171 below the opening 132, thereby extending the opening 132 deeper into the FinFET device 100B to expose the segment 123BM of the gate structure 123B. The dry etching process can be an anisotropic etching process.

[0137] Next, in Fig.39A and Fig.39B In the embodiment of the present invention, an isotropic etching process is performed to remove (e.g., completely remove) the exposed segment 123BM of the gate structure 123B. The isotropic etching process can be the same process as the wet etching process or dry etching process performed to remove the exposed segment 123BM of the gate structure 123B of the NSFET device 100, so the details are not repeated here. The advantages of using an isotropic etching process to remove the segment 123BM of the gate structure 123 are discussed above (e.g., avoiding asymmetric etching from scattered ions / radicals), so they are not repeated here.

[0138] Next, an anisotropic etching process 143 is performed to remove the portion of the fin 90 below the opening 132. In some embodiments, the anisotropic etching process 143 is the same as the plasma dry etching process 143 performed above for the NSFET device 100, so the details are not repeated. The anisotropic etching process 143 may include multiple etching cycles, each etching cycle including three etching steps: 1) a deposition step for forming a passivation layer; 2) a penetration step for removing the passivation layer from the etching front; and 3) an anisotropic etching step, wherein the plasma dry etching process 143 is performed to remove a portion of the fin 90 and deepen the opening 132. The details are the same or similar to those described above, so they are not repeated. Fig.39A and Fig.39B In the example shown in FIG. 5 , the opening 132 extends through the fin 90 and into the substrate 50 .

[0139] like Fig.39B As shown, due to the etch selectivity of anisotropic etch process 143, portions of fins 90A and 90B beneath opening 132 are removed, while STI region 96 remains substantially intact. The removal of portions of fins 90A and 90B results in two protrusions 132P of opening 132 extending through STI region 96 into substrate 50.

[0140] Next, in Fig.40A and Fig.40B In the process, a dielectric material 141 is formed in the opening 132 and on the hard mask layer 175. Next, a planarization process, such as CMP, is performed to remove the hard mask layer 175 and excess portions of the dielectric material 141 from the upper surface of the dielectric cap layer 115. The remaining portion of the dielectric material 141 in the opening 132 forms an isolation structure 141. Fig.40C FIG. 1 shows a top view of the FinFET device 100B. Fig.40C As shown, the isolation structure 141 is disposed between the dielectric plugs 125 and between the gate spacers 108 of the gate structure 123B.

[0141] Next, in Fig.41A and Fig.41B In the embodiment of the present invention, the sacrificial layer 171 is removed. A selective etching process using an etchant selective to the material of the sacrificial layer 171 (eg, a-Si) may be performed to remove the sacrificial layer 171. A recess 172 is formed at the location of the removed sacrificial layer 171 in the first ILD 114. The recess 172 exposes the gate structure 123 below.

[0142] Next, in Fig.42A and Fig.42B In the embodiment of the present invention, a dielectric material 179 (e.g., SiN) is formed to fill the recess 172. The dielectric material 179 may overfill the recess 172 and cover the upper surface of the dielectric cap layer 115. Next, a planarization process, such as CMP, is performed to remove the dielectric cap layer 115 from the upper surface of the first ILD 114 and remove excess portions of the dielectric material 179. The remaining portion of the dielectric material 179 in the recess 172 forms a gate mask 179 in a self-aligned manner.

[0143] Next, in Fig.43A and Fig.43BIn the process, some portions of the first ILD 114 are removed, for example, by a selective etching process performed using an etchant that is selective to the material (e.g., SiO) of the first ILD 114. Before the selective etching process, an etching mask may be formed over the first ILD 114. The etching mask exposes those portions of the first ILD 114 to be removed, which may be directly over the source / drain regions 112. After the selective etching process is completed, a recess 180 is formed over the source / drain regions 112.

[0144] Next, in Fig.44A and Fig.44B In the embodiment, source / drain contacts 181 are formed in a self-aligned manner by filling the recess 180 with a conductive material (e.g., W, Co, Cu, etc.) and then performing a planarization process to remove excess portions of the conductive material from the upper surface of the gate mask 179. Before the recess 180 is filled with a conductive material, a barrier material (e.g., TiN, TaN) may be formed to line the sidewalls and bottom of the recess 180.

[0145] Next, in Fig.45A and Fig.45B , a second ILD 145 is formed on a gate mask 179. A gate contact 148G is formed to extend through the second ILD 145 and the gate mask 179 to be electrically coupled to a corresponding gate structure 123. Vias and conductive lines are formed in the second ILD 145 to be electrically coupled to corresponding source / drain contacts 181. Next, a front interconnect structure 158 is formed on the second ILD 145 and electrically coupled to conductive features (e.g., vias and conductive lines) in the second ILD 145 and the gate contact 148G. Next, the front interconnect structure 158 is attached to the carrier 161. Next, a backside thinning process is performed to thin the FinFET device 100B from the back side of the substrate 50. The backside thinning process may remove portions of the substrate 50 and the fin 90. Next, a backside via 165 is formed to extend through the fin 90 to connect to the corresponding source / drain region 112. Next, a backside interconnect structure 168 electrically coupled to the backside via 165 is formed over the fin 90. A power rail 169 is formed in the backside interconnect structure 168. Additional processing may be performed to complete the fabrication of the FinFET device 100B, as will be readily appreciated by those skilled in the art, and the details are not discussed herein.

[0146] Embodiments can achieve advantages. By purposefully shifting the position of the opening 138 in the photoresist layer 139, the photoresist stripping problem is avoided. However, if the remaining portion of the gate structure covers the sidewall of the gate spacer 108, shifting the position of the opening 138 may result in an asymmetric sidewall profile of the opening 132. The present disclosure avoids the asymmetric sidewall profile problem by using an isotropic etching process that completely removes the gate structure (e.g., 123 or 102) and ensures that the scattered ions / radicals from the subsequent anisotropic plasma etching process have a symmetrical effect on deepening the opening 132. Since the asymmetric sidewall profile of the opening 132 may interfere with the formation of the back via 165, the disclosed embodiments achieve a symmetric sidewall profile of the opening 132, thereby reducing device failures and improving production yields.

[0147] Fig.46A and Fig.46B 1 and 2 show a flow chart of a method 1000 for forming a semiconductor device according to some embodiments. It should be understood that Fig.46A and Fig.46B The embodiment methods shown are only examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, deletions, substitutions, rearrangements, or repetitions may be made. Fig.46A and Fig.46B The various steps shown in .

[0148] refer to Fig.46A and Fig.46B , at block 1010, a gate structure is formed over the fin. At block 1020, an interlayer dielectric (ILD) layer is formed over the fin and around the gate structure. At block 1030, a first dielectric plug and a second dielectric plug are formed on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other. At block 1040, a patterned mask layer is formed over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure between the first dielectric plug and the second dielectric plug. At block 1050, using the patterned mask layer as an etching mask, a segment of the gate structure is etched using an isotropic etching process to form a recess in the gate structure. At block 1060, the recess is extended into the fin, wherein extending the recess includes performing an anisotropic etching process. At block 1070, after extending the recess, the recess is filled with a dielectric material.

[0149] In one embodiment, a method of forming a semiconductor device includes: forming a first fin, a second fin, and a third fin, the first fin, the second fin, and the third fin protruding higher than a substrate and extending parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure on the first fin, the second fin, and the third fin; forming a gate spacer along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer on the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug separating the gate structure into a plurality of sections, wherein the first dielectric plug is formed between the first fin and the third fin , and a second dielectric plug is formed between the third fin and the second fin; forming a patterned mask layer over the ILD layer, wherein a first opening of the patterned mask layer exposes a first segment of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing an isotropic etching process using the patterned mask layer as an etching mask, wherein the isotropic etching process removes the first segment of the gate structure and forms a recess between the gate spacers; after performing the isotropic etching process, performing an anisotropic etching process to deepen the recess, wherein after the anisotropic etching process, the recess extends through the third fin; and after performing the anisotropic etching process, filling the recess with a dielectric material. In one embodiment, the first opening of the patterned mask layer is formed to have a lateral offset relative to a longitudinal center axis of the gate structure. In one embodiment, the lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers. In one embodiment, forming a patterned mask layer includes: forming a mask layer on the ILD layer; forming a patterned photoresist layer having a second opening on the mask layer, wherein a third central axis of the second opening of the patterned photoresist layer is laterally offset from a longitudinal central axis of the gate structure by a predetermined amount; and patterning the mask layer using the patterned photoresist layer to form a patterned mask layer, wherein the second opening of the patterned photoresist layer is transferred to the mask layer as a first opening of the patterned mask layer by the patterned mask layer. In one embodiment, the predetermined amount is equal to the value of the lateral offset. In one embodiment, the isotropic etching process is a wet etching process performed using an etching fluid or a dry etching process performed using an etching gas, wherein the anisotropic etching process is a plasma etching process. In one embodiment, the anisotropic etching process includes a plurality of etching cycles, wherein each of the plurality of etching cycles is performed by: lining a sidewall and a bottom of the recess with a passivation layer; removing the passivation layer from the bottom of the recess by performing a first anisotropic plasma etching process; and after removing the passivation layer from the bottom of the recess, performing a second anisotropic plasma etching process different from the first anisotropic plasma etching process to deepen the recess. In one embodiment, after the anisotropic etching process, a lower portion of the recess extends through the third fin and into the substrate.In one embodiment, the gate structure is a dummy gate structure, wherein after filling the recess, the method further comprises: removing the patterned mask layer; and replacing the first segment of the dummy gate structure and the second segment of the dummy gate structure with a first replacement gate structure and a second replacement gate structure, respectively, wherein the first segment of the dummy gate structure overlies the first fin, and the second segment of the dummy gate structure overlies the second fin. In one embodiment, the method further comprises after filling the recess: forming a front interconnect structure electrically coupled to the gate structure over the gate structure; bonding the front interconnect structure to a carrier; after bonding, performing a backside thinning process to remove the substrate and portions of the first fin, the second fin, and the third fin; after the backside thinning process, forming a backside via extending through the second fin, wherein the backside via is electrically coupled to a source / drain region adjacent to the gate structure; and after forming the backside via, forming a backside interconnect structure electrically coupled to the backside via over the backside via. In one embodiment, the backside interconnect structure includes a conductive line configured to provide a supply voltage to the source / drain region, wherein a width of the conductive line is at least twice a width of the conductive line in the frontside interconnect structure.

[0150] In one embodiment, a method for forming a semiconductor device includes: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a segment of the gate structure between the first dielectric plug and the second dielectric plug; using the patterned mask layer as an etching mask, etching the segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess includes performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material. In one embodiment, extending the recess includes performing a plurality of etching cycles using a patterned mask layer as an etching mask, wherein each of the plurality of etching cycles is performed by: lining the sidewalls and the bottom of the recess with a passivation layer; after the lining, removing the passivation layer from the bottom of the recess; and after removing the passivation layer from the bottom of the recess, performing an anisotropic plasma etching process to deepen the recess. In one embodiment, the isotropic etching process is a wet etching process, and the anisotropic etching process is an anisotropic plasma etching process. In one embodiment, forming the patterned mask layer includes: forming the mask layer over the ILD layer; determining a position of the mask layer for forming an opening, wherein the position causes a lateral offset between a central axis of the opening and a longitudinal central axis of the gate structure, wherein the lateral offset is greater than a predetermined distance; and forming the opening at the position of the mask layer to form the patterned mask layer. In one embodiment, the predetermined distance is between about 5% and about 33% of the width of the gate structure.

[0151] In one embodiment, a method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug separate the gate structure into a plurality of segments; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a first segment of the gate structure between the first dielectric plug and the second dielectric plug, wherein the opening of the patterned mask layer is formed to be laterally displaced a predetermined distance relative to the first segment of the gate structure, wherein, in a top view, there is a lateral offset between a longitudinal axis of the gate structure and a central axis of the opening; etching the first segment of the gate structure using an isotropic etching process using the patterned mask layer as an etching mask to form a recess in the gate structure; after etching, deepening the recess by performing an anisotropic etching process; and after deepening the recess, filling the recess with a dielectric material. In one embodiment, the opening of the gate structure exposes a first portion of the first segment of the gate structure and covers a second portion of the first segment of the gate structure. In one embodiment, the isotropic etching process is a wet etching process, and the anisotropic etching process is an anisotropic plasma etching process. In one embodiment, the method further includes, after filling the recess: forming a front interconnect structure electrically coupled to the gate structure over the gate structure; bonding the front interconnect structure to the carrier; after bonding, forming a back via extending through the fin, wherein the back via is electrically coupled to a source / drain region adjacent to the gate structure; and after forming the back via, forming a back interconnect structure electrically coupled to the back via over the back via.

[0152] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a first fin, a second fin, and a third fin, wherein the first fin, the second fin, and the third fin protrude higher than the substrate and extend parallel to each other, wherein the third fin is between the first fin and the second fin; forming a gate structure on the first fin, the second fin, and the third fin; forming gate spacers along opposite sidewalls of the gate structure; forming an interlayer dielectric (ILD) layer over the first fin, the second fin, and the third fin and around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure, the first dielectric plug and the second dielectric plug dividing the gate structure into a plurality of sections, wherein the first dielectric plug is formed between the first fin and the third fin, and the second dielectric plug is formed between the third fin and the second fin; forming a patterned mask layer over the ILD layer, wherein a first opening of the patterned mask layer exposes a first section of the gate structure disposed between the first dielectric plug and the second dielectric plug; performing an isotropic etching process using the patterned mask layer as an etching mask, wherein the isotropic etching process removes a first section of the gate structure and forms a recess between the gate spacers; After performing the isotropic etching process, performing an anisotropic etching process to deepen the recess, wherein after the anisotropic etching process, the recess extends through the third fin; and After performing the anisotropic etching process, the recess is filled with a dielectric material.

2. The method according to claim 1, wherein: The first opening of the patterned mask layer is formed to have a lateral offset relative to a longitudinal center axis of the gate structure.

3. The method according to claim 2, wherein: The lateral offset is between about 5% and about 33% of a width of the gate structure measured between the gate spacers.

4. The method according to claim 2, wherein: Forming the patterned mask layer includes: forming a mask layer on the ILD layer; forming a patterned photoresist layer having a second opening over the mask layer, wherein a third central axis of the second opening of the patterned photoresist layer is laterally offset from a longitudinal central axis of the gate structure by a predetermined amount; and The mask layer is patterned using the patterned photoresist layer to form the patterned mask layer, wherein the second opening of the patterned photoresist layer is transferred to the mask layer as a first opening of the patterned mask layer by patterning the mask layer.

5. The method according to claim 4, wherein: The predetermined amount is equal to the value of the lateral offset.

6. The method according to claim 1, wherein: The isotropic etching process is a wet etching process performed using an etching fluid or a dry etching process performed using an etching gas, wherein the anisotropic etching process is a plasma etching process.

7. The method according to claim 6, wherein: The anisotropic etching process includes a plurality of etching cycles, wherein each of the plurality of etching cycles is performed by: lining the sidewalls and bottom of the recess with a passivation layer; removing the passivation layer from the bottom of the recess by performing a first anisotropic plasma etching process; and After removing the passivation layer from the bottom of the recess, a second anisotropic plasma etching process different from the first anisotropic plasma etching process is performed to deepen the recess.

8. The method according to claim 6, wherein: After the anisotropic etching process, a lower portion of the recess extends through the third fin and into the substrate.

9. A method for forming a semiconductor device, the method comprising: forming a gate structure over the fin; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of segments separated from each other; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a section of the gate structure between the first dielectric plug and the second dielectric plug; Using the patterned mask layer as an etching mask, etching a section of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin, wherein extending the recess comprises performing an anisotropic etching process; and After extending the recess, the recess is filled with a dielectric material.

10. A method for forming a semiconductor device, the method comprising: forming a gate structure over the fin protruding above the substrate; forming an interlayer dielectric (ILD) layer over the fin and around the gate structure; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, wherein the first dielectric plug and the second dielectric plug separate the gate structure into a plurality of sections; forming a patterned mask layer over the ILD layer, wherein an opening of the patterned mask layer exposes a first section of the gate structure between the first dielectric plug and the second dielectric plug, wherein the opening of the patterned mask layer is formed to be laterally displaced a predetermined distance relative to the first section of the gate structure, wherein in a top view, there is a lateral offset between a longitudinal axis of the gate structure and a central axis of the opening; Using the patterned mask layer as an etching mask, etching a first section of the gate structure using an isotropic etching process to form a recess in the gate structure; After the etching, deepening the recess by performing an anisotropic etching process; and After deepening the recess, the recess is filled with a dielectric material.

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