Semiconductor device structure, forming method and radio frequency switch

Abstract

The invention relates to a semiconductor device structure, a forming method and a radio frequency switch, the semiconductor device structure comprises a substrate, a gate structure located on the substrate, a first doped region, a second doped region, a third doped region and a fourth doped region, the first doped region, the second doped region, the third doped region and the fourth doped region are located in the substrate, and each of the first doped region and the second doped region comprises at least two sub-doped regions which are distributed side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region close to the gate structure is smaller than the doping concentration of the sub-doped region away from the gate structure. In the embodiment of the invention, while the resistance value of the on-state resistor of the switching device is kept unchanged or reduced, the doping concentration of the sub-doped regions, such as the first sub-doped region and the third sub-doped region, adjacent to the channel is relatively low, and the sub-doped regions and the well region are difficult to form a band-to-band tunneling current or the formed band-to-band tunneling current is relatively low, so that the resistance value of the on-state resistor of the switching device is reduced. And the requirement of high breakdown voltage can be met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device structure, a forming method and a radio frequency switch. Background Art

[0002] RF switches are an analog device widely used in the RF field. RF switches are used as switches for RF signals and are usually used in RF front-end modules. Specific application areas include mobile phones, WiFi, Bluetooth, etc. Common uses include antenna switches, band switches, tuners, etc. Since they are used as switches for RF signals, and RF signals usually have a certain power, RF switches need to meet a certain breakdown voltage.

[0003] As a switch, the RF switch has two working states, one is on and the other is off. When in the on state, the RF switch can be equivalent to a low-resistance metal wire. At this time, the requirements for the RF switch are: the on-resistance is as low as possible to reduce the loss when the RF signal passes through. When in the off state, the RF switch can be equivalent to a capacitor. At this time, the requirements for the RF switch are: the off-state capacitance is as low as possible to reduce the leakage of the RF signal, and at the same time, a certain breakdown voltage (Rreakdown Voltage, BV) must be met to avoid the device being broken down and unable to remain in the off state under a high-power RF signal. Based on the above requirements for RF switches, RF switches are usually made of 2.5V NMOS. The performance requirements for RF switches include high breakdown voltage, low on-resistance, low off-state capacitance, and small area occupied to achieve the same performance.

[0004] However, in actual process manufacturing, after the device architecture is determined, an optional means to improve the BV of the device is to adjust the ion implantation (IMP) of the lightly doped drain (LDD) process. At this time, the high breakdown voltage and low on-resistance of the device are a pair of trade-offs. While increasing the breakdown voltage by adjusting the injection amount through LDD, the on-resistance will also be increased. Therefore, how to increase the BV of the device without increasing the on-resistance is one of the keys to improving the competitiveness of switching devices and is also a problem that needs to be solved. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a semiconductor device structure, a formation method and a radio frequency switch.

[0006] In the first aspect, an embodiment of the present application discloses a semiconductor device structure, including: a substrate; a gate structure located on the substrate; a first doping region, a second doping region, a third doping region and a fourth doping region located in the substrate; the conductivity types corresponding to the first doping region, the second doping region, the third doping region and the fourth doping region are all the same; the first doping region and the third doping region are connected and located on the first side of the gate structure; the first doping region is closer to the gate structure than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region and the fourth doping region are connected and located on the second side of the gate structure; the second doping region is closer to the gate structure than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region; the first doping region and the second doping region each include at least two sub-doping regions distributed side by side; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the gate structure is less than the doping concentration of the sub-doping region far away from the gate structure.

[0007] In a second aspect, an embodiment of the present application discloses a method for forming a semiconductor device structure, the method comprising: providing a substrate; the substrate comprising an area for forming a gate structure; forming a first doping region and a second doping region in the substrate; the first doping region is located on a first side of the area for forming the gate structure; the second doping region is located on a second side of the area for forming the gate structure; wherein the first doping region and the second doping region each comprise at least two sub-doping regions distributed side by side; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the area for forming the gate structure is less than the doping concentration of the sub-doping region far from the area for forming the gate structure; forming a third doping region and a fourth doping region in the substrate; the third doping region is located on a first side of the area for forming the gate structure; the fourth doping region is located on a second side of the area for forming the gate structure; the first doping region and the third doping region are connected; the first doping region is closer to the area for forming the gate structure than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region and the fourth doping region are connected; the second doping region is closer to the area for forming the gate structure than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region.

[0008] In a third aspect, an embodiment of the present application discloses a radio frequency switch, which includes the semiconductor device structure as described above.

[0009] In a fourth aspect, an embodiment of the present application discloses an electronic device, which includes the semiconductor device structure as described above.

[0010] The technical solution provided by the embodiment of the present application has the following technical effects:

[0011] A substrate, a gate structure located on the substrate, a first doping region, a second doping region, a third doping region and a fourth doping region located in the substrate, the first doping region, the second doping region, the third doping region and the fourth doping region having the same conductivity type, the first doping region and the third doping region being connected and located on a first side of the gate structure, the first doping region being closer to the gate structure than the third doping region, the doping concentration of the first doping region being less than the doping concentration of the third doping region, the second doping region and the fourth doping region being connected and located on a second side of the gate structure, the second doping region being closer to the gate structure than the fourth doping region, the doping concentration of the second doping region being less than the doping concentration of the fourth doping region, the first doping region and the second doping region both comprising at least two sub-doping regions distributed side by side, and in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the gate structure is less than the doping concentration of the sub-doping region far from the gate structure. In the embodiment of the present application, while the on-state resistance of the switching device is kept unchanged or reduced, since the doping concentration of the sub-doping regions adjacent to the channel, such as the first sub-doping region and the third sub-doping region, is low, it is difficult to form a band-to-band tunneling current with the well region or the formed band-to-band tunneling current is low, and therefore, the high breakdown voltage requirement can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 1 ;

[0014] Figure 2 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 2 ;

[0015] Figure 3 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 3 ;

[0016] Figure 4 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 4 ;

[0017] Figure 5 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 5 ;

[0018] Figure 6A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 6 ;

[0019] Figure 7 A method for forming a semiconductor device structure provided in an embodiment of the present application is schematically shown Figure 1 ;

[0020] Figure 8 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 7 ;

[0021] Fig. 9 A method for forming a semiconductor device structure provided in an embodiment of the present application is schematically shown Figure 2 ;

[0022] Figures 10 to 15 is a structural schematic diagram of a semiconductor device structure during formation provided by an embodiment of the present application;

[0023] Fig.16 A method for forming a semiconductor device structure provided in an embodiment of the present application is schematically shown Figure 3 ;

[0024] Figures 17 to 19 is a structural schematic diagram of another semiconductor device structure during the formation process provided by an embodiment of the present application;

[0025] Figures 20-22 It is a structural schematic diagram of a process of forming an LDD region in a semiconductor device structure provided by an embodiment of the present application;

[0026] Figures 23 to 25 It is a structural schematic diagram of the formation process of the LDD region in another semiconductor device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0028] It should be noted that the "one embodiment" or "embodiment" referred to in the specification of the embodiment of the present application refers to a specific feature, structure or characteristic that can be included in at least one implementation of the present application. It should be understood that in the specification and claims of the embodiment of the present application and the above-mentioned drawings, the orientation or position relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, in the description of the present embodiment, unless otherwise specified, "plurality" means two or more. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system or product including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0030] In order to make the purpose, technical solution and advantages disclosed in the embodiments of the present application more clearly understood, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not used to limit the embodiments of the present application.

[0031] In the embodiment of the present application, the threshold voltage V t It refers to the gate voltage when a conductive channel is formed between the source and drain of the MOS tube. The subthreshold current refers to the gate voltage V G Below the threshold voltage V t , that is, a tiny leakage current between the source and the drain when in the subthreshold state.

[0032] In the embodiment of the present application, in the ideal current-voltage characteristic of the MOS tube, when the gate voltage V G Less than the threshold voltage V t , the drain current is 0. However, in actual situations, when the gate voltage V G Less than the threshold voltage V t , the MOS tube is in a weak inversion state on the surface (different from the strong inversion state when turned on), and this area is called the subthreshold region. When the MOS tube works in the subthreshold region, although there are carriers in the conductive channel, the concentration is low, so the leakage current is very small at this time, but it is actually not 0. This leakage current is called the subthreshold current.

[0033] In an optional embodiment, the RF switch is made of a 2.5V (volt) NMOS device, but in order to ensure that the on-state resistance of the RF switch is low enough, its gate length is often used to be less than 0.16um, which is much lower than the minimum gate length conventionally used for 2.5V devices. As a result, under the bias condition that the gate voltage Vg and the substrate voltage Vb are both equal to 0V, the off-state current Ioff of the switch device is very high, and the off-state effect on the RF signal cannot be achieved. Moreover, since the RF voltage swing will be coupled to the gate of the device, the voltage on the gate is higher than 0V in actual operation, and the device leakage current is greater. Therefore, in actual applications, the gate voltage Vg and substrate voltage Vb corresponding to the off-state switch usually use a DC bias of -2.5V to reduce the device off-state current Ioff, but when the DC bias of the gate is set to -2.5V, the switch device is in an accumulation state. When using the LDD process, if the LDD injection concentration is too high, obvious gate-induced drain leakage (GIDL) current will be generated due to band-to-band tunneling between the P-type accumulation layer of the channel and the high-concentration N-doped layer of the LDD, which will lead to a lower breakdown voltage BV and fail to meet the requirements of high breakdown voltage and low on-resistance of the RF switch.

[0034] Based on this, Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the semiconductor device structure includes:

[0035] A substrate 10, a gate structure 11 located on the substrate 10, and a first doping region 12, a second doping region 13, a third doping region 14, and a fourth doping region 15 located in the substrate 10. The first doping region 12, the second doping region 13, the third doping region 14, and the fourth doping region 15 have the same conductivity type.

[0036] The first doping region 12 is connected to the third doping region 14, and the first doping region 12 and the third doping region 14 are located on the first side of the gate structure 11. The first doping region 12 is closer to the gate structure 11 than the third doping region 14. The doping concentration of the first doping region 12 is less than the doping concentration of the third doping region 14. The second doping region 13 is connected to the fourth doping region 15, and the second doping region 13 and the fourth doping region 15 are located on the second side of the gate structure 11. The second doping region 13 is closer to the gate structure 11 than the fourth doping region 15. The doping concentration of the second doping region 13 is less than the doping concentration of the fourth doping region 15.

[0037] The first doping region 12 and the second doping region 13 each include at least two sub-doping regions distributed side by side. In the first doping region 12 and / or the second doping region 13 , the doping concentration of the sub-doping region close to the gate structure 11 is less than the doping concentration of the sub-doping region far from the gate structure 11 .

[0038] like Figure 1 As shown, the first doping region 12 may include two sub-doping regions, such as a first sub-doping region 121 close to the gate structure 11 and a second sub-doping region 122 far from the gate structure 11, wherein the doping concentration of the first sub-doping region 121 is less than the doping concentration of the second sub-doping region 122. The second doping region 13 may include two sub-doping regions, such as a third sub-doping region 131 close to the gate structure 11 and a fourth doping region 132 far from the gate structure 11, wherein the doping concentration of the third sub-doping region 131 is less than the doping concentration of the fourth sub-doping region 132.

[0039] In the embodiment of the present application, the substrate 10 mentioned above may be a SOI (Silicon-On-Insulator) substrate.

[0040] Since the RF switch made of the semiconductor device structure involved in the embodiment of the present application adopts a MOS device, such as an NMOS device or a PMOS device. In some possible embodiments, such as in an NMOS device, the conductivity type of the well region of the substrate 10 is different from the conductivity type of the third doping region 14 (the fourth doping region 15, the first doping region 12, and the second doping region 13), the doping example injected into the well region of the substrate 10 is a P-type impurity, and the doping examples injected into the first doping region 12, the second doping region 13, the third doping region 14, and the fourth doping region 15 located in the well region are all N-type impurities. Alternatively, in a PMOS device, the conductivity type of the well region of the substrate 10 is different from the conductivity type of the third doping region 14 (the fourth doping region 15, the first doping region 12, and the second doping region 13), the doping example injected into the well region of the substrate 10 is an N-type impurity, and the doping examples injected into the first doping region 12, the second doping region 13, the third doping region 14, and the fourth doping region 15 located in the well region are all P-type impurities. The following description will be based on NMOS devices. For embodiments related to PMOS devices, please refer to NMOS devices, which will not be described in detail here.

[0041] Optionally, the gate structure 11 includes a gate oxide layer and a polysilicon gate, wherein the gate oxide layer is located between the substrate 10 and the polysilicon gate. The third doping region 14 and the fourth doping region 15 can form a source and a drain respectively, and the first doping region 12 and the second doping region 13 can be considered as LDD regions.

[0042] Above Figure 1 A semiconductor device structure in a non-working state. Figure 2 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 2 , is the semiconductor device structure in working state, such as Figure 2 As shown, in Figure 1 The structural schematic diagram shown also includes a channel 16 shown in the substrate 10 under the gate structure 11. In other words, the first doping region 12 is connected to the third doping region 14, and the first doping region 12 and the third doping region 14 are located on a first side of the channel 16, and the first doping region 12 is closer to the channel 16 than the third doping region 14. The second doping region 13 is connected to the fourth doping region 15, and the second doping region 13 and the fourth doping region 15 are located on a second side of the channel 16, and the second doping region 13 is closer to the channel 16 than the fourth doping region 15.

[0043] As can be seen from the above structure, the two sub-doping regions respectively included in the first doping region 12 or the second doping region 13 can be regarded as a resistor formed by two sub-resistors connected in series, and the doping concentration of the sub-doping region close to the channel 16 is lower than the doping concentration of the sub-doping region far away from the channel 16. In this case, the resistor formed by the two sub-resistors in series can have the same or even lower resistance value as the resistor formed by the LDD region with the same original doping concentration, thereby keeping the resistance value of the on-state resistance of the switching device unchanged or decreasing. At the same time, since the sub-doping regions adjacent to the channel 16, such as the first sub-doping region 121 and the third sub-doping region 131, have a low doping concentration, it is difficult to form a band-to-band tunneling current with the well region or the formed band-to-band tunneling current is low, so the requirement of high breakdown voltage can be achieved.

[0044] In the embodiment of the present application, at least two sub-doping regions included in the first doping region 12 have the same region size, and at least two sub-doping regions included in the second doping region 13 have the same region size.

[0045] In an optional embodiment, the region size refers to the distance of the sub-doped region in a first direction, which may also be referred to as a length, wherein the first direction is parallel to the substrate direction and is the direction in which the gate extends toward the doped region. Figure 3 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 3 ,like Figure 3 As shown, the length L2 of the first sub-doping region 121 included in the first doping region 12 is the same as the length L1 of the second sub-doping region 122 . Similarly, the length of the third sub-doping region 131 included in the second doping region 13 is the same as the length of the fourth sub-doping region 132 .

[0046] In another optional embodiment, the region size refers to the distance in the second direction of the sub-doping region, which may also be referred to as thickness, the second direction being perpendicular to the substrate direction, and the first direction being perpendicular to the second direction. Figure 3 As shown, the thickness of the first sub-doping region 121 included in the first doping region 12 is the same as the thickness of the second sub-doping region 122 . Similarly, the thickness of the third sub-doping region 131 included in the second doping region 13 is the same as the thickness of the fourth sub-doping region 132 .

[0047] In the embodiment of the present application, at least two sub-doping regions included in the first doping region 12 have sub-doping regions of different sizes. Similarly, at least two sub-doping regions included in the second doping region 13 have sub-doping regions of different sizes.

[0048] In an optional embodiment, the region size refers to the distance of the sub-doping region in the first direction, which may also be referred to as the length. Figure 4 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 4 ,like Figure 4As shown, among the at least two sub-doping regions included in the first doping region 12, the area size of the sub-doping region with low doping concentration is larger than the area size of the sub-doping region with high doping concentration, that is, the length of the first sub-doping region 121 is larger than the length of the second sub-doping region 122. Similarly, among the at least two sub-doping regions included in the second doping region 13, the area size of the sub-doping region with low doping concentration is larger than the area size of the sub-doping region with high doping concentration, that is, the length of the third sub-doping region 131 is larger than the length of the fourth sub-doping region 132.

[0049] Alternatively, among the at least two sub-doping regions included in the first doping region 12, the sub-doping region with a low doping concentration has a smaller area size than the sub-doping region with a high doping concentration, that is, the length of the first sub-doping region 121 is smaller than the length of the second sub-doping region 122. Similarly, among the at least two sub-doping regions included in the second doping region 13, the sub-doping region with a low doping concentration has a smaller area size than the sub-doping region with a high doping concentration, that is, the length of the third sub-doping region 131 is smaller than the length of the fourth sub-doping region 132.

[0050] Alternatively, among the at least two sub-doping regions included in the first doping region 12, the area size of the sub-doping region with low doping concentration is larger than the area size of the sub-doping region with high doping concentration, that is, the length of the first sub-doping region 121 is larger than the length of the second sub-doping region 122. Among the at least two sub-doping regions included in the second doping region 13, the area size of the sub-doping region with low doping concentration is smaller than the area size of the sub-doping region with high doping concentration, that is, the length of the third sub-doping region 131 is smaller than the length of the fourth sub-doping region 132.

[0051] In another optional embodiment, the area size refers to the distance in the second direction of the sub-doping region, which can also be called thickness. Among the at least two sub-doping regions included in the first doping region 12, the area size of the sub-doping region with low doping concentration is greater than the area size of the sub-doping region with high doping concentration, that is, the thickness of the first sub-doping region 121 is greater than the thickness of the second sub-doping region 122. Similarly, among the at least two sub-doping regions included in the second doping region 13, the area size of the sub-doping region with low doping concentration is greater than the area size of the sub-doping region with high doping concentration, that is, the thickness of the third sub-doping region 131 is greater than the thickness of the fourth sub-doping region 132.

[0052] Alternatively, among the at least two sub-doping regions included in the first doping region 12, the sub-doping region with a low doping concentration has a smaller area size than the sub-doping region with a high doping concentration, that is, the thickness of the first sub-doping region 121 is smaller than the thickness of the second sub-doping region 122. Similarly, among the at least two sub-doping regions included in the second doping region 13, the sub-doping region with a low doping concentration has a smaller area size than the sub-doping region with a high doping concentration, that is, the thickness of the third sub-doping region 131 is smaller than the thickness of the fourth sub-doping region 132.

[0053] Alternatively, among the at least two sub-doping regions included in the first doping region 12, the sub-doping region with a low doping concentration has a larger area size than the sub-doping region with a high doping concentration, that is, the thickness of the first sub-doping region 121 is greater than the thickness of the second sub-doping region 122. Among the at least two sub-doping regions included in the second doping region 13, the sub-doping region with a low doping concentration has a smaller area size than the sub-doping region with a high doping concentration, that is, the thickness of the third sub-doping region 131 is smaller than the thickness of the fourth sub-doping region 132.

[0054] In the embodiment of the present application, in order to prepare the first doping region 12 and the second doping region 13, when injecting ions, the first doping region 12 and the second doping region 13 are avoided as much as possible to be injected below the gate structure 11 in the substrate 10, and the semiconductor device structure further includes two first retaining walls located on the substrate 10. Similarly, in order to prepare the third doping region 14 and the fourth doping region 15, when injecting ions, the third doping region 14 and the fourth doping region 15 are avoided as much as possible to be injected into the first doping region 12 and the second doping region 13, and the semiconductor device structure further includes two second retaining walls located on the substrate 10.

[0055] Figure 5 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 5 ,like Figure 5 As shown, it includes a first retaining wall 17 and a second retaining wall 18.

[0056] Optional, such as Figure 5 As shown, the two first retaining walls are respectively located on the first side and the second side of the gate structure 11, and the two first retaining walls are respectively contacted and connected with the side surfaces of the first side and the second side of the gate structure 11. Optionally, the side surface of the first side of one of the two first retaining walls 171 is contacted and connected with the side surface of the first side of the gate structure 11, and the side surface of the first side of the other of the two first retaining walls 172 is contacted and connected with the side surface of the second side of the gate structure 11.

[0057] like Figure 5 As shown, the two second retaining walls are respectively located on both sides of the gate structure 11, and are respectively in contact with the side of the first retaining wall. Among them, each first retaining wall is respectively located between each second retaining wall and the gate structure 11, that is, each first retaining wall is respectively located between the second retaining wall and the gate structure that are in contact with the first retaining wall. The two second retaining walls respectively block the first doping region 12 and the second doping region 13. Optionally, the side of the second side of one of the two first retaining walls 171 is in contact with one of the two second retaining walls 181, and the side of the second side of the other of the two first retaining walls 172 is in contact with the other of the two second retaining walls 182.

[0058] Optionally, the first doping region 12 and the second doping region 13 may be formed before forming the gate structure 11. Optionally, the first doping region 12 and the second doping region 13 may be formed after forming the gate structure 11 and the two first retaining walls and before forming the two second retaining walls.

[0059] In the embodiment of the present application, the at least two sub-doping regions included in the first doping region 12 and / or the second doping region 13 may be formed in a variety of ways.

[0060] In some possible embodiments, each of the at least two sub-doping regions included in the first doping region 12 and / or the second doping region 13 is formed by one round of doping. Taking the first doping region 12 as an example, the first sub-doping region 121 may be formed first, and then the second sub-doping region 122 may be formed, so that the first doping region 12 is obtained. Alternatively, the second sub-doping region 122 may be formed first, and then the first sub-doping region 121 may be formed, so that the first doping region 12 is obtained.

[0061] In some other possible embodiments, each of the at least two sub-doping regions included in the first doping region 12 and / or the second doping region 13 is formed by one round of doping or multiple rounds of doping. Taking the first doping region 12 as an example, each sub-doping region is formed by one round of doping or multiple rounds of doping, wherein the doping round number of the sub-doping region with low doping concentration is less than the doping round number of the sub-doping region with high doping concentration.

[0062] In the embodiment of the present application, since the preparation process of the semiconductor device structure is self-aligned, the area of ​​the first overlapping region corresponding to the first doping region 12 and the gate structure 11 is less than or equal to a preset value, and the area of ​​the second overlapping region corresponding to the second doping region 13 and the gate structure 11 is less than or equal to a preset value, and optionally, the preset value may be zero. That is, the ions in the first doping region 12 and the second doping region 13 will not be implanted into the substrate 10 under the gate.

[0063] The above-mentioned embodiment is described with the number of sub-doping regions included in the first doping region 12 and the second doping region 13 being two. In practical applications, in order to meet the high breakdown voltage and low on-resistance of the switching device, the number of sub-doping regions included in the first doping region 12 and the second doping region 13 may be three or more.

[0064] Figure 6 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 6 ,like Figure 6As shown, the first doping region 12 includes three sub-doping regions, wherein the doping concentration of the first sub-doping region 121 is less than the doping concentration of the second sub-doping region 122, and the doping concentration of the second sub-doping region 122 is less than the doping concentration of the fifth sub-doping region 123. The second doping region 13 includes three sub-doping regions, wherein the doping concentration of the third sub-doping region 131 is less than the doping concentration of the fourth sub-doping region 132, and the doping concentration of the fourth sub-doping region 132 is less than the doping concentration of the sixth sub-doping region 133.

[0065] Optionally, in some optional embodiments, the number of sub-doping regions in the first doping region 12 and the second doping region 13 is asymmetric, for example, the first doping region 12 includes two sub-doping regions, and the second doping region 13 includes three sub-doping regions.

[0066] Figure 7 A method for forming a semiconductor device structure according to an exemplary embodiment is shown in FIG. Figure 1 . It should be noted that this specification provides method operation steps as described in the embodiments or flow charts, but more or fewer operation steps may be included based on routine or non-creative work. The order of steps listed in the embodiments is only one way of executing the steps among many orders, and does not represent the only order of execution. When the actual system or product is executed, it can be executed in sequence or in parallel (for example, in a parallel processor or multi-threaded processing environment) according to the method shown in the embodiments or drawings. Specifically, Figure 7 As shown, the flow chart at least includes the following steps S701-S705:

[0067] In step S701 , a substrate is provided; the substrate includes a region where a gate structure is formed.

[0068] Optionally, the substrate includes a well region, and the well region includes a region where a gate structure is formed.

[0069] Figure 8 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 7 ,like Figure 8 As shown, the substrate 10 includes a supporting substrate 101, a buried oxide layer 102 located on the supporting substrate 101, a well region 103, and also includes shallow trench isolations 19 located on both sides of the well region.

[0070] In step S703, a first doping region and a second doping region are formed in the substrate; the first doping region is located on the first side of the region where the gate structure is formed; the second doping region is located on the second side of the region where the gate structure is formed; wherein the first doping region and the second doping region each include at least two sub-doping regions distributed side by side; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the region where the gate structure is formed is less than the doping concentration of the sub-doping region far from the region where the gate structure is formed.

[0071] In step S705, a third doping region and a fourth doping region are formed in the substrate; the third doping region is located on the first side of the region where the gate structure is formed; the fourth doping region is located on the second side of the region where the gate structure is formed; the first doping region and the third doping region are connected; the first doping region is closer to the region where the gate structure is formed than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region and the fourth doping region are connected; the second doping region is closer to the region where the gate structure is formed than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region.

[0072] In the embodiment of the present application, a first doping region and a second doping region are first formed in a well region within a substrate, and then a third doping region and a fourth doping region are formed in the well region within the substrate.

[0073] In the embodiment of the present application, the gate structure may be formed before the first doping region and the second doping region are formed, or after the first doping region and the second doping region are formed.

[0074] First embodiment: the gate structure may be formed before the first doping region and the second doping region are formed.

[0075] Fig. 9 A method for forming a semiconductor device structure according to an exemplary embodiment is shown in FIG. Figure 2 , such as Fig. 9 As shown, including:

[0076] In step S901 , a substrate is provided; the substrate includes a region where a gate structure is formed.

[0077] Fig.10 1 is a schematic diagram of a semiconductor device structure during formation according to an exemplary embodiment. The schematic diagram mainly includes a substrate 10, the substrate 10 includes a supporting substrate 101, an oxide buried layer 102 located on the supporting substrate 101, a well region 103, and also includes shallow trench isolation 19 located on both sides of the well region 103. Figure 1 For the schematic structure formation, please refer to the preparation process of NMOS or PMOS, which will not be repeated here.

[0078] In step S903 , a gate structure is formed on the substrate, and the gate structure is located in a region where the gate structure is to be formed.

[0079] exist Fig.10 A gate structure 11 may be formed on the basis of the substrate 10 shown. Fig.11It is a structural schematic diagram of a semiconductor device structure during formation according to an exemplary embodiment, wherein a gate structure 11 includes a gate oxide layer and a polysilicon gate, wherein the gate oxide layer is located between a substrate 10 and the polysilicon gate. Optionally, a gate oxide layer may be formed first, and then a polysilicon gate may be formed on the gate oxide layer, and then two first retaining walls 17 may be formed on both sides of the gate structure 11, and the two first retaining walls 17 are used to prevent ions from being implanted into the substrate 10 below the gate structure 11 when ions are implanted to form the first doping region 12 and the second doping region 13.

[0080] exist Fig.11 Based on the structure shown, a photoresist may be formed to prepare for ion implantation into the first doping region 12 and the second doping region 13 . Fig.12 is a structural schematic diagram showing a semiconductor device structure during formation according to an exemplary embodiment. Fig.12 As shown, a photoresist is formed above the third doping region 14 and the fourth doping region 15 to prevent ions from being implanted into other regions when implanting ions into the first doping region 12 and the second doping region 13 .

[0081] In step S905, a first doping region and a second doping region are formed in the substrate; the first doping region is located on the first side of the gate structure; the second doping region is located on the second side of the gate structure; wherein the first doping region and the second doping region each include at least two sub-doping regions distributed side by side; the first doping region and / or the second doping region include a sub-doping region close to the gate structure, wherein the doping concentration is less than the doping concentration of the sub-doping region far from the gate structure.

[0082] Fig.13 is a schematic structural diagram showing a process of forming a semiconductor device structure according to an exemplary embodiment. Fig.12 Based on the structure shown, a first doping region 12 and a second doping region 13 may be formed in the substrate 10 by light ion implantation.

[0083] In step S907, a third doping region and a fourth doping region are formed in the substrate; the third doping region is located on the first side of the gate structure; the fourth doping region is located on the second side of the gate structure; the first doping region and the third doping region are connected; the first doping region is closer to the gate structure than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region and the fourth doping region are connected; the second doping region is closer to the gate structure than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region.

[0084] Fig.14 is a schematic structural diagram showing a process of forming a semiconductor device structure according to an exemplary embodiment. Fig.13Based on the structure shown, two second retaining walls 18 can be formed to prevent ions from being implanted into the first doping region 12 and the second doping region 13 in the substrate 10 when the third doping region 14 and the fourth doping region 15 are formed by ion implantation.

[0085] Fig.15 is a schematic structural diagram showing a process of forming a semiconductor device structure according to an exemplary embodiment. Fig.14 Based on the structure shown, the photoresist on the substrate 10 can be removed, and the third doping region 14 and the fourth doping region 15 can be formed in the substrate 10 by ion re-implantation. The third doping region 14 and the fourth doping region 15 can form a source and a drain, respectively, and the first doping region 12 and the second doping region 13 can be considered as LDD regions.

[0086] Second embodiment: the gate structure may be formed after the first doping region and the second doping region are formed, and before the third doping region and the fourth doping region are formed.

[0087] Fig.16 A method for forming a semiconductor device structure according to an exemplary embodiment is shown in FIG. Figure 3 , such as Fig.16 As shown, including:

[0088] In step S1601, a substrate is provided; the substrate includes an area where a gate structure is formed.

[0089] like Fig.10 As shown, the structural schematic diagram mainly includes a substrate 10, and the substrate 10 includes a supporting substrate 101, an oxide buried layer 102 located on the supporting substrate 101, a well region 103, and also includes shallow trench isolations 19 located on both sides of the well region. Figure 1 For the schematic structure formation, please refer to the preparation process of NMOS or PMOS, which will not be repeated here.

[0090] In step S1603, a first doping region and a second doping region are formed in the substrate; the first doping region is located on the first side of the region where the gate structure is formed; the second doping region is located on the second side of the region where the gate structure is formed; wherein the first doping region and the second doping region each include at least two sub-doping regions distributed side by side; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the region where the gate structure is formed is less than the doping concentration of the sub-doping region far from the region where the gate structure is formed.

[0091] exist Fig.10 Based on the structure shown, a photoresist can be formed. Fig.17It is a structural schematic diagram of another semiconductor device structure formation process according to an exemplary embodiment, in which photoresist is formed in the region where the gate structure 11 is formed, above the third doping region 14 and above the fourth doping region 15, so that when ions are implanted into the first doping region 12 and the second doping region 13, they are prevented from being implanted into other regions.

[0092] Fig.18 FIG. 1 is a schematic diagram showing another semiconductor device structure during the formation process according to an exemplary embodiment. Fig.17 Based on the structure shown, Fig.18 As shown, the first doping region 12 and the second doping region 13 may be formed in the substrate 10 by light ion implantation.

[0093] In step S1605 , a gate structure is formed on the substrate, and the gate structure is located in a region where the gate structure is to be formed.

[0094] Fig.19 is a schematic structural diagram showing a process of forming another semiconductor device structure according to an exemplary embodiment. Fig.18 Based on the structure shown, Fig.19 As shown, the photoresist in the area where the gate structure 11 is formed is removed, a gate oxide layer is first formed, and then a polysilicon gate is formed on the gate oxide layer. Subsequently, two first retaining walls 17 are formed on both sides of the gate structure 11. The two first retaining walls 17 are used to prevent ions from being implanted into the substrate 10 below the gate structure 11 when ions are implanted to form the first doping region 12 and the second doping region 13.

[0095] In step S1607, a third doping region and a fourth doping region are formed in the substrate; the third doping region is located on the first side of the region where the gate structure is formed; the fourth doping region is located on the second side of the region where the gate structure is formed; the first doping region and the third doping region are connected; the first doping region is closer to the region where the gate structure is formed than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region and the fourth doping region are connected; the second doping region is closer to the region where the gate structure is formed than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region.

[0096] exist Fig.19 Based on the structure shown, Fig.14 As shown, two second retaining walls 18 may be formed, and the two second retaining walls 18 are used to prevent ions from being implanted into the first doping region 12 and the second doping region 13 in the substrate 10 when the third doping region 14 and the fourth doping region 15 are formed by ion implantation. Fig.15As shown, the photoresist on the substrate 10 is removed, and ion re-implantation is performed to form a third doping region 14 and a fourth doping region 15 in the substrate 10. The third doping region 14 and the fourth doping region 15 can form a source and a drain, respectively, and the first doping region 12 and the second doping region 13 can be considered as LDD regions.

[0097] The following describes the above two forming processes, step S905 ( Fig.12 After that) or step S1603 ( Fig.17 The first doping region 12 and the second doping region 13 are formed by combining two symmetrical sub-doping regions. Fig.17 Similarly, the first doping region 12 and the second doping region 13 include two symmetrical sub-doping regions. Fig.12 The embodiments of the present invention will not be described in detail here.

[0098] In the first embodiment, in the first doping region 12 and the second doping region 13, each sub-doping region is formed by one round of doping.

[0099] Optionally, when the first doping region 12 and the second doping region 13 both include two sub-doping regions, a first sub-doping region 121 in the first doping region 12 and a third sub-doping region 131 in the second doping region 13 are formed by ion implantation of a first concentration into the first preset region and the second preset region.

[0100] Fig. 20 is a schematic structural diagram showing a process of forming an LDD region in a semiconductor device structure according to an exemplary embodiment. Fig.17 On this basis, first, a photoresist can be formed above the third preset region and the fourth preset region, and ions of a first concentration can be implanted into the first preset region and the second preset region to form a first sub-doping region 121 in the first doping region 12 and a third sub-doping region 131 in the second doping region 13.

[0101] Fig.21 FIG. 1 is a schematic diagram showing a structure of a semiconductor device structure in a process of forming an LDD region according to an exemplary embodiment. Fig. 20 On this basis, a photoresist may be formed over the first sub-doping region 121 in the first doping region 12 and the third sub-doping region 131 in the second doping region 13, and the photoresist over the third preset region and the fourth preset region may be removed.

[0102] Fig. 22 FIG. 1 is a schematic diagram showing a structure of a semiconductor device structure in a process of forming an LDD region according to an exemplary embodiment. Fig.21On the basis of the above, ions of the second concentration can be implanted into the third preset region and the fourth preset region to form a second sub-doping region 122 in the first doping region 12 and a fourth sub-doping region 132 in the second doping region 13, wherein the first concentration is less than the second concentration. Since the combination of the first preset region and the third preset region corresponds to the first doping region 12, and the combination of the second preset region and the fourth preset region corresponds to the second doping region 13, the first doping region 12 and the second doping region 13 can be obtained.

[0103] In the second embodiment, in the first doping region 12 and the second doping region 13 , each sub-doping region is formed by one round of doping or multiple rounds of doping.

[0104] Fig.23 FIG. 1 is a schematic diagram of a structure in a process of forming an LDD region in another semiconductor device structure according to an exemplary embodiment. Fig.17 On the basis of, in the case where both the first doping region 12 and the second doping region 13 include two sub-doping regions, as Fig.23 As shown, ions of a first concentration are implanted into a first region corresponding to the first doping region 12 and a second region corresponding to the second doping region 13 .

[0105] Fig.24 FIG. 1 is a schematic structural diagram of another semiconductor device structure in a process of forming an LDD region according to an exemplary embodiment. Fig.24 On the basis of the above, a photoresist is formed on non-third regions in the first region and non-fourth regions in the second region.

[0106] Fig.25 FIG. 1 is a schematic structural diagram of another semiconductor device structure in a process of forming an LDD region according to an exemplary embodiment. Fig.25 On the basis of this, ions of the second concentration are implanted into the third region included in the first region and the fourth region included in the second region to form the first sub-doping region 121 and the second sub-doping region 122 included in the first doping region 12, and the third sub-doping region 131 and the fourth sub-doping region 132 included in the second doping region 13.

[0107] Among them, the first sub-doping region 121 in the first doping region 12 is the non-third region in the first region after ion injection, the second sub-doping region 122 in the first doping region 12 is the third region in the first region after ion injection, the third sub-doping region 131 in the second doping region 13 is the non-fourth region in the second region after ion injection, and the fourth sub-doping region 132 in the second doping region 13 is the fourth region in the second region after ion injection.

[0108] In the embodiment of the present application, the process of forming the semiconductor device structure (including materials, temperature, thickness, etc.) can refer to the process of forming a CMOS tube (NMOS tube or PMOS tube) in the prior art, and will not be repeated here.

[0109] It should be noted that the method provided in the above embodiment belongs to the same concept as the structural embodiment, and its specific implementation process is detailed in the structural embodiment, which will not be repeated here.

[0110] Correspondingly, an embodiment of the present application further provides a radio frequency switch, which includes the above-mentioned semiconductor device structure.

[0111] Correspondingly, an embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device structure.

[0112] The electronic device described in the embodiments of the present application may be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or any intermediate product including the above-mentioned storage device.

[0113] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0115] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor device structure, characterized in that: include: substrate; a gate structure located on the substrate; a first doping region, a second doping region, a third doping region and a fourth doping region located in the substrate; The first doping region, the second doping region, the third doping region and the fourth doping region all have the same conductivity type; The first doped region is connected to the third doped region and is located on a first side of the gate structure; The first doping region is closer to the gate structure than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; The second doping region is connected to the fourth doping region and is located on the second side of the gate structure; the second doping region is closer to the gate structure than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region; The first doping region and the second doping region each include at least two sub-doping regions distributed side by side; the doping concentration of the sub-doping region close to the gate structure in the first doping region and / or the second doping region is less than the doping concentration of the sub-doping region far from the gate structure.

2. The semiconductor device structure according to claim 1, characterized in that: The at least two sub-doping regions included in the first doping region have the same region size; The second doping region includes at least two sub-doping regions with the same area size.

3. The semiconductor device structure according to claim 1, characterized in that: Among the at least two sub-doping regions included in the first doping region, the sub-doping region with a low doping concentration has a larger area size than the sub-doping region with a high doping concentration; Among the at least two sub-doping regions included in the second doping region, the sub-doping region with a low doping concentration has a larger area size than the sub-doping region with a high doping concentration.

4. The semiconductor device structure according to any one of claims 1 to 3, characterized in that: Also included are two first retaining walls located on the substrate; The two first blocking walls are respectively located at the first side and the second side of the gate structure, and are respectively in contact with and connected to the side surfaces of the first side and the second side of the gate structure.

5. The semiconductor device structure according to claim 4, characterized in that: It also includes two second blocking walls located on the substrate and respectively shielding the first doping region and the second doping region; The two second retaining walls are respectively located on both sides of the gate structure and are respectively in contact with and connected to the side surfaces of the first retaining wall. Each of the first retaining walls is respectively located between each of the second retaining walls and the gate structure.

6. The semiconductor device structure according to any one of claims 1 to 3, characterized in that: An area of ​​a first overlapping region corresponding to the first doping region and the gate structure is less than or equal to a preset value; An area of ​​a second overlapping region corresponding to the second doping region and the gate structure is less than or equal to the preset value.

7. A method for forming a semiconductor device structure, characterized in that: The method comprises: Providing a substrate; the substrate includes an area where a gate structure is formed; A first doping region and a second doping region are formed in the substrate; the first doping region is located on a first side of the region where the gate structure is formed; the second doping region is located on a second side of the region where the gate structure is formed; wherein the first doping region and the second doping region each include at least two sub-doping regions distributed side by side; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the region where the gate structure is formed is less than the doping concentration of the sub-doping region far from the region where the gate structure is formed; A third doping region and a fourth doping region are formed in the substrate; the third doping region is located on a first side of the region where the gate structure is formed; the fourth doping region is located on a second side of the region where the gate structure is formed; the first doping region is connected to the third doping region; the first doping region is closer to the region where the gate structure is formed than the third doping region; the doping concentration of the first doping region is less than the doping concentration of the third doping region; the second doping region is connected to the fourth doping region; the second doping region is closer to the region where the gate structure is formed than the fourth doping region; the doping concentration of the second doping region is less than the doping concentration of the fourth doping region.

8. The method for forming a semiconductor device structure according to claim 7, characterized in that: The forming of the first doping region and the second doping region in the substrate comprises: In the case where both the first doping region and the second doping region include a first sub-doping region and a second sub-doping region, forming a first sub-doping region in the first doping region and a third sub-doping region in the second doping region by implanting ions of a first concentration into the first preset region and the second preset region; Forming a second sub-doping region in the first doping region and a fourth sub-doping region in the second doping region by implanting ions of a second concentration into the third preset region and the fourth preset region; the first concentration is less than the second concentration; The combination of the first preset region and the third preset region corresponds to the first doping region; the combination of the second preset region and the fourth preset region corresponds to the second doping region.

9. The method for forming a semiconductor device structure according to claim 7, wherein: The forming of the first doping region and the second doping region in the substrate comprises: In the case where both the first doping region and the second doping region include a first sub-doping region and a second sub-doping region, ions of a first concentration are implanted into a first region corresponding to the first doping region and a second region corresponding to the second doping region; Implanting ions of a second concentration into a third region included in the first region and a fourth region included in the second region to form a first sub-doping region and a second sub-doping region included in the first doping region and a first sub-doping region and a second sub-doping region included in the second doping region; The first sub-doping region in the first doping region is a non-third region in the first region after ion implantation; the second sub-doping region in the first doping region is a third region in the first region after ion implantation; The third sub-doping region in the second doping region is a non-fourth region in the second region after ion implantation; the fourth sub-doping region in the second doping region is a fourth region in the second region after ion implantation.

10. The method for forming a semiconductor device structure according to claim 7, characterized in that: Before forming the first doping region and the second doping region in the substrate, the method further includes: forming a gate structure on the substrate; the gate structure is located in the region where the gate structure is formed; Wherein, the first doping region is located at a first side of the gate structure; the second doping region is located at a second side of the gate structure; in the first doping region and / or the second doping region, the doping concentration of the sub-doping region close to the gate structure is less than the doping concentration of the sub-doping region far from the gate structure; The third doping region is located on a first side of the gate structure; the fourth doping region is located on a second side of the gate structure; the first doping region is closer to the gate structure than the third doping region; and the second doping region is closer to the gate structure than the fourth doping region.

11. The method for forming a semiconductor device structure according to claim 7, wherein: After forming the first doping region and the second doping region in the substrate, and before forming the third doping region and the fourth doping region in the substrate, the method further includes: forming a gate structure on the substrate; the gate structure is located in the region where the gate structure is formed; Among them, the third doping region is located on the first side of the gate structure; the fourth doping region is located on the second side of the gate structure; the first doping region is closer to the gate structure than the third doping region; and the second doping region is closer to the gate structure than the fourth doping region.

12. The method for forming a semiconductor device structure according to claim 10 or 11, characterized in that: The gate structure includes a gate oxide layer and a polysilicon gate; after the gate structure is formed on the substrate, the method further includes: Two first retaining walls are formed on the substrate at two sides of the gate structure.

13. The method for forming a semiconductor device structure according to claim 12, wherein: Before forming the third doping region and the fourth doping region in the substrate, the method further includes: On the substrate, two second retaining walls are formed outside the two first retaining walls; the two second retaining walls are used to respectively shield the first doping region and the second doping region.

14. A radio frequency switch, characterized in that: The radio frequency switch comprises the semiconductor device structure according to any one of claims 1 to 6.

15. An electronic device, characterized in that: The electronic device comprises the semiconductor device structure according to any one of claims 1 to 6.

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