Thin film transistor and preparation method thereof, array substrate and display device

Abstract

The invention provides a thin film transistor and a preparation method thereof, an array substrate and a display device. The thin film transistor includes: a substrate; the first conductive layer is located on one side of the substrate, and the first conductive layer comprises a grid electrode of a thin film transistor; the first gate insulating layer is positioned on one side, far away from the substrate, of the first conductive layer; the second gate insulating layer is positioned on one side, far away from the substrate, of the first gate insulating layer; the active layer is located on the side, away from the substrate, of the second gate insulating layer and comprises a first pole region, a second pole region and a channel region, the channel region is located between the first pole region and the second pole region, and in the first direction, the surface, close to the substrate, of the channel region and the surface, away from the substrate, of the gate are spaced by a first distance; the surface of the first pole region close to the substrate and the surface of the gate far away from the substrate are spaced by a second distance, the first distance is smaller than the second distance, and the first direction is parallel to the direction of the gate towards the active layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background Art

[0002] Thin Film Transistor (TFT) technology is widely used in display products due to its small size, low power consumption, and no radiation. With the continuous development of display technology, users have higher and higher requirements for refresh rates. In order to meet the requirements of high refresh rates, it is necessary to improve the charging rate of display products. The larger the on-state current of the thin film transistor, the better the effect on the charging rate of the display product. How to increase the on-state current of the thin film transistor is one of the important topics studied by researchers in this field.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In one aspect, a thin film transistor is provided, comprising:

[0005] substrate;

[0006] A first conductive layer, the first conductive layer is located on one side of the substrate, and the first conductive layer includes a gate of a thin film transistor;

[0007] a first gate insulating layer, wherein the first gate insulating layer is located on a side of the first conductive layer away from the substrate;

[0008] a second gate insulating layer, located on a side of the first gate insulating layer away from the substrate; and

[0009] an active layer, the active layer being located on a side of the second gate insulating layer away from the substrate, the active layer comprising a first polar region, a second polar region and a channel region, the channel region being located between the first polar region and the second polar region,

[0010] In which, in a first direction, the surface of the channel region close to the substrate is spaced apart from the surface of the gate away from the substrate by a first distance, the surface of the first polar region close to the substrate is spaced apart from the surface of the gate away from the substrate by a second distance, the first distance is smaller than the second distance, and the first direction is parallel to the direction of the gate toward the active layer.

[0011] According to some exemplary embodiments, in the first direction, a surface of the second polar region close to the substrate is spaced apart from a surface of the gate away from the substrate by a third distance, and the second distance is substantially equal to the third distance.

[0012] According to some exemplary embodiments, the first gate insulating layer includes a first insulating portion and a second insulating portion, an orthographic projection of the first polar region on the substrate at least partially overlaps with an orthographic projection of the first insulating portion on the substrate, and an orthographic projection of the second polar region on the substrate at least partially overlaps with an orthographic projection of the second insulating portion on the substrate; and

[0013] At least a portion of an orthographic projection of the channel region on the substrate falls within a gap region of orthographic projections of both the first insulating portion and the second insulating portion on the substrate.

[0014] According to some exemplary embodiments, the thin film transistor also includes a second conductive layer located on a side of the active layer away from the substrate, the second conductive layer includes a first electrode and a second electrode of the thin film transistor, the orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the first insulating portion on the substrate, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the second insulating portion on the substrate.

[0015] According to some exemplary embodiments, in the second direction, the channel region has a first width, adjacent first insulating portions and second insulating portions are spaced apart by a fourth distance, the first width and the fourth distance are substantially equal, and the second direction is parallel to a direction from the first polar region toward the second polar region.

[0016] According to some exemplary embodiments, an orthographic projection of the first insulating portion on the substrate and an orthographic projection of the first pole on the substrate substantially coincide with each other; and

[0017] An orthographic projection of the second insulating portion on the substrate substantially coincides with an orthographic projection of the second pole on the substrate.

[0018] According to some exemplary embodiments, in the second direction, the channel region has a first width, adjacent first insulating portions and second insulating portions are spaced apart by a fourth distance, the first width is smaller than the fourth distance, and the second direction is parallel to a direction from the first polar region toward the second polar region.

[0019] According to some exemplary embodiments, an orthographic projection of the first insulating portion on the substrate falls within an orthographic projection of the first pole on the substrate; and

[0020] An orthographic projection of the second insulating portion on the substrate falls within an orthographic projection of the second pole on the substrate.

[0021] According to some exemplary embodiments, in the second direction, the channel region has a first width, adjacent first insulating portions and second insulating portions are spaced apart by a fourth distance, the first width is greater than the fourth distance, and the second direction is parallel to a direction from the first polar region toward the second polar region.

[0022] According to some exemplary embodiments, an orthographic projection of the first pole on the substrate falls within an orthographic projection of the first insulating portion on the substrate; and

[0023] An orthographic projection of the second pole on the substrate falls within an orthographic projection of the second insulating portion on the substrate.

[0024] According to some exemplary embodiments, the shape of the orthographic projection of the first pole on the substrate includes a U-shape, the shape of the orthographic projection of the channel region on the substrate includes a U-shape, and the orthographic projection of the channel region on the substrate is half-surrounded by the orthographic projection of the first pole on the substrate.

[0025] According to some exemplary embodiments, a shape of an orthographic projection of the first insulating portion on the substrate includes a U-shape.

[0026] According to some exemplary embodiments, in a first direction, the first insulating portion has a first thickness, the first thickness is in a range of 500 angstroms to 4500 angstroms, and the first direction is parallel to a direction from the gate toward the active layer; and / or, in the first direction, the second gate insulating layer has a second thickness, the second thickness is in a range of 500 angstroms to 5500 angstroms.

[0027] According to some exemplary embodiments, the first gate insulation layer further includes an insulation protection portion, at least a portion of which is located between the first insulation portion and the second insulation portion, and the insulation protection portion has a third thickness in the first direction, and the third thickness is less than the first thickness.

[0028] In another aspect, an array substrate is provided, comprising the thin film transistor as described in any one of the above items.

[0029] According to some exemplary embodiments, the array substrate includes a plurality of pixel units, the array substrate includes a display area and a non-display area, the plurality of pixel units are located in the display area, and the orthographic projection of the first gate insulating layer on the array substrate is spaced apart from the display area; or, the thickness of the first gate insulating layer located in the display area is less than or equal to 1000 angstroms.

[0030] According to some exemplary embodiments, the first conductive layer further includes a first conductive transition portion, the first gate insulating layer further includes a third insulating portion, and an orthographic projection of the third insulating portion on the substrate falls within an orthographic projection of the first conductive transition portion on the substrate; and

[0031] The second conductive layer further includes a second conductive transition portion, and an orthographic projection of the second conductive transition portion on the substrate substantially coincides with an orthographic projection of the third insulating portion on the substrate.

[0032] On the other hand, a display device is provided, comprising the thin film transistor as described in any one of the above items or the array substrate as described in any one of the above items.

[0033] In yet another aspect, a method for preparing a thin film transistor is provided, comprising:

[0034] providing a substrate;

[0035] Forming a first conductive material layer on the substrate, and performing a patterning process on the first conductive material layer to form a first conductive layer, wherein the first conductive layer includes a gate of a thin film transistor;

[0036] forming a first gate insulating material layer on a side of the first conductive layer away from the substrate, and performing a patterning process on the first gate insulating material layer to form a first gate insulating layer;

[0037] forming a second gate insulating layer on a side of the first gate insulating layer away from the substrate; and

[0038] An active material layer is formed on a side of the second gate insulating layer away from the substrate, and a patterning process is performed on the active material layer to form an active layer, wherein the active layer includes a first polar region, a second polar region and a channel region, and the channel region is located between the first polar region and the second polar region.

[0039] In which, in a first direction, the surface of the channel region close to the substrate is spaced apart from the surface of the gate away from the substrate by a first distance, the surface of the first polar region close to the substrate is spaced apart from the surface of the gate away from the substrate by a second distance, the first distance is smaller than the second distance, and the first direction is parallel to the direction of the gate toward the active layer.

[0040] According to some exemplary embodiments, the method further includes: forming a second conductive material layer on a side of the active layer away from the substrate, and performing a patterning process on the second conductive material layer to form a second conductive layer, and the patterning process performed on the first gate insulating material layer and the patterning process performed on the second conductive material layer share the same mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above contents and other purposes, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0042] Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

[0043] Figure 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;

[0044] Figure 3 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure;

[0045] Figure 4 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure;

[0046] Figure 5 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure;

[0047] Figure 6 is along Figure 5 Schematic diagram of the cross section taken along the midline BB';

[0048] Figure 7 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure;

[0049] Figure 8 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure;

[0050] Fig. 9 is along Figure 8 Schematic diagram of the cross section taken along the center line CC';

[0051] Fig.10 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure;

[0052] Fig.11 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure;

[0053] Fig.12 is a schematic structural diagram of a thin film transistor according to some other embodiments of the present disclosure;

[0054] Fig.13 is a schematic structural diagram of a thin film transistor according to some other embodiments of the present disclosure;

[0055] Fig.14 is a schematic plan view of an array substrate according to an embodiment of the present disclosure;

[0056] Fig.15 is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0057] Fig.16 is a structural block diagram of a display device according to an embodiment of the present disclosure;

[0058] Fig.17 is a flow chart of a method for preparing a thin film transistor according to an embodiment of the present disclosure; and

[0059] Figures 18A-18G They are schematic diagrams of the structures of some film layers in the process of preparing a thin film transistor according to an embodiment of the present disclosure.

[0060] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0063] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by ordinary technicians in the field. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0064] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the device, element or component referred to must have a specific orientation, be constructed or operate in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the present disclosure.

[0065] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the substrate, that is, the dimension along the light emitting direction of the array substrate, or the dimension along the normal direction of the display device.

[0066] With the development of display technology, some display products have higher and higher requirements for refresh rate. For example, the refresh rate of some touch display products has developed from 100Hz to 120Hz and 144Hz, and some e-sports display screens have higher refresh rate requirements, such as the refresh rate needs to reach 165Hz, 180Hz or 240Hz. In order to meet the requirements of high refresh rate, it is necessary to improve the charging rate of display products. Usually, display products are driven by thin film transistors. The charging rate of display products is mainly achieved by increasing the on-state current I on to achieve.

[0067] Among them, the on-state current I of the thin film transistor on Satisfies the following formula:

[0068]

[0069] Where W is the channel width of the thin film transistor, L is the channel length of the thin film transistor, μ n is the electron mobility, C i is the capacitance at the channel, V GS is the gate-to-source voltage, V th is the threshold voltage, V ds is the voltage from drain to source.

[0070] The on-state current I of the thin film transistor on The improvement methods mainly include: increasing the channel width W of the thin film transistor, reducing the channel length L of the thin film transistor, and increasing the capacitance C at the channel of the thin film transistor. i .

[0071] In some embodiments, increasing the channel width W of the thin film transistor will cause the area of ​​the thin film transistor to become larger, which may reduce the aperture ratio of the display product when the thin film transistor is applied to the display product. However, the channel length L of the thin film transistor is difficult to be further reduced due to process capability limitations.

[0072] In order to increase the on-state current of a thin film transistor and reduce the influence of the thin film transistor on the aperture ratio of a display product, an embodiment of the present disclosure provides a thin film transistor, which has a capacitance C at a channel of the thin film transistor. i Optimize the design. Specifically, the thin film transistor includes: a substrate; a first conductive layer, the first conductive layer is located on one side of the substrate, and the first conductive layer includes a gate of the thin film transistor; a first gate insulating layer, the first gate insulating layer is located on the side of the first conductive layer away from the substrate; a second gate insulating layer is located on the side of the first gate insulating layer away from the substrate; and an active layer, the active layer is located on the side of the second gate insulating layer away from the substrate, the active layer includes a first polar region, a second polar region and a channel region, and the channel region is located between the first polar region and the second polar region. In the first direction, the surface of the channel region close to the substrate is separated from the surface of the gate away from the substrate by a first distance, the surface of the first polar region close to the substrate is separated from the surface of the gate away from the substrate by a second distance, the first distance is less than the second distance, and the first direction is parallel to the direction of the gate toward the active layer.

[0073] By designing a double-layer gate insulation layer combination and patterning one of the gate insulation layers, on the one hand, the spacing distance between the channel region and the gate can be reduced, thereby increasing the capacitance at the channel, which is beneficial to increasing the on-state current of the thin film transistor. On the other hand, the spacing distance between the source and drain of the thin film transistor and the gate metal layer can be made larger, which is beneficial to reducing the probability of short circuit. It can also ensure that the overlapping capacitance between the source and drain and the gate metal layer fluctuates less, which is beneficial to improving the performance stability of the thin film transistor.

[0074] Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.

[0075] In some embodiments, reference Figure 1 The thin film transistor 100 includes: a substrate 1 and a first conductive layer 2, a gate insulating layer GI, an active layer ACT and a second conductive layer 4 which are sequentially arranged away from the substrate.

[0076] The first conductive layer 2 may include a gate electrode 21 of the thin film transistor. The first conductive layer 2 may also be referred to as a gate metal layer.

[0077] The second conductive layer 4 may include a first electrode 41 and a second electrode 42 of a thin film transistor. Exemplarily, the first electrode 41 is a source electrode of the thin film transistor, and the second electrode 42 is a drain electrode of the thin film transistor; or, the first electrode 41 is a drain electrode of the thin film transistor, and the second electrode 42 is a source electrode of the thin film transistor. The second conductive layer 4 may also be referred to as a source-drain metal layer.

[0078] Exemplarily, the active layer ACT includes a channel region ACT2 , a first polar region ACT1 , and a second polar region ACT3 , and the channel region ACT2 is located between the first polar region ACT1 and the second polar region ACT3 .

[0079] In some embodiments, the channel region ACT2, the first polar region ACT1, and the second polar region ACT3 can achieve functional differentiation by adjusting the type and doping concentration of the doping material in the active layer. For example, the first polar region ACT1 and the second polar region ACT3 can be made conductive by heavy doping, so as to facilitate electrical connection with the source and drain metal layers.

[0080] Exemplarily, the thin film transistor 100 may further include an ohmic contact layer 3 between the active layer ACT and the second conductive layer 4. The ohmic contact layer 3 may include a first ohmic contact portion 31 and a second ohmic contact portion 32.

[0081] Exemplarily, the first pole region ACT1 is electrically connected to the first pole 41 through the ohmic contact layer 3 (eg, the first ohmic contact portion 31 ), and the second pole region ACT3 is electrically connected to the second pole 42 through the ohmic contact layer 3 .

[0082] Exemplarily, the thin film transistor may further include a passivation layer PVX and a third conductive layer 5 located on a side of the second conductive layer 4 away from the substrate 1 .

[0083] In the related art, by reducing the thickness d0 of the gate insulating layer GI, the spacing distance d1 between the channel region ACT2 and the gate 21 is reduced, thereby increasing the capacitance C at the channel of the thin film transistor. i However, when the thickness of the gate insulating layer GI of a thin film transistor with a single-layer gate insulating layer design is reduced, the thickness of the insulating layer between the first conductive layer 2 and the second conductive layer 4 may be reduced, thereby increasing the probability of a short circuit between the first conductive layer and the second conductive layer, affecting the yield of the thin film transistor.

[0084] Exemplarily, referring to Table 1, the inventors have found that when the thickness of the gate insulating layer GI is within a certain range, the thinner the thickness of the gate insulating layer GI is, the greater the probability of short circuit. For example, when the thickness of the gate insulating layer GI is 4000 angstroms, the probability of short circuit between the first conductive layer 2 and the second conductive layer 4 is about 0.66%; when the thickness of the gate insulating layer GI is 3000 angstroms, the probability of short circuit between the first conductive layer 2 and the second conductive layer 4 is about 2.1%; when the thickness of the gate insulating layer GI is 2500 angstroms, the probability of short circuit between the first conductive layer 2 and the second conductive layer 4 is about 10.3%; when the thickness of the gate insulating layer GI is 2000 angstroms, the probability of short circuit between the first conductive layer 2 and the second conductive layer 4 is about 20.6%.

[0085] It can be seen that the thinner the gate insulating layer, the greater the probability of short circuit between the gate metal layer and the source and drain metal layer. In addition, the thinning of the gate insulating layer may also increase the overlap capacitance between the gate metal layer and the source and drain metal layer, resulting in an increase in the load of the thin film transistor. The increase in load requires a higher on-state current I on , which may offset I on The extent of the increase will have an adverse impact on the charging rate of display products.

[0086] Table 1 - Relationship between gate insulation thickness and short circuit probability

[0087] GI film thickness (angstrom) Short circuit probability 4000 0.66％ 3000 2.1％ 2500 10.3％ 2000 20.6％

[0088] In order to increase the capacitance C at the channel of the thin film transistor i , while reducing the overlap capacitance between the gate metal layer and the source and drain metal layer, the embodiment of the present disclosure optimizes the design of the insulating layer between the gate and the source and drain. By adopting the design of a double-layer gate insulating layer, the thickness of the insulating layer under the channel area of ​​the thin film transistor and the thickness of the insulating layer under the source and drain area are designed separately, so that the thickness of the insulating layer under the channel area of ​​the thin film transistor is small, thereby increasing the capacitance C at the channel. i , while ensuring that the thickness of the insulating layer below the source and drain regions is relatively large, the overlapping capacitance between the gate metal layer and the source and drain metal layer can be reduced, which is beneficial to reducing the load of the thin film transistor and improving the yield of the thin film transistor.

[0089] Figure 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.

[0090] For example, in the embodiments of the present disclosure, referring to Figure 2, a thin film transistor 100 is provided. The thin film transistor 100 may include: a substrate 1; a first conductive layer 2, the first conductive layer 2 is located on one side of the substrate 1, and the first conductive layer 2 includes a gate 21 of the thin film transistor; a first gate insulating layer GI1, the first gate insulating layer GI1 is located on a side of the first conductive layer 2 away from the substrate 1; a second gate insulating layer GI2 is located on a side of the first gate insulating layer GI2 away from the substrate 1; and an active layer ACT, the active layer ACT is located on a side of the second gate insulating layer GI2 away from the substrate 1.

[0091] Exemplarily, the active layer ACT includes a first polar region ACT1, a second polar region ACT3, and a channel region ACT2, and the channel region ACT2 is located between the first polar region ACT1 and the second polar region ACT3.

[0092] Exemplarily, in the first direction Z, the surface ACT21 of the channel region ACT2 close to the substrate is separated from the surface 211 of the gate 21 away from the substrate by a first distance d1, the surface ACT11 of the first polar region ACT1 close to the substrate is separated from the surface 211 of the gate 21 away from the substrate by a second distance d2, and the first direction Z is parallel to the direction of the gate 21 toward the active layer ACT.

[0093] Exemplarily, the first distance d1 is smaller than the second distance d2. For example, the first distance d1 is about 2000 angstroms, and the second distance d2 is about 5000 angstroms.

[0094] Exemplarily, the first distance d1 is in the range of 450 angstroms to 4500 angstroms, and the second distance d2 is in the range of 900 angstroms to 10000 angstroms.

[0095] By patterning the first gate insulation layer, the first gate insulation layer under the channel region can be removed, and the first gate insulation layer under the source and drain regions can be retained, so that the first distance d1 between the channel region ACT2 and the first conductive layer 2 and the second distance d2 between the second conductive layer 4 and the first conductive layer 2 can be regulated respectively, so that the first distance d1 is smaller than the second distance d2.

[0096] By such a design, the overall thickness of the insulating layer under the channel region ACT2 can be reduced, thereby reducing the capacitance C at the channel. i , which is beneficial to increase the on-state current of the thin film transistor. At the same time, the overall thickness of the insulating layer between the second conductive layer 4 and the first conductive layer 2 can be thicker, which is beneficial to reduce the probability of short circuit of the thin film transistor. It can also reduce the overlap capacitance between the gate metal layer and the source and drain, which is beneficial to reduce the load of the thin film transistor.

[0097] Exemplarily, in the first direction Z, the surface ACT31 of the second polar region ACT3 close to the substrate is spaced apart from the surface 211 of the gate 21 away from the substrate by a third distance d3. Exemplarily, the second distance d2 and the third distance d3 are substantially equal. It should be noted that “substantially equal” here means that the ratio of the second distance d2 to the third distance d3 is in the range of 0.8 to 1.2.

[0098] Through such a design, the overlapping capacitance between the first electrode 41 (e.g., source) and the first conductive layer 2 can be made substantially consistent with the overlapping capacitance between the second electrode 42 (e.g., drain) and the first conductive layer 2, thereby avoiding the influence of the fluctuation of the overlapping capacitance on the stability of the thin film transistor.

[0099] It should be noted that the “first distance”, “second distance” and “third distance” herein refer to the average spacing distance between the surfaces of two film layers.

[0100] Exemplarily, the material of the first conductive layer 2 may include single-layer or stacked conductive film layers such as molybdenum, molybdenum / aluminum / molybdenum, copper, molybdenum niobide / copper, molybdenum / copper, indium tin oxide / copper, molybdenum / copper / molybdenum nickel titanium, and molybdenum nickel titanium / copper.

[0101] For example, the materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 may be the same or different. For example, the materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 may both be silicon nitride or silicon oxide. For another example, the material of the first gate insulating layer GI1 includes silicon nitride, and the material of the second gate insulating layer GI2 includes silicon oxide.

[0102] By way of example, the material of the active layer ACT may include amorphous silicon a-Si. The first polar region ACT1 and the second polar region ACT3 may be heavily doped to make a portion of the active layer ACT conductive.

[0103] For example, continue to refer to Figure 2 The first gate insulating layer GI1 includes a first insulating portion GI11 and a second insulating portion GI12. The orthographic projection of the first polar region ACT1 on the substrate at least partially overlaps with the orthographic projection of the first insulating portion GI11 on the substrate, and the orthographic projection of the second polar region ACT3 on the substrate at least partially overlaps with the orthographic projection of the second insulating portion GI12 on the substrate.

[0104] The thin film transistor 100 may further include a second conductive layer 4 located on the side of the active layer ACT away from the substrate. The second conductive layer 4 includes a first electrode 41 and a second electrode 42 of the thin film transistor. The first electrode 41 is electrically connected to the first electrode region ACT1, and the second electrode 42 is electrically connected to the second electrode region ACT3.

[0105] Exemplarily, the orthographic projection of the first pole 41 on the substrate at least partially overlaps with the orthographic projection of the first insulating portion GI11 on the substrate, and the orthographic projection of the second pole 42 on the substrate at least partially overlaps with the orthographic projection of the second insulating portion GI12 on the substrate.

[0106] Through such a design, the insulating layer below the first pole region ACT1 and the second pole region ACT3 can include a double-layer structure of the first gate insulating layer GI1 and the second gate insulating layer GI2, so that the spacing distance between the first pole 41 and the second pole 42 and the first conductive layer 2 below can be larger, which is beneficial to reducing the probability of short circuit between the second conductive layer 4 and the first conductive layer 2. At the same time, it can also reduce the overlapping capacitance between the first conductive layer 2 and the source and drain, which is beneficial to reducing the load of the thin film transistor.

[0107] Exemplarily, at least a portion of the orthographic projection of the channel region ACT2 on the substrate falls into the gap region between the orthographic projections of the first insulating portion GI11 and the second insulating portion GI12 on the substrate. For example, the first gate insulating layer GI1 below the channel region ACT2 may be partially etched so that at least a portion of the first gate insulating layer GI1 below the channel region ACT2 is removed.

[0108] Through such a design, the thickness of the insulating layer between the channel region and the gate can be reduced, thereby reducing the capacitance C at the channel. i , which is beneficial to improving the on-state current of the thin film transistor.

[0109] Exemplarily, the thin film transistor may further include an ohmic contact layer 3, which is located on a side of the active layer ACT away from the substrate 1. The ohmic contact layer 3 may form an ohmic contact with the first electrode region ACT1 and the second electrode region ACT3, thereby improving the electrical connection performance between the first electrode region ACT1 and the first electrode 41 and between the second electrode region ACT3 and the second electrode 42.

[0110] In some embodiments, the shape of the orthographic projection of the channel region on the substrate can be any one of a straight-line design, an L-shaped design, or a U-shaped design.

[0111] Figure 3 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure, Figure 4 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure.

[0112] For example, in some embodiments of the present disclosure, Figure 2 It can be based on Figure 3 Schematic diagram of the cross section taken along the midline AA'. Figure 2 and Figure 3In the second direction X, the channel region ACT2 has a first width D1, and the adjacent first insulating portion G111 and second insulating portion GI12 are spaced apart by a fourth distance d4, wherein the second direction X is parallel to the direction from the first polar region ACT1 toward the second polar region ACT3.

[0113] Exemplarily, the first width D1 and the fourth distance d4 are substantially equal. It should be noted that “substantially equal” here means that the ratio between the first width D1 and the fourth distance d4 is in the range of 0.8 to 1.2.

[0114] For example, refer to Figure 4 , the orthographic projection of the first insulating portion GI11 on the substrate and the orthographic projection of the first pole 41 on the substrate basically coincide with each other.

[0115] Exemplarily, an orthographic projection of the second insulating portion GI12 on the substrate and an orthographic projection of the second pole 42 on the substrate substantially coincide with each other.

[0116] Such a design can facilitate the alignment design of the first gate insulating layer and the second conductive layer, and can avoid large offset between the first gate insulating layer and the second conductive layer, thereby avoiding fluctuations in the overlapping capacitance between the gate metal layer and the source and drain metal layer, resulting in poor display.

[0117] In some embodiments, the shape of the orthographic projection of the channel region ACT2 on the substrate includes a U-shape. Figure 3 The shape of the orthographic projection of the first polar region ACT1 on the substrate includes a U-shape, and the shape of the orthographic projection of the second polar region ACT3 on the substrate includes a straight line. The channel region ACT2 includes a portion located between the first polar region ACT1 and the second polar region ACT3.

[0118] Exemplarily, the orthographic projection of the channel region ACT2 on the substrate is half-surrounded by the orthographic projection of the first pole 41 on the substrate.

[0119] Exemplarily, the shape of the orthographic projection of the first insulating portion GI11 on the substrate includes a U-shape.

[0120] Through such a design, the channel width W and the capacitance C of the thin film transistor can be increased at the same time. i , which is beneficial to further improve the on-state current of the thin film transistor.

[0121] Figure 5 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure, Figure 6 is along Figure 5 Schematic diagram of the cross section taken along the midline BB', Figure 7 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure.

[0122] In some embodiments, the trenches between the first gate insulating layers (ie, the spacing between adjacent first insulating portions GI11 and second insulating portions G112) may be further increased. Figure 5-Figure 7 In the second direction X, the channel region ACT2 has a first width D1, the adjacent first insulating portion G111 and the second insulating portion G112 are spaced apart by a fourth distance d4, and the second direction X is parallel to the direction from the first polar region ACT1 toward the second polar region ACT3.

[0123] Exemplarily, the first width D1 is smaller than the fourth distance d4. That is, in some embodiments of the present disclosure, a local area of ​​the first gate insulating layer G11 below the first pole 41 and the second pole 42 may be etched to retain the first gate insulating layer G11 in a partial area below the first pole 41 and the second pole 42, for example Figure 6 The first insulating portion GI11 and the second insulating portion GI12 are shown. Through such a design, the thickness of the insulating layer below the channel region can be thinner, and the thickness of the insulating layer below at least part of the source and drain can be thicker, so that the capacitance at the channel can be reduced, which is beneficial to increase the on-state current of the thin film transistor and reduce the probability of short circuit between the source, drain and gate metal layer.

[0124] Exemplarily, the orthographic projection of the first insulating portion G111 on the substrate falls within the orthographic projection of the first pole 41 on the substrate. Figure 7 The orthographic projection of the first insulating portion GI11 on the substrate is in a U-shape, and the orthographic projection of the first pole 41 on the substrate is also in a U-shape. The orthographic projection of the first insulating portion GI11 on the substrate falls within the orthographic projection of the first pole 41 on the substrate.

[0125] Exemplarily, the orthographic projection of the second insulating portion GI12 on the substrate falls within the orthographic projection of the second pole 42 on the substrate.

[0126] Through such a design, the orthographic projections of the first pole 41 and the second pole 42 located above on the substrate can completely cover the orthographic projections of the first insulating part GI11 and the second insulating part GI12 located below on the substrate. In this way, when there is a certain degree of alignment offset between the second conductive layer 4 and the first insulating layer GI1, the overlapping capacitance between the first pole 41 and the first conductive layer 2 and the overlapping capacitance between the second pole 42 and the first conductive layer 2 are both affected by the offset in the same way, thereby reducing the fluctuation of the overlapping capacitance between the source, drain and gate metal layers, which is beneficial to improving the stability of the thin film transistor.

[0127] Figure 8 is a schematic plan view of a portion of film layers of a thin film transistor according to an embodiment of the present disclosure, Fig. 9 is along Figure 8Schematic diagram of the cross section taken along the center line CC', Fig.10 is a schematic plan view of a first gate insulating layer and a second conductive layer according to an embodiment of the present disclosure.

[0128] In some embodiments, the trenches between the first gate insulating layers (i.e., the spacing between the adjacent first insulating portions GI11 and second insulating portions G112) can be appropriately reduced so that a single-layer gate insulating layer is disposed under a portion of the channel region, and a double-layer gate insulating layer is disposed under another portion of the channel region. This can also reduce the capacitance C at the channel to a certain extent. i , increasing the on-state current of the thin film transistor.

[0129] For example, in conjunction with reference Figure 8-10 In the second direction X, the channel region ACT2 has a first width D1, the adjacent first insulating portion GI11 and the second insulating portion GI12 are spaced apart by a fourth distance d4, and the second direction X is parallel to the direction from the first polar region ACT1 to the second polar region ACT3.

[0130] Exemplarily, the first width D1 is greater than the fourth distance d4. That is, in some embodiments of the present disclosure, a local area of ​​the first gate insulating layer GI1 below the channel area ACT2 may be etched so that the spacing distance between at least a portion of the channel area ACT2 and the first conductive layer 2 is reduced. For example, the spacing distance between at least a portion of the channel area ACT2 and the first conductive layer 2 is less than the spacing distance between the first polar area ACT1 and the first conductive layer 2. Through such a design, the capacitance at the channel can be reduced, which is beneficial to increasing the on-state current of the thin film transistor.

[0131] For example, refer to Fig.10 , the orthographic projection of the first pole 41 on the substrate falls within the orthographic projection of the first insulating portion GI11 on the substrate.

[0132] Exemplarily, the orthographic projection of the second pole 42 on the substrate falls within the orthographic projection of the second insulating portion GI12 on the substrate.

[0133] Through such a design, the orthographic projections of the first electrode 41 and the second electrode 42 located above on the substrate can completely fall within the orthographic projections of the first insulating part GI11 and the second insulating part GI12 located below on the substrate. In this way, when there is a certain degree of alignment offset between the second conductive layer 4 and the first gate insulating layer GI1, the overlapping capacitance between the first electrode 41 and the first conductive layer 2 and the overlapping capacitance between the second electrode 42 and the first conductive layer 2 are both affected by the offset in the same way, thereby reducing the fluctuation of the overlapping capacitance between the source, drain and gate metal layers, which is beneficial to improving the stability of the thin film transistor.

[0134] Exemplarily, in the first direction Z, the first insulating portion GI1 has a first thickness h1, the first thickness h1 is in the range of 500 angstroms to 4500 angstroms, and the first direction Z is parallel to the direction from the gate 21 toward the active layer ACT. For example, the first thickness h1 may be approximately 500 angstroms, 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 4500 angstroms. It should be noted that the first thickness h1 here refers to the average thickness of the first gate insulating layer in the region where the first gate insulating layer is retained, such as the average thickness of the first insulating portion.

[0135] Exemplarily, in the first direction Z, the second gate insulating layer GI2 has a second thickness h2, and the second thickness h2 is in the range of 500 angstroms to 5500 angstroms. For example, the second thickness h2 may be approximately 500 angstroms, 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 5500 angstroms. It should be noted that the second thickness h2 here refers to the average thickness of the second gate insulating layer.

[0136] In some embodiments, a portion of the insulating material in the region between the first insulating portion and the second insulating portion in the first gate insulating layer may be retained. For example, the first insulating portion and the second insulating portion may be protected by photoresist, and then the remaining portion may be etched using an etching technique. By adjusting the etching time, the thickness of the insulating material retained in the remaining portion may be adjusted, so that when the first gate insulating layer is etched, the underlying gate metal layer may be avoided from being exposed, which is beneficial to reducing the probability of a short circuit.

[0137] Fig.11 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.

[0138] For example, Fig.11 The thin film transistor of the embodiment shown in FIG. Figure 2 The thin film transistors of the illustrated embodiments differ in that: Fig.11 In the embodiment shown, the first gate insulating layer GI1 is thinned except for the first insulating portion GI11 and the second insulating portion GI12, but is not completely removed. Fig.11 The first gate insulating layer GI1 further includes an insulating protection portion GI13, at least a portion of which is located between the first insulating portion GI11 and the second insulating portion GI12. The insulating protection portion GI13 has a third thickness h3 in the first direction Z, and the third thickness h3 is less than the first thickness h1.

[0139] It should be noted that the first thickness h1 here refers to the average thickness of the first insulating portion GI1, and the third thickness h3 refers to the average thickness of the insulating protection portion GI13.

[0140] Exemplarily, the insulating protection portion GI13 may further include a portion located on a side of the first insulating portion GI11 away from the second insulating portion GI12 and another portion located on the second insulating portion GI12 away from the first insulating portion GI11 .

[0141] Illustratively, an orthographic projection of the first gate insulating layer GI1 on the substrate substantially overlaps with an orthographic projection of the second gate insulating layer GI2 on the substrate.

[0142] Exemplarily, the third thickness h3 is in the range of 100 angstroms to 1000 angstroms, and the first thickness is in the range of 500 angstroms to 4500 angstroms. For example, the third thickness is about 100 angstroms, and the first thickness is about 3000 angstroms.

[0143] Through such a design, on the one hand, the capacitance at the channel can be reduced and the on-state current can be increased; on the other hand, the insulating protection part can reduce the damage to other film layers during the etching process of the first gate insulating layer, which is beneficial to reduce the probability of short circuit.

[0144] Fig.12 is a schematic structural diagram of a thin film transistor according to some other embodiments of the present disclosure.

[0145] For example, Fig.12 The thin film transistor of the embodiment shown in FIG. Figure 6 The difference between the thin film transistor of the embodiment shown is that the other parts of the first gate insulating layer GI1 except the first insulating portion G111 and the second insulating portion G112 are thinned but not completely removed. Fig.12 , the first gate insulating layer GI1 also includes an insulating protection part GI13, at least a portion of which is located between the first insulating part GI11 and the second insulating part GI12. The insulating protection part GI13 has a third thickness h3 in the first direction Z, and the third thickness h3 is less than the first thickness h1. For example, the third thickness h3 is less than or equal to 1000 angstroms. It should be noted that the first thickness h1 here refers to the average thickness of the first insulating part GI11, and the third thickness h3 refers to the average thickness of the insulating protection part GI13.

[0146] Through such a design, on the one hand, the capacitance at the channel can be reduced and the on-state current can be increased; on the other hand, the insulating protection part can reduce the damage to other film layers during the etching process of the first gate insulating layer, which is beneficial to reduce the probability of short circuit.

[0147] Fig.13 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.

[0148] For example, Fig.13 The thin film transistor of the embodiment shown in FIG. Fig. 9The difference between the thin film transistor of the embodiment shown is that the other parts of the first gate insulating layer GI1 except the first insulating portion GI11 and the second insulating portion GI12 are thinned but not completely removed. Fig.13 The first gate insulating layer GI1 further includes an insulating protection portion GI13, at least a portion of which is located between the first insulating portion GI11 and the second insulating portion GI12. The insulating protection portion GI13 has a third thickness h3 in the first direction Z, and the third thickness h3 is less than the first thickness h1. For example, the third thickness h3 is less than or equal to 1000 angstroms.

[0149] It should be noted that the first thickness h1 here refers to the average thickness of the first insulating portion GI1, and the third thickness h3 refers to the average thickness of the insulating protection portion GI13.

[0150] Illustratively, when etching the first gate insulation layer, a portion of the first gate insulation layer below the channel region can be retained by adjusting the etching time, so that the first gate insulation layer becomes thinner at the channel to form a groove, and at least a portion of the insulating protection portion is located in the groove.

[0151] The gate can be wrapped and protected by a thin first gate insulating layer to prevent the gate metal from being exposed. This design can reduce the capacitance at the channel and increase the on-state current. On the other hand, the insulating protection part can reduce the damage to other film layers during the etching process of the first gate insulating layer, which is conducive to reducing the probability of short circuit.

[0152] Fig.14 is a schematic plan view of an array substrate according to an embodiment of the present disclosure, Fig.15 is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure.

[0153] In some embodiments of the present disclosure, an array substrate 200 is further provided. Fig.14 and Fig.15 , the array substrate 200 may include the thin film transistor 100 as described in any one of the above items.

[0154] For example, the array substrate 200 may include a plurality of pixel units PX arranged in an array, and the pixel units PX include light emitting elements 50. The array substrate 200 may further include a driving circuit layer, and the driving circuit layer includes a plurality of thin film transistors 100.

[0155] Exemplarily, the light emitting element 50 is electrically connected to the thin film transistor 100 , and emits light when driven by the thin film transistor 100 .

[0156] Exemplarily, the array substrate 200 includes a display area AA and a non-display area NA, and a plurality of pixel units PX are located in the display area AA.

[0157] Exemplarily, the orthographic projection of the first gate insulating layer GI1 on the array substrate is spaced apart from the display area AA. That is, in the area (i.e., the light-emitting area) where the picture is displayed on the array substrate, the first gate insulating layer is completely removed, which can reduce the overall thickness of the insulating layer in the display area, which is beneficial to improving the transmittance of the display area.

[0158] In some embodiments, the display area AA may retain a relatively thin first gate insulating layer, for example, the thickness of the first gate insulating layer in the display area is less than or equal to 1000 angstroms. With such a design, it is possible to avoid the first conductive layer in the display area from being exposed during the etching process of the first gate insulating layer, which is beneficial to improving the yield of the array substrate.

[0159] For example, refer to Fig.15 The first conductive layer 2 may further include a first conductive transition portion 22. For example, the first conductive transition portion 22 may be electrically connected to the gate 21 to transmit a control signal (eg, a scanning control signal) to the gate of the thin film transistor.

[0160] Exemplarily, the first gate insulating layer GI1 further includes a third insulating portion GI13 , and an orthographic projection of the third insulating portion GI13 on the substrate falls within an orthographic projection of the first conductive transfer portion 22 on the substrate.

[0161] Exemplarily, the second conductive layer 4 further includes a second conductive transition portion 43. For example, the second conductive transition portion 43 may include a data line, and the data signal may be transmitted to the source and drain of the thin film transistor through the second conductive transition portion 43.

[0162] Exemplarily, an orthographic projection of the second conductive transition portion 43 on the substrate substantially coincides with an orthographic projection of the third insulating portion GI13 on the substrate.

[0163] With such a design, the thickness of the insulating layer between the first conductive layer and the second conductive layer can be ensured to be thicker, thereby reducing the probability of short circuit between the first conductive layer and the second conductive layer, which is beneficial to improving the yield of the array substrate.

[0164] Exemplarily, the array substrate 200 may further include: a passivation layer PVX located on a side of the second conductive layer 4 away from the substrate; and a third conductive layer 5 located on a side of the passivation layer PVX away from the substrate, wherein the third conductive layer 5 includes a third conductive transition portion 51 .

[0165] Exemplarily, the third conductive transition portion 51 may be electrically connected to one of the source and drain electrodes (eg, the second electrode 42 ) of the thin film transistor through an opening in the passivation layer.

[0166] Exemplarily, the material of the third conductive layer 5 includes indium tin oxide.

[0167] Fig.16 is a structural block diagram of a display device according to an embodiment of the present disclosure.

[0168] Exemplarily, an embodiment of the present disclosure further provides a display device. Fig.16 The display device 300 may include the thin film transistor 100 as described in any one of the above items or the array substrate 200 as described in any one of the above items. The display device may include but is not limited to: electronic paper, mobile phones, tablet computers, monitors, notebook computers, digital photo frames, navigators, and any other products or components with display functions. It should be understood that the display device has the same beneficial effects as the thin film transistor or array substrate provided in the above embodiments.

[0169] Fig.17 is a flow chart of a method for preparing a thin film transistor according to an embodiment of the present disclosure, Figures 18A-18G They are schematic diagrams of the structures of some film layers in the process of preparing a thin film transistor according to an embodiment of the present disclosure.

[0170] For example, in conjunction with reference Figure 17-18G The embodiment of the present disclosure provides a method for manufacturing a thin film transistor, wherein the method may include the following steps S01-S06.

[0171] In step S01, a substrate 1 is provided. For example, the substrate 1 includes a glass substrate.

[0172] In step S02, refer to Fig.18A A first conductive material layer is formed on a substrate 1, and a patterning process is performed on the first conductive material layer to form a first conductive layer 2. The first conductive layer 2 includes a gate of a thin film transistor.

[0173] Exemplarily, the material of the first conductive layer 2 may include a single layer or a stacked layer of conductive film layers such as molybdenum, molybdenum / aluminum / molybdenum, copper, molybdenum niobide / copper, molybdenum / copper, indium tin oxide / copper, molybdenum / copper / molybdenum nickel titanium, and molybdenum nickel titanium / copper.

[0174] In step S03, combined with reference Fig.18B and Fig. 18C A first gate insulating material layer is formed on a side of the first conductive layer 2 away from the substrate 1, and a patterning process is performed on the first gate insulating material layer to form a first gate insulating layer GI1. For example, the thickness of the first gate insulating layer GI1 is in the range of 500 angstroms to 4500 angstroms.

[0175] Illustratively, the first gate insulating layer at positions corresponding to the source and drain electrodes may be retained through processes such as exposure and etching.

[0176] In some embodiments, the first gate insulating layer at a position corresponding to the data line may also be retained.

[0177] In step S04, refer to Fig.18D A second gate insulating layer GI2 is formed on a side of the first gate insulating layer GI1 away from the substrate 1. For example, the thickness of the second gate insulating layer GI2 is in a range of 500 angstroms to 5500 angstroms.

[0178] In step S05, combined with reference Figure 2 and Fig.18E An active material layer is formed on the side of the second gate insulating layer GI2 away from the substrate, and a patterning process is performed on the active material layer to form an active layer ACT. The active layer ACT includes a first polar region ACT1, a second polar region ACT3 and a channel region ACT2, and the channel region ACT2 is located between the first polar region ACT1 and the second polar region ACT3.

[0179] Exemplarily, in the first direction Z, the surface ACT21 of the channel region ACT2 close to the substrate 1 is separated from the surface 211 of the gate 21 away from the substrate by a first distance d1, the surface ACT11 of the first polar region ACT1 close to the substrate is separated from the surface 211 of the gate 21 away from the substrate by a second distance d2, the first distance d1 is smaller than the second distance d2, and the first direction Z is parallel to the direction of the gate 21 toward the active layer ACT.

[0180] By using this method, the thickness of the insulating layer below the channel of the thin film transistor can be reduced, thereby increasing the capacitance C at the channel. i , while ensuring that the thickness of the insulating layer below the source and drain regions is relatively large, the overlapping capacitance between the gate metal layer and the source and drain electrodes can be reduced, which is beneficial to reducing the load of the thin film transistor and improving the yield of the thin film transistor.

[0181] In some embodiments, after forming the active layer ACT, an ohmic contact layer 3 may be formed on a side of the active layer ACT away from the substrate 1. For example, the ohmic contact layer 3 includes a first ohmic contact portion 31 and a second ohmic contact portion 32, the first ohmic contact portion 31 forms an ohmic contact with the first polar region ACT1, and the second ohmic contact portion 32 forms an ohmic contact with the second polar region ACT3. By such a method, the electrical connection performance between the source, drain and active layer can be improved, thereby improving the performance of the thin film transistor.

[0182] Exemplarily, the method further comprises step S06: referring to Fig.18F , a second conductive material layer is formed on a side of the active layer ACT away from the substrate 1 , and a patterning process is performed on the second conductive material layer to form a second conductive layer 4 .

[0183] Exemplarily, the material of the second conductive layer 4 may include a single layer or a stacked layer of conductive film layers such as molybdenum, molybdenum / aluminum / molybdenum, copper, molybdenum niobide / copper, molybdenum / copper, indium tin oxide / copper, molybdenum / copper / molybdenum nickel titanium, and molybdenum nickel titanium / copper.

[0184] For example, the patterning process performed on the first gate insulating material layer and the patterning process performed on the second conductive material layer can share the same mask. This method can not only improve the alignment accuracy and avoid large offsets, thereby avoiding fluctuations in the overlap capacitance between the source, drain and gate metal layers to produce display defects, but also save masks and reduce costs.

[0185] In some embodiments, the method for preparing a thin film transistor may further include: forming a passivation layer PVX on a side of the second conductive layer 4 away from the substrate; and forming a third conductive layer 5 on a side of the passivation layer PVX away from the substrate 1 .

[0186] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A thin film transistor, characterized in that: include: substrate; A first conductive layer, the first conductive layer is located on one side of the substrate, and the first conductive layer includes a gate of a thin film transistor; a first gate insulating layer, wherein the first gate insulating layer is located on a side of the first conductive layer away from the substrate; a second gate insulating layer, located on a side of the first gate insulating layer away from the substrate; and an active layer, the active layer being located on a side of the second gate insulating layer away from the substrate, the active layer comprising a first polar region, a second polar region and a channel region, the channel region being located between the first polar region and the second polar region, In which, in a first direction, the surface of the channel region close to the substrate is spaced apart from the surface of the gate away from the substrate by a first distance, the surface of the first polar region close to the substrate is spaced apart from the surface of the gate away from the substrate by a second distance, the first distance is smaller than the second distance, and the first direction is parallel to the direction of the gate toward the active layer.

2. The thin film transistor according to claim 1, wherein: In the first direction, a surface of the second polar region close to the substrate is spaced apart from a surface of the gate away from the substrate by a third distance, and the second distance is substantially equal to the third distance.

3. The thin film transistor according to claim 2, wherein: The first gate insulating layer includes a first insulating portion and a second insulating portion, an orthographic projection of the first polar region on the substrate at least partially overlaps with an orthographic projection of the first insulating portion on the substrate, and an orthographic projection of the second polar region on the substrate at least partially overlaps with an orthographic projection of the second insulating portion on the substrate; as well as At least a portion of an orthographic projection of the channel region on the substrate falls within a gap region of orthographic projections of both the first insulating portion and the second insulating portion on the substrate.

4. The thin film transistor according to claim 3, wherein: The thin film transistor also includes a second conductive layer located on a side of the active layer away from the substrate, the second conductive layer includes a first electrode and a second electrode of the thin film transistor, the orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the first insulating portion on the substrate, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the second insulating portion on the substrate.

5. The thin film transistor according to claim 3 or 4, wherein: In the second direction, the channel region has a first width, the adjacent first insulating parts and the second insulating parts are spaced apart by a fourth distance, the first width and the fourth distance are substantially equal, and the second direction is parallel to the direction from the first polar region toward the second polar region.

6. The thin film transistor according to claim 5, wherein: The orthographic projection of the first insulating portion on the substrate and the orthographic projection of the first pole on the substrate substantially coincide with each other; as well as An orthographic projection of the second insulating portion on the substrate substantially coincides with an orthographic projection of the second pole on the substrate.

7. The thin film transistor according to claim 3 or 4, wherein: In the second direction, the channel region has a first width, the adjacent first insulating parts and the second insulating parts are spaced apart by a fourth distance, the first width is smaller than the fourth distance, and the second direction is parallel to the direction from the first polar region toward the second polar region.

8. The thin film transistor according to claim 7, wherein: The orthographic projection of the first insulating portion on the substrate falls within the orthographic projection of the first pole on the substrate; as well as An orthographic projection of the second insulating portion on the substrate falls within an orthographic projection of the second pole on the substrate.

9. The thin film transistor according to claim 3 or 4, wherein: In the second direction, the channel region has a first width, the adjacent first insulating parts and the second insulating parts are spaced apart by a fourth distance, the first width is greater than the fourth distance, and the second direction is parallel to the direction from the first polar region toward the second polar region.

10. The thin film transistor according to claim 9, wherein: The orthographic projection of the first pole on the substrate falls within the orthographic projection of the first insulating portion on the substrate; as well as An orthographic projection of the second pole on the substrate falls within an orthographic projection of the second insulating portion on the substrate.

11. The thin film transistor according to claim 4, wherein: The orthographic projection of the first pole on the substrate has a U-shape, the orthographic projection of the channel region on the substrate has a U-shape, and the orthographic projection of the channel region on the substrate is half-surrounded by the orthographic projection of the first pole on the substrate.

12. The thin film transistor according to claim 11, wherein: The orthographic projection of the first insulating portion on the substrate includes a U-shape.

13. The thin film transistor according to any one of claims 4 to 12, wherein: In a first direction, the first insulating portion has a first thickness, the first thickness is in a range of 500 angstroms to 4500 angstroms, and the first direction is parallel to a direction from the gate toward the active layer; and / or, In the first direction, the second gate insulating layer has a second thickness in a range of 500 angstroms to 5500 angstroms.

14. The thin film transistor according to any one of claims 3 to 13, wherein: The first gate insulating layer further includes an insulating protection portion, at least a portion of which is located between the first insulating portion and the second insulating portion, and the insulating protection portion has a third thickness in the first direction, and the third thickness is less than the first thickness.

15. An array substrate comprising the thin film transistor according to any one of claims 1 to 14.

16. The array substrate according to claim 15, wherein: The array substrate includes a plurality of pixel units, the array substrate includes a display area and a non-display area, the plurality of pixel units are located in the display area, and the orthographic projection of the first gate insulating layer on the array substrate is spaced apart from the display area; or, the thickness of the first gate insulating layer located in the display area is less than or equal to 1000 angstroms.

17. The array substrate according to claim 16, wherein: The first conductive layer further includes a first conductive transition portion, and the first gate insulating layer further includes a third insulating portion, wherein an orthographic projection of the third insulating portion on the substrate falls within an orthographic projection of the first conductive transition portion on the substrate; as well as The second conductive layer further includes a second conductive transition portion, and an orthographic projection of the second conductive transition portion on the substrate substantially coincides with an orthographic projection of the third insulating portion on the substrate.

18. A display device, comprising the thin film transistor according to any one of claims 1 to 14 or the array substrate according to any one of claims 15 to 17.

19. A method for preparing a thin film transistor, characterized in that: include: providing a substrate; Forming a first conductive material layer on the substrate, and performing a patterning process on the first conductive material layer to form a first conductive layer, wherein the first conductive layer includes a gate of a thin film transistor; forming a first gate insulating material layer on a side of the first conductive layer away from the substrate, and performing a patterning process on the first gate insulating material layer to form a first gate insulating layer; forming a second gate insulating layer on a side of the first gate insulating layer away from the substrate; as well as An active material layer is formed on a side of the second gate insulating layer away from the substrate, and a patterning process is performed on the active material layer to form an active layer, wherein the active layer includes a first polar region, a second polar region and a channel region, and the channel region is located between the first polar region and the second polar region. In which, in a first direction, the surface of the channel region close to the substrate is spaced apart from the surface of the gate away from the substrate by a first distance, the surface of the first polar region close to the substrate is spaced apart from the surface of the gate away from the substrate by a second distance, the first distance is smaller than the second distance, and the first direction is parallel to the direction of the gate toward the active layer.

20. The preparation method according to claim 19, wherein: The method further includes: forming a second conductive material layer on a side of the active layer away from the substrate, and performing a patterning process on the second conductive material layer to form a second conductive layer; The patterning process performed on the first gate insulating material layer and the patterning process performed on the second conductive material layer share the same mask.

Images