A split-gate SiC MOSFET device and its fabrication method
By employing an array-arranged cell structure and a stepped P-region design in the split-gate SiC MOSFET device, the problems of excessive Miller charge and poor gate oxide reliability are solved, achieving high-speed switching and high reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2025-01-16
- Publication Date
- 2026-05-12
AI Technical Summary
In existing split-gate SiC MOSFET devices, the Miller charge Qgd is too large, which slows down the switching speed, increases switching losses, and results in poor gate oxide reliability, making it prone to parasitic conduction and reliability problems.
The array-arranged cell structure is used to form a stepped P-region in the epitaxial layer by ion implantation, which reduces the contact area between the gate and the drain and enhances the reliability of the device. This includes setting N+ regions between adjacent or diagonal cell structures and forming stepped P-regions on the upper surface of the N+ regions to reduce the electric field strength of the gate oxide layer.
It effectively reduces the capacitive charge of the device, optimizes dynamic performance, enhances device reliability, prevents electric field concentration in the gate oxide layer, reduces parasitic conduction, and improves switching speed and withstand voltage.
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Figure CN119947207B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a split-gate SiC MOSFET device and its fabrication method. Background Technology
[0002] As a typical representative of third-generation semiconductor materials, SiC material has many advantages such as wide bandgap, high thermal conductivity, high critical electric field, and high electron mobility. Devices made from SiC are among the most promising devices currently available, featuring low impedance, high voltage, high temperature, high frequency, high efficiency, and radiation resistance. Therefore, SiC is widely used in automotive electronics, photovoltaic inverters, energy storage, and aerospace.
[0003] SiC devices mainly consist of three series: SiC SBDs, SiC MOSFETs, and SiC IGBTs. Currently, the market is primarily focused on the development of SiC SBDs and SiC MOSFETs. In SiC MOSFET field-effect transistors, breakdown typically occurs at the edge curve, i.e., the PN junction corner curve, in the region covered by the gate oxide layer. The electric field strength is greatest at this location when the MOSFET is in operation. In some existing split-gate device designs, the original monolithic gate is divided into left and right parts to reduce the overlap area between the gate and drain. This reduces the charge capacitance at the gate oxide without reducing the on-resistance, improving dynamic and short-circuit performance. While the split-gate design reduces gate capacitance and gate charge, the split-gate SiC MOSFET exposes the edge of the gate (Poly-Si), leading to a high electric field in the gate oxide layer under blocking characteristics.
[0004] Therefore, there is an urgent need to provide a discrete-gate SiC MOSFET device to improve the shortcomings of the existing technology. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a split-gate SiC MOSFET device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0006] In a first aspect, the present invention provides a split-gate SiC MOSFET device, comprising:
[0007] A cellular structure with multiple arrays arranged in an array; the cellular structure includes a body region disposed in an epitaxial layer, an N+ source region disposed in the middle region of the body region, and a P+ region disposed in the middle region of the N+ source region; wherein, a portion of the upper surface of the body region, a portion of the upper surface of the N+ source region, and the upper surface of the P+ region are exposed.
[0008] An N+ region is provided between adjacent cell structures, and a stepped P region is provided on the upper surface of the N+ region;
[0009] And / or, an N+ region is provided between the diagonal cell structures, and a stepped P region is provided on the upper surface of the N+ region.
[0010] Secondly, the present invention also provides a method for fabricating a split-gate SiC MOSFET device, for fabricating the aforementioned split-gate SiC MOSFET device, comprising:
[0011] Provide an epitaxial layer;
[0012] Multiple arrayed bulk regions are formed in the epitaxial layer by ion implantation;
[0013] An N+ source region is formed in the middle region of the bulk region by ion implantation;
[0014] A P+ region is formed in the middle region of the N+ source region by ion implantation;
[0015] N+ regions are formed between adjacent bulk regions by ion implantation; step-like P regions are formed in the N+ regions by ion implantation.
[0016] And / or, by ion implantation, N+ regions are formed between diagonal regions; by ion implantation, step-like P regions are formed in the N+ regions.
[0017] The beneficial effects of this invention are:
[0018] This invention provides a split-gate SiC MOSFET device and its fabrication method, comprising an epitaxial layer, in which arrayed cell structures are disposed, each cell structure including a body region, an N+ source region disposed in the middle region of the body region, and a P+ region disposed in the middle region of the N+ source region. The P+ region extends through the entire N+ source region along a direction perpendicular to the epitaxial layer. The entire upper surface of the P+ region, the upper surface of the side regions of the N+ source region, and the upper surface of the side regions of the body region are exposed. Further, N+ regions are disposed between adjacent cell structures, and the upper surface of the N+ regions... A stepped P-region is provided, and both the N+ region and the stepped P-region are located in the epitaxial layer, with the upper surface of the stepped P-region exposed; and / or, an N+ region is provided between diagonal cell structures, and a stepped P-region is provided on the upper surface of the N+ region, with both the N+ region and the stepped P-region located in the epitaxial layer, with the upper surface of the stepped P-region exposed; thus, by providing a stepped P-region between adjacent body regions, i.e., in the JFET region, the stepped P-region forms a pinch-off with the body region more quickly during device breakdown, reducing the electric field strength that the gate oxide layer needs to withstand and enhancing device reliability.
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a split-gate SiC MOSFET device provided in an embodiment of the present invention;
[0021] Figure 2 This is another schematic diagram of the split-gate SiC MOSFET device provided in an embodiment of the present invention;
[0022] Figure 3 This is a top view of a split-gate SiC MOSFET device provided in an embodiment of the present invention;
[0023] Figure 4 This is another top view of the split-gate SiC MOSFET device provided in an embodiment of the present invention;
[0024] Figure 5 This is another top view of the split-gate SiC MOSFET device provided in an embodiment of the present invention;
[0025] Figure 6 This is a flowchart of a method for fabricating a split-gate SiC MOSFET device provided in an embodiment of the present invention. Detailed Implementation
[0026] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0027] In the prior art, split-gate SiC MOSFET devices have the following drawbacks, specifically:
[0028] 1. The Miller charge Qgd of the SiC MOSFET device is too large;
[0029] The gate charge of a SiC MOSFET device includes Qgs (gate-source charge) and Qgd (gate-drain charge), with Qgd also known as Miller charge.
[0030] An excessively large Qgd will cause the device to require a longer charging time, which will slow down its switching speed and increase the switching losses of the device. In addition, excessive accumulation of gate charge will also impair the reliability of the device and cause failures such as HTRB and HTGB.
[0031] Meanwhile, an excessively large Qgd may also cause parasitic conduction in SiC MOSFET devices, resulting in temporary partial conduction and potential damage. Therefore, measures need to be taken to reduce the parasitic conduction factor (PTO) to avoid this parasitic conduction. The formula for calculating the parasitic conduction factor (PTO) is as follows:
[0032]
[0033] 2. SiC MOSFET devices have poor gate oxide reliability;
[0034] SiC MOSFETs have attracted significant attention in the field of power conversion due to their high voltage, high frequency, high temperature, and high power density characteristics. For SiC MOSFETs, gate oxide reliability is a crucial aspect of device reliability evaluation. SiC has a larger bandgap than Si, resulting in smaller devices and allowing for higher electric field strengths to be withstood by the gate oxide.
[0035] In summary, to improve the performance of SiC MOSFET devices, it is necessary to reduce the charge Qgd and protect the gate oxide.
[0036] In view of this, the present invention proposes a split-gate SiC MOSFET device that reduces the charge Qgd and capacitance Ciss, and on this basis, adds a protective gate oxide layer structure.
[0037] Please see Figure 1 , Figure 1 This is a schematic diagram of a split-gate SiC MOSFET device provided in an embodiment of the present invention. The split-gate SiC MOSFET device provided by the present invention includes: a plurality of cell structures 10 arranged in an array; the cell structure 10 includes a body region 30 disposed in an epitaxial layer 20, an N+ source region 40 disposed in the middle region of the body region 30, and a P+ region 50 disposed in the middle region of the N+ source region 40; wherein, a portion of the upper surface of the body region 30, a portion of the upper surface of the N+ source region 40, and the upper surface of the P+ region 50 are exposed;
[0038] An N+ region 60 is provided between adjacent cell structures 10, and a stepped P region 70 is provided on the upper surface of the N+ region 60.
[0039] And / or, an N+ region 60 is provided between the diagonal cell structures 10, and a stepped P region 70 is provided on the upper surface of the N+ region 60.
[0040] For details, please continue to see Figure 1The discrete-gate SiC MOSFET device provided in this embodiment has fast switching characteristics and can be used in high-frequency applications. It includes a substrate and an epitaxial layer 20 stacked sequentially. The epitaxial layer 20 contains arrayed cell structures 10, each including a body region 30. An N+ source region 40 is disposed in the middle region of the body region 30, and a P+ region 50 is disposed in the middle region of the N+ source region 40. Along a direction D2 perpendicular to the epitaxial layer, the P+ region 50 penetrates the entire N+ source region 40. The entire upper surface of the P+ region 50 is exposed, as are the upper surfaces of a portion of the N+ source region 40 and a portion of the upper surface of the body region 30. Furthermore, N+ regions 6 are disposed between adjacent cell structures 10. 0. A stepped P-region 70 is provided on the upper surface of the N+ region 60. Both the N+ region 60 and the stepped P-region 70 are disposed in the epitaxial layer 20, and the upper surface of the stepped P-region 70 is exposed. 2. Or, an N+ region 60 is provided between the diagonal cell structures 10. A stepped P-region 70 is provided on the upper surface of the N+ region 60. Both the N+ region 60 and the stepped P-region 70 are disposed in the epitaxial layer 20, and the upper surface of the stepped P-region 70 is exposed. Thus, a stepped P-region 70 is provided between adjacent body regions 30, i.e., in the JFET region. When the device withstands voltage, the stepped P-region 70 and the body region 30 form a pinch-off more quickly, reducing the electric field strength that the gate oxide layer needs to withstand and enhancing the reliability of the device.
[0041] Furthermore, when the device is reverse biased, the PN junction is reverse biased, and as the breakdown voltage increases, the depletion region gradually expands, protecting the gate oxide layer and enhancing the device's reliability. Figure 2 As shown.
[0042] In addition, in this embodiment, an N+ region 60 is provided between adjacent cell structures 10 and / or between diagonal cell structures 10. During the conduction of the SiC MOSFET device, the device resistance is mainly the channel resistance, the JFET region resistance, and the drift region resistance. N+ injection is performed in the JFET region to increase the carrier concentration, thereby reducing the JFET region resistance.
[0043] It should be noted that, Figure 1 The embodiments shown are only schematic representations of the positional relationships of the various film layers included in the SiC MOSFET device and do not represent its actual dimensions; Figure 2 The embodiment shown is only a schematic diagram of the depletion region of the SiC MOSFET device; in addition, the SiC MOSFET device also includes a drain located on the lower surface of the substrate, a gate dielectric located on the upper surface and side of the gate 90, and a source covering the uppermost layer.
[0044] In an optional embodiment of the present invention, please continue to refer to... Figure 1It also includes: a gate dielectric layer 80, disposed on the upper surface of the epitaxial layer 20, covering the upper surface of the exposed body region 30, and in contact with a portion of the upper surface of the exposed N+ source region 40, and in contact with a portion of the upper surface of the stepped P region 70.
[0045] Gate 90 is disposed on the upper surface of gate dielectric layer 80, and along the direction D2 perpendicular to the epitaxial layer, the orthogonal projection of gate 90 overlaps with the orthogonal projection of gate dielectric layer 80.
[0046] For details, please continue to see Figure 1 The split-gate SiC MOSFET device provided in this embodiment further includes a gate dielectric layer 80 disposed on the upper surface of the epitaxial layer 20. The gate dielectric layer 80 covers the upper surface of the exposed body region 30, a portion of the upper surface of the exposed N+ source region 40, and a portion of the upper surface of the exposed stepped P-region 70. The gate 90 covers the upper surface of the gate dielectric layer 80. In this embodiment, the gate 90 is configured as a split-gate structure, and the gate 90 is not completely covered in the area between adjacent body regions 30, but only covers a portion of the upper surface of the stepped P-region 70. This effectively reduces the contact area between the gate 90 and the drain, thereby reducing the capacitor charge.
[0047] Considering the existing full-area gate structure, the middle area below the gate oxide layer is often the weakest point and is prone to burn-in. This embodiment is set as a split gate structure, which can effectively avoid the occurrence of burn-in.
[0048] Furthermore, due to the two-dimensional curvature effect, the electric field strength at the gate apex is the highest. Due to the stress concentration at the corner, degradation is also likely to occur in practical applications, affecting the long-term reliability of the device. In this embodiment, the stepped P-region 70 covers the corner stress concentration area, and the electric field shielding effect of the stepped P-region 70 can prevent gate oxide breakdown caused by electric field concentration at this location.
[0049] It should be noted that in existing planar SiC MOSFET devices, the gate extends completely from the upper surface of one body region to the upper surface of another body region. During the turn-on and turn-off processes, the overlap area between the gate and drain is large, resulting in excessively large Miller charge Qgd and transfer capacitance Ciss values, which is not conducive to high-speed switching applications. The split gate structure provided by this invention can effectively reduce the capacitive charge of the gate 90 portion of the device and optimize the dynamic performance of the device.
[0050] Furthermore, in existing planar SiC MOSFET devices, the JFET region is uniformly N-type doped, resulting in excessively high electric field strength at the center of the gate oxide layer, which can lead to gate reliability failure. This phenomenon is even more pronounced in the split gate design. The present invention provides a stepped P-region 70 below the split gate, which can reduce the high electric field stress of the gate oxide layer.
[0051] In an optional embodiment of the present invention, along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the gate 90 is a ring structure, and the orthographic projections of adjacent gates 90 overlap with the orthographic projections of the same stepped P region 70.
[0052] Specifically, by setting the gate 90 to a ring structure, the contact area between the gate 90 and the drain can be reduced, thereby reducing the capacitive charge of the device and optimizing the dynamic performance of the SiC MOSFET device.
[0053] In an optional embodiment of the present invention, please continue to refer to... Figure 4 The stepped P-region 70 includes a first P-region 71 and a second P-region 72. The first P-region 71 is located on the upper surface of the N+ region 60. The second P-region 72 is located on both sides of the first P-region 71 along the direction D1 parallel to the epitaxial layer and along the direction D2 perpendicular to the epitaxial layer. The orthographic projection of the first P-region 71 overlaps with the orthographic projection of the N+ region 60, while the orthographic projection of the second P-region 72 does not overlap with the orthographic projection of the N+ region 60.
[0054] Along direction D2 perpendicular to the epitaxial layer, the height of the first P region 71 is greater than the height of the second P region 72.
[0055] For details, please continue to see Figure 2 The stepped P-region 70 provided in this embodiment includes a first P-region 71 and a second P-region 72. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the gate 90 overlaps with the orthographic projection of the second P-region 72 located on one side of the first P-region 71. The orthographic projections of adjacent gates 90 overlap with the orthographic projections of the second P-region 72 located on both sides of the first P-region 71 of the same stepped P-region 70. In this way, the P-region is set in a stepped shape, which protects the gate dielectric layer 80 while minimizing the JFET region resistance.
[0056] It should be noted that, as Figure 2 As shown, in this embodiment, second P regions 72 are formed by ion implantation on both sides of the first P region 71, forming a stepped P region 70, which enables the stepped P region 70 to cover the top corner of the gate oxide layer where the electric field intensity is concentrated.
[0057] In an optional embodiment of the present invention, the doping concentration of the first P region 71 is less than the doping concentration of the second P region 72.
[0058] Specifically, in this embodiment, since there is an N+ region 60 in the JFET region to reduce the resistance of the JFET region, a concentrated implantation is performed above the N+ region 60, i.e. at the first P region 71, to protect the gate oxide layer from the influence of the N+ implantation region. The implantation concentration in the second P region 72 can be lower than that in the first P region 71.
[0059] In an optional embodiment of the present invention, the doping concentration of the first P-region 71 is 1E16 to 1E20 cm⁻¹. 2 The doping concentration of the second P-region 72 is 1E16~1E18 cm⁻¹. 2 .
[0060] In an optional embodiment of the present invention, please refer to Figure 3 , Figure 3 This is a top view of the split-gate SiC MOSFET device provided in an embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P-region 70 presents a grid-like structure, which is disposed between adjacent cell structures 10 and between diagonal cell structures 10.
[0061] For details, please continue to see Figure 3 The stepped P-region 70 provided in this embodiment presents a grid pattern and is arranged between adjacent cell structures 10 and between diagonal cell structures 10. The stepped P-region 70 can be set at the position where the electric field intensity is highest.
[0062] In an optional embodiment of the present invention, please refer to Figure 4 , Figure 4 This is another top view of the separated gate SiC MOSFET device provided in the embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P region 70 presents an intermittent strip shape, which is disposed between adjacent cell structures 10.
[0063] For details, please continue to see Figure 4 The stepped P-region 70 provided in this embodiment is in the form of discontinuous strips, arranged between adjacent cell structures 10, and not set between diagonal cell structures 10. The stepped P-region 70 can be set at the position where the electric field strength is highest.
[0064] In an optional embodiment of the present invention, please refer to Figure 5 , Figure 5 This is another top view of the separated gate SiC MOSFET device provided in the embodiment of the present invention. Along the direction D2 perpendicular to the epitaxial layer, the orthographic projection of the stepped P region 70 appears as a dot, which is disposed between the diagonal cell structures 10.
[0065] For details, please continue to see Figure 5 The stepped P-region 70 provided in this embodiment is dot-shaped and is only arranged between diagonal cell structures 10, and is not set between adjacent cell structures 10. The stepped P-region 70 can be set at the position where the electric field intensity is highest.
[0066] Based on the same inventive concept, please refer to Figure 6 , Figure 6This is a flowchart of a method for fabricating a split-gate SiC MOSFET device according to an embodiment of the present invention. The present invention also provides a method for fabricating a split-gate SiC MOSFET device, used to fabricate the split-gate SiC MOSFET device provided in the above embodiments. Examples of SiC MOSFET devices are described above and will not be repeated here. The fabrication method includes:
[0067] S101, Provide an epitaxial layer 20;
[0068] S102. Multiple arrayed bulk regions 30 are formed in the epitaxial layer 20 by ion implantation.
[0069] S103. An N+ source region 40 is formed in the middle region of the bulk region 30 by ion implantation.
[0070] S104. A P+ region 50 is formed in the middle region of the N+ source region 40 by ion implantation.
[0071] S105. An N+ region 60 is formed between adjacent bulk regions 30 by ion implantation; a stepped P region 70 is formed in the N+ region 60 by ion implantation.
[0072] Alternatively, N+ regions 60 can be formed between the diagonal regions 30 by ion implantation; and stepped P regions 70 can be formed in the N+ regions 60 by ion implantation.
[0073] Specifically, an N+ region 60 is formed by ion implantation between adjacent body regions 30, a first P region 71 is formed by ion implantation in the N+ region 60, and a second P region 72 is formed by ion implantation on the side of the first P region 71; or, an N+ region 60 is formed by ion implantation between diagonal body regions 30, a first P region 71 is formed by ion implantation in the N+ region 60, and a second P region 72 is formed by ion implantation on the side of the first P region 71.
[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0076] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A split-gate SiC MOSFET device, characterized in that, include: A cellular structure with multiple arrays arranged in a single array; the cellular structure includes a body region disposed in an epitaxial layer, an N+ source region disposed in the middle region of the body region, and a P+ region disposed in the middle region of the N+ source region; wherein a portion of the upper surface of the body region, a portion of the upper surface of the N+ source region, and the upper surface of the P+ region are exposed. An N+ region is provided between adjacent cell structures, and a stepped P region is provided on the upper surface of the N+ region; And / or, an N+ region is provided between the diagonally opposite cell structures, and a stepped P region is provided on the upper surface of the N+ region; The stepped P-region includes a first P-region and a second P-region. The first P-region is located on the upper surface of the N+ region. The second P-region is located on both sides of the first P-region along a direction parallel to the epitaxial layer and along a direction perpendicular to the epitaxial layer. The orthographic projection of the first P-region overlaps with the orthographic projection of the N+ region, while the orthographic projection of the second P-region does not overlap with the orthographic projection of the N+ region. Along the direction perpendicular to the epitaxial layer, the height of the first P region is greater than the height of the second P region, and the doping concentration of the first P region is less than the doping concentration of the second P region.
2. The split-gate SiC MOSFET device according to claim 1, characterized in that, Also includes: A gate dielectric layer is disposed on the upper surface of the epitaxial layer and covers the upper surface of the exposed body region, and contacts a portion of the upper surface of the exposed N+ source region and a portion of the upper surface of the stepped P region. A gate is disposed on the upper surface of the gate dielectric layer, and along a direction perpendicular to the epitaxial layer, the orthogonal projection of the gate overlaps with the orthogonal projection of the gate dielectric layer.
3. The split-gate SiC MOSFET device according to claim 2, characterized in that, Along the direction perpendicular to the epitaxial layer, the orthographic projection of the gate is a ring structure, and the orthographic projections of adjacent gates overlap with the orthographic projections of the same stepped P-region.
4. The split-gate SiC MOSFET device according to claim 1, characterized in that, The doping concentration of the first P-region is 1E16~1E20 cm⁻¹ 2 The doping concentration of the second P-region is 1E16~1E18 cm⁻¹ 2 .
5. The split-gate SiC MOSFET device according to claim 1, characterized in that, Along the direction perpendicular to the epitaxial layer, the orthogonal projection of the stepped P-region presents a grid-like pattern, disposed between adjacent cell structures and between diagonally opposite cell structures.
6. The split-gate SiC MOSFET device according to claim 1, characterized in that, Along the direction perpendicular to the epitaxial layer, the orthographic projection of the stepped P-region presents a discontinuous strip shape, which is disposed between adjacent cell structures.
7. The split-gate SiC MOSFET device according to claim 1, characterized in that, Along the direction perpendicular to the epitaxial layer, the orthographic projection of the stepped P-region appears as a dot, disposed between the diagonally opposite cell structures.
8. A method for fabricating a split-gate SiC MOSFET device, used to fabricate the split-gate SiC MOSFET device as described in any one of claims 1 to 7, characterized in that, include: Provide an epitaxial layer; Multiple arrayed bulk regions are formed in the epitaxial layer by ion implantation; An N+ source region is formed in the middle region of the body region by ion implantation. A P+ region is formed in the middle region of the N+ source region by ion implantation. An N+ region is formed between adjacent bulk regions by ion implantation; a stepped P region is formed in the N+ region by ion implantation. And / or, by means of ion implantation, N+ regions are formed between the diagonally opposite body regions; and by means of ion implantation, stepped P regions are formed in the N+ regions.