Methods for improving leakage of core components

Abstract

The present invention provides a method for improving leakage in core components. The method comprises: providing a semiconductor structure comprising a semiconductor substrate, a gate structure, a first sidewall spacer, and a hard mask layer; etching the hard mask layer to expose the semiconductor substrate between the gate structures, and forming a second sidewall spacer outside the first sidewall spacer, with a trim step performed before etching; performing a first vertical etching process on the semiconductor substrate using the second sidewall spacer of the gate structure as a self-aligned condition to form a trench, wherein the trench has an inverted trapezoidal shape; performing a lateral etching process on the trench to give the trench a spherical shape; performing a second vertical etching process on the trench to reduce the trench to a predetermined depth; and performing a TMAH etching process on the trench to give the trench a Sigma-shaped shape. The present invention solves the problem of leakage in existing core components.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for improving leakage of core components. Background Art

[0002] The 28nm HV platform integrates high-voltage devices (32V, gate drive), medium-voltage devices (8V, source drive), and low-voltage devices (LV 1.2V, Mipi; CORE / SRAM 0.9V, logic operation / information drive). As CORE components shrink significantly in size, when the width of the source and drain depletion regions approaches the device channel length, source-drain punchthrough will occur in short-channel devices. As the drain voltage increases, the self-built barrier height (DIBL) between the source and substrate decreases, making it impossible for the device to control drain leakage through the gate. Furthermore, to improve device performance, PMOS devices use SiGe technology. However, the introduction of SiGe technology increases the short channel effect (SCE), which in turn increases core component leakage.

[0003] Currently, a common method is to reduce leakage by adjusting the device speed through LDD halo implant, but this method will affect device performance. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the leakage of core components, so as to solve the problem that the existing core components are prone to leakage.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for improving leakage of core components, the method comprising:

[0006] A semiconductor structure is provided, comprising a semiconductor substrate, a gate structure formed on a surface of the semiconductor substrate, first spacers formed on both sides of the gate structure, and a hard mask layer covering the gate structure, the first spacers, and the semiconductor substrate, wherein the semiconductor substrate at least includes a PMOS formation region, and the gate structure is formed at least in the PMOS formation region;

[0007] Etching the hard mask layer to expose the semiconductor substrate between the gate structures, and forming a second sidewall spacer outside the first sidewall spacer, and performing a trim step before etching the second sidewall spacer;

[0008] Performing a first vertical etching process on the semiconductor substrate with the second sidewall of the gate structure as a self-aligned condition to form a trench, wherein the trench is in an inverted trapezoidal shape;

[0009] Continuing to perform a lateral etching process on the trench so that the trench has a spherical shape, wherein two points of the spherical trench having the largest distance in the horizontal direction are two first tips, the first tips are vertically spaced from the surface of the semiconductor substrate by a first distance, and the first tips are horizontally spaced from the gate structure by a second distance;

[0010] Continuing to perform a second vertical etching process on the trench so that the trench reaches a predetermined depth;

[0011] The TMAH etching process is continued to be performed on the trench so that the trench is Sigma-shaped, and the depth of the Sigma-shaped trench remains unchanged, the two points with the largest distance in the horizontal direction are two second tips, the distance between the second tip and the surface of the semiconductor substrate in the vertical direction is a third distance, and the third distance is equal to the first distance, the distance between the second tip and the gate structure in the horizontal direction is a fourth distance, and the fourth distance is less than the second distance.

[0012] Optionally, when performing the trim step, at a rate of .

[0013] Optionally, the second distance is 108 nm.

[0014] Optionally, the fourth distance is 60 nm.

[0015] Optionally, the material of the hard mask layer includes silicon nitride.

[0016] Optionally, the gate structure includes a gate dielectric layer, a polysilicon gate formed on a surface of the gate dielectric layer, and a gate mask layer formed on a surface of the polysilicon gate.

[0017] Optionally, the material of the first sidewall spacer includes silicon oxide.

[0018] Optionally, the semiconductor substrate further includes an NMOS formation region, and when the semiconductor substrate is etched to form the trench, a protection layer is used to protect the device structure of the NMOS region.

[0019] Optionally, the protection layer includes a BARC layer.

[0020] As described above, the method of improving core component leakage of the present invention adjusts the rate of the trim step of the PMOS transistor trench in the core component to adjust the time used and the lateral etching time. On the basis of maintaining the trench depth (i.e., the distance between the trench bottom and the semiconductor substrate surface) and the sigma depth (i.e., the distance between the tip and the semiconductor substrate surface) unchanged, the tip-to-gate distance is shortened, thereby reducing the risk of holes diffusing into the channel due to thermal processes, thereby effectively reducing the core component DIBL leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 6 It is a schematic cross-sectional structural diagram showing the process of forming a sigma-type trench according to the present invention.

[0022] Explanation of Figure Numbers

[0023] 10: semiconductor structure; 11: semiconductor substrate; 12: gate structure; 121: polysilicon gate; 122: gate mask layer; 122a: silicon oxide layer; 122b: silicon nitride layer; 13: first sidewall spacer; 20: hard mask layer; 21: second sidewall spacer; 30: trench; 40: protective layer; 50: shallow trench isolation structure; 60: photoresist layer DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.

[0025] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0026] This embodiment provides a method for improving leakage of core components, the method comprising:

[0027] A semiconductor structure 10 is provided, comprising a semiconductor substrate 11, a gate structure 12 formed on a surface of the semiconductor substrate 11, first spacers 13 formed on both sides of the gate structure 12, and a hard mask layer 20 covering the gate structure 12, the first spacers 13, and the semiconductor substrate 11. The semiconductor substrate 11 at least includes a PMOS formation region, and the gate structure 12 is formed at least in the PMOS formation region.

[0028] The hard mask layer 20 is etched to expose the semiconductor substrate 11 between the gate structures 12, and a second spacer 21 is formed outside the first spacer 13, and a trim step is performed before etching the second spacer 21;

[0029] Performing a first vertical etching process on the semiconductor substrate 11 under a self-aligned condition with the second sidewall spacer 21 of the gate structure to form a trench 30, wherein the trench 30 is in an inverted trapezoidal shape;

[0030] The trench 30 is further subjected to a lateral etching process so that the trench 30 is spherical, and the two points of the spherical trench 30 with the largest distance in the horizontal direction are two first tips, the first tips are vertically spaced from the surface of the semiconductor substrate 11 by a first distance D1, and the first tips are horizontally spaced from the gate structure 12 by a second distance D2;

[0031] Continuing to perform a second vertical etching process on the trench 30 so that the trench 30 reaches a predetermined depth;

[0032] The TMAH etching process is continued to be performed on the trench 30 so that the trench 30 is Sigma-shaped, and the depth of the Sigma-shaped trench 30 remains unchanged, and the two points with the largest distance in the horizontal direction are two second tips, and the distance between the second tip and the surface of the semiconductor substrate 11 in the vertical direction is a third distance D3, and the third distance is equal to the first distance, and the distance between the second tip and the gate structure 12 in the horizontal direction is a fourth distance D4, and the fourth distance D4 is less than the second distance D2.

[0033] In this embodiment, the Sigma-shaped trench 30 is used to fill the SiGe epitaxial layer. Furthermore, since the angle between the (111) and (100) crystal planes remains constant, when the trench depth is fixed, the height of the second tip of the Sigma-shaped trench does not change with the TMAH etching time, but only shifts horizontally toward the sides of the Sigma-shaped trench.

[0034] Specifically, the gate structure 12 includes a gate dielectric layer, a polysilicon gate 121 formed on a surface of the gate dielectric layer, and a gate mask layer 122 formed on a surface of the polysilicon gate 121 .

[0035] like Figure 1 As shown, in this embodiment, the gate mask layer 122 includes a silicon oxide layer 122a and a silicon nitride layer 122b, and the silicon nitride layer 122b is formed on the surface of the silicon oxide layer 122a. It should be noted that the gate dielectric layer is not shown in this embodiment.

[0036] Specifically, the first sidewall spacer 13 is made of silicon oxide.

[0037] Specifically, the material of the hard mask layer 20 includes silicon nitride.

[0038] Specifically, the semiconductor substrate 11 further includes an NMOS formation region, and when the semiconductor substrate 11 is etched to form the trench 30 , the protection layer 40 is used to protect the device structure of the NMOS region.

[0039] like Figure 1 As shown, in this embodiment, the NMOS formation region also includes the gate structure 12, the first spacer 13, and the hard mask layer 20 formed on the surface of the gate structure 12, the surface of the first spacer 13, and the semiconductor substrate 11. Moreover, the NMOS formation region is separated from the PMOS formation region by a shallow trench isolation structure 50.

[0040] More specifically, the protection layer 40 includes a BARC layer.

[0041] In this embodiment, the method for forming the BARC layer in the NMOS formation area includes: forming the BARC layer on the entire surface of the semiconductor structure and forming a photoresist layer 60 on the BARC layer; patterning the photoresist layer 60 to expose the BARC layer formed in the PMOS formation area; and etching the BARC layer located in the PMOS formation area until the hard mask layer 20 is exposed.

[0042] Specifically, when executing the trim step, at a rate of .

[0043] In this embodiment, the trim step is performed after etching the BARC layer and before etching the hard mask layer 20, and when performing the trim step, the trim step is performed by using rate to shorten the time taken.

[0044] Specifically, the second distance D2 is 108 nm.

[0045] Specifically, the fourth distance D4 is 60 nm.

[0046] In summary, the present invention improves core component leakage by adjusting the rate of the trim step of the PMOS transistor trench in the core component to adjust the time used and the lateral etching time. This reduces the tip-to-gate distance between the tip and the gate structure while maintaining the same trench depth (i.e., the distance between the trench bottom and the semiconductor substrate surface) and sigma depth (i.e., the distance between the tip and the semiconductor substrate surface). This reduces the risk of holes diffusing into the channel due to thermal processes, thereby effectively reducing core component DIBL leakage. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving leakage of core components, characterized in that: The method comprises: A semiconductor structure is provided, comprising a semiconductor substrate, a gate structure formed on a surface of the semiconductor substrate, first spacers formed on both sides of the gate structure, and a hard mask layer covering the gate structure, the first spacers, and the semiconductor substrate, wherein the semiconductor substrate at least includes a PMOS formation region, and the gate structure is formed at least in the PMOS formation region; Etching the hard mask layer to expose the semiconductor substrate between the gate structures, and forming a second sidewall spacer outside the first sidewall spacer, and performing a trim step before etching the second sidewall spacer; Performing a first vertical etching process on the semiconductor substrate with the second sidewall of the gate structure as a self-aligned condition to form a trench, wherein the trench is in an inverted trapezoidal shape; Continuing to perform a lateral etching process on the trench so that the trench has a spherical shape, wherein two points of the spherical trench having the largest distance in the horizontal direction are two first tips, the first tips are vertically spaced from the surface of the semiconductor substrate by a first distance, and the first tips are horizontally spaced from the gate structure by a second distance; Continuing to perform a second vertical etching process on the trench so that the trench reaches a predetermined depth; The TMAH etching process is continued to be performed on the trench so that the trench is Sigma-shaped, and the depth of the Sigma-shaped trench remains unchanged, the two points with the largest distance in the horizontal direction are two second tips, the distance between the second tip and the surface of the semiconductor substrate in the vertical direction is a third distance, and the third distance is equal to the first distance, the distance between the second tip and the gate structure in the horizontal direction is a fourth distance, and the fourth distance is less than the second distance.

2. The method for improving leakage of core components according to claim 1, characterized in that: When performing the trim step, at a rate of .

3. The method for improving leakage of core components according to claim 1, characterized in that: The second distance is 108 nm.

4. The method for improving leakage of core components according to claim 1, characterized in that: The fourth distance is 60 nm.

5. The method for improving leakage of core components according to claim 1, characterized in that: The material of the hard mask layer includes silicon nitride.

6. The method for improving leakage of core components according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a polysilicon gate formed on a surface of the gate dielectric layer, and a gate mask layer formed on a surface of the polysilicon gate.

7. The method for improving leakage of core components according to claim 1, characterized in that: The material of the first sidewall spacer includes silicon oxide.

8. The method for improving leakage of core components according to claim 1, characterized in that: The semiconductor substrate further includes an NMOS formation region, and when the semiconductor substrate is etched to form the trench, a protection layer is used to protect the device structure of the NMOS region.

9. The method for improving leakage of core components according to claim 8, characterized in that: The protection layer includes a BARC layer.

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