Semiconductor device and method of manufacturing the same
Patent Information
- Application Number
- CN202510039625.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2045-01-09
AI Technical Summary
[0005]本申请提供了一种半导体器件及其制备方法，可以解决CMOS器件中中压器件的Ioff偏大的问题
[0031]本申请中，在不额外增加光罩的情况下，通过调整CMOS器件的用于打开轻掺杂漏区的光罩，扩大CMOS器件中的中压器件区的轻掺杂漏区二之间的间距，使得在制备中压器件区的栅极之后，本申请中压器件区的栅极与轻掺杂漏区二在空间上重叠区域的横向尺寸比传统中压器件的栅极与轻掺杂漏区在空间上重叠区域的横向尺寸小，同时减薄中压器件区的氧化介质层使得最终的栅氧化层厚度小于传统中压器件的栅氧化层厚度，这样既能降低中压器件在关态时的电流Ioff，又能提升中压器件在饱和区工作时的电流Idsat，在器件尺寸进一步缩小的情况下，减小器件的漏电，改善器件的电性能。
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Figure CN119947222B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a semiconductor device and its fabrication method. Background Technology
[0002] Using the UD18 CMOS device can replace the existing UD33 / UD55 CMOS devices used for switching functions, which can reduce area and thus improve competitiveness.
[0003] However, current UD18 CMOS device models are based on an 8V gate oxide layer, resulting in poor roll-off performance. The length (P18L) of the UD1.8V PMOS device is 0.67μm. off The current under reverse bias is too high, and the turn-on speed of the UD1.8V NMOS device is too slow.
[0004] Currently, due to the slow turn-on speed of the UD1.8V NMOS device, gate oxide layer thinning is being considered for future product use. After thinning the gate oxide layer of the CMOS device, the length (P18L) of the UD1.8V PMOS device is 0.78 / 0.83μm. The length of the UD1.8V PMOS device after thinning is better than that before thinning, thus improving the turn-on speed of the UD1.8V NMOS device. However, I... off It is still too large and does not meet the electrical requirements of the device. Summary of the Invention
[0005] This application provides a semiconductor device and its fabrication method, which can solve the I / O problem of medium-voltage devices in CMOS devices. off The problem is that it's too big.
[0006] On one hand, embodiments of this application provide a method for fabricating a semiconductor device, including:
[0007] A substrate is provided, the substrate comprising a low-voltage device region, a medium-voltage device region and a high-voltage device region, wherein a plurality of shallow trench isolation structures for isolating different device regions are formed in the substrate;
[0008] Ion implantation was performed on the substrate to form a lightly doped drain region 1 in the low-voltage device region, a lightly doped drain region 2 in the medium-voltage device region, and a lightly doped drain region 3 in the high-voltage device region.
[0009] An oxide dielectric layer is formed, the oxide dielectric layer covering the substrate;
[0010] A photoresist layer is coated on the oxide dielectric layer;
[0011] The opening pattern of the medium-voltage device region is defined on the photoresist layer by photolithography to obtain a patterned photoresist layer;
[0012] Using a patterned photoresist layer as a mask, a portion of the oxide dielectric layer in the medium-voltage device region is etched to obtain the gate oxide layer in the medium-voltage device region;
[0013] Remove the patterned photoresist layer;
[0014] A polysilicon layer is formed, which covers the gate oxide layer of the medium-voltage device region;
[0015] The polysilicon layer of the medium-voltage device region is etched to obtain the gate of the medium-voltage device region, wherein the lateral dimension of the area where the gate and the lightly doped drain region 2 in the substrate overlap in space does not exceed one-sixth of the lateral dimension of the gate of the medium-voltage device region.
[0016] Optionally, in the method for fabricating the semiconductor device, in the substrate of the medium-voltage device region, the spacing between the two lightly doped drain regions on both sides of the gate of the medium-voltage device region is at least three-fifths of the lateral dimension of the gate of the medium-voltage device region.
[0017] Optionally, in the method for fabricating the semiconductor device, the thickness of the gate oxide layer in the medium-voltage device region is less than or equal to...
[0018] Optionally, in the method for fabricating the semiconductor device, before removing the patterned photoresist layer and after forming the polysilicon layer, the method further includes:
[0019] Ion implantation is performed on the substrate of the medium-voltage device region to form source and drain regions in the lightly doped drain regions on both sides of the gate of the medium-voltage device region.
[0020] Optionally, in the method for fabricating the semiconductor device, after etching the polysilicon layer of the medium-voltage device region to obtain the gate of the medium-voltage device region, the method for fabricating the semiconductor device further includes:
[0021] A gate sidewall is formed, which is located on both sides of the gate in the medium voltage device region and on the gate oxide layer.
[0022] On the other hand, embodiments of this application also provide a semiconductor device, including:
[0023] A substrate comprising a low-voltage device region, a medium-voltage device region, and a high-voltage device region, wherein a plurality of shallow trench isolation structures are formed in the substrate for isolating different device regions;
[0024] Lightly doped drain region 1, lightly doped drain region 2, and lightly doped drain region 3, wherein lightly doped drain region 1 is located in the substrate of the low-voltage device region, lightly doped drain region 2 is located in the substrate of the medium-voltage device region, and lightly doped drain region 3 is located in the substrate of the high-voltage device region;
[0025] An oxide dielectric layer, the oxide dielectric layer covering the substrate of the low-voltage device region and the high-voltage device region;
[0026] A gate oxide layer covering the substrate of the medium-voltage device region;
[0027] A gate located on the gate oxide layer, wherein the lateral dimension of the area in which the gate and the lightly doped drain region 2 in the substrate overlap spatially does not exceed one-sixth of the lateral dimension of the gate in the medium voltage device region.
[0028] Optionally, in the semiconductor device, in the substrate of the medium-voltage device region, the spacing between the two lightly doped drain regions on both sides of the gate of the medium-voltage device region is at least three-fifths of the lateral dimension of the gate of the medium-voltage device region.
[0029] Optionally, in the semiconductor device, the thickness of the gate oxide layer in the medium-voltage device region is less than or equal to
[0030] The technical solution of this application has at least the following advantages:
[0031] In this application, without adding an additional photomask, the spacing between the two lightly doped drain regions in the medium-voltage device region of the CMOS device is increased by adjusting the photomask used to open the lightly doped drain region. This results in the lateral dimension of the spatially overlapping region between the gate and the lightly doped drain region in the medium-voltage device region of this application being smaller than that of the conventional medium-voltage device after the gate is fabricated. Simultaneously, the oxide dielectric layer of the medium-voltage device region is thinned, resulting in a final gate oxide layer thickness that is less than that of the conventional medium-voltage device. This reduces the current I of the medium-voltage device in the off-state. off It can also increase the current I of medium-voltage devices when they are operating in the saturation region. dsat As device size is further reduced, leakage current is decreased and electrical performance is improved. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0033] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0034] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention;
[0035] The reference numerals in the attached figures are explained as follows:
[0036] 10-Substrate, 11-Shallow trench isolation structure, 21-Photoresist layer one, 22-Photoresist layer two, 31-Lightly doped drain region one, 32-Lightly doped drain region two, 33-Lightly doped drain region three, 40-Oxide dielectric layer, 41-Gate oxide layer of medium voltage device, 50-Gate of medium voltage device. Detailed Implementation
[0037] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0040] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0041] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes:
[0042] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after the formation of a shallow trench isolation structure according to an embodiment of this application. A substrate 10 is provided, which includes a low-voltage device region, a medium-voltage device region and a high-voltage device region. A plurality of shallow trench isolation structures 11 for isolating different device regions (high-voltage device region, medium-voltage device region and low-voltage device region) are formed in the substrate 10.
[0043] This embodiment takes PMOS as an example in the medium-voltage device region to continue to introduce the fabrication method of the semiconductor device provided in this application.
[0044] In this embodiment, an N-type well region (not shown) is also formed in the substrate 10 of the medium-voltage device region.
[0045] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of lightly doped drain region 1, lightly doped drain region 2, and lightly doped drain region 3 according to an embodiment of this application. First, a photoresist layer 21 is coated on the substrate 10. Then, a lightly doped drain region pattern is defined on the photoresist layer 21 using a specific photomask. Next, the patterned photoresist layer 21 is used as a mask. Finally, ion implantation is performed on the substrate 10 to form lightly doped drain region 31 in the low-voltage device region, lightly doped drain region 32 in the medium-voltage device region, and lightly doped drain region 33 in the high-voltage device region.
[0046] In this embodiment, P-type ion implantation is performed on the substrate 10 of the medium-voltage device region to form a lightly doped P-type drain region 32 in the medium-voltage device region.
[0047] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the oxide dielectric layer according to an embodiment of this application. The oxide dielectric layer 40 is formed and covers the substrate 10.
[0048] Further reference Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the oxide dielectric layer of each device region is formed according to an embodiment of this application. The oxide dielectric layer 40 can be etched to obtain the oxide dielectric layer 40 of each device region (high voltage device region, medium voltage device region and low voltage device region).
[0049] Next, proceed to step S4: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the gate oxide layer of the medium voltage device region is formed according to an embodiment of this application. A photoresist layer 22 is coated on the oxide dielectric layer 40 and the surface of the substrate 10.
[0050] Further, proceed to step S5: Continue to refer to... Figure 6 The opening pattern (gate oxide layer) of the medium-voltage device region is defined on the photoresist layer 22 by photolithography to obtain the patterned photoresist layer 22.
[0051] Next, proceed to step S6: Continue to refer to Figure 6 Using the patterned photoresist layer 22 as a mask, a portion of the oxide dielectric layer 40 of the medium-voltage device region is etched to obtain the gate oxide layer 41 of the medium-voltage device region.
[0052] Preferably, the thickness of the gate oxide layer 41 in the medium-voltage device region is less than or equal to
[0053] Further, step S7 is performed: removing the patterned photoresist layer 22.
[0054] In this embodiment, after removing the patterned photoresist layer 22, ion implantation can be performed on the substrate 10 of the medium-voltage device region to form source and drain regions (not shown) in the lightly doped drain regions 32 on both sides of the gate 50 of the medium-voltage device region.
[0055] In other embodiments, after removing the patterned photoresist layer 22, the oxide dielectric layer 40 of the high-voltage device region and the oxide dielectric layer 40 of the low-voltage device region can be etched back through the same photolithography and etching process to obtain the gate oxide layer of the high-voltage device region and the gate oxide layer of the low-voltage device region (not shown).
[0056] Next, step S8 is performed: forming a polysilicon layer (not shown), the polysilicon layer at least covering the gate oxide layer 41 of the medium voltage device region.
[0057] Finally, proceed to step S9: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the gate of the medium-voltage device region is formed according to an embodiment of this application. The polysilicon layer of the medium-voltage device region is etched to obtain the gate 50 of the medium-voltage device region. The lateral dimension d1 of the spatially overlapping region between the gate 50 and the lightly doped drain region 32 in the substrate 10 does not exceed one-sixth of the lateral dimension d2 of the gate of the medium-voltage device region. Without adding an additional photomask, this application expands the spacing between two adjacent lightly doped drain regions 32 in the medium-voltage device region of the CMOS device by adjusting the photomask that opens the lightly doped drain region. This results in the lateral dimension of the spatially overlapping region between the gate and the lightly doped drain region 32 of the medium-voltage device region after the gate of the medium-voltage device region is fabricated, which is smaller than the lateral dimension of the spatially overlapping region between the gate and the lightly doped drain region of a conventional medium-voltage device. This reduces the current I of the medium-voltage device in the off-state when the device size is further reduced. off .
[0058] In this embodiment, the lateral dimension d1 of the spatially overlapping region between the gate 50 and the lightly doped drain region 32 in the substrate 10 is one-sixth of the lateral dimension d2 of the gate in the medium-voltage device region.
[0059] Preferably, in the substrate of the medium-voltage device region, the spacing between the two lightly doped drain regions on both sides of the gate of the medium-voltage device region is at least three-fifths of the lateral dimension d2 of the gate of the medium-voltage device region.
[0060] In this embodiment, in the substrate of the medium-voltage device region, the spacing between the two lightly doped drain regions on both sides of the gate of the medium-voltage device region is three-fifths of the lateral dimension d2 of the gate of the medium-voltage device region.
[0061] In this application, without adding an additional photomask, the spacing between two adjacent lightly doped drain regions in the medium-voltage device region of the CMOS device is increased by adjusting the photomask that opens the lightly doped drain region. This results in the lateral dimension of the spatially overlapping region between the gate and the lightly doped drain region in the medium-voltage device region of this application being smaller than that of the spatially overlapping region between the gate and the lightly doped drain region in conventional medium-voltage devices after the gate of the medium-voltage device region is fabricated. At the same time, the oxide dielectric layer of the medium-voltage device region is thinned so that the final gate oxide layer thickness is smaller than that of conventional medium-voltage devices. This reduces the current I of the medium-voltage device in the off-state. off It can also increase the current I of medium-voltage devices when they are operating in the saturation region. dsatAs device size is further reduced, leakage current is decreased and electrical performance is improved.
[0062] Furthermore, after etching the polysilicon layer of the medium-voltage device region to obtain the gate 50 of the medium-voltage device region, the method for fabricating the semiconductor device may further include: forming a gate sidewall (not shown), the gate sidewall being located on both sides of the gate of the medium-voltage device region and on the gate oxide layer.
[0063] Based on the same inventive concept, this application also provides a semiconductor device, see reference. Figure 7 The semiconductor device includes:
[0064] Substrate 10, which includes a low-voltage device region, a medium-voltage device region and a high-voltage device region, and a plurality of shallow trench isolation structures 11 are formed in the substrate for isolating different device regions;
[0065] Lightly doped drain region 1 31, lightly doped drain region 2 32, and lightly doped drain region 33 are provided. Lightly doped drain region 1 31 is located in the substrate 10 of the low-voltage device region, lightly doped drain region 2 32 is located in the substrate 10 of the medium-voltage device region, and lightly doped drain region 33 is located in the substrate 10 of the high-voltage device region.
[0066] An oxide dielectric layer 40 is located on the substrate 10 of the low-voltage device region and the high-voltage device region;
[0067] A gate oxide layer 41 is located on the substrate 10 of the medium-voltage device region.
[0068] The gate 50 of the medium-voltage device region is located on the gate oxide layer 41, wherein the lateral dimension d1 of the area where the gate 50 and the lightly doped drain region 32 in the substrate 10 overlap in space does not exceed one-sixth of the lateral dimension d2 of the gate of the medium-voltage device region.
[0069] Preferably, in the substrate 10 of the medium-voltage device region, the spacing between the two lightly doped drain regions 32 on both sides of the gate 50 of the medium-voltage device region is at least three-fifths of the lateral dimension d2 of the gate 50 of the medium-voltage device region.
[0070] Preferably, the thickness of the gate oxide layer 41 in the medium-voltage device region is less than or equal to
[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The semiconductor device manufacturing method comprises the following steps: providing a substrate, the substrate comprising a low-voltage device region, a medium-voltage device region and a high-voltage device region, and a plurality of shallow trench isolation structures formed in the substrate for isolating different device regions; performing ion implantation on the substrate respectively to form a lightly doped drain region one in the low-voltage device region, a lightly doped drain region two in the medium-voltage device region and a lightly doped drain region three in the high-voltage device region respectively; forming an oxide medium layer covering the substrate; coating a photoresist layer on the oxide medium layer; defining an opening pattern of the medium-voltage device region on the photoresist layer by a photolithography process to obtain a patterned photoresist layer; masking with the patterned photoresist layer, etching a partial thickness of the oxide medium layer of the medium-voltage device region to obtain a gate oxide layer of the medium-voltage device region; removing the patterned photoresist layer; forming a polysilicon layer covering the gate oxide layer of the medium-voltage device region; etching the polysilicon layer of the medium-voltage device region to obtain a gate electrode of the medium-voltage device region, wherein a lateral dimension of a spatially overlapping area between the gate electrode and the lightly doped drain region two in the substrate is not more than one sixth of a lateral dimension of the gate electrode of the medium-voltage device region.
2. The method of producing a semiconductor device according to claim 1, wherein In the substrate of the medium-voltage device region, a spacing between the two lightly doped drain regions two on both sides of the gate electrode of the medium-voltage device region is at least three fifths of the lateral dimension of the gate electrode of the medium-voltage device region.
3. The method of manufacturing a semiconductor device according to claim 1, wherein A thickness of the gate oxide layer of the medium-voltage device region is less than or equal to 140 Å.
4. The method of producing a semiconductor device according to Claim 1, wherein Before removing the patterned photoresist layer and after forming the polysilicon layer, the semiconductor device manufacturing method further comprises: performing ion implantation on the substrate of the medium-voltage device region respectively to form a source region and a drain region in the lightly doped drain regions two on both sides of the gate electrode of the medium-voltage device region respectively.
5. The method of producing a semiconductor device according to Claim 1, wherein After etching the polysilicon layer of the medium-voltage device region to obtain a gate electrode of the medium-voltage device region, the semiconductor device manufacturing method further comprises: forming a gate side wall on both sides of the gate electrode of the medium-voltage device region and on the gate oxide layer.
6. The semiconductor device prepared by the method of claim 1, wherein The semiconductor device comprises: a substrate comprising a low-voltage device region, a medium-voltage device region and a high-voltage device region, and a plurality of shallow trench isolation structures formed in the substrate for isolating different device regions; a lightly doped drain region one in the substrate of the low-voltage device region, a lightly doped drain region two in the substrate of the medium-voltage device region and a lightly doped drain region three in the substrate of the high-voltage device region; an oxide medium layer covering the substrate of the low-voltage device region and the high-voltage device region; a gate oxide layer covering the substrate of the medium-voltage device region; a gate electrode on the gate oxide layer, wherein a lateral dimension of a spatially overlapping area between the gate electrode and the lightly doped drain region two in the substrate is not more than one sixth of a lateral dimension of the gate electrode of the medium-voltage device region.
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