Method for manufacturing u-shaped trench gate with in-line sidewall structure

Abstract

The application provides a manufacturing method of U-shaped trench gate with side wall structure, which forms a side wall structure at each protruding polysilicon side wall, and the side wall structure is extended from the top side wall of the polysilicon layer to the epitaxial layer; a metal pre-interlayer is formed, a second photoresist layer is formed on the metal pre-interlayer, the second photoresist layer is opened by photoetching to define the forming position of the contact hole, the contact hole located in the cell area and between the two side wall structures is formed by using the high selectivity etching of the metal pre-interlayer relative to the outer protective layer, the contact hole is extended from the upper surface of the metal pre-interlayer to the epitaxial layer, the second photoresist layer is removed, and a metal layer filling the contact hole is formed. In the small period deep trench MOSFET process, the contact hole short circuit to the polysilicon layer caused by the fluctuation of the contact hole photoetching critical dimension or overlaying can not cause the device failure, or the contact hole injection close to the MOS channel can cause the device parameter fluctuation, and the gate-source capacitance can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of U-shaped trench gate with inner side wall structure. BACKGROUND

[0002] Generally, the trench type MOSFET with trench contact hole is a non-self-alignment process, and the distance between the trench contact hole and the trench gate is controlled by the layout design and the precision of the photoetch process. In the process of continuously pursuing size reduction and reducing on-resistance, when the pitch is less than 0.6 um, the contact hole with good morphology brings great challenges to the photoetch and etching process.

[0003] In order to solve the above problems, a new manufacturing method of U-shaped trench gate with inner side wall structure is needed. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a manufacturing method of U-shaped trench gate with inner side wall structure, which is used to solve the problem that the contact hole with good morphology brings great challenges to the photoetch and etching process with the size reduction in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of U-shaped trench gate with inner side wall structure, comprising:

[0006] Step one, providing a substrate, forming an epitaxial layer on the substrate, forming a hard mask layer on the epitaxial layer, forming a first photoresist layer on the hard mask layer, and opening the first photoresist layer by photoetching to expose part of the hard mask layer, so as to define the formation position of the gate trench on the cell area and the substrate lead-out area;

[0007] Step two, etching the exposed hard mask layer to the exposed epitaxial layer to form an opening pattern, removing the remaining first photoresist layer, and continuing to etch the exposed epitaxial layer to form a deep trench;

[0008] Step three, forming a gate dielectric layer in the deep trench and a polysilicon layer filling the remaining deep trench;

[0009] Step four, removing the hard mask layer, the top end of the polysilicon layer being convex relative to the epitaxial layer, and forming a body region and a source region on the cell area by ion implantation;

[0010] Step five, forming a thermal oxidation layer on the epitaxial layer and the convex polysilicon layer by a thermal oxidation method, depositing an outer protective layer, and etching back the thermal oxidation layer and the outer protective layer to form a side wall structure at each side wall of the convex polysilicon, the side wall structure extending from the top end side wall of the polysilicon layer to the epitaxial layer.

[0011] Step six, forming a metal pre-mediating layer, forming a second photoresist layer on the metal pre-mediating layer, opening the second photoresist layer by photoetching to define the forming position of the contact hole, forming the contact hole in the cell region and between the two side wall structures by high selective etching of the metal pre-mediating layer relative to the outer protective layer, the contact hole extending from the upper surface of the metal pre-mediating layer to the epitaxial layer, removing the second photoresist layer, and forming a metal layer filling the contact hole.

[0012] Preferably, the material of the hard mask layer in step one is oxide.

[0013] Preferably, the method of etching in step two is dry etching.

[0014] Preferably, the method of forming the gate dielectric layer in the deep trench and the polysilicon layer filling the remaining deep trench in step three comprises: forming the gate dielectric layer in the deep trench by thermal oxidation; depositing the polysilicon layer and grinding the polysilicon layer to the hard mask layer.

[0015] Preferably, the side wall structure in step five has two approximately elliptical shapes on both sides of the same deep trench from the perspective of cross section.

[0016] Preferably, the material of the outer protective layer in step five is Si3N4.

[0017] Preferably, step six further comprises ion implantation to the contact hole before forming the metal layer filling the contact hole.

[0018] As described above, the manufacturing method of the U-shaped trench gate with side wall structure of the present application has the following beneficial effects:

[0019] The present application does not cause device failure due to short circuit of the contact hole to the polysilicon layer caused by fluctuation of the photoetching critical dimension or overlay of the contact hole, or fluctuation of device parameters caused by contact hole implantation close to the MOS channel, and can reduce the gate-source capacitance in the small period deep trench MOSFET process. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The process flow diagram of the present application is shown;

[0021] Figure 2 The photoetching opening of the first photoresist layer of the present application is shown;

[0022] Figure 3 The opening of the hard mask layer of the present application is shown;

[0023] Figure 4A schematic diagram showing the formation of deep trenches according to the present application;

[0024] Figure 5 A schematic diagram showing the formation of a gate dielectric layer and a polysilicon layer according to the present application;

[0025] Figure 6 A schematic diagram showing the removal of a hard mask layer according to the present application;

[0026] Figure 7 A schematic diagram showing the formation of a sidewall structure according to the present application;

[0027] Figure 8 A schematic diagram showing the formation of a self-aligned contact hole according to the present application. DETAILED DESCRIPTION

[0028] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description of the embodiments of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the present description can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0029] Referring to Figure 1 , the present application provides a method for manufacturing a U-shaped trench gate with a sidewall structure, comprising:

[0030] Step one, providing a substrate 101, forming an epitaxial layer 102 on the substrate 101, forming a hard mask layer 103 on the epitaxial layer 102, forming a first photoresist layer 104 on the hard mask layer 103, and opening the first photoresist layer 104 by photolithography to expose part of the hard mask layer 103, so as to define the formation position of the gate trench on the cell region and the substrate 101 leading-out region, forming a structure as shown in Figure 2

[0031] In some embodiments, the material of the hard mask layer 103 in step one is oxide.

[0032] Step two, etching the exposed hard mask layer 103 to expose the epitaxial layer 102 to form an opening pattern, and removing the remaining first photoresist layer 104, which can be removed by methods such as ashing process and wet cleaning, forming a structure as shown in Figure 3 Figure 4

[0033] In some embodiments, the etching method in step two is dry etching.

[0034] Step three, forming a gate dielectric layer 105 in the deep trench and a polysilicon layer 106 to fill the remaining deep trench, forming a structure as shown in​​​Figure 5 the structure shown in FIG. 4B;

[0035] In some embodiments, the method of forming the gate dielectric layer 105 in the deep trench and the polysilicon layer 106 to fill the remaining deep trench in step three includes: forming the gate dielectric layer 105 on the epitaxial layer 102 in the deep trench by thermal oxidation; depositing the polysilicon layer 106, and grinding the polysilicon layer 106 to the hard mask layer 103, the grinding method is usually chemical mechanical planarization grinding.

[0036] Step four, removing the hard mask layer 103, the top end of the polysilicon layer 106 is convex relative to the epitaxial layer 102, forming the body region 107 and the source region 108 on the cell region by ion implantation, forming the structure as shown in FIG. 4C; Figure 6 the structure shown in FIG. 4C;

[0037] Step five, forming the thermal oxide layer 1091 on the epitaxial layer 102 and the convex polysilicon layer 106 by thermal oxidation, depositing the outer protective layer 1092, and etching back the thermal oxide layer 1091 and the outer protective layer 1092, the etching back method can be dry etching or wet etching, forming the side wall structure 109 at each side wall of the convex polysilicon, the side wall structure 109 extends from the top end side wall of the polysilicon layer 106 to the epitaxial layer 102, forming the structure as shown in FIG. 4D; Figure 7 the structure shown in FIG. 4D;

[0038] In some embodiments, the side wall structure 109 in step five is approximately elliptical in shape on both sides of the same deep trench from the perspective of the cross section.

[0039] In some embodiments, the material of the outer protective layer 1092 in step five is Si3N4.

[0040] Step six, forming the metal pre-mediun layer 110, forming the second photoresist layer on the metal pre-mediun layer 110, and opening the second photoresist layer by lithography to define the formation position of the contact hole, forming the contact hole in the cell region and between the two side wall structures 109 by high selectivity etching of the metal pre-mediun layer 110 relative to the outer protective layer 1092, the contact hole extends from the upper surface of the metal pre-mediun layer 110 to the epitaxial layer 102, removing the second photoresist layer, and forming the metal layer 111 to fill the contact hole, forming the structure as shown in FIG. 4E; Figure 8The metal pre-dielectric material is oxide, and the material of the outer layer protection layer 1092 in the side wall structure 109 is Si3N4. By using the high selectivity etching of oxide relative to Si3N4, a self-aligned contact hole can be formed. In a small pitch deep trench MOSFET process, the contact hole short-circuiting to the polysilicon layer 106 caused by fluctuation of the contact hole lithography CD (critical dimension) or Overlay (overlay) does not cause device failure, or the contact hole implantation close to the MOS channel causes fluctuation of device parameters, and the gate-source capacitance Cgs can be reduced.

[0041] In some embodiments, before forming the metal layer 111 filling the contact hole in step six, ion implantation to the contact hole is further included.

[0042] In some embodiments, the metal layer 111 filling the contact hole can include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some examples, the contact hole can further include a barrier layer such as tantalum and tantalum nitride, titanium and titanium nitride.

[0043] It should be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be randomly changed in shape, number and proportion, and the layout pattern of the components can be more complex.

[0044] In summary, in a small pitch deep trench MOSFET process, the present application can prevent the contact hole short-circuiting to the polysilicon layer caused by fluctuation of the contact hole lithography critical dimension or Overlay from causing device failure, or the contact hole implantation close to the MOS channel from causing fluctuation of device parameters, and can reduce the gate-source capacitance. Therefore, the present application effectively overcomes the various disadvantages in the prior art and has a high industrial utilization value.

[0045] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method of manufacturing a U-shaped trench gate with an in-line spacer structure, characterized by, At least comprising: Step one, providing a substrate, forming an epitaxial layer on the substrate, forming a hard mask layer on the epitaxial layer, forming a first photoresist layer on the hard mask layer, opening the first photoresist layer by lithography to expose part of the hard mask layer to define the formation position of gate trenches on the cell region and the substrate lead-out region; Step two, etching the exposed hard mask layer to the epitaxial layer to form an opening pattern, removing the remaining first photoresist layer, and continuing to etch the exposed epitaxial layer to form a deep trench; Step three, forming a gate dielectric layer in the deep trench and a polysilicon layer to fill the remaining deep trench; Step four, removing the hard mask layer, the top end of the polysilicon layer is convex relative to the epitaxial layer, and ion implantation is used to form a body region and a source region on the cell region; Step five, forming a thermal oxide layer on the epitaxial layer and the convex polysilicon layer by thermal oxidation, depositing an outer protective layer, etching back the thermal oxide layer and the outer protective layer to form a side wall structure at each side wall of the convex polysilicon, the side wall structure extends from the top end side wall of the polysilicon layer to the epitaxial layer; Step six, forming a metal pre-mediator layer, forming a second photoresist layer on the metal pre-mediator layer, opening the second photoresist layer by lithography to define the formation position of a contact hole, using the metal pre-mediator layer to etch relative to the outer protective layer with a high selectivity to form a contact hole in the cell region and between the two side wall structures, the contact hole extends from the upper surface of the metal pre-mediator layer to the epitaxial layer, removing the second photoresist layer, and forming a metal layer to fill the contact hole.

2. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: The material of the hard mask layer in step one is oxide.

3. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: The etching method in step two is dry etching.

4. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: The method of forming a gate dielectric layer in the deep trench and a polysilicon layer to fill the remaining deep trench in step three includes: using thermal oxidation to form the gate dielectric layer in the deep trench; depositing the polysilicon layer and grinding the polysilicon layer to the hard mask layer.

5. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: The side wall structure in step five is in the shape of two approximate ellipses on both sides of the same deep trench from the perspective of cross-section.

6. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: The material of the outer protective layer in step five is Si3N4.

7. The method of manufacturing a U-shaped trench gate with in-line spacers as recited in claim 1, wherein: Before forming the metal layer to fill the contact hole in step six, ion implantation of the contact hole is also included.

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