Semiconductor structure and preparation method thereof, and semiconductor structure identification method

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a semiconductor structure identification method. The semiconductor structure comprises a substrate which comprises a standard region and a feature region which are arranged along a first direction; the standard virtual grids are located in the standard area, the multiple standard virtual grids are arranged in the first direction and extend in the second direction, a standard distance is formed between every two adjacent standard virtual grids, and an included angle is formed between the second direction and the first direction; the feature virtual grids are located in the feature area, the multiple feature virtual grids are arranged in the first direction and extend in the second direction, a feature interval exists between every two adjacent feature virtual grids, and the feature interval is the deviation value of the standard interval; the feature intervals of the plurality of feature virtual gates are sequentially combined into feature codes of the semiconductor structure, and the feature codes are used for marking the semiconductor structure. According to the technical scheme, the process type or designer of the semiconductor structure is identified through the feature code.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof, and a semiconductor structure identification method. Background Art

[0002] At present, the basic function of the standard dummy fill structure (Dummy Fill) is only to assist in the chemical mechanical polishing (CMP), thermal annealing, epitaxy (EPI), lithography (Litho) and other processes of integrated circuit design for manufacturability (DFM). Therefore, how to identify the process and designer of the structure through the semiconductor product structure is a problem that needs to be solved at present. Summary of the invention

[0003] The technical problem to be solved by the present invention is how to identify the process and designer of the structure through the structure of a semiconductor product, and provides a semiconductor structure and a preparation method thereof, and a semiconductor structure identification method.

[0004] In order to solve the above problems, the present invention provides a semiconductor structure, including: a substrate, including a standard area and a feature area arranged along a first direction; a standard virtual gate, located in the standard area, a plurality of the standard virtual gates are arranged along the first direction and extend along a second direction, and a standard spacing is provided between two adjacent standard virtual gates, wherein the second direction forms an angle with the first direction; a feature virtual gate, located in the feature area, a plurality of the feature virtual gates are arranged along the first direction and extend along the second direction, and a feature spacing is provided between two adjacent feature virtual gates, and the feature spacing is an offset value of the standard spacing; the feature spacings of the plurality of feature virtual gates are sequentially combined into a feature code of the semiconductor structure, and the feature code is used to mark the semiconductor structure.

[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: providing a substrate and a feature code, and obtaining a combination order of feature spacings corresponding to the feature code, wherein the substrate comprises a standard area and a feature area arranged along a first direction; forming a feature virtual gate arranged along the first direction and extending along a second direction in the feature area on the surface of the substrate according to the combination order of the feature spacings, and forming a standard virtual gate arranged along the first direction and extending along the second direction in the standard area on the surface of the substrate, wherein the second direction forms an angle with the first direction, a standard spacing is provided between two adjacent standard virtual gates, a feature spacing is provided between two adjacent feature virtual gates, and the feature spacing is an offset value of the standard spacing.

[0006] In order to solve the above problems, the present invention provides a semiconductor structure identification method, comprising the following steps: providing a semiconductor structure, wherein the semiconductor structure adopts the semiconductor structure as described in any one of claims 1 to 8; performing slice analysis on the semiconductor structure to sequentially obtain characteristic spacings between all adjacent characteristic virtual gates; obtaining a characteristic code of the semiconductor structure through the characteristic spacings of all the characteristic virtual gates, and then identifying the semiconductor structure.

[0007] The above technical solution sets a characteristic virtual gate in the semiconductor structure and sets different characteristic spacings between multiple characteristic virtual gates. The process used by the semiconductor and its designer are marked by a specific sequential combination of different characteristic spacings. When the semiconductor structure is sliced ​​and analyzed, the characteristic code of the semiconductor structure can be obtained by the sequential combination of the characteristic spacings, and the process type or designer of the semiconductor structure can be identified by the characteristic code.

[0008] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 It is a structural schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0011] Figure 2 FIG. 4 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention.

[0012] Figure 3 The figure is a flow chart of the steps of an embodiment of the method for preparing a semiconductor structure according to the present invention.

[0013] Figure 4 A schematic structural diagram of a substrate is provided for one embodiment of the method for preparing a semiconductor structure of the present invention.

[0014] Figure 5 The figure is a flowchart of one embodiment of the semiconductor structure identification method of the present invention. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] See also Figure 1 , which is a schematic diagram of the structure of an embodiment of the semiconductor structure of the present invention. Figure 1 As shown, the semiconductor structure includes a substrate 10, a standard virtual gate 11 and a characteristic virtual gate 12. The substrate 10 includes a standard area 101 and a characteristic area 102 arranged along a first direction D1, wherein the boundary between the standard area 101 and the characteristic area 102 is drawn with a dotted line. The standard virtual gate 11 is located in the standard area 101, and a plurality of the standard virtual gates 11 are arranged along the first direction D1 and extend along the second direction D2. A standard spacing X0 is provided between two adjacent standard virtual gates 11, wherein the second direction D2 forms an angle with the first direction D1. The characteristic virtual gate 12 is located in the characteristic area 102, and a plurality of the characteristic virtual gates 12 are arranged along the first direction D1 and extend along the second direction D2. A characteristic spacing Xn is provided between two adjacent characteristic virtual gates 12, and the characteristic spacing Xn is an offset value of the standard spacing X0. The characteristic spacings Xn of the plurality of characteristic virtual gates 12 are sequentially combined into a characteristic code of the semiconductor structure, and the characteristic code is used to mark the semiconductor structure.

[0017] The above technical solution sets a characteristic virtual gate in the semiconductor structure and sets different characteristic spacings between multiple characteristic virtual gates. The process used by the semiconductor and its designer are marked by a specific sequential combination of different characteristic spacings. When the semiconductor structure is sliced ​​and analyzed, the characteristic code of the semiconductor structure can be obtained by the sequential combination of the characteristic spacings, and the process type or designer of the semiconductor structure can be identified by the characteristic code.

[0018] In some embodiments, there are multiple characteristic spacings Xn, and the multiple characteristic spacings Xn have different offset values ​​relative to the standard spacing X0, and each characteristic spacing Xn corresponds to a characteristic character.

[0019] In some embodiments, the characteristic spacing Xn is 26, and the characteristic characters are English letters;

[0020] The first characteristic character is the English letter A, and the corresponding characteristic spacing Xn is a nm+b nm;

[0021] The second characteristic character is the English letter B, and the corresponding characteristic spacing Xn is a nm+b nm+c*1 nm;

[0022] And so on.

[0023] The last characteristic character is the English letter Z, and the corresponding characteristic spacing Xn is a nm+b nm+c*25nm;

[0024] Wherein, a nm is the standard spacing X0, b nm is the starting point of the offset value, and c nm is the interval increment interval.

[0025] In some embodiments, the characteristic spacing Xn of a plurality of the characteristic virtual gates 12 is sequentially combined by corresponding characteristic characters to obtain the characteristic code of the semiconductor structure.

[0026] In some embodiments, the feature code is used to mark the process type or designer of the semiconductor structure.

[0027] In this embodiment, the standard spacing X0 is 250nm; the offset value starts from 5nm and gradually increases at intervals of 1nm. Taking the characteristic characters as English letters as an example, the characteristic spacing X1 corresponding to the first characteristic character English letter A is 250nm+5nm=255nm; the characteristic spacing X2 corresponding to the second characteristic character English letter B is 250nm+5nm+1*1nm=256nm; and so on, the characteristic spacing X26 corresponding to the last characteristic character English letter Z is 250nm+5nm+1*25nm=280nm.

[0028] On this basis, the semiconductor structure in this embodiment includes four characteristic virtual gates 12 and two standard virtual gates 11. Among them, the characteristic spacing X7 between the first characteristic virtual gate 121 and the second characteristic virtual gate 122 adjacent to each other is 261nm, corresponding to the characteristic character English letter G; the characteristic spacing X20 between the second characteristic virtual gate 122 and the third characteristic virtual gate 123 adjacent to each other is 271nm, corresponding to the characteristic character English letter T; the characteristic spacing X1 between the third characteristic virtual gate 123 and the fourth characteristic virtual gate 124 adjacent to each other is 255nm, corresponding to the characteristic character English letter A. Therefore, according to the sequential combination of the characteristic spacings Xn of the four characteristic virtual gates 12 in this embodiment, a characteristic code "GTA" is formed to mark the designer of the semiconductor structure. When the semiconductor structure in this embodiment is sliced ​​and analyzed, the characteristic spacings Xn of the four characteristic virtual gates 12 can be obtained, and then the characteristic code "GTA" is obtained to identify the designer of the semiconductor structure, effectively ensuring that the designer's technology and process are not infringed.

[0029] The spacing between two adjacent standard virtual gates 11 is the standard spacing X0, and the spacing between the standard virtual gate 11 and the adjacent characteristic virtual gate 124 is also the standard spacing X0, that is, 250nm. The standard virtual gate 11 is located after the last characteristic virtual gate 12, and serves to mark the end of the characteristic code.

[0030] In other embodiments, the characteristic character may also be a number, or a combination of a number and an English letter.

[0031] See also Figure 2 , which is a structural schematic diagram of another embodiment of the semiconductor structure described in the present invention. Figure 2 The embodiment shown is Figure 1 The difference from the embodiment shown is that in this embodiment, a virtual active area 23 is further formed in the substrate 20, and the virtual active area 23 partially overlaps with the standard virtual gate 21 and / or the characteristic virtual gate 22. Adding the virtual active area 23 in the substrate 20 can further accurately simulate the MOS structure, ensure that the density of the active area meets the process requirements, and improve the device performance.

[0032] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a semiconductor structure.

[0033] See also Figure 3 , which is a flow chart of steps of an embodiment of the method for preparing a semiconductor structure according to the present invention. Figure 3 As shown, the semiconductor structure preparation method includes the following steps: step S31, providing a substrate and a feature code, and obtaining a combination order of feature spacings corresponding to the feature code, wherein the substrate includes a standard area and a feature area arranged along a first direction; step S32, forming a feature virtual gate arranged along the first direction and extending along a second direction in the feature area on the surface of the substrate according to the combination order of the feature spacings, and forming a standard virtual gate arranged along the first direction and extending along the second direction in the standard area on the surface of the substrate, wherein the second direction forms an angle with the first direction, a standard spacing is provided between two adjacent standard virtual gates, and a feature spacing is provided between two adjacent feature virtual gates, and the feature spacing is an offset value of the standard spacing.

[0034] Please refer to Figure 4 And step S31, providing a substrate 10 and a feature code, and obtaining a combination sequence of feature spacings corresponding to the feature code, wherein the substrate 10 includes a standard area 101 and a feature area 102 arranged along a first direction D1.

[0035] In this embodiment, the characteristic code is "GTA", which is used to mark the designer. The characteristic code is three characters, corresponding to the three characteristic spacings. Among them, the standard spacing is 250nm, the characteristic spacing X7 corresponding to the English letter G is 250nm+5nm+1*6nm=261nm; the characteristic spacing X20 corresponding to the English letter T is 250nm+5nm+1*19nm=274nm; the characteristic spacing X1 corresponding to the English letter A is 250nm+5nm+1*0nm=255nm. The combination order of the characteristic spacings obtained according to the characteristic code is 261nm, 274nm, and 255nm, and four characteristic virtual gates need to be set.

[0036] Please refer to Figure 1 And step S32, according to the combination sequence of the characteristic spacings, a characteristic virtual gate 12 arranged along the first direction D1 and extending along the second direction D2 is formed in the characteristic area 102 on the surface of the substrate 10, and a standard virtual gate 11 arranged along the first direction D1 and extending along the second direction D2 is formed in the standard area 101 on the surface of the substrate 10, wherein the second direction D2 forms an angle with the first direction D1, and there is a standard spacing X0 between two adjacent standard virtual gates 11, and there is a characteristic spacing Xn between two adjacent characteristic virtual gates 12, and the characteristic spacing Xn is the offset value of the standard spacing X0.

[0037] In this embodiment, the characteristic spacing combination sequence of 261nm, 274nm, and 255nm is obtained according to the characteristic code, and four characteristic virtual gates 12 are formed on the surface of the substrate 10. The standard virtual gate 11 is formed after the last virtual characteristic gate 12 to mark the cutoff of the characteristic code.

[0038] In other embodiments, a process code corresponding to the semiconductor structure may also be provided to form the characteristic virtual gate capable of identifying the special process adopted by the semiconductor structure.

[0039] The above technical solution sets a characteristic virtual gate in the semiconductor structure and sets different characteristic spacings between multiple characteristic virtual gates. The process used by the semiconductor and its designer are marked by a specific sequential combination of different characteristic spacings. When the semiconductor structure is sliced ​​and analyzed, the characteristic code of the semiconductor structure can be obtained by the sequential combination of the characteristic spacings, and the process type or designer of the semiconductor structure can be identified by the characteristic code.

[0040] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure identification method.

[0041] See also Figure 5, which is a flow chart of steps of an embodiment of the semiconductor structure identification method of the present invention. Figure 5 As shown, the semiconductor structure identification method includes the following steps: step S51, providing a semiconductor structure, the semiconductor structure adopts the semiconductor structure described in the present invention; step S52, slicing the semiconductor structure to sequentially obtain the characteristic spacing between all adjacent characteristic virtual gates; step S53, obtaining the characteristic code of the semiconductor structure through the characteristic spacing of all the characteristic virtual gates, and then identifying the semiconductor structure.

[0042] Please refer to Figure 1 And step S51, providing a semiconductor structure, the semiconductor structure adopts the semiconductor structure of the present invention. In this embodiment, the semiconductor structure adopts Figure 1 The semiconductor structure shown.

[0043] Please refer to Figure 1 And step S52, slice analysis is performed on the semiconductor structure to sequentially obtain characteristic spacings Xn between all adjacent characteristic virtual gates 12. In this embodiment, the semiconductor structure includes four characteristic virtual gates 12, and the characteristic spacings Xn between two adjacent characteristic virtual gates 12 are X7=261nm, X20=274nm, and X1=255nm.

[0044] Please refer to Figure 1 And step S53, obtaining the characteristic code of the semiconductor structure through the characteristic spacing Xn of all the characteristic virtual gates 12, thereby identifying the semiconductor structure.

[0045] In some embodiments, each characteristic spacing Xn corresponds to a characteristic character, and the step of obtaining the characteristic code of the semiconductor structure by sequentially combining the characteristic spacings Xn of the characteristic virtual gates 12 to further identify the semiconductor structure further includes the following steps:

[0046] (1) Sequentially obtain the characteristic characters corresponding to each characteristic spacing Xn. In this embodiment, the characteristic spacing X7=261nm corresponds to the English letter G, the characteristic spacing X20=274nm corresponds to the English letter T, and the characteristic spacing X1=255nm corresponds to the English letter A.

[0047] (2) Obtaining the characteristic code of the semiconductor structure according to the characteristic characters corresponding to the characteristic spacings Xn of all the characteristic virtual gates 12. In this embodiment, the obtained characteristic characters G, T, and A are combined to obtain the characteristic code "GTA".

[0048] (3) Identifying the process type or designer of the semiconductor structure according to the feature code. In this embodiment, the feature code "GTA" can be used to identify that the designer of the semiconductor structure is "GTA".

[0049] The above technical solution sets a characteristic virtual gate in the semiconductor structure and sets different characteristic spacings between multiple characteristic virtual gates. The process used by the semiconductor and its designer are marked by a specific sequential combination of different characteristic spacings. When the semiconductor structure is sliced ​​and analyzed, the characteristic code of the semiconductor structure can be obtained by the sequential combination of the characteristic spacings, and the process type or designer of the semiconductor structure can be identified by the characteristic code.

[0050] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0051] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0052] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0053] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate comprising a standard area and a feature area arranged along a first direction; A standard virtual gate is located in the standard area, a plurality of the standard virtual gates are arranged along the first direction and extend along the second direction, and a standard spacing exists between two adjacent standard virtual gates, wherein the second direction forms an angle with the first direction; A characteristic virtual gate is located in the characteristic area, a plurality of the characteristic virtual gates are arranged along the first direction and extend along the second direction, and a characteristic spacing is provided between two adjacent characteristic virtual gates, and the characteristic spacing is an offset value of the standard spacing; The characteristic pitches of the plurality of characteristic virtual gates are sequentially combined into a characteristic code of the semiconductor structure, and the characteristic code is used to mark the semiconductor structure.

2. The semiconductor structure according to claim 1, characterized in that: There are multiple characteristic spacings, and the multiple characteristic spacings have different offset values ​​relative to the standard spacing. Each characteristic spacing corresponds to a characteristic character.

3. The semiconductor structure according to claim 2, characterized in that: The characteristic spacing is 26, and the characteristic characters are English letters; The first characteristic character is the English letter A, and the corresponding characteristic spacing is a nm+b nm; The second characteristic character is the English letter B, and the corresponding characteristic spacing is a nm+b nm+c*1nm; and so on. The last characteristic character is the English letter Z, and the corresponding characteristic spacing is a nm+b nm+c*25 nm; wherein a nm is the standard spacing, b nm is the starting point of the offset value, and c nm is the incremental interval.

4. The semiconductor structure according to claim 3, characterized in that: The characteristic spacings of the plurality of characteristic virtual gates are combined in sequence with the corresponding characteristic characters to obtain the characteristic code of the semiconductor structure.

5. The semiconductor structure according to claim 2, characterized in that: The characteristic character is a number.

6. The semiconductor structure according to claim 1, characterized in that The feature code is used to mark the process type or designer of the semiconductor structure.

7. The semiconductor structure according to claim 1, characterized in that: A virtual active region is also formed in the substrate, and the virtual active region partially overlaps with the standard virtual gate or the characteristic virtual gate.

8. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate and a feature code, and obtaining a combination sequence of feature spacings corresponding to the feature code, wherein the substrate includes a standard area and a feature area arranged along a first direction; According to the combination sequence of the characteristic spacings, characteristic virtual gates arranged along the first direction and extending along the second direction are formed in the characteristic area on the surface of the substrate, and standard virtual gates arranged along the first direction and extending along the second direction are formed in the standard area on the surface of the substrate, wherein the second direction forms an angle with the first direction, a standard spacing exists between two adjacent standard virtual gates, a characteristic spacing exists between two adjacent characteristic virtual gates, and the characteristic spacing is an offset value of the standard spacing.

9. A semiconductor structure identification method, characterized in that: The steps include: Providing a semiconductor structure, wherein the semiconductor structure adopts the semiconductor structure according to any one of claims 1 to 7; Performing slice analysis on the semiconductor structure to sequentially obtain characteristic spacings between all adjacent characteristic virtual gates; The characteristic code of the semiconductor structure is obtained through the characteristic spacing of all the characteristic virtual gates, so as to identify the semiconductor structure.

10. The method according to claim 9, characterized in that Each of the characteristic spacings corresponds to a characteristic character, and the step of obtaining the characteristic code of the semiconductor structure through the characteristic spacings of all the characteristic virtual gates and then identifying the semiconductor structure further comprises the following steps: Sequentially obtain the characteristic characters corresponding to each characteristic spacing; Obtaining the characteristic code of the semiconductor structure according to the characteristic characters corresponding to the characteristic spacings of all the characteristic virtual gates; The process type or designer of the semiconductor structure is identified according to the feature code.

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